target/linux/sunxi/patches-3.12/104-arm-sunxi_add_pll5-6_dts.patch

   1 From 4f40ad1587e9435a2085703fa2a7d7c9245306b2 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Sun, 26 May 2013 14:08:59 -0300
   4 Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
  10 device trees.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 ---
  14  arch/arm/boot/dts/sun4i-a10.dtsi  | 19 +++++++++++++++++--
  15  arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
  16  arch/arm/boot/dts/sun5i-a13.dtsi  | 19 +++++++++++++++++--
  17  arch/arm/boot/dts/sun7i-a20.dtsi  | 28 ++++++++++++++++------------
  18  4 files changed, 67 insertions(+), 18 deletions(-)
  19
  20 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
  21 index a6c1cae..5e2fc45 100644
  22 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  23 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  24 @@ -73,6 +73,22 @@
  25                         clocks = <&osc24M>;
  26                 };
  27
  28 +               pll5: pll5@01c20020 {
  29 +                       #clock-cells = <1>;
  30 +                       compatible = "allwinner,sun4i-pll5-clk";
  31 +                       reg = <0x01c20020 0x4>;
  32 +                       clocks = <&osc24M>;
  33 +                       clock-output-names = "pll5_ddr", "pll5_other";
  34 +               };
  35 +
  36 +               pll6: pll6@01c20028 {
  37 +                       #clock-cells = <1>;
  38 +                       compatible = "allwinner,sun4i-pll6-clk";
  39 +                       reg = <0x01c20028 0x4>;
  40 +                       clocks = <&osc24M>;
  41 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
  42 +               };
  43 +
  44                 /* dummy is 200M */
  45                 cpu: cpu@01c20054 {
  46                         #clock-cells = <0>;
  47 @@ -138,12 +154,11 @@
  48                                 "apb0_ir1", "apb0_keypad";
  49                 };
  50
  51 -               /* dummy is pll62 */
  52                 apb1_mux: apb1_mux@01c20058 {
  53                         #clock-cells = <0>;
  54                         compatible = "allwinner,sun4i-apb1-mux-clk";
  55                         reg = <0x01c20058 0x4>;
  56 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
  57 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
  58                 };
  59
  60                 apb1: apb1@01c20058 {
  61 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
  62 index c3f4eed..b29412a 100644
  63 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  64 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  65 @@ -70,6 +70,22 @@
  66                         clocks = <&osc24M>;
  67                 };
  68
  69 +               pll5: pll5@01c20020 {
  70 +                       #clock-cells = <1>;
  71 +                       compatible = "allwinner,sun4i-pll5-clk";
  72 +                       reg = <0x01c20020 0x4>;
  73 +                       clocks = <&osc24M>;
  74 +                       clock-output-names = "pll5_ddr", "pll5_other";
  75 +               };
  76 +
  77 +               pll6: pll6@01c20028 {
  78 +                       #clock-cells = <1>;
  79 +                       compatible = "allwinner,sun4i-pll6-clk";
  80 +                       reg = <0x01c20028 0x4>;
  81 +                       clocks = <&osc24M>;
  82 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
  83 +               };
  84 +
  85                 /* dummy is 200M */
  86                 cpu: cpu@01c20054 {
  87                         #clock-cells = <0>;
  88 @@ -130,12 +146,11 @@
  89                                 "apb0_ir", "apb0_keypad";
  90                 };
  91
  92 -               /* dummy is pll62 */
  93                 apb1_mux: apb1_mux@01c20058 {
  94                         #clock-cells = <0>;
  95                         compatible = "allwinner,sun4i-apb1-mux-clk";
  96                         reg = <0x01c20058 0x4>;
  97 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
  98 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
  99                 };
 100
 101                 apb1: apb1@01c20058 {
 102 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
 103 index 8c4a9c3..cded3c7 100644
 104 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 105 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 106 @@ -74,6 +74,22 @@
 107                         clocks = <&osc24M>;
 108                 };
 109
 110 +               pll5: pll5@01c20020 {
 111 +                       #clock-cells = <1>;
 112 +                       compatible = "allwinner,sun4i-pll5-clk";
 113 +                       reg = <0x01c20020 0x4>;
 114 +                       clocks = <&osc24M>;
 115 +                       clock-output-names = "pll5_ddr", "pll5_other";
 116 +               };
 117 +
 118 +               pll6: pll6@01c20028 {
 119 +                       #clock-cells = <1>;
 120 +                       compatible = "allwinner,sun4i-pll6-clk";
 121 +                       reg = <0x01c20028 0x4>;
 122 +                       clocks = <&osc24M>;
 123 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
 124 +               };
 125 +
 126                 /* dummy is 200M */
 127                 cpu: cpu@01c20054 {
 128                         #clock-cells = <0>;
 129 @@ -132,12 +148,11 @@
 130                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
 131                 };
 132
 133 -               /* dummy is pll6 */
 134                 apb1_mux: apb1_mux@01c20058 {
 135                         #clock-cells = <0>;
 136                         compatible = "allwinner,sun4i-apb1-mux-clk";
 137                         reg = <0x01c20058 0x4>;
 138 -                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
 139 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 140                 };
 141
 142                 apb1: apb1@01c20058 {
 143 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
 144 index 21bf143..2e39ed9 100644
 145 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
 146 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
 147 @@ -69,23 +69,27 @@
 148                         clocks = <&osc24M>;
 149                 };
 150
 151 -               /*
 152 -                * This is a dummy clock, to be used as placeholder on
 153 -                * other mux clocks when a specific parent clock is not
 154 -                * yet implemented. It should be dropped when the driver
 155 -                * is complete.
 156 -                */
 157 -               pll6: pll6 {
 158 -                       #clock-cells = <0>;
 159 -                       compatible = "fixed-clock";
 160 -                       clock-frequency = <0>;
 161 +               pll5: pll5@01c20020 {
 162 +                       #clock-cells = <1>;
 163 +                       compatible = "allwinner,sun4i-pll5-clk";
 164 +                       reg = <0x01c20020 0x4>;
 165 +                       clocks = <&osc24M>;
 166 +                       clock-output-names = "pll5_ddr", "pll5_other";
 167 +               };
 168 +
 169 +               pll6: pll6@01c20028 {
 170 +                       #clock-cells = <1>;
 171 +                       compatible = "allwinner,sun4i-pll6-clk";
 172 +                       reg = <0x01c20028 0x4>;
 173 +                       clocks = <&osc24M>;
 174 +                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
 175                 };
 176
 177                 cpu: cpu@01c20054 {
 178                         #clock-cells = <0>;
 179                         compatible = "allwinner,sun4i-cpu-clk";
 180                         reg = <0x01c20054 0x4>;
 181 -                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
 182 +                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 183                 };
 184
 185                 axi: axi@01c20054 {
 186 @@ -144,7 +148,7 @@
 187                         #clock-cells = <0>;
 188                         compatible = "allwinner,sun4i-apb1-mux-clk";
 189                         reg = <0x01c20058 0x4>;
 190 -                       clocks = <&osc24M>, <&pll6>, <&osc32k>;
 191 +                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 192                 };
 193
 194                 apb1: apb1@01c20058 {
 195 --
 196 1.8.4
 197