target/linux/s3c24xx/patches-2.6.31/070-s3c24xx-time.patch

   1 From 730b77ed17f637237c16579ad9849b2a994b61a3 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Tue, 21 Jul 2009 12:50:43 +0200
   4 Subject: [PATCH] 070-s3c24xx-time.patch
   5
   6 ---
   7  arch/arm/plat-s3c24xx/time.c |  480 ++++++++++++++++++++++++++++++++++++++++++
   8  1 files changed, 480 insertions(+), 0 deletions(-)
   9  create mode 100644 arch/arm/plat-s3c24xx/time.c
  10
  11 diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
  12 new file mode 100644
  13 index 0000000..713a6bc
  14 --- /dev/null
  15 +++ b/arch/arm/plat-s3c24xx/time.c
  16 @@ -0,0 +1,480 @@
  17 +/* linux/arch/arm/plat-s3c24xx/time.c
  18 + *
  19 + * Copyright (C) 2003-2005 Simtec Electronics
  20 + *     Ben Dooks, <ben@simtec.co.uk>
  21 + *
  22 + * dyn_tick support by Andrzej Zaborowski based on omap_dyn_tick_timer.
  23 + *
  24 + * This program is free software; you can redistribute it and/or modify
  25 + * it under the terms of the GNU General Public License as published by
  26 + * the Free Software Foundation; either version 2 of the License, or
  27 + * (at your option) any later version.
  28 + *
  29 + * This program is distributed in the hope that it will be useful,
  30 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32 + * GNU General Public License for more details.
  33 + *
  34 + * You should have received a copy of the GNU General Public License
  35 + * along with this program; if not, write to the Free Software
  36 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  37 + */
  38 +
  39 +#include <linux/kernel.h>
  40 +#include <linux/sched.h>
  41 +#include <linux/init.h>
  42 +#include <linux/interrupt.h>
  43 +#include <linux/irq.h>
  44 +#include <linux/err.h>
  45 +#include <linux/clk.h>
  46 +
  47 +#include <asm/system.h>
  48 +#include <asm/leds.h>
  49 +#include <asm/mach-types.h>
  50 +
  51 +#include <asm/io.h>
  52 +#include <asm/irq.h>
  53 +#include <mach/map.h>
  54 +#include <asm/plat-s3c/regs-timer.h>
  55 +#include <mach/regs-irq.h>
  56 +#include <asm/mach/time.h>
  57 +
  58 +#include <asm/plat-s3c24xx/clock.h>
  59 +#include <asm/plat-s3c24xx/cpu.h>
  60 +
  61 +static unsigned long timer_startval;
  62 +static unsigned long timer_usec_ticks;
  63 +static struct work_struct resume_work;
  64 +
  65 +unsigned long pclk;
  66 +struct clk *clk;
  67 +
  68 +#define TIMER_USEC_SHIFT 16
  69 +
  70 +/* we use the shifted arithmetic to work out the ratio of timer ticks
  71 + * to usecs, as often the peripheral clock is not a nice even multiple
  72 + * of 1MHz.
  73 + *
  74 + * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
  75 + * for the current HZ value of 200 without producing overflows.
  76 + *
  77 + * Original patch by Dimitry Andric, updated by Ben Dooks
  78 +*/
  79 +
  80 +
  81 +/* timer_mask_usec_ticks
  82 + *
  83 + * given a clock and divisor, make the value to pass into timer_ticks_to_usec
  84 + * to scale the ticks into usecs
  85 +*/
  86 +
  87 +static inline unsigned long
  88 +timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
  89 +{
  90 +       unsigned long den = pclk / 1000;
  91 +
  92 +       return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
  93 +}
  94 +
  95 +/* timer_ticks_to_usec
  96 + *
  97 + * convert timer ticks to usec.
  98 +*/
  99 +
 100 +static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
 101 +{
 102 +       unsigned long res;
 103 +
 104 +       res = ticks * timer_usec_ticks;
 105 +       res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
 106 +
 107 +       return res >> TIMER_USEC_SHIFT;
 108 +}
 109 +
 110 +/***
 111 + * Returns microsecond  since last clock interrupt.  Note that interrupts
 112 + * will have been disabled by do_gettimeoffset()
 113 + * IRQs are disabled before entering here from do_gettimeofday()
 114 + */
 115 +
 116 +#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
 117 +
 118 +unsigned long s3c2410_gettimeoffset (void)
 119 +{
 120 +       unsigned long tdone;
 121 +       unsigned long irqpend;
 122 +       unsigned long tval;
 123 +
 124 +       /* work out how many ticks have gone since last timer interrupt */
 125 +
 126 +        tval =  __raw_readl(S3C2410_TCNTO(4));
 127 +       tdone = timer_startval - tval;
 128 +
 129 +       /* check to see if there is an interrupt pending */
 130 +
 131 +       irqpend = __raw_readl(S3C2410_SRCPND);
 132 +       if (irqpend & SRCPND_TIMER4) {
 133 +               /* re-read the timer, and try and fix up for the missed
 134 +                * interrupt. Note, the interrupt may go off before the
 135 +                * timer has re-loaded from wrapping.
 136 +                */
 137 +
 138 +               tval =  __raw_readl(S3C2410_TCNTO(4));
 139 +               tdone = timer_startval - tval;
 140 +
 141 +               if (tval != 0)
 142 +                       tdone += timer_startval;
 143 +       }
 144 +
 145 +       return timer_ticks_to_usec(tdone);
 146 +}
 147 +
 148 +
 149 +/*
 150 + * IRQ handler for the timer
 151 + */
 152 +static irqreturn_t
 153 +s3c2410_timer_interrupt(int irq, void *dev_id)
 154 +{
 155 +       timer_tick();
 156 +       return IRQ_HANDLED;
 157 +}
 158 +
 159 +static struct irqaction s3c2410_timer_irq = {
 160 +       .name           = "S3C2410 Timer Tick",
 161 +       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 162 +       .handler        = s3c2410_timer_interrupt,
 163 +};
 164 +
 165 +#define use_tclk1_12() ( \
 166 +       machine_is_bast()       || \
 167 +       machine_is_vr1000()     || \
 168 +       machine_is_anubis()     || \
 169 +       machine_is_osiris() )
 170 +
 171 +/*
 172 + * Set up timer interrupt, and return the current time in seconds.
 173 + *
 174 + * Currently we only use timer4, as it is the only timer which has no
 175 + * other function that can be exploited externally
 176 + */
 177 +static void s3c2410_timer_setup (void)
 178 +{
 179 +       unsigned long tcon;
 180 +       unsigned long tcnt;
 181 +       unsigned long tcfg1;
 182 +       unsigned long tcfg0;
 183 +
 184 +       tcnt = 0xffff;  /* default value for tcnt */
 185 +
 186 +       /* read the current timer configuration bits */
 187 +
 188 +       tcon = __raw_readl(S3C2410_TCON);
 189 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
 190 +       tcfg0 = __raw_readl(S3C2410_TCFG0);
 191 +
 192 +       /* configure the system for whichever machine is in use */
 193 +
 194 +       if (use_tclk1_12()) {
 195 +               /* timer is at 12MHz, scaler is 1 */
 196 +               timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
 197 +               tcnt = 12000000 / HZ;
 198 +
 199 +               tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
 200 +               tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
 201 +       } else {
 202 +               /* since values around 50 to
 203 +                * 70MHz are not values we can directly generate the timer
 204 +                * value from, we need to pre-scale and divide before using it.
 205 +                *
 206 +                * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
 207 +                * (8.45 ticks per usec)
 208 +                */
 209 +
 210 +               /* configure clock tick */
 211 +               timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
 212 +               printk("timer_usec_ticks = %lu\n", timer_usec_ticks);
 213 +
 214 +               tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
 215 +               tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
 216 +
 217 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
 218 +               tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
 219 +
 220 +               tcnt = (pclk / 6) / HZ;
 221 +       }
 222 +
 223 +       /* timers reload after counting zero, so reduce the count by 1 */
 224 +
 225 +       tcnt--;
 226 +
 227 +       printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
 228 +              tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
 229 +
 230 +       /* check to see if timer is within 16bit range... */
 231 +       if (tcnt > 0xffff) {
 232 +               panic("setup_timer: HZ is too small, cannot configure timer!");
 233 +               return;
 234 +       }
 235 +
 236 +       __raw_writel(tcfg1, S3C2410_TCFG1);
 237 +       __raw_writel(tcfg0, S3C2410_TCFG0);
 238 +
 239 +       timer_startval = tcnt;
 240 +       __raw_writel(tcnt, S3C2410_TCNTB(4));
 241 +
 242 +       /* ensure timer is stopped... */
 243 +
 244 +       tcon &= ~(7<<20);
 245 +       tcon |= S3C2410_TCON_T4RELOAD;
 246 +       tcon |= S3C2410_TCON_T4MANUALUPD;
 247 +
 248 +       __raw_writel(tcon, S3C2410_TCON);
 249 +       __raw_writel(tcnt, S3C2410_TCNTB(4));
 250 +       __raw_writel(tcnt, S3C2410_TCMPB(4));
 251 +
 252 +       /* start the timer running */
 253 +       tcon |= S3C2410_TCON_T4START;
 254 +       tcon &= ~S3C2410_TCON_T4MANUALUPD;
 255 +       __raw_writel(tcon, S3C2410_TCON);
 256 +
 257 +       __raw_writel(__raw_readl(S3C2410_INTMSK) & (~(1UL << 14)),
 258 +                    S3C2410_INTMSK);
 259 +
 260 +}
 261 +
 262 +struct sys_timer s3c24xx_timer;
 263 +static void timer_resume_work(struct work_struct *work)
 264 +{
 265 +       clk_enable(clk);
 266 +
 267 +#ifdef CONFIG_NO_IDLE_HZ
 268 +       if (s3c24xx_timer.dyn_tick->state & DYN_TICK_ENABLED)
 269 +               s3c24xx_timer.dyn_tick->enable();
 270 +       else
 271 +#endif
 272 +               s3c2410_timer_setup();
 273 +}
 274 +
 275 +static void __init s3c2410_timer_init (void)
 276 +{
 277 +       if (!use_tclk1_12()) {
 278 +               /* for the h1940 (and others), we use the pclk from the core
 279 +                * to generate the timer values.
 280 +                */
 281 +
 282 +               /* this is used as default if no other timer can be found */
 283 +               clk = clk_get(NULL, "timers");
 284 +               if (IS_ERR(clk))
 285 +                       panic("failed to get clock for system timer");
 286 +
 287 +               clk_enable(clk);
 288 +
 289 +               pclk = clk_get_rate(clk);
 290 +               printk("pclk = %lu\n", pclk);
 291 +       }
 292 +
 293 +       INIT_WORK(&resume_work, timer_resume_work);
 294 +       s3c2410_timer_setup();
 295 +       setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
 296 +}
 297 +
 298 +static void s3c2410_timer_resume_work(struct work_struct *work)
 299 +{
 300 +       s3c2410_timer_setup();
 301 +}
 302 +
 303 +static void s3c2410_timer_resume(void)
 304 +{
 305 +       static DECLARE_WORK(work, s3c2410_timer_resume_work);
 306 +       int res;
 307 +
 308 +       res = schedule_work(&work);
 309 +       if (!res)
 310 +               printk(KERN_ERR
 311 +                   "s3c2410_timer_resume_work already queued ???\n");
 312 +}
 313 +
 314 +#ifdef CONFIG_NO_IDLE_HZ
 315 +/*
 316 + * We'll set a constant prescaler so we don't have to bother setting it
 317 + * when reprogramming and so that we avoid costly divisions.
 318 + *
 319 + * (2 * HZ) << INPUT_FREQ_SHIFT is the desired frequency after prescaler.
 320 + * At HZ == 200, HZ * 1024 should work for PCLKs of up to ~53.5 MHz.
 321 + */
 322 +#define INPUT_FREQ_SHIFT       9
 323 +
 324 +static int ticks_last;
 325 +static int ticks_left;
 326 +static uint32_t tcnto_last;
 327 +
 328 +static inline int s3c24xx_timer_read(void)
 329 +{
 330 +       uint32_t tcnto = __raw_readl(S3C2410_TCNTO(4));
 331 +
 332 +       /*
 333 +        * WARNING: sometimes we get called before TCNTB has been
 334 +        * loaded into the counter and TCNTO then returns its previous
 335 +        * value and kill us, so don't do anything before counter is
 336 +        * reloaded.
 337 +        */
 338 +       if (unlikely(tcnto == tcnto_last))
 339 +               return ticks_last;
 340 +
 341 +       tcnto_last = -1;
 342 +       return tcnto <<
 343 +               ((__raw_readl(S3C2410_TCFG1) >> S3C2410_TCFG1_MUX4_SHIFT) & 3);
 344 +}
 345 +
 346 +static inline void s3c24xx_timer_program(int ticks)
 347 +{
 348 +       uint32_t tcon = __raw_readl(S3C2410_TCON) & ~(7 << 20);
 349 +       uint32_t tcfg1 = __raw_readl(S3C2410_TCFG1) & ~S3C2410_TCFG1_MUX4_MASK;
 350 +
 351 +       /* Just make sure the timer is stopped.  */
 352 +       __raw_writel(tcon, S3C2410_TCON);
 353 +
 354 +       /* TODO: add likely()ies / unlikely()ies */
 355 +       if (ticks >> 18) {
 356 +               ticks_last = min(ticks, 0xffff << 3);
 357 +               ticks_left = ticks - ticks_last;
 358 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV16, S3C2410_TCFG1);
 359 +               __raw_writel(ticks_last >> 3, S3C2410_TCNTB(4));
 360 +       } else if (ticks >> 17) {
 361 +               ticks_last = ticks;
 362 +               ticks_left = 0;
 363 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV8, S3C2410_TCFG1);
 364 +               __raw_writel(ticks_last >> 2, S3C2410_TCNTB(4));
 365 +       } else if (ticks >> 16) {
 366 +               ticks_last = ticks;
 367 +               ticks_left = 0;
 368 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV4, S3C2410_TCFG1);
 369 +               __raw_writel(ticks_last >> 1, S3C2410_TCNTB(4));
 370 +       } else {
 371 +               ticks_last = ticks;
 372 +               ticks_left = 0;
 373 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV2, S3C2410_TCFG1);
 374 +               __raw_writel(ticks_last >> 0, S3C2410_TCNTB(4));
 375 +       }
 376 +
 377 +       tcnto_last = __raw_readl(S3C2410_TCNTO(4));
 378 +       __raw_writel(tcon | S3C2410_TCON_T4MANUALUPD,
 379 +                       S3C2410_TCON);
 380 +       __raw_writel(tcon | S3C2410_TCON_T4START,
 381 +                       S3C2410_TCON);
 382 +}
 383 +
 384 +/*
 385 + * If we have already waited all the time we were supposed to wait,
 386 + * kick the timer, setting the longest allowed timeout value just
 387 + * for time-keeping.
 388 + */
 389 +static inline void s3c24xx_timer_program_idle(void)
 390 +{
 391 +       s3c24xx_timer_program(0xffff << 3);
 392 +}
 393 +
 394 +static inline void s3c24xx_timer_update(int restart)
 395 +{
 396 +       int ticks_cur = s3c24xx_timer_read();
 397 +       int jiffies_elapsed = (ticks_last - ticks_cur) >> INPUT_FREQ_SHIFT;
 398 +       int subjiffy = ticks_last - (jiffies_elapsed << INPUT_FREQ_SHIFT);
 399 +
 400 +       if (restart) {
 401 +               if (ticks_left >= (1 << INPUT_FREQ_SHIFT))
 402 +                       s3c24xx_timer_program(ticks_left);
 403 +               else
 404 +                       s3c24xx_timer_program_idle();
 405 +               ticks_last += subjiffy;
 406 +       } else
 407 +               ticks_last = subjiffy;
 408 +
 409 +       while (jiffies_elapsed --)
 410 +               timer_tick();
 411 +}
 412 +
 413 +/* Called when the timer expires.  */
 414 +static irqreturn_t s3c24xx_timer_handler(int irq, void *dev_id)
 415 +{
 416 +       tcnto_last = -1;
 417 +       s3c24xx_timer_update(1);
 418 +
 419 +       return IRQ_HANDLED;
 420 +}
 421 +
 422 +/* Called to update jiffies with time elapsed.  */
 423 +static irqreturn_t s3c24xx_timer_handler_dyn_tick(int irq, void *dev_id)
 424 +{
 425 +       s3c24xx_timer_update(0);
 426 +
 427 +       return IRQ_HANDLED;
 428 +}
 429 +
 430 +/*
 431 + * Programs the next timer interrupt needed.  Called when dynamic tick is
 432 + * enabled, and to reprogram the ticks to skip from pm_idle.  The CPU goes
 433 + * to sleep directly after this.
 434 + */
 435 +static void s3c24xx_timer_reprogram_dyn_tick(unsigned long next_jiffies)
 436 +{
 437 +       int subjiffy_left = ticks_last - s3c24xx_timer_read();
 438 +
 439 +       s3c24xx_timer_program(max((int) next_jiffies, 1) << INPUT_FREQ_SHIFT);
 440 +       ticks_last += subjiffy_left;
 441 +}
 442 +
 443 +static unsigned long s3c24xx_timer_offset_dyn_tick(void)
 444 +{
 445 +       /* TODO */
 446 +       return 0;
 447 +}
 448 +
 449 +static int s3c24xx_timer_enable_dyn_tick(void)
 450 +{
 451 +       /* Set our constant prescaler.  */
 452 +       uint32_t tcfg0 = __raw_readl(S3C2410_TCFG0);
 453 +       int prescaler =
 454 +               max(min(256, (int) pclk / (HZ << (INPUT_FREQ_SHIFT + 1))), 1);
 455 +
 456 +       tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
 457 +       tcfg0 |= (prescaler - 1) << S3C2410_TCFG_PRESCALER1_SHIFT;
 458 +       __raw_writel(tcfg0, S3C2410_TCFG0);
 459 +
 460 +       /* Override handlers.  */
 461 +       s3c2410_timer_irq.handler = s3c24xx_timer_handler;
 462 +       s3c24xx_timer.offset = s3c24xx_timer_offset_dyn_tick;
 463 +
 464 +       printk(KERN_INFO "dyn_tick enabled on s3c24xx timer 4, "
 465 +                       "%li Hz pclk with prescaler %i\n", pclk, prescaler);
 466 +
 467 +       s3c24xx_timer_program_idle();
 468 +
 469 +       return 0;
 470 +}
 471 +
 472 +static int s3c24xx_timer_disable_dyn_tick(void)
 473 +{
 474 +       s3c2410_timer_irq.handler = s3c2410_timer_interrupt;
 475 +       s3c24xx_timer.offset = s3c2410_gettimeoffset;
 476 +       s3c2410_timer_setup();
 477 +
 478 +       return 0;
 479 +}
 480 +
 481 +static struct dyn_tick_timer s3c24xx_dyn_tick_timer = {
 482 +       .enable         = s3c24xx_timer_enable_dyn_tick,
 483 +       .disable        = s3c24xx_timer_disable_dyn_tick,
 484 +       .reprogram      = s3c24xx_timer_reprogram_dyn_tick,
 485 +       .handler        = s3c24xx_timer_handler_dyn_tick,
 486 +};
 487 +#endif /* CONFIG_NO_IDLE_HZ */
 488 +
 489 +struct sys_timer s3c24xx_timer = {
 490 +       .init           = s3c2410_timer_init,
 491 +       .offset         = s3c2410_gettimeoffset,
 492 +       .resume         = s3c2410_timer_resume,
 493 +#ifdef CONFIG_NO_IDLE_HZ
 494 +       .dyn_tick       = &s3c24xx_dyn_tick_timer,
 495 +#endif
 496 +};
 497 --
 498 1.5.6.5
 499