2 * HDQ generic GPIO bitbang driver using FIQ
4 * (C) 2006-2007 by Openmoko, Inc.
5 * Author: Andy Green <andy@openmoko.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/hdq.h>
21 #define HDQ_WRITE 0x80
23 enum hdq_bitbang_states {
26 HDQB_TX_BREAK_RECOVERY,
36 static struct hdq_priv {
37 u8 hdq_probed; /* nonzero after HDQ driver probed */
38 struct mutex hdq_lock; /* if you want to use hdq, you have to take lock */
39 unsigned long hdq_gpio_pin; /* GTA02 = GPD14 which pin to meddle with */
40 u8 hdq_ads; /* b7..b6 = register address, b0 = r/w */
41 u8 hdq_tx_data; /* data to tx for write action */
42 u8 hdq_rx_data; /* data received in read action */
43 u8 hdq_request_ctr; /* incremented by "user" to request a transfer */
44 u8 hdq_transaction_ctr; /* incremented after each transfer */
45 u8 hdq_error; /* 0 = no error */
51 enum hdq_bitbang_states hdq_state;
54 struct hdq_platform_data *pdata;
58 static void hdq_bad(void)
60 if (!hdq_priv.reported_error)
61 printk(KERN_ERR "HDQ error: %d\n", hdq_priv.hdq_error);
62 hdq_priv.reported_error = 1;
65 static void hdq_good(void)
67 if (hdq_priv.reported_error)
68 printk(KERN_INFO "HDQ responds again\n");
69 hdq_priv.reported_error = 0;
72 int hdq_fiq_handler(void)
74 if (!hdq_priv.hdq_probed)
77 switch (hdq_priv.hdq_state) {
79 if (hdq_priv.hdq_request_ctr == hdq_priv.hdq_transaction_ctr)
81 hdq_priv.hdq_ctr = 250 / HDQ_SAMPLE_PERIOD_US;
82 hdq_priv.pdata->gpio_set(0);
83 hdq_priv.pdata->gpio_dir_out();
84 hdq_priv.hdq_tx_data_done = 0;
85 hdq_priv.hdq_state = HDQB_TX_BREAK;
88 case HDQB_TX_BREAK: /* issue low for > 190us */
89 if (--hdq_priv.hdq_ctr == 0) {
90 hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
91 hdq_priv.hdq_state = HDQB_TX_BREAK_RECOVERY;
92 hdq_priv.pdata->gpio_set(1);
96 case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */
97 if (--hdq_priv.hdq_ctr)
99 hdq_priv.hdq_shifter = hdq_priv.hdq_ads;
100 hdq_priv.hdq_bit = 8; /* 8 bits of ads / rw */
101 hdq_priv.hdq_tx_data_done = 0; /* doing ads */
102 /* fallthru on last one */
104 if (hdq_priv.hdq_shifter & 1)
105 hdq_priv.hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US;
107 hdq_priv.hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US;
108 /* carefully precompute the other phase length */
109 hdq_priv.hdq_ctr2 = (210 - (hdq_priv.hdq_ctr * HDQ_SAMPLE_PERIOD_US)) /
110 HDQ_SAMPLE_PERIOD_US;
111 hdq_priv.hdq_state = HDQB_ADS_LOW;
112 hdq_priv.hdq_shifter >>= 1;
114 hdq_priv.pdata->gpio_set(0);
118 if (--hdq_priv.hdq_ctr)
120 hdq_priv.pdata->gpio_set(1);
121 hdq_priv.hdq_state = HDQB_ADS_HIGH;
125 if (--hdq_priv.hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */
127 if (hdq_priv.hdq_bit) { /* more bits to do */
128 hdq_priv.hdq_state = HDQB_ADS_CALC;
131 /* no more bits, wait it out until hdq_priv.hdq_ctr2 exhausted */
132 if (hdq_priv.hdq_ctr2)
134 /* ok no more bits and very last state */
135 hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
137 if (hdq_priv.hdq_ads & 0x80) { /* write the byte out */
138 /* set delay before payload */
139 hdq_priv.hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
140 /* already high, no need to write */
141 hdq_priv.hdq_state = HDQB_WAIT_TX;
144 /* read the next byte */
145 hdq_priv.hdq_bit = 8; /* 8 bits of data */
146 hdq_priv.hdq_ctr = 2500 / HDQ_SAMPLE_PERIOD_US;
147 hdq_priv.hdq_state = HDQB_WAIT_RX;
148 hdq_priv.pdata->gpio_dir_in();
151 case HDQB_WAIT_TX: /* issue low for > 40us */
152 if (--hdq_priv.hdq_ctr)
154 if (!hdq_priv.hdq_tx_data_done) { /* was that the data sent? */
155 hdq_priv.hdq_tx_data_done++;
156 hdq_priv.hdq_shifter = hdq_priv.hdq_tx_data;
157 hdq_priv.hdq_bit = 8; /* 8 bits of data */
158 hdq_priv.hdq_state = HDQB_ADS_CALC; /* start sending */
161 hdq_priv.hdq_error = 0;
162 hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
163 hdq_priv.hdq_state = HDQB_IDLE; /* all tx is done */
164 /* idle in input mode, it's pulled up by 10K */
165 hdq_priv.pdata->gpio_dir_in();
168 case HDQB_WAIT_RX: /* wait for battery to talk to us */
169 if (hdq_priv.pdata->gpio_get() == 0) {
170 /* it talks to us! */
171 hdq_priv.hdq_ctr2 = 1;
172 hdq_priv.hdq_bit = 8; /* 8 bits of data */
174 hdq_priv.hdq_ctr = 500 / HDQ_SAMPLE_PERIOD_US;
175 hdq_priv.hdq_state = HDQB_DATA_RX_LOW;
178 if (--hdq_priv.hdq_ctr == 0) { /* timed out, error */
179 hdq_priv.hdq_error = 1;
180 hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
181 hdq_priv.hdq_state = HDQB_IDLE; /* abort */
186 * HDQ basically works by measuring the low time of the bit cell
187 * 32-50us --> '1', 80 - 145us --> '0'
190 case HDQB_DATA_RX_LOW:
191 if (hdq_priv.pdata->gpio_get()) {
192 hdq_priv.hdq_rx_data >>= 1;
193 if (hdq_priv.hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US))
194 hdq_priv.hdq_rx_data |= 0x80;
196 if (--hdq_priv.hdq_bit == 0) {
197 hdq_priv.hdq_error = 0;
198 hdq_priv.hdq_transaction_ctr =
199 hdq_priv.hdq_request_ctr;
201 hdq_priv.hdq_state = HDQB_IDLE;
203 hdq_priv.hdq_state = HDQB_DATA_RX_HIGH;
205 hdq_priv.hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US;
206 hdq_priv.hdq_ctr2 = 1;
210 if (--hdq_priv.hdq_ctr)
212 /* timed out, error */
213 hdq_priv.hdq_error = 2;
214 hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
215 hdq_priv.hdq_state = HDQB_IDLE; /* abort */
218 case HDQB_DATA_RX_HIGH:
219 if (!hdq_priv.pdata->gpio_get()) {
220 /* it talks to us! */
221 hdq_priv.hdq_ctr2 = 1;
223 hdq_priv.hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US;
224 hdq_priv.hdq_state = HDQB_DATA_RX_LOW;
227 if (--hdq_priv.hdq_ctr)
229 /* timed out, error */
230 hdq_priv.hdq_error = 3;
231 hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
233 /* we're in input mode already */
234 hdq_priv.hdq_state = HDQB_IDLE; /* abort */
238 /* Are we interested in keeping the FIQ source alive ? */
239 if (hdq_priv.hdq_state != HDQB_IDLE)
244 static int fiq_busy(void)
246 int request = (volatile u8)hdq_priv.hdq_request_ctr;
247 int transact = (volatile u8)hdq_priv.hdq_transaction_ctr;
250 return (request != transact);
253 int hdq_initialized(void)
255 return hdq_priv.hdq_probed;
257 EXPORT_SYMBOL_GPL(hdq_initialized);
259 int hdq_read(int address)
261 int count_sleeps = 5;
264 if (!hdq_priv.hdq_probed)
267 mutex_lock(&hdq_priv.hdq_lock);
269 hdq_priv.hdq_error = 0;
270 hdq_priv.hdq_ads = address | HDQ_READ;
271 hdq_priv.hdq_request_ctr++;
272 hdq_priv.pdata->kick_fiq();
274 * FIQ takes care of it while we block our calling process
275 * But we're not spinning -- other processes run normally while
276 * we wait for the result
278 while (count_sleeps--) {
279 msleep(10); /* valid transaction always completes in < 10ms */
284 if (hdq_priv.hdq_error) {
286 goto done; /* didn't see a response in good time */
290 ret = hdq_priv.hdq_rx_data;
295 mutex_unlock(&hdq_priv.hdq_lock);
298 EXPORT_SYMBOL_GPL(hdq_read);
300 int hdq_write(int address, u8 data)
302 int count_sleeps = 5;
305 if (!hdq_priv.hdq_probed)
308 mutex_lock(&hdq_priv.hdq_lock);
310 hdq_priv.hdq_error = 0;
311 hdq_priv.hdq_ads = address | HDQ_WRITE;
312 hdq_priv.hdq_tx_data = data;
313 hdq_priv.hdq_request_ctr++;
314 hdq_priv.pdata->kick_fiq();
316 * FIQ takes care of it while we block our calling process
317 * But we're not spinning -- other processes run normally while
318 * we wait for the result
320 while (count_sleeps--) {
321 msleep(10); /* valid transaction always completes in < 10ms */
324 continue; /* something bad with FIQ */
326 if (hdq_priv.hdq_error) {
328 goto done; /* didn't see a response in good time */
337 mutex_unlock(&hdq_priv.hdq_lock);
340 EXPORT_SYMBOL_GPL(hdq_write);
344 static ssize_t hdq_sysfs_dump(struct device *dev, struct device_attribute *attr,
349 u8 u8a[128]; /* whole address space for HDQ */
352 if (!hdq_priv.hdq_probed)
355 /* the dump does not take care about 16 bit regs, because at this
356 * bus level we don't know about the chip details
358 for (n = 0; n < sizeof(u8a); n++) {
365 for (n = 0; n < sizeof(u8a); n += 16) {
366 hex_dump_to_buffer(u8a + n, sizeof(u8a), 16, 1, end, 4096, 0);
374 return sprintf(buf, "ERROR %d\n", v);
377 /* you write by <address> <data>, eg, "34 128" */
379 #define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
381 static ssize_t hdq_sysfs_write(struct device *dev,
382 struct device_attribute *attr,
383 const char *buf, size_t count)
385 const char *end = buf + count;
386 int address = atoi(buf);
388 if (!hdq_priv.hdq_probed)
391 while ((buf != end) && (*buf != ' '))
395 while ((buf < end) && (*buf == ' '))
400 hdq_write(address, atoi(buf));
405 static DEVICE_ATTR(dump, 0400, hdq_sysfs_dump, NULL);
406 static DEVICE_ATTR(write, 0600, NULL, hdq_sysfs_write);
408 static struct attribute *hdq_sysfs_entries[] = {
410 &dev_attr_write.attr,
414 static struct attribute_group hdq_attr_group = {
416 .attrs = hdq_sysfs_entries,
421 static int hdq_suspend(struct platform_device *pdev, pm_message_t state)
423 /* after 18s of this, the battery monitor will also go to sleep */
424 hdq_priv.pdata->gpio_dir_in();
425 hdq_priv.pdata->disable_fiq();
429 static int hdq_resume(struct platform_device *pdev)
431 hdq_priv.pdata->gpio_set(1);
432 hdq_priv.pdata->gpio_dir_out();
433 hdq_priv.pdata->enable_fiq();
438 static int __init hdq_probe(struct platform_device *pdev)
440 struct resource *r = platform_get_resource(pdev, 0, 0);
442 struct hdq_platform_data *pdata = pdev->dev.platform_data;
447 platform_set_drvdata(pdev, NULL);
449 mutex_init(&hdq_priv.hdq_lock);
451 /* set our HDQ comms pin from the platform data */
452 hdq_priv.hdq_gpio_pin = r->start;
453 hdq_priv.pdata = pdata;
455 hdq_priv.pdata->gpio_set(1);
456 hdq_priv.pdata->gpio_dir_out();
459 if (hdq_priv.pdata->enable_fiq() < 0) {
460 dev_err(&pdev->dev, "Could not enable FIQ source\n");
464 ret = sysfs_create_group(&pdev->dev.kobj, &hdq_attr_group);
468 hdq_priv.hdq_probed = 1; /* we are ready to do stuff now */
471 * if wanted, users can defer registration of devices
472 * that depend on HDQ until after we register, and can use our
473 * device as parent so suspend-resume ordering is correct
475 if (pdata->attach_child_devices)
476 (pdata->attach_child_devices)(&pdev->dev);
478 hdq_priv.pdata = pdata;
483 static int hdq_remove(struct platform_device *pdev)
485 sysfs_remove_group(&pdev->dev.kobj, &hdq_attr_group);
489 static struct platform_driver hdq_driver = {
491 .remove = hdq_remove,
493 .suspend = hdq_suspend,
494 .resume = hdq_resume,
501 static int __init hdq_init(void)
503 return platform_driver_register(&hdq_driver);
506 static void __exit hdq_exit(void)
508 platform_driver_unregister(&hdq_driver);
511 module_init(hdq_init);
512 module_exit(hdq_exit);
514 MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
515 MODULE_DESCRIPTION("HDQ driver");