target/linux/s3c24xx/files-2.6.31/drivers/mfd/glamo/glamo-regs.h

   1 #ifndef _GLAMO_REGS_H
   2 #define _GLAMO_REGS_H
   3
   4 /* Smedia Glamo 336x/337x driver
   5  *
   6  * (C) 2007 by Openmoko, Inc.
   7  * Author: Harald Welte <laforge@openmoko.org>
   8  * All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 enum glamo_regster_offsets {
  27         GLAMO_REGOFS_GENERIC    = 0x0000,
  28         GLAMO_REGOFS_HOSTBUS    = 0x0200,
  29         GLAMO_REGOFS_MEMORY     = 0x0300,
  30         GLAMO_REGOFS_VIDCAP     = 0x0400,
  31         GLAMO_REGOFS_ISP        = 0x0500,
  32         GLAMO_REGOFS_JPEG       = 0x0800,
  33         GLAMO_REGOFS_MPEG       = 0x0c00,
  34         GLAMO_REGOFS_LCD        = 0x1100,
  35         GLAMO_REGOFS_MMC        = 0x1400,
  36         GLAMO_REGOFS_MPROC0     = 0x1500,
  37         GLAMO_REGOFS_MPROC1     = 0x1580,
  38         GLAMO_REGOFS_CMDQUEUE   = 0x1600,
  39         GLAMO_REGOFS_RISC       = 0x1680,
  40         GLAMO_REGOFS_2D         = 0x1700,
  41         GLAMO_REGOFS_3D         = 0x1b00,
  42         GLAMO_REGOFS_END        = 0x2400,
  43 };
  44
  45
  46 enum glamo_register_generic {
  47         GLAMO_REG_GCONF1        = 0x0000,
  48         GLAMO_REG_GCONF2        = 0x0002,
  49 #define GLAMO_REG_DEVICE_ID     GLAMO_REG_GCONF2
  50         GLAMO_REG_GCONF3        = 0x0004,
  51 #define GLAMO_REG_REVISION_ID   GLAMO_REG_GCONF3
  52         GLAMO_REG_IRQ_GEN1      = 0x0006,
  53 #define GLAMO_REG_IRQ_ENABLE    GLAMO_REG_IRQ_GEN1
  54         GLAMO_REG_IRQ_GEN2      = 0x0008,
  55 #define GLAMO_REG_IRQ_SET       GLAMO_REG_IRQ_GEN2
  56         GLAMO_REG_IRQ_GEN3      = 0x000a,
  57 #define GLAMO_REG_IRQ_CLEAR     GLAMO_REG_IRQ_GEN3
  58         GLAMO_REG_IRQ_GEN4      = 0x000c,
  59 #define GLAMO_REG_IRQ_STATUS    GLAMO_REG_IRQ_GEN4
  60         GLAMO_REG_CLOCK_HOST    = 0x0010,
  61         GLAMO_REG_CLOCK_MEMORY  = 0x0012,
  62         GLAMO_REG_CLOCK_LCD     = 0x0014,
  63         GLAMO_REG_CLOCK_MMC     = 0x0016,
  64         GLAMO_REG_CLOCK_ISP     = 0x0018,
  65         GLAMO_REG_CLOCK_JPEG    = 0x001a,
  66         GLAMO_REG_CLOCK_3D      = 0x001c,
  67         GLAMO_REG_CLOCK_2D      = 0x001e,
  68         GLAMO_REG_CLOCK_RISC1   = 0x0020,       /* 3365 only? */
  69         GLAMO_REG_CLOCK_RISC2   = 0x0022,       /* 3365 only? */
  70         GLAMO_REG_CLOCK_MPEG    = 0x0024,
  71         GLAMO_REG_CLOCK_MPROC   = 0x0026,
  72
  73         GLAMO_REG_CLOCK_GEN5_1  = 0x0030,
  74         GLAMO_REG_CLOCK_GEN5_2  = 0x0032,
  75         GLAMO_REG_CLOCK_GEN6    = 0x0034,
  76         GLAMO_REG_CLOCK_GEN7    = 0x0036,
  77         GLAMO_REG_CLOCK_GEN8    = 0x0038,
  78         GLAMO_REG_CLOCK_GEN9    = 0x003a,
  79         GLAMO_REG_CLOCK_GEN10   = 0x003c,
  80         GLAMO_REG_CLOCK_GEN11   = 0x003e,
  81         GLAMO_REG_PLL_GEN1      = 0x0040,
  82         GLAMO_REG_PLL_GEN2      = 0x0042,
  83         GLAMO_REG_PLL_GEN3      = 0x0044,
  84         GLAMO_REG_PLL_GEN4      = 0x0046,
  85         GLAMO_REG_PLL_GEN5      = 0x0048,
  86         GLAMO_REG_GPIO_GEN1     = 0x0050,
  87         GLAMO_REG_GPIO_GEN2     = 0x0052,
  88         GLAMO_REG_GPIO_GEN3     = 0x0054,
  89         GLAMO_REG_GPIO_GEN4     = 0x0056,
  90         GLAMO_REG_GPIO_GEN5     = 0x0058,
  91         GLAMO_REG_GPIO_GEN6     = 0x005a,
  92         GLAMO_REG_GPIO_GEN7     = 0x005c,
  93         GLAMO_REG_GPIO_GEN8     = 0x005e,
  94         GLAMO_REG_GPIO_GEN9     = 0x0060,
  95         GLAMO_REG_GPIO_GEN10    = 0x0062,
  96         GLAMO_REG_DFT_GEN1      = 0x0070,
  97         GLAMO_REG_DFT_GEN2      = 0x0072,
  98         GLAMO_REG_DFT_GEN3      = 0x0074,
  99         GLAMO_REG_DFT_GEN4      = 0x0076,
 100
 101         GLAMO_REG_DFT_GEN5      = 0x01e0,
 102         GLAMO_REG_DFT_GEN6      = 0x01f0,
 103 };
 104
 105 #define GLAMO_REG_HOSTBUS(x)    (GLAMO_REGOFS_HOSTBUS-2+(x*2))
 106
 107 #define REG_MEM(x)              (GLAMO_REGOFS_MEMORY+(x))
 108 #define GLAMO_REG_MEM_TIMING(x) (GLAMO_REG_MEM_TIMING1-2+(x*2))
 109
 110 enum glamo_register_mem {
 111         GLAMO_REG_MEM_TYPE      = REG_MEM(0x00),
 112         GLAMO_REG_MEM_GEN       = REG_MEM(0x02),
 113         GLAMO_REG_MEM_TIMING1   = REG_MEM(0x04),
 114         GLAMO_REG_MEM_TIMING2   = REG_MEM(0x06),
 115         GLAMO_REG_MEM_TIMING3   = REG_MEM(0x08),
 116         GLAMO_REG_MEM_TIMING4   = REG_MEM(0x0a),
 117         GLAMO_REG_MEM_TIMING5   = REG_MEM(0x0c),
 118         GLAMO_REG_MEM_TIMING6   = REG_MEM(0x0e),
 119         GLAMO_REG_MEM_TIMING7   = REG_MEM(0x10),
 120         GLAMO_REG_MEM_TIMING8   = REG_MEM(0x12),
 121         GLAMO_REG_MEM_TIMING9   = REG_MEM(0x14),
 122         GLAMO_REG_MEM_TIMING10  = REG_MEM(0x16),
 123         GLAMO_REG_MEM_TIMING11  = REG_MEM(0x18),
 124         GLAMO_REG_MEM_POWER1    = REG_MEM(0x1a),
 125         GLAMO_REG_MEM_POWER2    = REG_MEM(0x1c),
 126         GLAMO_REG_MEM_LCD_BUF1  = REG_MEM(0x1e),
 127         GLAMO_REG_MEM_LCD_BUF2  = REG_MEM(0x20),
 128         GLAMO_REG_MEM_LCD_BUF3  = REG_MEM(0x22),
 129         GLAMO_REG_MEM_LCD_BUF4  = REG_MEM(0x24),
 130         GLAMO_REG_MEM_BIST1     = REG_MEM(0x26),
 131         GLAMO_REG_MEM_BIST2     = REG_MEM(0x28),
 132         GLAMO_REG_MEM_BIST3     = REG_MEM(0x2a),
 133         GLAMO_REG_MEM_BIST4     = REG_MEM(0x2c),
 134         GLAMO_REG_MEM_BIST5     = REG_MEM(0x2e),
 135         GLAMO_REG_MEM_MAH1      = REG_MEM(0x30),
 136         GLAMO_REG_MEM_MAH2      = REG_MEM(0x32),
 137         GLAMO_REG_MEM_DRAM1     = REG_MEM(0x34),
 138         GLAMO_REG_MEM_DRAM2     = REG_MEM(0x36),
 139         GLAMO_REG_MEM_CRC       = REG_MEM(0x38),
 140 };
 141
 142 #define GLAMO_MEM_TYPE_MASK     0x03
 143
 144 enum glamo_reg_mem_dram1 {
 145         /* b0 - b10 == refresh period, 1 -> 2048 clocks */
 146         GLAMO_MEM_DRAM1_EN_GATE_CLK     = (1 << 11),
 147         GLAMO_MEM_DRAM1_SELF_REFRESH    = (1 << 12),
 148         GLAMO_MEM_DRAM1_EN_GATE_CKE     = (1 << 13),
 149         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH = (1 << 14),
 150         GLAMO_MEM_DRAM1_EN_MODEREG_SET  = (1 << 15),
 151 };
 152
 153 enum glamo_reg_mem_dram2 {
 154         GLAMO_MEM_DRAM2_DEEP_PWRDOWN    = (1 << 12),
 155 };
 156
 157 enum glamo_irq_index {
 158         GLAMO_IRQIDX_HOSTBUS    = 0,
 159         GLAMO_IRQIDX_JPEG       = 1,
 160         GLAMO_IRQIDX_MPEG       = 2,
 161         GLAMO_IRQIDX_MPROC1     = 3,
 162         GLAMO_IRQIDX_MPROC0     = 4,
 163         GLAMO_IRQIDX_CMDQUEUE   = 5,
 164         GLAMO_IRQIDX_2D         = 6,
 165         GLAMO_IRQIDX_MMC        = 7,
 166         GLAMO_IRQIDX_RISC       = 8,
 167 };
 168
 169 enum glamo_irq {
 170         GLAMO_IRQ_HOSTBUS       = (1 << GLAMO_IRQIDX_HOSTBUS),
 171         GLAMO_IRQ_JPEG          = (1 << GLAMO_IRQIDX_JPEG),
 172         GLAMO_IRQ_MPEG          = (1 << GLAMO_IRQIDX_MPEG),
 173         GLAMO_IRQ_MPROC1        = (1 << GLAMO_IRQIDX_MPROC1),
 174         GLAMO_IRQ_MPROC0        = (1 << GLAMO_IRQIDX_MPROC0),
 175         GLAMO_IRQ_CMDQUEUE      = (1 << GLAMO_IRQIDX_CMDQUEUE),
 176         GLAMO_IRQ_2D            = (1 << GLAMO_IRQIDX_2D),
 177         GLAMO_IRQ_MMC           = (1 << GLAMO_IRQIDX_MMC),
 178         GLAMO_IRQ_RISC          = (1 << GLAMO_IRQIDX_RISC),
 179 };
 180
 181 enum glamo_reg_clock_host {
 182         GLAMO_CLOCK_HOST_DG_BCLK        = 0x0001,
 183         GLAMO_CLOCK_HOST_DG_M0CLK       = 0x0004,
 184         GLAMO_CLOCK_HOST_RESET          = 0x1000,
 185 };
 186
 187 enum glamo_reg_clock_mem {
 188         GLAMO_CLOCK_MEM_DG_M1CLK        = 0x0001,
 189         GLAMO_CLOCK_MEM_EN_M1CLK        = 0x0002,
 190         GLAMO_CLOCK_MEM_DG_MOCACLK      = 0x0004,
 191         GLAMO_CLOCK_MEM_EN_MOCACLK      = 0x0008,
 192         GLAMO_CLOCK_MEM_RESET           = 0x1000,
 193         GLAMO_CLOCK_MOCA_RESET          = 0x2000,
 194 };
 195
 196 enum glamo_reg_clock_lcd {
 197         GLAMO_CLOCK_LCD_DG_DCLK         = 0x0001,
 198         GLAMO_CLOCK_LCD_EN_DCLK         = 0x0002,
 199         GLAMO_CLOCK_LCD_DG_DMCLK        = 0x0004,
 200         GLAMO_CLOCK_LCD_EN_DMCLK        = 0x0008,
 201         //
 202         GLAMO_CLOCK_LCD_EN_DHCLK        = 0x0020,
 203         GLAMO_CLOCK_LCD_DG_M5CLK        = 0x0040,
 204         GLAMO_CLOCK_LCD_EN_M5CLK        = 0x0080,
 205         GLAMO_CLOCK_LCD_RESET           = 0x1000,
 206 };
 207
 208 enum glamo_reg_clock_mmc {
 209         GLAMO_CLOCK_MMC_DG_TCLK         = 0x0001,
 210         GLAMO_CLOCK_MMC_EN_TCLK         = 0x0002,
 211         GLAMO_CLOCK_MMC_DG_M9CLK        = 0x0004,
 212         GLAMO_CLOCK_MMC_EN_M9CLK        = 0x0008,
 213         GLAMO_CLOCK_MMC_RESET           = 0x1000,
 214 };
 215
 216 enum glamo_reg_basic_mmc {
 217         /* set to disable CRC error rejection */
 218         GLAMO_BASIC_MMC_DISABLE_CRC     = 0x0001,
 219         /* enable completion interrupt */
 220         GLAMO_BASIC_MMC_EN_COMPL_INT    = 0x0002,
 221         /* stop MMC clock while enforced idle waiting for data from card */
 222         GLAMO_BASIC_MMC_NO_CLK_RD_WAIT  = 0x0004,
 223         /* 0 = 1-bit bus to card, 1 = use 4-bit bus (has to be negotiated) */
 224         GLAMO_BASIC_MMC_EN_4BIT_DATA    = 0x0008,
 225         /* enable 75K pullups on D3..D0 */
 226         GLAMO_BASIC_MMC_EN_DATA_PUPS    = 0x0010,
 227         /* enable 75K pullup on CMD */
 228         GLAMO_BASIC_MMC_EN_CMD_PUP      = 0x0020,
 229         /* IO drive strength 00=weak -> 11=strongest */
 230         GLAMO_BASIC_MMC_EN_DR_STR0      = 0x0040,
 231         GLAMO_BASIC_MMC_EN_DR_STR1      = 0x0080,
 232         /* TCLK delay stage A, 0000 = 500ps --> 1111 = 8ns */
 233         GLAMO_BASIC_MMC_EN_TCLK_DLYA0   = 0x0100,
 234         GLAMO_BASIC_MMC_EN_TCLK_DLYA1   = 0x0200,
 235         GLAMO_BASIC_MMC_EN_TCLK_DLYA2   = 0x0400,
 236         GLAMO_BASIC_MMC_EN_TCLK_DLYA3   = 0x0800,
 237         /* TCLK delay stage B (cumulative), 0000 = 500ps --> 1111 = 8ns */
 238         GLAMO_BASIC_MMC_EN_TCLK_DLYB0   = 0x1000,
 239         GLAMO_BASIC_MMC_EN_TCLK_DLYB1   = 0x2000,
 240         GLAMO_BASIC_MMC_EN_TCLK_DLYB2   = 0x4000,
 241         GLAMO_BASIC_MMC_EN_TCLK_DLYB3   = 0x8000,
 242 };
 243
 244 enum glamo_reg_stat1_mmc {
 245         /* command "counter" (really: toggle) */
 246         GLAMO_STAT1_MMC_CMD_CTR = 0x8000,
 247         /* engine is idle */
 248         GLAMO_STAT1_MMC_IDLE    = 0x4000,
 249         /* readback response is ready */
 250         GLAMO_STAT1_MMC_RB_RRDY = 0x0200,
 251         /* readback data is ready */
 252         GLAMO_STAT1_MMC_RB_DRDY = 0x0100,
 253         /* no response timeout */
 254         GLAMO_STAT1_MMC_RTOUT   = 0x0020,
 255         /* no data timeout */
 256         GLAMO_STAT1_MMC_DTOUT   = 0x0010,
 257         /* CRC error on block write */
 258         GLAMO_STAT1_MMC_BWERR   = 0x0004,
 259         /* CRC error on block read */
 260         GLAMO_STAT1_MMC_BRERR   = 0x0002
 261 };
 262
 263 enum glamo_reg_fire_mmc {
 264         /* command "counter" (really: toggle)
 265          * the STAT1 register reflects this so you can ensure you don't look
 266          * at status for previous command
 267          */
 268         GLAMO_FIRE_MMC_CMD_CTR  = 0x8000,
 269         /* sets kind of response expected */
 270         GLAMO_FIRE_MMC_RES_MASK = 0x0700,
 271         /* sets command type */
 272         GLAMO_FIRE_MMC_TYP_MASK = 0x00C0,
 273         /* sets command class */
 274         GLAMO_FIRE_MMC_CLS_MASK = 0x000F,
 275 };
 276
 277 enum glamo_fire_mmc_response_types {
 278         GLAMO_FIRE_MMC_RSPT_R1  = 0x0000,
 279         GLAMO_FIRE_MMC_RSPT_R1b = 0x0100,
 280         GLAMO_FIRE_MMC_RSPT_R2  = 0x0200,
 281         GLAMO_FIRE_MMC_RSPT_R3  = 0x0300,
 282         GLAMO_FIRE_MMC_RSPT_R4  = 0x0400,
 283         GLAMO_FIRE_MMC_RSPT_R5  = 0x0500,
 284 };
 285
 286 enum glamo_fire_mmc_command_types {
 287         /* broadcast, no response */
 288         GLAMO_FIRE_MMC_CMDT_BNR = 0x0000,
 289         /* broadcast, with response */
 290         GLAMO_FIRE_MMC_CMDT_BR  = 0x0040,
 291         /* addressed, no data */
 292         GLAMO_FIRE_MMC_CMDT_AND = 0x0080,
 293         /* addressed, with data */
 294         GLAMO_FIRE_MMC_CMDT_AD  = 0x00C0,
 295 };
 296
 297 enum glamo_fire_mmc_command_class {
 298         /* "Stream Read" */
 299         GLAMO_FIRE_MMC_CC_STRR  = 0x0000,
 300         /* Single Block Read */
 301         GLAMO_FIRE_MMC_CC_SBR   = 0x0001,
 302         /* Multiple Block Read With Stop */
 303         GLAMO_FIRE_MMC_CC_MBRS  = 0x0002,
 304         /* Multiple Block Read No Stop */
 305         GLAMO_FIRE_MMC_CC_MBRNS = 0x0003,
 306         /* RESERVED for "Stream Write" */
 307         GLAMO_FIRE_MMC_CC_STRW  = 0x0004,
 308         /* "Stream Write" */
 309         GLAMO_FIRE_MMC_CC_SBW   = 0x0005,
 310         /* RESERVED for Multiple Block Write With Stop */
 311         GLAMO_FIRE_MMC_CC_MBWS  = 0x0006,
 312         /* Multiple Block Write No Stop */
 313         GLAMO_FIRE_MMC_CC_MBWNS = 0x0007,
 314         /* STOP command */
 315         GLAMO_FIRE_MMC_CC_STOP  = 0x0008,
 316         /* Cancel on Running Command */
 317         GLAMO_FIRE_MMC_CC_CANCL = 0x0009,
 318         /* "Basic Command" */
 319         GLAMO_FIRE_MMC_CC_BASIC = 0x000a,
 320 };
 321
 322 /* these are offsets from the start of the MMC register region */
 323 enum glamo_register_mmc {
 324         /* MMC command, b15..8 = cmd arg b7..0; b7..1 = CRC; b0 = end bit */
 325         GLAMO_REG_MMC_CMD_REG1  = 0x00,
 326         /* MMC command, b15..0 = cmd arg b23 .. 8 */
 327         GLAMO_REG_MMC_CMD_REG2  = 0x02,
 328         /* MMC command, b15=start, b14=transmission,
 329          * b13..8=cmd idx, b7..0=cmd arg b31..24
 330          */
 331         GLAMO_REG_MMC_CMD_REG3  = 0x04,
 332         GLAMO_REG_MMC_CMD_FIRE  = 0x06,
 333         GLAMO_REG_MMC_CMD_RSP1  = 0x10,
 334         GLAMO_REG_MMC_CMD_RSP2  = 0x12,
 335         GLAMO_REG_MMC_CMD_RSP3  = 0x14,
 336         GLAMO_REG_MMC_CMD_RSP4  = 0x16,
 337         GLAMO_REG_MMC_CMD_RSP5  = 0x18,
 338         GLAMO_REG_MMC_CMD_RSP6  = 0x1a,
 339         GLAMO_REG_MMC_CMD_RSP7  = 0x1c,
 340         GLAMO_REG_MMC_CMD_RSP8  = 0x1e,
 341         GLAMO_REG_MMC_RB_STAT1  = 0x20,
 342         GLAMO_REG_MMC_RB_BLKCNT = 0x22,
 343         GLAMO_REG_MMC_RB_BLKLEN = 0x24,
 344         GLAMO_REG_MMC_BASIC     = 0x30,
 345         GLAMO_REG_MMC_RDATADS1  = 0x34,
 346         GLAMO_REG_MMC_RDATADS2  = 0x36,
 347         GLAMO_REG_MMC_WDATADS1  = 0x38,
 348         GLAMO_REG_MMC_WDATADS2  = 0x3a,
 349         GLAMO_REG_MMC_DATBLKCNT = 0x3c,
 350         GLAMO_REG_MMC_DATBLKLEN = 0x3e,
 351         GLAMO_REG_MMC_TIMEOUT   = 0x40,
 352
 353 };
 354
 355 enum glamo_reg_clock_isp {
 356         GLAMO_CLOCK_ISP_DG_I1CLK        = 0x0001,
 357         GLAMO_CLOCK_ISP_EN_I1CLK        = 0x0002,
 358         GLAMO_CLOCK_ISP_DG_CCLK         = 0x0004,
 359         GLAMO_CLOCK_ISP_EN_CCLK         = 0x0008,
 360         //
 361         GLAMO_CLOCK_ISP_EN_SCLK         = 0x0020,
 362         GLAMO_CLOCK_ISP_DG_M2CLK        = 0x0040,
 363         GLAMO_CLOCK_ISP_EN_M2CLK        = 0x0080,
 364         GLAMO_CLOCK_ISP_DG_M15CLK       = 0x0100,
 365         GLAMO_CLOCK_ISP_EN_M15CLK       = 0x0200,
 366         GLAMO_CLOCK_ISP1_RESET          = 0x1000,
 367         GLAMO_CLOCK_ISP2_RESET          = 0x2000,
 368 };
 369
 370 enum glamo_reg_clock_jpeg {
 371         GLAMO_CLOCK_JPEG_DG_JCLK        = 0x0001,
 372         GLAMO_CLOCK_JPEG_EN_JCLK        = 0x0002,
 373         GLAMO_CLOCK_JPEG_DG_M3CLK       = 0x0004,
 374         GLAMO_CLOCK_JPEG_EN_M3CLK       = 0x0008,
 375         GLAMO_CLOCK_JPEG_RESET          = 0x1000,
 376 };
 377
 378 enum glamo_reg_clock_2d {
 379         GLAMO_CLOCK_2D_DG_GCLK          = 0x0001,
 380         GLAMO_CLOCK_2D_EN_GCLK          = 0x0002,
 381         GLAMO_CLOCK_2D_DG_M7CLK         = 0x0004,
 382         GLAMO_CLOCK_2D_EN_M7CLK         = 0x0008,
 383         GLAMO_CLOCK_2D_DG_M6CLK         = 0x0010,
 384         GLAMO_CLOCK_2D_EN_M6CLK         = 0x0020,
 385         GLAMO_CLOCK_2D_RESET            = 0x1000,
 386         GLAMO_CLOCK_2D_CQ_RESET         = 0x2000,
 387 };
 388
 389 enum glamo_reg_clock_3d {
 390         GLAMO_CLOCK_3D_DG_ECLK          = 0x0001,
 391         GLAMO_CLOCK_3D_EN_ECLK          = 0x0002,
 392         GLAMO_CLOCK_3D_DG_RCLK          = 0x0004,
 393         GLAMO_CLOCK_3D_EN_RCLK          = 0x0008,
 394         GLAMO_CLOCK_3D_DG_M8CLK         = 0x0010,
 395         GLAMO_CLOCK_3D_EN_M8CLK         = 0x0020,
 396         GLAMO_CLOCK_3D_BACK_RESET       = 0x1000,
 397         GLAMO_CLOCK_3D_FRONT_RESET      = 0x2000,
 398 };
 399
 400 enum glamo_reg_clock_mpeg {
 401         GLAMO_CLOCK_MPEG_DG_X0CLK       = 0x0001,
 402         GLAMO_CLOCK_MPEG_EN_X0CLK       = 0x0002,
 403         GLAMO_CLOCK_MPEG_DG_X1CLK       = 0x0004,
 404         GLAMO_CLOCK_MPEG_EN_X1CLK       = 0x0008,
 405         GLAMO_CLOCK_MPEG_DG_X2CLK       = 0x0010,
 406         GLAMO_CLOCK_MPEG_EN_X2CLK       = 0x0020,
 407         GLAMO_CLOCK_MPEG_DG_X3CLK       = 0x0040,
 408         GLAMO_CLOCK_MPEG_EN_X3CLK       = 0x0080,
 409         GLAMO_CLOCK_MPEG_DG_X4CLK       = 0x0100,
 410         GLAMO_CLOCK_MPEG_EN_X4CLK       = 0x0200,
 411         GLAMO_CLOCK_MPEG_DG_X6CLK       = 0x0400,
 412         GLAMO_CLOCK_MPEG_EN_X6CLK       = 0x0800,
 413         GLAMO_CLOCK_MPEG_ENC_RESET      = 0x1000,
 414         GLAMO_CLOCK_MPEG_DEC_RESET      = 0x2000,
 415 };
 416
 417 enum glamo_reg_clock51 {
 418         GLAMO_CLOCK_GEN51_EN_DIV_MCLK   = 0x0001,
 419         GLAMO_CLOCK_GEN51_EN_DIV_SCLK   = 0x0002,
 420         GLAMO_CLOCK_GEN51_EN_DIV_JCLK   = 0x0004,
 421         GLAMO_CLOCK_GEN51_EN_DIV_DCLK   = 0x0008,
 422         GLAMO_CLOCK_GEN51_EN_DIV_DMCLK  = 0x0010,
 423         GLAMO_CLOCK_GEN51_EN_DIV_DHCLK  = 0x0020,
 424         GLAMO_CLOCK_GEN51_EN_DIV_GCLK   = 0x0040,
 425         GLAMO_CLOCK_GEN51_EN_DIV_TCLK   = 0x0080,
 426         /* FIXME: higher bits */
 427 };
 428
 429 enum glamo_reg_hostbus2 {
 430         GLAMO_HOSTBUS2_MMIO_EN_ISP      = 0x0001,
 431         GLAMO_HOSTBUS2_MMIO_EN_JPEG     = 0x0002,
 432         GLAMO_HOSTBUS2_MMIO_EN_MPEG     = 0x0004,
 433         GLAMO_HOSTBUS2_MMIO_EN_LCD      = 0x0008,
 434         GLAMO_HOSTBUS2_MMIO_EN_MMC      = 0x0010,
 435         GLAMO_HOSTBUS2_MMIO_EN_MICROP0  = 0x0020,
 436         GLAMO_HOSTBUS2_MMIO_EN_MICROP1  = 0x0040,
 437         GLAMO_HOSTBUS2_MMIO_EN_CQ       = 0x0080,
 438         GLAMO_HOSTBUS2_MMIO_EN_RISC     = 0x0100,
 439         GLAMO_HOSTBUS2_MMIO_EN_2D       = 0x0200,
 440         GLAMO_HOSTBUS2_MMIO_EN_3D       = 0x0400,
 441 };
 442
 443 /* LCD Controller */
 444
 445 #define REG_LCD(x)      (x)
 446 enum glamo_reg_lcd {
 447         GLAMO_REG_LCD_MODE1             = REG_LCD(0x00),
 448         GLAMO_REG_LCD_MODE2             = REG_LCD(0x02),
 449         GLAMO_REG_LCD_MODE3             = REG_LCD(0x04),
 450         GLAMO_REG_LCD_WIDTH             = REG_LCD(0x06),
 451         GLAMO_REG_LCD_HEIGHT            = REG_LCD(0x08),
 452         GLAMO_REG_LCD_POLARITY          = REG_LCD(0x0a),
 453         GLAMO_REG_LCD_A_BASE1           = REG_LCD(0x0c),
 454         GLAMO_REG_LCD_A_BASE2           = REG_LCD(0x0e),
 455         GLAMO_REG_LCD_B_BASE1           = REG_LCD(0x10),
 456         GLAMO_REG_LCD_B_BASE2           = REG_LCD(0x12),
 457         GLAMO_REG_LCD_C_BASE1           = REG_LCD(0x14),
 458         GLAMO_REG_LCD_C_BASE2           = REG_LCD(0x16),
 459         GLAMO_REG_LCD_PITCH             = REG_LCD(0x18),
 460         /* RES */
 461         GLAMO_REG_LCD_HORIZ_TOTAL       = REG_LCD(0x1c),
 462         /* RES */
 463         GLAMO_REG_LCD_HORIZ_RETR_START  = REG_LCD(0x20),
 464         /* RES */
 465         GLAMO_REG_LCD_HORIZ_RETR_END    = REG_LCD(0x24),
 466         /* RES */
 467         GLAMO_REG_LCD_HORIZ_DISP_START  = REG_LCD(0x28),
 468         /* RES */
 469         GLAMO_REG_LCD_HORIZ_DISP_END    = REG_LCD(0x2c),
 470         /* RES */
 471         GLAMO_REG_LCD_VERT_TOTAL        = REG_LCD(0x30),
 472         /* RES */
 473         GLAMO_REG_LCD_VERT_RETR_START   = REG_LCD(0x34),
 474         /* RES */
 475         GLAMO_REG_LCD_VERT_RETR_END     = REG_LCD(0x38),
 476         /* RES */
 477         GLAMO_REG_LCD_VERT_DISP_START   = REG_LCD(0x3c),
 478         /* RES */
 479         GLAMO_REG_LCD_VERT_DISP_END     = REG_LCD(0x40),
 480         /* RES */
 481         GLAMO_REG_LCD_POL               = REG_LCD(0x44),
 482         GLAMO_REG_LCD_DATA_START        = REG_LCD(0x46),
 483         GLAMO_REG_LCD_FRATE_CONTRO      = REG_LCD(0x48),
 484         GLAMO_REG_LCD_DATA_CMD_HDR      = REG_LCD(0x4a),
 485         GLAMO_REG_LCD_SP_START          = REG_LCD(0x4c),
 486         GLAMO_REG_LCD_SP_END            = REG_LCD(0x4e),
 487         GLAMO_REG_LCD_CURSOR_BASE1      = REG_LCD(0x50),
 488         GLAMO_REG_LCD_CURSOR_BASE2      = REG_LCD(0x52),
 489         GLAMO_REG_LCD_CURSOR_PITCH      = REG_LCD(0x54),
 490         GLAMO_REG_LCD_CURSOR_X_SIZE     = REG_LCD(0x56),
 491         GLAMO_REG_LCD_CURSOR_Y_SIZE     = REG_LCD(0x58),
 492         GLAMO_REG_LCD_CURSOR_X_POS      = REG_LCD(0x5a),
 493         GLAMO_REG_LCD_CURSOR_Y_POS      = REG_LCD(0x5c),
 494         GLAMO_REG_LCD_CURSOR_PRESET     = REG_LCD(0x5e),
 495         GLAMO_REG_LCD_CURSOR_FG_COLOR   = REG_LCD(0x60),
 496         /* RES */
 497         GLAMO_REG_LCD_CURSOR_BG_COLOR   = REG_LCD(0x64),
 498         /* RES */
 499         GLAMO_REG_LCD_CURSOR_DST_COLOR  = REG_LCD(0x68),
 500         /* RES */
 501         GLAMO_REG_LCD_STATUS1           = REG_LCD(0x80),
 502         GLAMO_REG_LCD_STATUS2           = REG_LCD(0x82),
 503         GLAMO_REG_LCD_STATUS3           = REG_LCD(0x84),
 504         GLAMO_REG_LCD_STATUS4           = REG_LCD(0x86),
 505         /* RES */
 506         GLAMO_REG_LCD_COMMAND1          = REG_LCD(0xa0),
 507         GLAMO_REG_LCD_COMMAND2          = REG_LCD(0xa2),
 508         /* RES */
 509         GLAMO_REG_LCD_WFORM_DELAY1      = REG_LCD(0xb0),
 510         GLAMO_REG_LCD_WFORM_DELAY2      = REG_LCD(0xb2),
 511         /* RES */
 512         GLAMO_REG_LCD_GAMMA_CORR        = REG_LCD(0x100),
 513         /* RES */
 514         GLAMO_REG_LCD_GAMMA_R_ENTRY01   = REG_LCD(0x110),
 515         GLAMO_REG_LCD_GAMMA_R_ENTRY23   = REG_LCD(0x112),
 516         GLAMO_REG_LCD_GAMMA_R_ENTRY45   = REG_LCD(0x114),
 517         GLAMO_REG_LCD_GAMMA_R_ENTRY67   = REG_LCD(0x116),
 518         GLAMO_REG_LCD_GAMMA_R_ENTRY8    = REG_LCD(0x118),
 519         /* RES */
 520         GLAMO_REG_LCD_GAMMA_G_ENTRY01   = REG_LCD(0x130),
 521         GLAMO_REG_LCD_GAMMA_G_ENTRY23   = REG_LCD(0x132),
 522         GLAMO_REG_LCD_GAMMA_G_ENTRY45   = REG_LCD(0x134),
 523         GLAMO_REG_LCD_GAMMA_G_ENTRY67   = REG_LCD(0x136),
 524         GLAMO_REG_LCD_GAMMA_G_ENTRY8    = REG_LCD(0x138),
 525         /* RES */
 526         GLAMO_REG_LCD_GAMMA_B_ENTRY01   = REG_LCD(0x150),
 527         GLAMO_REG_LCD_GAMMA_B_ENTRY23   = REG_LCD(0x152),
 528         GLAMO_REG_LCD_GAMMA_B_ENTRY45   = REG_LCD(0x154),
 529         GLAMO_REG_LCD_GAMMA_B_ENTRY67   = REG_LCD(0x156),
 530         GLAMO_REG_LCD_GAMMA_B_ENTRY8    = REG_LCD(0x158),
 531         /* RES */
 532         GLAMO_REG_LCD_SRAM_DRIVING1     = REG_LCD(0x160),
 533         GLAMO_REG_LCD_SRAM_DRIVING2     = REG_LCD(0x162),
 534         GLAMO_REG_LCD_SRAM_DRIVING3     = REG_LCD(0x164),
 535 };
 536
 537 enum glamo_reg_lcd_mode1 {
 538         GLAMO_LCD_MODE1_PWRSAVE         = 0x0001,
 539         GLAMO_LCD_MODE1_PARTIAL_PRT     = 0x0002,
 540         GLAMO_LCD_MODE1_HWFLIP          = 0x0004,
 541         GLAMO_LCD_MODE1_LCD2            = 0x0008,
 542         /* RES */
 543         GLAMO_LCD_MODE1_PARTIAL_MODE    = 0x0020,
 544         GLAMO_LCD_MODE1_CURSOR_DSTCOLOR = 0x0040,
 545         GLAMO_LCD_MODE1_PARTIAL_ENABLE  = 0x0080,
 546         GLAMO_LCD_MODE1_TVCLK_IN_ENABLE = 0x0100,
 547         GLAMO_LCD_MODE1_HSYNC_HIGH_ACT  = 0x0200,
 548         GLAMO_LCD_MODE1_VSYNC_HIGH_ACT  = 0x0400,
 549         GLAMO_LCD_MODE1_HSYNC_FLIP      = 0x0800,
 550         GLAMO_LCD_MODE1_GAMMA_COR_EN    = 0x1000,
 551         GLAMO_LCD_MODE1_DITHER_EN       = 0x2000,
 552         GLAMO_LCD_MODE1_CURSOR_EN       = 0x4000,
 553         GLAMO_LCD_MODE1_ROTATE_EN       = 0x8000,
 554 };
 555
 556 enum glamo_reg_lcd_mode2 {
 557         GLAMO_LCD_MODE2_CRC_CHECK_EN    = 0x0001,
 558         GLAMO_LCD_MODE2_DCMD_PER_LINE   = 0x0002,
 559         GLAMO_LCD_MODE2_NOUSE_BDEF      = 0x0004,
 560         GLAMO_LCD_MODE2_OUT_POS_MODE    = 0x0008,
 561         GLAMO_LCD_MODE2_FRATE_CTRL_EN   = 0x0010,
 562         GLAMO_LCD_MODE2_SINGLE_BUFFER   = 0x0020,
 563         GLAMO_LCD_MODE2_SER_LSB_TO_MSB  = 0x0040,
 564         /* FIXME */
 565 };
 566
 567 enum glamo_reg_lcd_mode3 {
 568         /* LCD color source data format */
 569         GLAMO_LCD_SRC_RGB565            = 0x0000,
 570         GLAMO_LCD_SRC_ARGB1555          = 0x4000,
 571         GLAMO_LCD_SRC_ARGB4444          = 0x8000,
 572         /* interface type */
 573         GLAMO_LCD_MODE3_LCD             = 0x1000,
 574         GLAMO_LCD_MODE3_RGB             = 0x0800,
 575         GLAMO_LCD_MODE3_CPU             = 0x0000,
 576         /* mode */
 577         GLAMO_LCD_MODE3_RGB332          = 0x0000,
 578         GLAMO_LCD_MODE3_RGB444          = 0x0100,
 579         GLAMO_LCD_MODE3_RGB565          = 0x0200,
 580         GLAMO_LCD_MODE3_RGB666          = 0x0300,
 581         /* depth */
 582         GLAMO_LCD_MODE3_6BITS           = 0x0000,
 583         GLAMO_LCD_MODE3_8BITS           = 0x0010,
 584         GLAMO_LCD_MODE3_9BITS           = 0x0020,
 585         GLAMO_LCD_MODE3_16BITS          = 0x0030,
 586         GLAMO_LCD_MODE3_18BITS          = 0x0040,
 587 };
 588
 589 enum glamo_lcd_rot_mode {
 590         GLAMO_LCD_ROT_MODE_0            = 0x0000,
 591         GLAMO_LCD_ROT_MODE_180          = 0x2000,
 592         GLAMO_LCD_ROT_MODE_MIRROR       = 0x4000,
 593         GLAMO_LCD_ROT_MODE_FLIP         = 0x6000,
 594         GLAMO_LCD_ROT_MODE_90           = 0x8000,
 595         GLAMO_LCD_ROT_MODE_270          = 0xa000,
 596 };
 597 #define GLAMO_LCD_ROT_MODE_MASK         0xe000
 598
 599 enum glamo_lcd_cmd_type {
 600         GLAMO_LCD_CMD_TYPE_DISP         = 0x0000,
 601         GLAMO_LCD_CMD_TYPE_PARALLEL     = 0x4000,
 602         GLAMO_LCD_CMD_TYPE_SERIAL       = 0x8000,
 603         GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,
 604 };
 605 #define GLAMO_LCD_CMD_TYPE_MASK         0xc000
 606
 607 enum glamo_lcd_cmds {
 608         GLAMO_LCD_CMD_DATA_DISP_FIRE    = 0x00,
 609         GLAMO_LCD_CMD_DATA_DISP_SYNC    = 0x01,         /* RGB only */
 610         /* switch to command mode, no display */
 611         GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02,
 612         /* display until VSYNC, switch to command */
 613         GLAMO_LCD_CMD_DATA_FIRE_VSYNC   = 0x11,
 614         /* display until HSYNC, switch to command */
 615         GLAMO_LCD_CMD_DATA_FIRE_HSYNC   = 0x12,
 616         /* display until VSYNC, 1 black frame, VSYNC, switch to command */
 617         GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13,
 618         /* don't care about display and switch to command */
 619         GLAMO_LCD_CMD_DATA_FIRE_FREE    = 0x14,         /* RGB only */
 620         /* don't care about display, keep data display but disable data,
 621          * and switch to command */
 622         GLAMO_LCD_CMD_DATA_FIRE_FREE_D  = 0x15,         /* RGB only */
 623 };
 624
 625 enum glamo_core_revisions {
 626         GLAMO_CORE_REV_A0               = 0x0000,
 627         GLAMO_CORE_REV_A1               = 0x0001,
 628         GLAMO_CORE_REV_A2               = 0x0002,
 629         GLAMO_CORE_REV_A3               = 0x0003,
 630 };
 631
 632 #endif /* _GLAMO_REGS_H */