target/linux/rb532-2.6/patches/100-rb5xx_support.patch

   1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
   2 --- linux.old/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
   3 +++ linux.dev/arch/mips/Kconfig 2006-10-11 21:56:38.000000000 +0200
   4 @@ -742,6 +742,19 @@
   5         select SYS_SUPPORTS_BIG_ENDIAN
   6         select TOSHIBA_BOARDS
   7
   8 +config MIKROTIK_RB500
   9 +       bool "Support for RB5xx boards"
  10 +       select HW_HAS_PCI
  11 +       select IRQ_CPU
  12 +       select SYS_HAS_CPU_MIPS32_R1
  13 +       select SYS_SUPPORTS_LITTLE_ENDIAN
  14 +       select SYS_SUPPORTS_32BIT_KERNEL
  15 +       select SWAP_IO_SPACE
  16 +       select DMA_NONCOHERENT
  17 +       help
  18 +         Support the Mikrotik(tm) Routerboard 500 series,
  19 +         such as the RB532.
  20 +
  21  config TOSHIBA_RBTX4927
  22         bool "Toshiba TBTX49[23]7 board"
  23         select DMA_NONCOHERENT
  24 @@ -1028,7 +1041,7 @@
  25
  26  config MIPS_L1_CACHE_SHIFT
  27         int
  28 -       default "4" if MACH_DECSTATION
  29 +       default "4" if MACH_DECSTATION || MIKROTIK_RB500
  30         default "7" if SGI_IP27
  31         default "5"
  32
  33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
  34 --- linux.old/arch/mips/Makefile        2006-10-11 21:55:59.000000000 +0200
  35 +++ linux.dev/arch/mips/Makefile        2006-10-11 21:56:38.000000000 +0200
  36 @@ -580,6 +580,13 @@
  37  load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
  38
  39  #
  40 +# Routerboard 532 board
  41 +#
  42 +core-$(CONFIG_MIKROTIK_RB500)  += arch/mips/rb500/
  43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
  44 +load-$(CONFIG_MIKROTIK_RB500)  += 0xffffffff80101000
  45 +
  46 +#
  47  # Toshiba RBTX4927 board or
  48  # Toshiba RBTX4937 board
  49  #
  50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
  51 --- linux.old/arch/mips/mm/tlbex.c      2006-06-18 03:49:35.000000000 +0200
  52 +++ linux.dev/arch/mips/mm/tlbex.c      2006-10-11 21:56:38.000000000 +0200
  53 @@ -876,7 +876,6 @@
  54         case CPU_R10000:
  55         case CPU_R12000:
  56         case CPU_R14000:
  57 -       case CPU_4KC:
  58         case CPU_SB1:
  59         case CPU_SB1A:
  60         case CPU_4KSC:
  61 @@ -904,6 +903,7 @@
  62                 tlbw(p);
  63                 break;
  64
  65 +       case CPU_4KC:
  66         case CPU_4KEC:
  67         case CPU_24K:
  68         case CPU_34K:
  69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
  70 --- linux.old/arch/mips/pci/fixup-rb500.c       1970-01-01 01:00:00.000000000 +0100
  71 +++ linux.dev/arch/mips/pci/fixup-rb500.c       2006-10-11 21:56:38.000000000 +0200
  72 @@ -0,0 +1,49 @@
  73 +/*
  74 + * Copyright 2001 MontaVista Software Inc.
  75 + * Author: MontaVista Software, Inc.
  76 + *             stevel@mvista.com or source@mvista.com
  77 + *
  78 + *  This program is free software; you can redistribute  it and/or modify it
  79 + *  under  the terms of  the GNU General  Public License as published by the
  80 + *  Free Software Foundation;  either version 2 of the  License, or (at your
  81 + *  option) any later version.
  82 + *
  83 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  84 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  85 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  86 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  87 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  88 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  89 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  90 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  91 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  92 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  93 + *
  94 + *  You should have received a copy of the  GNU General Public License along
  95 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  96 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  97 + */
  98 +
  99 +#include <linux/config.h>
 100 +#include <linux/types.h>
 101 +#include <linux/pci.h>
 102 +#include <linux/kernel.h>
 103 +#include <linux/init.h>
 104 +
 105 +#include <asm/rc32434/rc32434.h>
 106 +
 107 +static int __devinitdata irq_map[2][12] = {
 108 +       { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
 109 +       { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
 110 +};
 111 +
 112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 113 +{
 114 +       int irq = 0;
 115 +
 116 +       if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
 117 +               irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
 118 +       }
 119 +       return irq + GROUP4_IRQ_BASE + 4;
 120 +}
 121 +
 122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
 123 --- linux.old/arch/mips/pci/Makefile    2006-06-18 03:49:35.000000000 +0200
 124 +++ linux.dev/arch/mips/pci/Makefile    2006-10-11 21:56:38.000000000 +0200
 125 @@ -57,3 +57,4 @@
 126  obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
 127  obj-$(CONFIG_VICTOR_MPC30X)    += fixup-mpc30x.o
 128  obj-$(CONFIG_ZAO_CAPCELLA)     += fixup-capcella.o
 129 +obj-$(CONFIG_MIKROTIK_RB500)   += pci-rc32434.o ops-rc32434.o fixup-rb500.o
 130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
 131 --- linux.old/arch/mips/pci/ops-rc32434.c       1970-01-01 01:00:00.000000000 +0100
 132 +++ linux.dev/arch/mips/pci/ops-rc32434.c       2006-10-11 21:56:38.000000000 +0200
 133 @@ -0,0 +1,195 @@
 134 +/**************************************************************************
 135 + *
 136 + *  BRIEF MODULE DESCRIPTION
 137 + *     pci_ops for IDT EB434 board
 138 + *
 139 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 140 + *
 141 + *  This program is free software; you can redistribute  it and/or modify it
 142 + *  under  the terms of  the GNU General  Public License as published by the
 143 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 144 + *  option) any later version.
 145 + *
 146 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 147 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 148 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 149 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 150 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 151 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 152 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 153 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 154 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 155 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 156 + *
 157 + *  You should have received a copy of the  GNU General Public License along
 158 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 159 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 160 + *
 161 + *
 162 + **************************************************************************
 163 + * May 2004 rkt, neb
 164 + *
 165 + * Initial Release
 166 + *
 167 + *
 168 + *
 169 + **************************************************************************
 170 + */
 171 +
 172 +#include <linux/config.h>
 173 +#include <linux/init.h>
 174 +#include <linux/pci.h>
 175 +#include <linux/types.h>
 176 +#include <linux/delay.h>
 177 +
 178 +#include <asm/cpu.h>
 179 +#include <asm/io.h>
 180 +
 181 +#include <asm/rc32434/rc32434.h>
 182 +#include <asm/rc32434/pci.h>
 183 +
 184 +#define PCI_ACCESS_READ  0
 185 +#define PCI_ACCESS_WRITE 1
 186 +
 187 +
 188 +#define PCI_CFG_SET(bus,slot,func,off) \
 189 +       (rc32434_pci->pcicfga = (0x80000000 | \
 190 +                               ((bus) << 16) | ((slot)<<11) | \
 191 +                               ((func)<<8) | (off)))
 192 +
 193 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
 194 +                         unsigned int devfn, unsigned char where,
 195 +                         u32 * data)
 196 +{
 197 +       unsigned int slot = PCI_SLOT(devfn);
 198 +       u8 func = PCI_FUNC(devfn);
 199 +
 200 +       /* Setup address */
 201 +       PCI_CFG_SET(bus->number, slot, func, where);
 202 +       rc32434_sync();
 203 +
 204 +       if (access_type == PCI_ACCESS_WRITE)
 205 +               rc32434_pci->pcicfgd = *data;
 206 +       else
 207 +               *data = rc32434_pci->pcicfgd;
 208 +
 209 +       rc32434_sync();
 210 +
 211 +       return 0;
 212 +}
 213 +
 214 +
 215 +/*
 216 + * We can't address 8 and 16 bit words directly.  Instead we have to
 217 + * read/write a 32bit word and mask/modify the data we actually want.
 218 + */
 219 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 220 +                            int where, u8 * val)
 221 +{
 222 +       u32 data;
 223 +       int ret;
 224 +
 225 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 226 +       *val = (data >> ((where & 3) << 3)) & 0xff;
 227 +       return ret;
 228 +}
 229 +
 230 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 231 +                            int where, u16 * val)
 232 +{
 233 +       u32 data;
 234 +       int ret;
 235 +
 236 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 237 +       *val = (data >> ((where & 3) << 3)) & 0xffff;
 238 +       return ret;
 239 +}
 240 +
 241 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 242 +                             int where, u32 * val)
 243 +{
 244 +       int ret;
 245 +
 246 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
 247 +       return ret;
 248 +}
 249 +
 250 +static int
 251 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 252 +                  u8 val)
 253 +{
 254 +       u32 data = 0;
 255 +
 256 +       if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 257 +               return -1;
 258 +
 259 +       data = (data & ~(0xff << ((where & 3) << 3))) |
 260 +               (val << ((where & 3) << 3));
 261 +
 262 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 263 +               return -1;
 264 +
 265 +       return PCIBIOS_SUCCESSFUL;
 266 +}
 267 +
 268 +
 269 +static int
 270 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
 271 +                  u16 val)
 272 +{
 273 +       u32 data = 0;
 274 +
 275 +       if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 276 +               return -1;
 277 +
 278 +       data = (data & ~(0xffff << ((where & 3) << 3))) |
 279 +               (val << ((where & 3) << 3));
 280 +
 281 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 282 +               return -1;
 283 +
 284 +
 285 +       return PCIBIOS_SUCCESSFUL;
 286 +}
 287 +
 288 +
 289 +static int
 290 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
 291 +                   u32 val)
 292 +{
 293 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 294 +               return -1;
 295 +
 296 +       return PCIBIOS_SUCCESSFUL;
 297 +}
 298 +
 299 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
 300 +                          int where, int size, u32 * val)
 301 +{
 302 +       switch (size) {
 303 +       case 1:
 304 +               return read_config_byte(bus, devfn, where, (u8 *) val);
 305 +       case 2:
 306 +               return read_config_word(bus, devfn, where, (u16 *) val);
 307 +       default:
 308 +               return read_config_dword(bus, devfn, where, val);
 309 +       }
 310 +}
 311 +
 312 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
 313 +                           int where, int size, u32 val)
 314 +{
 315 +       switch (size) {
 316 +       case 1:
 317 +               return write_config_byte(bus, devfn, where, (u8) val);
 318 +       case 2:
 319 +               return write_config_word(bus, devfn, where, (u16) val);
 320 +       default:
 321 +               return write_config_dword(bus, devfn, where, val);
 322 +       }
 323 +}
 324 +
 325 +struct pci_ops rc32434_pci_ops = {
 326 +       .read =  pci_config_read,
 327 +       .write = pci_config_write,
 328 +};
 329 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
 330 --- linux.old/arch/mips/pci/pci-rc32434.c       1970-01-01 01:00:00.000000000 +0100
 331 +++ linux.dev/arch/mips/pci/pci-rc32434.c       2006-10-11 21:56:38.000000000 +0200
 332 @@ -0,0 +1,234 @@
 333 +/**************************************************************************
 334 + *
 335 + *  BRIEF MODULE DESCRIPTION
 336 + *     PCI initialization for IDT EB434 board
 337 + *
 338 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 339 + *
 340 + *  This program is free software; you can redistribute  it and/or modify it
 341 + *  under  the terms of  the GNU General  Public License as published by the
 342 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 343 + *  option) any later version.
 344 + *
 345 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 346 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 347 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 348 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 349 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 350 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 351 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 352 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 353 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 354 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 355 + *
 356 + *  You should have received a copy of the  GNU General Public License along
 357 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 358 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 359 + *
 360 + *
 361 + **************************************************************************
 362 + * May 2004 rkt, neb
 363 + *
 364 + * Initial Release
 365 + *
 366 + *
 367 + *
 368 + **************************************************************************
 369 + */
 370 +
 371 +#include <linux/config.h>
 372 +#include <linux/types.h>
 373 +#include <linux/pci.h>
 374 +#include <linux/kernel.h>
 375 +#include <linux/init.h>
 376 +
 377 +#include <asm/rc32434/rc32434.h>
 378 +#include <asm/rc32434/pci.h>
 379 +
 380 +#define PCI_ACCESS_READ  0
 381 +#define PCI_ACCESS_WRITE 1
 382 +
 383 +/* define an unsigned array for the PCI registers */
 384 +unsigned int korinaCnfgRegs[25] = {
 385 +       KORINA_CNFG1,    KORINA_CNFG2,  KORINA_CNFG3,  KORINA_CNFG4,
 386 +       KORINA_CNFG5,    KORINA_CNFG6,  KORINA_CNFG7,  KORINA_CNFG8,
 387 +       KORINA_CNFG9,    KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
 388 +       KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
 389 +       KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
 390 +       KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
 391 +};
 392 +static struct resource rc32434_res_pci_mem1;
 393 +static struct resource rc32434_res_pci_mem2;
 394 +
 395 +static struct resource rc32434_res_pci_mem1 = {
 396 +       .name = "PCI MEM1",
 397 +       .start = 0x50000000,
 398 +       .end = 0x5FFFFFFF,
 399 +       .flags = IORESOURCE_MEM,
 400 +       .parent = &rc32434_res_pci_mem1,
 401 +       .sibling = NULL,
 402 +       .child = &rc32434_res_pci_mem2
 403 +};
 404 +
 405 +static struct resource rc32434_res_pci_mem2 = {
 406 +       .name = "PCI Mem2",
 407 +       .start = 0x60000000,
 408 +       .end = 0x6FFFFFFF,
 409 +       .flags = IORESOURCE_MEM,
 410 +       .parent = &rc32434_res_pci_mem1,
 411 +       .sibling = NULL,
 412 +       .child = NULL
 413 +};
 414 +
 415 +static struct resource rc32434_res_pci_io1 = {
 416 +       .name = "PCI I/O1",
 417 +       .start = 0x18800000,
 418 +       .end = 0x188FFFFF,
 419 +       .flags = IORESOURCE_IO,
 420 +};
 421 +
 422 +extern struct pci_ops rc32434_pci_ops;
 423 +
 424 +#define PCI_MEM1_START PCI_ADDR_START
 425 +#define PCI_MEM1_END   PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
 426 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
 427 +#define PCI_MEM2_END   PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN)  - 1
 428 +#define PCI_IO1_START  PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
 429 +#define PCI_IO1_END    PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
 430 +#define PCI_IO2_START  PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
 431 +#define PCI_IO2_END    PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
 432 +
 433 +
 434 +struct pci_controller rc32434_controller2;
 435 +
 436 +struct pci_controller rc32434_controller = {
 437 +       .pci_ops        = &rc32434_pci_ops,
 438 +       .mem_resource   = &rc32434_res_pci_mem1,
 439 +       .io_resource    = &rc32434_res_pci_io1,
 440 +       .mem_offset     = 0,
 441 +       .io_offset      = 0,
 442 +
 443 +};
 444 +
 445 +#ifdef __MIPSEB__
 446 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
 447 +#else
 448 +#define PCI_ENDIAN_FLAG 0
 449 +#endif
 450 +
 451 +static int __init rc32434_pcibridge_init(void)
 452 +{
 453 +       unsigned int pcicValue, pcicData = 0;
 454 +       unsigned int dummyRead, pciCntlVal;
 455 +       int loopCount;
 456 +       unsigned int pciConfigAddr;
 457 +
 458 +       pcicValue = rc32434_pci->pcic;
 459 +       pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
 460 +       if (!((pcicValue == PCIM_H_EA) ||
 461 +                (pcicValue == PCIM_H_IA_FIX) ||
 462 +               (pcicValue == PCIM_H_IA_RR))) {
 463 +               printk("PCI init error!!!\n");
 464 +               /* Not in Host Mode, return ERROR */
 465 +               return -1;
 466 +       }
 467 +       /* Enables the Idle Grant mode, Arbiter Parking */
 468 +       pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
 469 +       rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
 470 +       /* Zero out the PCI status & PCI Status Mask */
 471 +       for(;;)
 472 +       {
 473 +          pcicData = rc32434_pci->pcis;
 474 +          if (!(pcicData & PCIS_rip_m))
 475 +                   break;
 476 +       }
 477 +
 478 +       rc32434_pci->pcis = 0;
 479 +       rc32434_pci->pcism = 0xFFFFFFFF;
 480 +       /* Zero out the PCI decoupled registers */
 481 +       rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
 482 +       rc32434_pci->pcidas=0; /* clear the status */
 483 +       rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
 484 +       /* Mask PCI Messaging Interrupts */
 485 +       rc32434_pci_msg->pciiic = 0;
 486 +       rc32434_pci_msg->pciiim = 0xFFFFFFFF;
 487 +       rc32434_pci_msg->pciioic = 0;
 488 +       rc32434_pci_msg->pciioim = 0;
 489 +
 490 +
 491 +       /* Setup PCILB0 as Memory Window */
 492 +       rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
 493 +
 494 +       /* setup the PCI map address as same as the local address */
 495 +
 496 +       rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
 497 +
 498 +
 499 +       /* Setup PCILBA1 as MEM */
 500 +       rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
 501 +       dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
 502 +       rc32434_pci->pcilba[1].a = 0x60000000;
 503 +       rc32434_pci->pcilba[1].m = 0x60000000;
 504 +
 505 +       /* setup PCILBA2 as IO Window*/
 506 +       rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
 507 +       dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
 508 +       rc32434_pci->pcilba[2].a = 0x18C00000;
 509 +       rc32434_pci->pcilba[2].m = 0x18FFFFFF;
 510 +
 511 +       /* setup PCILBA2 as IO Window*/
 512 +       rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
 513 +       dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
 514 +
 515 +       /* Setup PCILBA3 as IO Window */
 516 +       rc32434_pci->pcilba[3].a = 0x18800000;
 517 +       rc32434_pci->pcilba[3].m = 0x18800000;
 518 +       rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
 519 +       dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
 520 +
 521 +       pciConfigAddr=(unsigned int)(0x80000004);
 522 +       for(loopCount=0;loopCount<24;loopCount++){
 523 +               rc32434_pci->pcicfga=pciConfigAddr;
 524 +               dummyRead=rc32434_pci->pcicfga;
 525 +               rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
 526 +               dummyRead=rc32434_pci->pcicfgd;
 527 +               pciConfigAddr += 4;
 528 +       }
 529 +       rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
 530 +               | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
 531 +
 532 +       pciCntlVal=rc32434_pci->pcic;
 533 +       pciCntlVal &=~(PCIC_tnr_m);
 534 +       rc32434_pci->pcic = pciCntlVal;
 535 +       pciCntlVal=rc32434_pci->pcic;
 536 +       return 0;
 537 +}
 538 +
 539 +/* Do platform specific device initialization at pci_enable_device() time */
 540 +int pcibios_plat_dev_init(struct pci_dev *dev)
 541 +{
 542 +       if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
 543 +               /* disable prefetched memory range */
 544 +               pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
 545 +               pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
 546 +
 547 +               pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
 548 +       }
 549 +       return 0;
 550 +}
 551 +
 552 +static int __init rc32434_pci_init(void)
 553 +{
 554 +       printk("PCI: Initializing PCI\n");
 555 +
 556 +       ioport_resource.start = rc32434_res_pci_io1.start;
 557 +       ioport_resource.end = rc32434_res_pci_io1.end;
 558 +
 559 +       rc32434_pcibridge_init();
 560 +
 561 +       register_pci_controller(&rc32434_controller);
 562 +       rc32434_sync();
 563 +}
 564 +
 565 +arch_initcall(rc32434_pci_init);
 566 +
 567 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
 568 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
 569 +++ linux.dev/arch/mips/rb500/devices.c 2006-10-11 21:56:38.000000000 +0200
 570 @@ -0,0 +1,211 @@
 571 +#include <linux/kernel.h>
 572 +#include <linux/init.h>
 573 +#include <linux/module.h>
 574 +#include <linux/ctype.h>
 575 +#include <linux/string.h>
 576 +#include <linux/platform_device.h>
 577 +#include <asm/unaligned.h>
 578 +#include <asm/io.h>
 579 +
 580 +#include <asm/rc32434/rc32434.h>
 581 +#include <asm/rc32434/dma.h>
 582 +#include <asm/rc32434/dma_v.h>
 583 +#include <asm/rc32434/eth.h>
 584 +#include <asm/rc32434/rb.h>
 585 +
 586 +#define ETH0_DMA_RX_IRQ        GROUP1_IRQ_BASE + 0
 587 +#define ETH0_DMA_TX_IRQ        GROUP1_IRQ_BASE + 1
 588 +#define ETH0_RX_OVR_IRQ        GROUP3_IRQ_BASE + 9
 589 +#define ETH0_TX_UND_IRQ        GROUP3_IRQ_BASE + 10
 590 +
 591 +#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
 592 +#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
 593 +
 594 +static struct resource korina_dev0_res[] = {
 595 +       {
 596 +               .name  = "korina_regs",
 597 +               .start = ETH0_PhysicalAddress,
 598 +               .end   = ETH0_PhysicalAddress + sizeof(ETH_t),
 599 +               .flags = IORESOURCE_MEM,
 600 +       },
 601 +       {
 602 +               .name  = "korina_rx",
 603 +               .start = ETH0_DMA_RX_IRQ,
 604 +               .end   = ETH0_DMA_RX_IRQ,
 605 +               .flags = IORESOURCE_IRQ
 606 +       },
 607 +       {
 608 +               .name  = "korina_tx",
 609 +               .start = ETH0_DMA_TX_IRQ,
 610 +               .end   = ETH0_DMA_TX_IRQ,
 611 +               .flags = IORESOURCE_IRQ
 612 +       },
 613 +       {
 614 +               .name  = "korina_ovr",
 615 +               .start = ETH0_RX_OVR_IRQ,
 616 +               .end   = ETH0_RX_OVR_IRQ,
 617 +               .flags = IORESOURCE_IRQ
 618 +       },
 619 +       {
 620 +               .name  = "korina_und",
 621 +               .start = ETH0_TX_UND_IRQ,
 622 +               .end   = ETH0_TX_UND_IRQ,
 623 +               .flags = IORESOURCE_IRQ
 624 +       },
 625 +       {
 626 +               .name  = "korina_dma_rx",
 627 +               .start = ETH0_RX_DMA_ADDR,
 628 +               .end   = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 629 +               .flags = IORESOURCE_MEM,
 630 +       },
 631 +       {
 632 +               .name  = "korina_dma_tx",
 633 +               .start = ETH0_TX_DMA_ADDR,
 634 +               .end   = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 635 +               .flags = IORESOURCE_MEM,
 636 +       }
 637 +};
 638 +
 639 +static struct korina_device korina_dev0_data = {
 640 +       .name = "korina0",
 641 +       .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
 642 +};
 643 +
 644 +static struct platform_device korina_dev0 = {
 645 +       .id = 0,
 646 +       .name = "korina",
 647 +       .dev.platform_data = &korina_dev0_data,
 648 +       .resource = korina_dev0_res,
 649 +       .num_resources = ARRAY_SIZE(korina_dev0_res),
 650 +};
 651 +
 652 +
 653 +#define CF_GPIO_NUM 13
 654 +
 655 +static struct resource cf_slot0_res[] = {
 656 +       {
 657 +               .name  = "cf_membase",
 658 +               .flags = IORESOURCE_MEM
 659 +       },
 660 +       {
 661 +               .name  = "cf_irq",
 662 +               .start = (8 + 4 * 32 + CF_GPIO_NUM),  /* 149 */
 663 +               .end   = (8 + 4 * 32 + CF_GPIO_NUM),
 664 +               .flags = IORESOURCE_IRQ
 665 +       }
 666 +};
 667 +
 668 +static struct cf_device cf_slot0_data = {
 669 +       .gpio_pin = 13
 670 +};
 671 +
 672 +static struct platform_device cf_slot0 = {
 673 +       .id = 0,
 674 +       .name = "rb500-cf",
 675 +       .dev.platform_data = &cf_slot0_data,
 676 +       .resource = cf_slot0_res,
 677 +       .num_resources = ARRAY_SIZE(cf_slot0_res),
 678 +};
 679 +
 680 +
 681 +
 682 +static struct platform_device *rb500_devs[] = {
 683 +       &korina_dev0,
 684 +       &cf_slot0
 685 +};
 686 +
 687 +static void __init parse_mac_addr(char* macstr)
 688 +{
 689 +       int i, j;
 690 +       unsigned char result, value;
 691 +
 692 +       for (i=0; i<6; i++) {
 693 +               result = 0;
 694 +               if (i != 5 && *(macstr+2) != ':') {
 695 +                       return;
 696 +               }
 697 +               for (j=0; j<2; j++) {
 698 +                       if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
 699 +                                                 toupper(*macstr)-'A'+10) < 16) {
 700 +                               result = result*16 + value;
 701 +                               macstr++;
 702 +                       }
 703 +                       else return;
 704 +               }
 705 +
 706 +               macstr++;
 707 +               korina_dev0_data.mac[i] = result;
 708 +       }
 709 +}
 710 +
 711 +
 712 +/* DEVICE CONTROLLER 1 */
 713 +#define CFG_DC_DEV1 (void*)0xb8010010
 714 +#define CFG_DC_DEVBASE    0x0
 715 +#define CFG_DC_DEVMASK    0x4
 716 +#define CFG_DC_DEVC       0x8
 717 +#define CFG_DC_DEVTC      0xC
 718 +
 719 +
 720 +static int __init plat_setup_devices(void)
 721 +{
 722 +       /* Look for the CF card reader */
 723 +       if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
 724 +               rb500_devs[1] = NULL;
 725 +       else {
 726 +               cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
 727 +               cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
 728 +       }
 729 +
 730 +       return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
 731 +}
 732 +
 733 +static int __init setup_kmac(char *s)
 734 +{
 735 +    printk("korina mac = %s\n",s);
 736 +       parse_mac_addr(s);
 737 +    return 0;
 738 +}
 739 +
 740 +__setup("kmac=", setup_kmac);
 741 +arch_initcall(plat_setup_devices);
 742 +
 743 +
 744 +#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS)
 745 +extern void block2mtd_setup(char *initstr);
 746 +extern void mount_devfs_fs(void);
 747 +
 748 +static int __init setup_mtd(void)
 749 +{
 750 +       struct hd_struct **part;
 751 +       int num = 0, i;
 752 +       char initstr[64];
 753 +
 754 +       if (cf_slot0_data.gd == NULL)
 755 +               return 0;
 756 +
 757 +       /* count partitions */
 758 +       part = cf_slot0_data.gd->part;
 759 +       while (part[num] != NULL) {
 760 +               num++;
 761 +       }
 762 +
 763 +       if (num < 2)
 764 +               return 0;
 765 +
 766 +       mount_devfs_fs();
 767 +       printk("Setting up block2mtd devices\n");
 768 +
 769 +       block2mtd_setup("/dev/cf/card0/part1,131072,kernel");
 770 +       block2mtd_setup("/dev/cf/card0/part2,131072,rootfs");
 771 +
 772 +       for (i = 2; part[i]; i++) {
 773 +               sprintf(initstr, "/dev/cf/card0/part%d,131072,part%d", i + 1, i + 1);
 774 +               block2mtd_setup(initstr);
 775 +       }
 776 +
 777 +       return 0;
 778 +}
 779 +
 780 +late_initcall(setup_mtd);
 781 +#endif
 782 diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c
 783 --- linux.old/arch/mips/rb500/early_serial.c    1970-01-01 01:00:00.000000000 +0100
 784 +++ linux.dev/arch/mips/rb500/early_serial.c    2006-10-11 21:56:38.000000000 +0200
 785 @@ -0,0 +1,199 @@
 786 +/**************************************************************************
 787 + *
 788 + *  BRIEF MODULE DESCRIPTION
 789 + *      EB434 specific polling driver for 16550 UART.
 790 + *
 791 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 792 + *
 793 + *  This program is free software; you can redistribute  it and/or modify it
 794 + *  under  the terms of  the GNU General  Public License as published by the
 795 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 796 + *  option) any later version.
 797 + *
 798 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 799 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 800 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 801 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 802 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 803 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 804 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 805 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 806 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 807 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 808 + *
 809 + *  You should have received a copy of the  GNU General Public License along
 810 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 811 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 812 + *
 813 + *
 814 + **************************************************************************
 815 + * Copyright (C) 2000 by Lineo, Inc.
 816 + * Written by Quinn Jensen (jensenq@lineo.com)
 817 + **************************************************************************
 818 + * P. Sadik  Oct 20, 2003
 819 + *
 820 + * DIVISOR is made a function of idt_cpu_freq
 821 + **************************************************************************
 822 + * P. Sadik  Oct 30, 2003
 823 + *
 824 + * added reset_cons_port
 825 + **************************************************************************
 826 + */
 827 +
 828 +#include <linux/serial_reg.h>
 829 +
 830 +/* turn this on to watch the debug protocol echoed on the console port */
 831 +#define DEBUG_REMOTE_DEBUG
 832 +
 833 +#define CONS_BAUD 115200
 834 +
 835 +extern unsigned int idt_cpu_freq;
 836 +
 837 +#define EXT_FREQ    24000000
 838 +#define INT_FREQ    idt_cpu_freq
 839 +
 840 +#define EXT_PORT    0xb9800000u
 841 +#define EXT_SHIFT   0
 842 +
 843 +#ifdef __MIPSEB__
 844 +#define INT_PORT    0xb8058003u
 845 +#else
 846 +#define INT_PORT    0xb8058000u
 847 +#endif
 848 +#define INT_SHIFT   2
 849 +
 850 +#define INT_FCR     UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14
 851 +#define EXT_FCR     UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT
 852 +
 853 +typedef struct
 854 +{
 855 +  volatile unsigned char *base;
 856 +  unsigned int shift;
 857 +  unsigned int freq;
 858 +  unsigned int fcr;
 859 +} ser_port;
 860 +
 861 +ser_port ports[2] =
 862 +{
 863 +  { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR},
 864 +  { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR}
 865 +};
 866 +
 867 +#define CONS_PORT   0
 868 +
 869 +void cons_putc(char c);
 870 +int port_getc(int port);
 871 +void port_putc(int port, char c);
 872 +
 873 +int cons_getc(void)
 874 +{
 875 +       return port_getc(CONS_PORT);
 876 +}
 877 +
 878 +void cons_putc(char c)
 879 +{
 880 +       port_putc(CONS_PORT, c);
 881 +}
 882 +
 883 +void cons_puts(char *s)
 884 +{
 885 +       while(*s) {
 886 +               if(*s == '\n') cons_putc('\r');
 887 +               cons_putc(*s);
 888 +               s++;
 889 +       }
 890 +}
 891 +
 892 +void cons_do_putn(int n)
 893 +{
 894 +       if(n) {
 895 +               cons_do_putn(n / 10);
 896 +               cons_putc(n % 10 + '0');
 897 +       }
 898 +}
 899 +
 900 +void cons_putn(int n)
 901 +{
 902 +       if(n < 0) {
 903 +               cons_putc('-');
 904 +               n = -n;
 905 +       }
 906 +
 907 +       if (n == 0) {
 908 +               cons_putc('0');
 909 +       } else {
 910 +               cons_do_putn(n);
 911 +       }
 912 +}
 913 +
 914 +int port_getc(int p)
 915 +{
 916 +       volatile unsigned char *port = ports[p].base;
 917 +       int s = ports[p].shift;
 918 +       int c;
 919 +
 920 +       while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) {
 921 +               continue;
 922 +       }
 923 +
 924 +       c = *(port + (UART_RX << s));
 925 +
 926 +       return c;
 927 +}
 928 +
 929 +int port_getc_ready(int p)
 930 +{
 931 +       volatile unsigned char *port = ports[p].base;
 932 +       int s = ports[p].shift;
 933 +
 934 +       return *(port + (UART_LSR << s)) & UART_LSR_DR;
 935 +}
 936 +
 937 +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
 938 +
 939 +void port_putc(int p, char c)
 940 +{
 941 +       volatile unsigned char *port = ports[p].base;
 942 +       int s = ports[p].shift;
 943 +       volatile unsigned char *lsr = port + (UART_LSR << s);
 944 +
 945 +       while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
 946 +               continue;
 947 +       }
 948 +
 949 +       *(port + (UART_TX << s)) = c;
 950 +}
 951 +
 952 +void reset_cons_port(void)
 953 +{
 954 +  volatile unsigned char *port = ports[CONS_PORT].base;
 955 +  unsigned int s = ports[CONS_PORT].shift;
 956 +  unsigned int DIVISOR;
 957 +
 958 +  if (ports[CONS_PORT].freq)
 959 +    DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD);
 960 +  else
 961 +    DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
 962 +
 963 +  /* reset the port */
 964 +  *(port + (UART_CSR << s)) = 0;
 965 +
 966 +  /* clear and enable the FIFOs */
 967 +  *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr;
 968 +
 969 +  /* set the baud rate */
 970 +  *(port + (UART_LCR << s)) = UART_LCR_DLAB;         /* enable DLL, DLM registers */
 971 +
 972 +  *(port + (UART_DLL << s)) = DIVISOR;
 973 +  *(port + (UART_DLM << s)) = DIVISOR >> 8;
 974 +  /* set the line control stuff and disable DLL, DLM regs */
 975 +
 976 +  *(port + (UART_LCR << s)) = UART_LCR_STOP |        /* 2 stop bits */
 977 +    UART_LCR_WLEN8;                         /* 8 bit word length */
 978 +
 979 +  /* leave interrupts off */
 980 +  *(port + (UART_IER << s)) = 0;
 981 +
 982 +  /* the modem controls don't leave the chip on this port, so leave them alone */
 983 +  *(port + (UART_MCR << s)) = 0;
 984 +}
 985 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
 986 --- linux.old/arch/mips/rb500/irq.c     1970-01-01 01:00:00.000000000 +0100
 987 +++ linux.dev/arch/mips/rb500/irq.c     2006-10-11 21:56:38.000000000 +0200
 988 @@ -0,0 +1,264 @@
 989 +/*
 990 + * BRIEF MODULE DESCRIPTION
 991 + *     RC32434 interrupt routines.
 992 + *
 993 + * Copyright 2002 MontaVista Software Inc.
 994 + * Author: MontaVista Software, Inc.
 995 + *             stevel@mvista.com or source@mvista.com
 996 + *
 997 + *  This program is free software; you can redistribute         it and/or modify it
 998 + *  under  the terms of         the GNU General  Public License as published by the
 999 + *  Free Software Foundation;  either version 2 of the License, or (at your
1000 + *  option) any later version.
1001 + *
1002 + *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
1003 + *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
1004 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
1005 + *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
1006 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1007 + *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
1008 + *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1009 + *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR TORT
1010 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1011 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1012 + *
1013 + *  You should have received a copy of the  GNU General Public License along
1014 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1015 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1016 + */
1017 +
1018 +#include <linux/errno.h>
1019 +#include <linux/init.h>
1020 +#include <linux/kernel_stat.h>
1021 +#include <linux/module.h>
1022 +#include <linux/signal.h>
1023 +#include <linux/sched.h>
1024 +#include <linux/types.h>
1025 +#include <linux/interrupt.h>
1026 +#include <linux/ioport.h>
1027 +#include <linux/timex.h>
1028 +#include <linux/slab.h>
1029 +#include <linux/random.h>
1030 +#include <linux/delay.h>
1031 +
1032 +#include <asm/bitops.h>
1033 +#include <asm/bootinfo.h>
1034 +#include <asm/io.h>
1035 +#include <asm/irq.h>
1036 +#include <asm/time.h>
1037 +#include <asm/mipsregs.h>
1038 +#include <asm/system.h>
1039 +#include <asm/rc32434/rc32434.h>
1040 +#include <asm/rc32434/gpio.h>
1041 +
1042 +extern void set_debug_traps(void);
1043 +extern irq_cpustat_t irq_stat [NR_CPUS];
1044 +unsigned int local_bh_count[NR_CPUS];
1045 +unsigned int local_irq_count[NR_CPUS];
1046 +
1047 +static unsigned int startup_irq(unsigned int irq);
1048 +static void rb500_end_irq(unsigned int irq_nr);
1049 +static void mask_and_ack_irq(unsigned int irq_nr);
1050 +static void rb500_enable_irq(unsigned int irq_nr);
1051 +static void rb500_disable_irq(unsigned int irq_nr);
1052 +
1053 +extern void __init init_generic_irq(void);
1054 +
1055 +typedef struct {
1056 +  u32 mask;       /* mask of valid bits in pending/mask registers */
1057 +  volatile u32 *base_addr;
1058 +} intr_group_t;
1059 +
1060 +#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
1061 +
1062 +#if (NR_IRQS < RC32434_NR_IRQS)
1063 +#error Too little irqs defined. Did you override <asm/irq.h> ?
1064 +#endif
1065 +
1066 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
1067 +  { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
1068 +  { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
1069 +  { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
1070 +  { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
1071 +  { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
1072 +};
1073 +
1074 +#define READ_PEND(base) (*(base))
1075 +#define READ_MASK(base) (*(base + 2))
1076 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
1077 +
1078 +static inline int irq_to_group(unsigned int irq_nr)
1079 +{
1080 +  return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
1081 +}
1082 +
1083 +static inline int group_to_ip(unsigned int group)
1084 +{
1085 +  return group + 2;
1086 +}
1087 +
1088 +static inline void enable_local_irq(unsigned int ip)
1089 +{
1090 +  int ipnum = 0x100 << ip;
1091 +  clear_c0_cause(ipnum);
1092 +  set_c0_status(ipnum);
1093 +}
1094 +
1095 +static inline void disable_local_irq(unsigned int ip)
1096 +{
1097 +  int ipnum = 0x100 << ip;
1098 +  clear_c0_status(ipnum);
1099 +}
1100 +
1101 +static inline void ack_local_irq(unsigned int ip)
1102 +{
1103 +  int ipnum = 0x100 << ip;
1104 +  clear_c0_cause(ipnum);
1105 +}
1106 +
1107 +static void rb500_enable_irq(unsigned int irq_nr)
1108 +{
1109 +  int           ip = irq_nr - GROUP0_IRQ_BASE;
1110 +  unsigned int  group, intr_bit;
1111 +  volatile unsigned int  *addr;
1112 +
1113 +
1114 +  if (ip < 0)
1115 +    enable_local_irq(irq_nr);
1116 +  else {
1117 +    group = ip >> 5;
1118 +
1119 +    ip &= (1<<5)-1;
1120 +    intr_bit = 1 << ip;
1121 +
1122 +    enable_local_irq(group_to_ip(group));
1123 +
1124 +    addr = intr_group[group].base_addr;
1125 +    WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1126 +  }
1127 +}
1128 +
1129 +static void rb500_disable_irq(unsigned int irq_nr)
1130 +{
1131 +  int           ip = irq_nr - GROUP0_IRQ_BASE;
1132 +  unsigned int  group, intr_bit, mask;
1133 +  volatile unsigned int  *addr;
1134 +
1135 +  if (ip < 0) {
1136 +       disable_local_irq(irq_nr);
1137 +    }else{
1138 +    group = ip >> 5;
1139 +
1140 +    ip &= (1<<5) -1;
1141 +    intr_bit = 1 << ip;
1142 +    addr = intr_group[group].base_addr;
1143 +    mask = READ_MASK(addr);
1144 +    mask |= intr_bit;
1145 +    WRITE_MASK(addr,mask);
1146 +
1147 +    /*
1148 +     * if there are no more interrupts enabled in this
1149 +     * group, disable corresponding IP
1150 +     */
1151 +    if (mask == intr_group[group].mask)
1152 +      disable_local_irq(group_to_ip(group));
1153 +  }
1154 +}
1155 +
1156 +static unsigned int startup_irq(unsigned int irq_nr)
1157 +{
1158 +  rb500_enable_irq(irq_nr);
1159 +  return 0;
1160 +}
1161 +
1162 +static void shutdown_irq(unsigned int irq_nr)
1163 +{
1164 +  rb500_disable_irq(irq_nr);
1165 +  return;
1166 +}
1167 +
1168 +static void mask_and_ack_irq(unsigned int irq_nr)
1169 +{
1170 +  rb500_disable_irq(irq_nr);
1171 +  ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
1172 +}
1173 +
1174 +static void rb500_end_irq(unsigned int irq_nr)
1175 +{
1176 +
1177 +  int ip = irq_nr - GROUP0_IRQ_BASE;
1178 +  unsigned int intr_bit, group;
1179 +  volatile unsigned int *addr;
1180 +
1181 +       if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
1182 +               printk("warning: end_irq %d did not enable (%x)\n",
1183 +                       irq_nr, irq_desc[irq_nr].status);
1184 +               return;
1185 +       }
1186 +
1187 +       if (ip < 0) {
1188 +               enable_local_irq(irq_nr);
1189 +       } else {
1190 +               group = ip >> 5;
1191 +
1192 +               ip &= (1 << 5) - 1;
1193 +               intr_bit = 1 << ip;
1194 +
1195 +               if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
1196 +                       gpio->gpioistat = gpio->gpioistat & ~intr_bit;
1197 +               }
1198 +
1199 +               enable_local_irq(group_to_ip(group));
1200 +
1201 +               addr = intr_group[group].base_addr;
1202 +               WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1203 +       }
1204 +}
1205 +
1206 +static struct hw_interrupt_type rc32434_irq_type = {
1207 +  .typename = "RB500",
1208 +  .startup = startup_irq,
1209 +  .shutdown = shutdown_irq,
1210 +  .enable = rb500_enable_irq,
1211 +  .disable = rb500_disable_irq,
1212 +  .ack = mask_and_ack_irq,
1213 +  .end = rb500_end_irq,
1214 +};
1215 +
1216 +
1217 +void __init arch_init_irq(void)
1218 +{
1219 +       int i;
1220 +
1221 +       printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1222 +       memset(irq_desc, 0, sizeof(irq_desc));
1223 +
1224 +       for (i = 0; i < RC32434_NR_IRQS; i++) {
1225 +               irq_desc[i].status = IRQ_DISABLED;
1226 +               irq_desc[i].action = NULL;
1227 +               irq_desc[i].depth = 1;
1228 +               irq_desc[i].handler = &rc32434_irq_type;
1229 +               spin_lock_init(&irq_desc[i].lock);
1230 +       }
1231 +}
1232 +
1233 +/* Main Interrupt dispatcher */
1234 +asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
1235 +{
1236 +       unsigned int ip, pend, group;
1237 +       volatile unsigned int *addr;
1238 +       unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1239 +
1240 +       if (cp0_cause & CAUSEF_IP7) {
1241 +               ll_timer_interrupt(7, regs);
1242 +       } else if ((ip = (cp0_cause & 0x7c00))) {
1243 +               group = 21 - rc32434_clz(ip);
1244 +
1245 +               addr = intr_group[group].base_addr;
1246 +
1247 +               pend = READ_PEND(addr);
1248 +               pend &= ~READ_MASK(addr); // only unmasked interrupts
1249 +               pend = 39 - rc32434_clz(pend);
1250 +               do_IRQ((group << 5) + pend, regs);
1251 +       }
1252 +}
1253 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1254 --- linux.old/arch/mips/rb500/Makefile  1970-01-01 01:00:00.000000000 +0100
1255 +++ linux.dev/arch/mips/rb500/Makefile  2006-10-11 21:56:38.000000000 +0200
1256 @@ -0,0 +1,5 @@
1257 +#
1258 +# Makefile for the RB500 board specific parts of the kernel
1259 +#
1260 +
1261 +obj-y   += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o
1262 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1263 --- linux.old/arch/mips/rb500/misc.c    1970-01-01 01:00:00.000000000 +0100
1264 +++ linux.dev/arch/mips/rb500/misc.c    2006-10-11 21:56:38.000000000 +0200
1265 @@ -0,0 +1,54 @@
1266 +#include <linux/module.h>
1267 +#include <linux/kernel.h>   /* printk() */
1268 +#include <linux/types.h>    /* size_t */
1269 +#include <linux/pci.h>
1270 +#include <linux/spinlock.h>
1271 +#include <asm/rc32434/rb.h>
1272 +
1273 +#define GPIO_BADDR  0xb8050000
1274 +
1275 +
1276 +static unsigned char *devCtl3Base = (unsigned char *) KSEG1ADDR(0x18010030);
1277 +static unsigned char latchU5State = 0;
1278 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1279 +
1280 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1281 +    unsigned flags, data;
1282 +    unsigned i = 0;
1283 +    spin_lock_irqsave(&clu5Lock, flags);
1284 +    data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1285 +    for (i = 0; i != len; ++i) {
1286 +       if (val & (1 << i)) data |= (1 << (i + bit));
1287 +       else data &= ~(1 << (i + bit));
1288 +    }
1289 +    *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1290 +    spin_unlock_irqrestore(&clu5Lock, flags);
1291 +}
1292 +
1293 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1294 +    unsigned flags;
1295 +    spin_lock_irqsave(&clu5Lock, flags);
1296 +    latchU5State = (latchU5State | orMask) & ~nandMask;
1297 +    *devCtl3Base = latchU5State;
1298 +    spin_unlock_irqrestore(&clu5Lock, flags);
1299 +}
1300 +
1301 +u32 gpio_get(gpio_func func)
1302 +{
1303 +       return readl((void *) GPIO_BADDR + func);
1304 +}
1305 +
1306 +void gpio_set(gpio_func func, u32 mask, u32 value)
1307 +{
1308 +       u32 val = readl((void *) GPIO_BADDR + func);
1309 +
1310 +       val &= ~mask;
1311 +       val |= value & mask;
1312 +
1313 +       writel(val, (void *) GPIO_BADDR + func);
1314 +}
1315 +
1316 +EXPORT_SYMBOL(gpio_set);
1317 +EXPORT_SYMBOL(gpio_get);
1318 +EXPORT_SYMBOL(set434Reg);
1319 +EXPORT_SYMBOL(changeLatchU5);
1320 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1321 --- linux.old/arch/mips/rb500/prom.c    1970-01-01 01:00:00.000000000 +0100
1322 +++ linux.dev/arch/mips/rb500/prom.c    2006-10-11 21:56:38.000000000 +0200
1323 @@ -0,0 +1,181 @@
1324 +/*
1325 +* prom.c
1326 +**********************************************************************
1327 +* P . Sadik Oct 10, 2003
1328 +*
1329 +* Started change log
1330 +* idt_cpu_freq is make a kernel configuration parameter
1331 +* idt_cpu_freq is exported so that other modules can use it.
1332 +* Code cleanup
1333 +**********************************************************************
1334 +* P. Sadik Oct 20, 2003
1335 +*
1336 +* Removed NVRAM code from here, since they are already available under
1337 +* nvram directory.
1338 +* Added serial port initialisation.
1339 +**********************************************************************
1340 +**********************************************************************
1341 +* P. Sadik Oct 30, 2003
1342 +*
1343 +* Added reset_cons_port
1344 +**********************************************************************
1345 +
1346 +  P.Christeas, 2005-2006
1347 +  Port to 2.6, add 2.6 cmdline parsing
1348 +
1349 +*/
1350 +
1351 +#include <linux/config.h>
1352 +#include <linux/init.h>
1353 +#include <linux/mm.h>
1354 +#include <linux/module.h>
1355 +#include <linux/string.h>
1356 +#include <linux/console.h>
1357 +#include <asm/bootinfo.h>
1358 +#include <linux/bootmem.h>
1359 +#include <linux/ioport.h>
1360 +#include <linux/blkdev.h>
1361 +#include <asm/rc32434/ddr.h>
1362 +
1363 +#define PROM_ENTRY(x)   (0xbfc00000+((x)*8))
1364 +extern void __init setup_serial_port(void);
1365 +extern void cons_putc(char c);
1366 +extern void cons_puts(char *s);
1367 +
1368 +unsigned int idt_cpu_freq = 132000000;
1369 +EXPORT_SYMBOL(idt_cpu_freq);
1370 +unsigned int board_type = 500;
1371 +EXPORT_SYMBOL(board_type);
1372 +unsigned int gpio_bootup_state = 0;
1373 +EXPORT_SYMBOL(gpio_bootup_state);
1374 +
1375 +
1376 +char mips_mac_address[18] = "08:00:06:05:40:01";
1377 +EXPORT_SYMBOL(mips_mac_address);
1378 +
1379 +/* what to append to cmdline when button is [not] pressed */
1380 +#define GPIO_INIT_NOBUTTON ""
1381 +#define GPIO_INIT_BUTTON   " 2"
1382 +
1383 +#ifdef CONFIG_MIKROTIK_RB500
1384 +unsigned soft_reboot = 0;
1385 +EXPORT_SYMBOL(soft_reboot);
1386 +#endif
1387 +
1388 +#define SR_NMI                 0x00180000      /* NMI */
1389 +#define SERIAL_SPEED_ENTRY     0x00000001
1390 +
1391 +#ifdef CONFIG_REMOTE_DEBUG
1392 +extern int remote_debug;
1393 +#endif
1394 +
1395 +extern unsigned long mips_machgroup;
1396 +extern unsigned long mips_machtype;
1397 +
1398 +#define FREQ_TAG   "HZ="
1399 +#define GPIO_TAG   "gpio="
1400 +#define KMAC_TAG   "kmac="
1401 +#define MEM_TAG           "mem="
1402 +#define BOARD_TAG  "board="
1403 +#define IGNORE_CMDLINE_MEM 1
1404 +#define DEBUG_DDR
1405 +
1406 +void parse_soft_settings(unsigned *ptr, unsigned size);
1407 +void parse_hard_settings(unsigned *ptr, unsigned size);
1408 +
1409 +void __init prom_setup_cmdline(void);
1410 +
1411 +#ifdef DEBUG_DDR
1412 +void cons_puthex4(u32 h){
1413 +       h&=0x0f;
1414 +       if (h>=10)
1415 +               cons_putc((h-10)+'a');
1416 +       else
1417 +               cons_putc(h+'0');
1418 +}
1419 +
1420 +void cons_putreg32(u32 reg){
1421 +       char c;
1422 +       cons_putc('0');
1423 +       cons_putc('x');
1424 +       for (c=28;c>=0;c-=4)
1425 +               cons_puthex4(reg>>c);
1426 +}
1427 +#endif
1428 +
1429 +void __init prom_init(void)
1430 +{
1431 +       DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1432 +       phys_t memsize = 0-ddr->ddrmask;
1433 +
1434 +       /* this should be the very first message, even before serial is properly initialized */
1435 +       prom_setup_cmdline();
1436 +       setup_serial_port();
1437 +
1438 +       mips_machgroup = MACH_GROUP_MIKROTIK;
1439 +       soft_reboot = read_c0_status() & SR_NMI;
1440 +       pm_power_off = NULL;
1441 +
1442 +       /*
1443 +        * give all RAM to boot allocator,
1444 +        * except for the first 0x400 and the last 0x200 bytes
1445 +        */
1446 +       add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1447 +}
1448 +
1449 +void prom_free_prom_memory(void)
1450 +{
1451 +       /* FIXME: STUB */
1452 +}
1453 +
1454 +void __init prom_setup_cmdline(void){
1455 +       char cmd_line[CL_SIZE];
1456 +       char *cp;
1457 +       int prom_argc;
1458 +       char **prom_argv, **prom_envp;
1459 +       int i;
1460 +
1461 +       prom_argc = fw_arg0;
1462 +       prom_argv = (char **) fw_arg1;
1463 +       prom_envp = (char **) fw_arg2;
1464 +
1465 +       cp=cmd_line;
1466 +               /* Note: it is common that parameters start at argv[1] and not argv[0],
1467 +               however, our elf loader starts at [0] */
1468 +       for(i=0;i<prom_argc;i++){
1469 +               if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1470 +                       idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1471 +                       continue;
1472 +               }
1473 +#ifdef IGNORE_CMDLINE_MEM
1474 +               /* parses out the "mem=xx" arg */
1475 +               if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1476 +                       continue;
1477 +               }
1478 +#endif
1479 +               if (i>0) *(cp++) = ' ';
1480 +               if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1481 +                       board_type =  simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1482 +               }
1483 +               if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1484 +                       gpio_bootup_state =  simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1485 +               }
1486 +               strcpy(cp,prom_argv[i]);
1487 +               cp+=strlen(prom_argv[i]);
1488 +       }
1489 +
1490 +       i=strlen(arcs_cmdline);
1491 +       if (i>0){
1492 +               *(cp++) = ' ';
1493 +               strcpy(cp,arcs_cmdline);
1494 +               cp+=strlen(arcs_cmdline);
1495 +       }
1496 +       if (gpio_bootup_state&0x02)
1497 +               strcpy(cp,GPIO_INIT_NOBUTTON);
1498 +       else
1499 +               strcpy(cp,GPIO_INIT_BUTTON);
1500 +       cmd_line[CL_SIZE-1] = '\0';
1501 +
1502 +       strcpy(arcs_cmdline,cmd_line);
1503 +}
1504 +
1505 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1506 --- linux.old/arch/mips/rb500/serial.c  1970-01-01 01:00:00.000000000 +0100
1507 +++ linux.dev/arch/mips/rb500/serial.c  2006-10-11 21:56:38.000000000 +0200
1508 @@ -0,0 +1,79 @@
1509 +/**************************************************************************
1510 + *
1511 + *  BRIEF MODULE DESCRIPTION
1512 + *     Serial port initialisation.
1513 + *
1514 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
1515 + *
1516 + *  This program is free software; you can redistribute  it and/or modify it
1517 + *  under  the terms of  the GNU General  Public License as published by the
1518 + *  Free Software Foundation;  either version 2 of the  License, or (at your
1519 + *  option) any later version.
1520 + *
1521 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
1522 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
1523 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
1524 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
1525 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1526 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
1527 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1528 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
1529 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1530 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1531 + *
1532 + *  You should have received a copy of the  GNU General Public License along
1533 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1534 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1535 + *
1536 + *
1537 + **************************************************************************
1538 + * May 2004 rkt, neb
1539 + *
1540 + * Initial Release
1541 + *
1542 + *
1543 + *
1544 + **************************************************************************
1545 + */
1546 +
1547 +
1548 +#include <linux/config.h>
1549 +#include <linux/init.h>
1550 +#include <linux/sched.h>
1551 +#include <linux/pci.h>
1552 +#include <linux/interrupt.h>
1553 +#include <linux/tty.h>
1554 +#include <linux/serial.h>
1555 +#include <linux/serial_core.h>
1556 +
1557 +#include <asm/time.h>
1558 +#include <asm/cpu.h>
1559 +#include <asm/bootinfo.h>
1560 +#include <asm/irq.h>
1561 +#include <asm/serial.h>
1562 +#include <asm/rc32434/rc32434.h>
1563 +
1564 +extern unsigned int idt_cpu_freq;
1565 +
1566 +static struct uart_port serial_req = {
1567 +       .type = PORT_16550A,
1568 +       .line = 0,
1569 +       .irq = RC32434_UART0_IRQ,
1570 +       .flags = STD_COM_FLAGS,
1571 +       .iotype = UPIO_MEM,
1572 +       .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1573 +//     .fifosize = 14
1574 +       .regshift = 2
1575 +};
1576 +
1577 +int __init setup_serial_port(void)
1578 +{
1579 +       serial_req.uartclk = idt_cpu_freq;
1580 +
1581 +       if (early_serial_setup(&serial_req)){
1582 +               cons_puts("Serial setup failed!\n");
1583 +               return -ENODEV;
1584 +       }
1585 +
1586 +       return(0);
1587 +}
1588 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1589 --- linux.old/arch/mips/rb500/setup.c   1970-01-01 01:00:00.000000000 +0100
1590 +++ linux.dev/arch/mips/rb500/setup.c   2006-10-11 21:56:38.000000000 +0200
1591 @@ -0,0 +1,84 @@
1592 +/*
1593 + * setup.c - boot time setup code
1594 + */
1595 +
1596 +#include <linux/init.h>
1597 +#include <linux/mm.h>
1598 +#include <linux/sched.h>
1599 +#include <linux/irq.h>
1600 +#include <asm/bootinfo.h>
1601 +#include <asm/io.h>
1602 +#include <linux/ioport.h>
1603 +#include <asm/mipsregs.h>
1604 +#include <asm/pgtable.h>
1605 +#include <asm/reboot.h>
1606 +#include <asm/addrspace.h>     /* for KSEG1ADDR() */
1607 +#include <asm/rc32434/rc32434.h>
1608 +#include <linux/pm.h>
1609 +#include <asm/rc32434/pci.h>
1610 +
1611 +extern void (*board_time_init)(void);
1612 +extern void (*board_timer_setup)(struct irqaction *irq);
1613 +extern void rc32434_time_init(void);
1614 +extern void rc32434_timer_setup(struct irqaction *irq);
1615 +#ifdef CONFIG_PCI
1616 +extern int __init rc32434_pcibridge_init(void);
1617 +#endif
1618 +
1619 +#define epldMask ((volatile unsigned char *)0xB900000d)
1620 +
1621 +static void rb_machine_restart(char *command)
1622 +{
1623 +       /* just jump to the reset vector */
1624 +       * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1625 +       ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1626 +}
1627 +
1628 +static void rb_machine_halt(void)
1629 +{
1630 +       for(;;) continue;
1631 +}
1632 +
1633 +#ifdef CONFIG_CPU_HAS_WB
1634 +void (*__wbflush) (void);
1635 +
1636 +static void rb_write_buffer_flush(void)
1637 +{
1638 +       __asm__ __volatile__
1639 +           ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1640 +}
1641 +#endif
1642 +
1643 +void __init plat_setup(void)
1644 +{
1645 +       unsigned int pciCntlVal;
1646 +
1647 +       board_time_init = rc32434_time_init;
1648 +       board_timer_setup = rc32434_timer_setup;
1649 +
1650 +#ifdef CONFIG_CPU_HAS_WB
1651 +       __wbflush = rb_write_buffer_flush;
1652 +#endif
1653 +       _machine_restart = rb_machine_restart;
1654 +       _machine_halt = rb_machine_halt;
1655 +       /*_machine_power_off = rb_machine_power_halt;*/
1656 +       pm_power_off = rb_machine_halt;
1657 +
1658 +       set_io_port_base(KSEG1);
1659 +
1660 +       pciCntlVal=rc32434_pci->pcic;
1661 +       pciCntlVal &= 0xFFFFFF7;
1662 +       rc32434_pci->pcic = pciCntlVal;
1663 +
1664 +#ifdef CONFIG_PCI
1665 +       /* Enable PCI interrupts in EPLD Mask register */
1666 +       *epldMask = 0x0;
1667 +       *(epldMask + 1) = 0x0;
1668 +#endif
1669 +       write_c0_wired(0);
1670 +}
1671 +
1672 +const char *get_system_type(void)
1673 +{
1674 +       return "MIPS RB500";
1675 +}
1676 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1677 --- linux.old/arch/mips/rb500/time.c    1970-01-01 01:00:00.000000000 +0100
1678 +++ linux.dev/arch/mips/rb500/time.c    2006-10-11 21:56:38.000000000 +0200
1679 @@ -0,0 +1,94 @@
1680 +/*
1681 +****************************************************************************
1682 +* Carsten Langgaard, carstenl@mips.com
1683 +* Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1684 +*
1685 +***************************************************************************
1686 +*
1687 +*  This program is free software; you can distribute it and/or modify it
1688 +*  under the terms of the GNU General Public License (Version 2) as
1689 +*  published by the Free Software Foundation.
1690 +*
1691 +*  This program is distributed in the hope it will be useful, but WITHOUT
1692 +*  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1693 +*  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1694 +*  for more details.
1695 +*
1696 +*  You should have received a copy of the GNU General Public License along
1697 +*  with this program; if not, write to the Free Software Foundation, Inc.,
1698 +*  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1699 +*
1700 +****************************************************************************
1701 +*
1702 +* Setting up the clock on the MIPS boards.
1703 +*
1704 +****************************************************************************
1705 +* P. Sadik Oct 10, 2003
1706 +*
1707 +* Started change log.
1708 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1709 +* Code cleanup
1710 +****************************************************************************
1711 +*/
1712 +
1713 +#include <linux/config.h>
1714 +#include <linux/init.h>
1715 +#include <linux/kernel_stat.h>
1716 +#include <linux/sched.h>
1717 +#include <linux/spinlock.h>
1718 +#include <linux/mc146818rtc.h>
1719 +#include <linux/irq.h>
1720 +#include <linux/timex.h>
1721 +
1722 +#include <asm/mipsregs.h>
1723 +#include <asm/ptrace.h>
1724 +#include <asm/debug.h>
1725 +#include <asm/rc32434/rc32434.h>
1726 +
1727 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1728 +static unsigned long r4k_cur;    /* What counter should be at next timer irq */
1729 +extern void ll_timer_interrupt(int irq, struct pt_regs *regs);
1730 +extern unsigned int mips_hpt_frequency;
1731 +extern unsigned int idt_cpu_freq;
1732 +
1733 +/*
1734 + * Figure out the r4k offset, the amount to increment the compare
1735 + * register for each time tick. There is no RTC available.
1736 + *
1737 + * The RC32434 counts at half the CPU *core* speed.
1738 + */
1739 +static unsigned long __init cal_r4koff(void)
1740 +{
1741 +       mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1742 +       return (mips_hpt_frequency / HZ);
1743 +}
1744 +
1745 +
1746 +void __init rc32434_time_init(void)
1747 +{
1748 +       unsigned int est_freq, flags;
1749 +
1750 +       local_irq_save(flags);
1751 +
1752 +       printk("calculating r4koff... ");
1753 +       r4k_offset = cal_r4koff();
1754 +       printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1755 +
1756 +       est_freq = 2*r4k_offset*HZ;
1757 +       est_freq += 5000;       /* round */
1758 +       est_freq -= est_freq%10000;
1759 +       printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1760 +              (est_freq%1000000)*100/1000000);
1761 +       local_irq_restore(flags);
1762 +}
1763 +
1764 +void __init rc32434_timer_setup(struct irqaction *irq)
1765 +{
1766 +       /* we are using the cpu counter for timer interrupts */
1767 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1768 +
1769 +       /* to generate the first timer interrupt */
1770 +       r4k_cur = (read_c0_count() + r4k_offset);
1771 +       write_c0_compare(r4k_cur);
1772 +}
1773 +
1774 diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c
1775 --- linux.old/drivers/mtd/devices/block2mtd.c   2006-10-11 21:55:59.000000000 +0200
1776 +++ linux.dev/drivers/mtd/devices/block2mtd.c   2006-10-11 22:24:51.000000000 +0200
1777 @@ -26,7 +26,6 @@
1778  #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
1779  #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
1780
1781 -
1782  /* Info for the block device */
1783  struct block2mtd_dev {
1784         struct list_head list;
1785 @@ -104,7 +103,7 @@
1786
1787         while (pages) {
1788                 page = page_readahead(mapping, index);
1789 -               if (!page)
1790 +               if (!page || !page_address(page))
1791                         return -ENOMEM;
1792                 if (IS_ERR(page))
1793                         return PTR_ERR(page);
1794 @@ -285,7 +284,7 @@
1795
1796
1797  /* FIXME: ensure that mtd->size % erase_size == 0 */
1798 -static struct block2mtd_dev *add_device(char *devname, int erase_size)
1799 +static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias)
1800  {
1801         struct block_device *bdev;
1802         struct block2mtd_dev *dev;
1803 @@ -328,14 +327,15 @@
1804
1805         /* Setup the MTD structure */
1806         /* make the name contain the block device in */
1807 -       dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname),
1808 +       dev->mtd.name = kmalloc(strlen((alias ?: devname)),
1809                         GFP_KERNEL);
1810         if (!dev->mtd.name)
1811                 goto devinit_err;
1812
1813 -       sprintf(dev->mtd.name, "block2mtd: %s", devname);
1814 +       strcpy(dev->mtd.name, (alias ?: devname));
1815
1816         dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
1817 +       dev->mtd.size -= dev->mtd.size % erase_size;
1818         dev->mtd.erasesize = erase_size;
1819         dev->mtd.type = MTD_RAM;
1820         dev->mtd.flags = MTD_CAP_RAM;
1821 @@ -353,7 +353,7 @@
1822         }
1823         list_add(&dev->list, &blkmtd_device_list);
1824         INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index,
1825 -                       dev->mtd.name + strlen("blkmtd: "),
1826 +                       dev->mtd.name,
1827                         dev->mtd.erasesize >> 10, dev->mtd.erasesize);
1828         return dev;
1829
1830 @@ -429,7 +429,7 @@
1831  {
1832         char buf[80 + 12]; /* 80 for device, 12 for erase size */
1833         char *str = buf;
1834 -       char *token[2];
1835 +       char *token[3];
1836         char *name;
1837         size_t erase_size = PAGE_SIZE;
1838         int i, ret;
1839 @@ -440,7 +440,7 @@
1840         strcpy(str, val);
1841         kill_final_newline(str);
1842
1843 -       for (i = 0; i < 2; i++)
1844 +       for (i = 0; i < 3; i++)
1845                 token[i] = strsep(&str, ",");
1846
1847         if (str)
1848 @@ -461,13 +461,13 @@
1849                 }
1850         }
1851
1852 -       add_device(name, erase_size);
1853 +       add_device(name, erase_size, token[2]);
1854
1855         return 0;
1856  }
1857
1858
1859 -static int block2mtd_setup(const char *val, struct kernel_param *kp)
1860 +int block2mtd_setup(const char *val, struct kernel_param *kp)
1861  {
1862  #ifdef MODULE
1863         return block2mtd_setup2(val);
1864 @@ -496,6 +496,7 @@
1865
1866  module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
1867  MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
1868 +EXPORT_SYMBOL(block2mtd_setup);
1869
1870  static int __init block2mtd_init(void)
1871  {
1872 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1873 --- linux.old/drivers/pci/Makefile      2006-06-18 03:49:35.000000000 +0200
1874 +++ linux.dev/drivers/pci/Makefile      2006-10-11 21:56:38.000000000 +0200
1875 @@ -27,6 +27,7 @@
1876  obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
1877  obj-$(CONFIG_X86_VISWS) += setup-irq.o
1878  obj-$(CONFIG_PCI_MSI) += msi.o
1879 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1880
1881  #
1882  # ACPI Related PCI FW Functions
1883 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1884 --- linux.old/include/asm-mips/bootinfo.h       2006-06-18 03:49:35.000000000 +0200
1885 +++ linux.dev/include/asm-mips/bootinfo.h       2006-10-11 21:56:38.000000000 +0200
1886 @@ -218,6 +218,8 @@
1887  #define MACH_GROUP_TITAN       22      /* PMC-Sierra Titan             */
1888  #define  MACH_TITAN_YOSEMITE   1       /* PMC-Sierra Yosemite          */
1889
1890 +#define MACH_GROUP_MIKROTIK    24 /* Mikrotik Boards                       */
1891 +
1892  #define CL_SIZE                        COMMAND_LINE_SIZE
1893
1894  const char *get_system_type(void);
1895 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1896 --- linux.old/include/asm-mips/cpu.h    2006-06-18 03:49:35.000000000 +0200
1897 +++ linux.dev/include/asm-mips/cpu.h    2006-10-11 21:56:38.000000000 +0200
1898 @@ -200,7 +200,8 @@
1899  #define CPU_SB1A               62
1900  #define CPU_74K                        63
1901  #define CPU_R14000             64
1902 -#define CPU_LAST               64
1903 +#define CPU_RC32300            65
1904 +#define CPU_LAST               65
1905
1906  /*
1907   * ISA Level encodings
1908 diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h
1909 --- linux.old/include/asm-mips/rc32434/crom.h   1970-01-01 01:00:00.000000000 +0100
1910 +++ linux.dev/include/asm-mips/rc32434/crom.h   2006-10-11 21:56:38.000000000 +0200
1911 @@ -0,0 +1,98 @@
1912 +#ifndef __IDT_CROM_H__
1913 +#define __IDT_CROM_H__
1914 +
1915 +/*******************************************************************************
1916 + *
1917 + * Copyright 2002 Integrated Device Technology, Inc.
1918 + *             All rights reserved.
1919 + *
1920 + * Configuration ROM register definitions.
1921 + *
1922 + * File   : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1923 + *
1924 + * Author : Allen.Stichter@idt.com
1925 + * Date   : 20020118
1926 + * Update :
1927 + *         $Log: crom.h,v $
1928 + *         Revision 1.2  2002/06/06 18:34:03  astichte
1929 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
1930 + *
1931 + *         Revision 1.1  2002/05/29 17:33:21  sysarch
1932 + *         jba File moved from vcode/include/idt/acacia
1933 + *
1934 + *
1935 + ******************************************************************************/
1936 +
1937 +#include  <asm/rc32434/types.h>
1938 +
1939 +enum
1940 +{
1941 +       CROM0_PhysicalAddress   = 0x100b8000,
1942 +       CROM_PhysicalAddress    = CROM0_PhysicalAddress,
1943 +
1944 +       CROM0_VirtualAddress    = 0xb00b8000,
1945 +       CROM_VirtualAddress     = CROM0_VirtualAddress,
1946 +} ;
1947 +
1948 +typedef struct CROM_s
1949 +{
1950 +       U32     cromw0 ;                // use CROMW0_
1951 +       U32     cromw1 ;                // use CROMW1_
1952 +       U32     cromw2 ;                // use CROMW2_
1953 +} volatile * CROM_t ;
1954 +
1955 +enum
1956 +{
1957 +       CROMW0_xloc_b   = 0,
1958 +       CROMW0_xloc_m   = 0x0000003f,
1959 +       CROMW0_yloc_b   = 8,
1960 +       CROMW0_yloc_m   = 0x00003f00,
1961 +       CROMW0_speed_b  = 16,
1962 +       CROMW0_speed_m  = 0x01ff0000,
1963 +       CROMW1_wafer_b  = 0,
1964 +       CROMW1_wafer_m  = 0x0000001f,
1965 +       CROMW1_lot_b    = 8,
1966 +       CROMW1_lot_m    = 0x0fffff00,
1967 +       CROMW1_fab_b    = 28,
1968 +       CROMW1_fab_m    = 0xf0000000,
1969 +       CROMW2_pci_b    = 0,
1970 +       CROMW2_pci_m    = 0x00000001,
1971 +       CROMW2_eth0_b   = 1,
1972 +       CROMW2_eth0_m   = 0x00000002,
1973 +       CROMW2_eth1_b   = 2,
1974 +       CROMW2_eth1_m   = 0x00000004
1975 +       CROMW2_i2c_b    = 3,
1976 +       CROMW2_i2c_m    = 0x00000008,
1977 +       CROMW2_rng_b    = 4,
1978 +       CROMW2_rng_m    = 0x00000010,
1979 +       CROMW2_se_b     = 5,
1980 +       CROMW2_se_m     = 0x00000020,
1981 +       CROMW2_des_b    = 6,
1982 +       CROMW2_des_m    = 0x00000040,
1983 +       CROMW2_tdes_b   = 7,
1984 +       CROMW2_tdes_m   = 0x00000080,
1985 +       CROMW2_a128_b   = 8,
1986 +       CROMW2_a128_m   = 0x00000100,
1987 +       CROMW2_a192_b   = 9,
1988 +       CROMW2_a192_m   = 0x00000200,
1989 +       CROMW2_a256_b   = 10,
1990 +       CROMW2_a256_m   = 0x00000400,
1991 +       CROMW2_md5_b    = 11,
1992 +       CROMW2_md5_m    = 0x00000800,
1993 +       CROMW2_s1_b     = 12,
1994 +       CROMW2_s1_m     = 0x00001000,
1995 +       CROMW2_s256_b   = 13,
1996 +       CROMW2_s256_m   = 0x00002000,
1997 +       CROMW2_pka_b    = 14,
1998 +       CROMW2_pka_m    = 0x00004000,
1999 +       CROMW2_exp_b    = 15,
2000 +       CROMW2_exp_m    = 0x00018000,
2001 +               CROMW2_exp_8192_v       = 0,
2002 +               CROMW2_exp_1536_v       = 1,
2003 +               CROMW2_exp_1024_v       = 2,
2004 +               CROMW2_exp_512_v        = 3,
2005 +       CROMW2_rocfg_b  = 17,
2006 +       CROMW2_rocfg_m  = 0x000e0000,
2007 +} ;
2008 +
2009 +#endif // __IDT_CROM_H__
2010 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
2011 --- linux.old/include/asm-mips/rc32434/ddr.h    1970-01-01 01:00:00.000000000 +0100
2012 +++ linux.dev/include/asm-mips/rc32434/ddr.h    2006-10-11 21:56:38.000000000 +0200
2013 @@ -0,0 +1,175 @@
2014 +#ifndef __IDT_DDR_H__
2015 +#define __IDT_DDR_H__
2016 +
2017 +/*******************************************************************************
2018 + *
2019 + * Copyright 2002 Integrated Device Technology, Inc.
2020 + *             All rights reserved.
2021 + *
2022 + * DDR register definition.
2023 + *
2024 + * File   : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2025 + *
2026 + * Author : ryan.holmQVist@idt.com
2027 + * Date   : 20011005
2028 + * Update :
2029 + *          $Log: ddr.h,v $
2030 + *          Revision 1.2  2002/06/06 18:34:03  astichte
2031 + *          Added XXX_PhysicalAddress and XXX_VirtualAddress
2032 + *
2033 + *          Revision 1.1  2002/05/29 17:33:21  sysarch
2034 + *          jba File moved from vcode/include/idt/acacia
2035 + *
2036 + *
2037 + ******************************************************************************/
2038 +
2039 +#include  <asm/rc32434/types.h>
2040 +
2041 +enum
2042 +{
2043 +       DDR0_PhysicalAddress    = 0x18018000,
2044 +       DDR_PhysicalAddress     = DDR0_PhysicalAddress,         // Default
2045 +
2046 +       DDR0_VirtualAddress     = 0xb8018000,
2047 +       DDR_VirtualAddress      = DDR0_VirtualAddress,          // Default
2048 +} ;
2049 +
2050 +typedef struct DDR_s
2051 +{
2052 +       U32     ddrbase ;
2053 +       U32     ddrmask ;
2054 +       U32     res1;
2055 +       U32     res2;
2056 +       U32     ddrc ;
2057 +       U32     ddrabase ;
2058 +       U32     ddramask ;
2059 +       U32     ddramap ;
2060 +       U32     ddrcust;
2061 +       U32     ddrrdc;
2062 +       U32     ddrspare;
2063 +} volatile *DDR_t ;
2064 +
2065 +enum
2066 +{
2067 +       DDR0BASE_baseaddr_b     = 16,
2068 +       DDR0BASE_baseaddr_m     = 0xffff0000,
2069 +
2070 +       DDR0MASK_mask_b         = 16,
2071 +       DDR0MASK_mask_m         = 0xffff0000,
2072 +
2073 +       DDR1BASE_baseaddr_b     = 16,
2074 +       DDR1BASE_baseaddr_m     = 0xffff0000,
2075 +
2076 +       DDR1MASK_mask_b         = 16,
2077 +       DDR1MASK_mask_m         = 0xffff0000,
2078 +
2079 +       DDRC_ata_b              = 5,
2080 +       DDRC_ata_m              = 0x000000E0,
2081 +       DDRC_dbw_b              = 8,
2082 +       DDRC_dbw_m              = 0x00000100,
2083 +       DDRC_wr_b               = 9,
2084 +       DDRC_wr_m               = 0x00000600,
2085 +       DDRC_ps_b               = 11,
2086 +       DDRC_ps_m               = 0x00001800,
2087 +       DDRC_dtype_b            = 13,
2088 +       DDRC_dtype_m            = 0x0000e000,
2089 +       DDRC_rfc_b              = 16,
2090 +       DDRC_rfc_m              = 0x000f0000,
2091 +       DDRC_rp_b               = 20,
2092 +       DDRC_rp_m               = 0x00300000,
2093 +       DDRC_ap_b               = 22,
2094 +       DDRC_ap_m               = 0x00400000,
2095 +       DDRC_rcd_b              = 23,
2096 +       DDRC_rcd_m              = 0x01800000,
2097 +       DDRC_cl_b               = 25,
2098 +       DDRC_cl_m               = 0x06000000,
2099 +       DDRC_dbm_b              = 27,
2100 +       DDRC_dbm_m              = 0x08000000,
2101 +       DDRC_sds_b              = 28,
2102 +       DDRC_sds_m              = 0x10000000,
2103 +       DDRC_atp_b              = 29,
2104 +       DDRC_atp_m              = 0x60000000,
2105 +       DDRC_re_b               = 31,
2106 +       DDRC_re_m               = 0x80000000,
2107 +
2108 +       DDRRDC_ces_b            = 0,
2109 +       DDRRDC_ces_m            = 0x00000001,
2110 +       DDRRDC_ace_b            = 1,
2111 +       DDRRDC_ace_m            = 0x00000002,
2112 +
2113 +       DDRABASE_baseaddr_b     = 16,
2114 +       DDRABASE_baseaddr_m     = 0xffff0000,
2115 +
2116 +       DDRAMASK_mask_b         = 16,
2117 +       DDRAMASK_mask_m         = 0xffff0000,
2118 +
2119 +       DDRAMAP_map_b           = 16,
2120 +       DDRAMAP_map_m           = 0xffff0000,
2121 +
2122 +       DDRCUST_cs_b            = 0,
2123 +       DDRCUST_cs_m            = 0x00000003,
2124 +       DDRCUST_we_b            = 2,
2125 +       DDRCUST_we_m            = 0x00000004,
2126 +       DDRCUST_ras_b           = 3,
2127 +       DDRCUST_ras_m           = 0x00000008,
2128 +       DDRCUST_cas_b           = 4,
2129 +       DDRCUST_cas_m           = 0x00000010,
2130 +       DDRCUST_cke_b           = 5,
2131 +       DDRCUST_cke_m           = 0x00000020,
2132 +       DDRCUST_ba_b            = 6,
2133 +       DDRCUST_ba_m            = 0x000000c0,
2134 +
2135 +       RCOUNT_rcount_b         = 0,
2136 +       RCOUNT_rcount_m         = 0x0000ffff,
2137 +
2138 +       RCOMPARE_rcompare_b     = 0,
2139 +       RCOMPARE_rcompare_m     = 0x0000ffff,
2140 +
2141 +       RTC_ce_b                = 0,
2142 +       RTC_ce_m                = 0x00000001,
2143 +       RTC_to_b                = 1,
2144 +       RTC_to_m                = 0x00000002,
2145 +       RTC_rqe_b               = 2,
2146 +       RTC_rqe_m               = 0x00000004,
2147 +
2148 +       DDRDQSC_dm_b            = 0,
2149 +       DDRDQSC_dm_m            = 0x00000003,
2150 +       DDRDQSC_dqsbs_b         = 2,
2151 +       DDRDQSC_dqsbs_m         = 0x000000fc,
2152 +       DDRDQSC_db_b            = 8,
2153 +       DDRDQSC_db_m            = 0x00000100,
2154 +       DDRDQSC_dbsp_b          = 9,
2155 +       DDRDQSC_dbsp_m          = 0x01fffe00,
2156 +       DDRDQSC_bdp_b           = 25,
2157 +       DDRDQSC_bdp_m           = 0x7e000000,
2158 +
2159 +       DDRDLLC_eao_b           = 0,
2160 +       DDRDLLC_eao_m           = 0x00000001,
2161 +       DDRDLLC_eo_b            = 1,
2162 +       DDRDLLC_eo_m            = 0x0000003e,
2163 +       DDRDLLC_fs_b            = 6,
2164 +       DDRDLLC_fs_m            = 0x000000c0,
2165 +       DDRDLLC_as_b            = 8,
2166 +       DDRDLLC_as_m            = 0x00000700,
2167 +       DDRDLLC_sp_b            = 11,
2168 +       DDRDLLC_sp_m            = 0x001ff800,
2169 +
2170 +       DDRDLLFC_men_b          = 0,
2171 +       DDRDLLFC_men_m          = 0x00000001,
2172 +       DDRDLLFC_aen_b          = 1,
2173 +       DDRDLLFC_aen_m          = 0x00000002,
2174 +       DDRDLLFC_ff_b           = 2,
2175 +       DDRDLLFC_ff_m           = 0x00000004,
2176 +
2177 +       DDRDLLTA_addr_b         = 2,
2178 +       DDRDLLTA_addr_m         = 0xfffffffc,
2179 +
2180 +       DDRDLLED_dbe_b          = 0,
2181 +       DDRDLLED_dbe_m          = 0x00000001,
2182 +       DDRDLLED_dte_b          = 1,
2183 +       DDRDLLED_dte_m          = 0x00000002,
2184 +
2185 +
2186 +} ;
2187 +
2188 +#endif // __IDT_DDR_H__
2189 diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
2190 --- linux.old/include/asm-mips/rc32434/dev.h    1970-01-01 01:00:00.000000000 +0100
2191 +++ linux.dev/include/asm-mips/rc32434/dev.h    2006-10-11 21:56:38.000000000 +0200
2192 @@ -0,0 +1,134 @@
2193 +#ifndef __IDT_DEV_H__
2194 +#define __IDT_DEV_H__
2195 +
2196 +/*******************************************************************************
2197 + *
2198 + * Copyright 2002 Integrated Device Technology, Inc.
2199 + *             All rights reserved.
2200 + *
2201 + * Device Controller register definition.
2202 + *
2203 + * File   : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2204 + *
2205 + * Author : John.Ahrens@idt.com
2206 + * Date   : 200112013
2207 + * Update :
2208 + *         $Log: dev.h,v $
2209 + *         Revision 1.2  2002/06/06 18:34:03  astichte
2210 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2211 + *
2212 + *         Revision 1.1  2002/05/29 17:33:21  sysarch
2213 + *         jba File moved from vcode/include/idt/acacia
2214 + *
2215 + *
2216 + ******************************************************************************/
2217 +
2218 +#include  <asm/rc32434/types.h>
2219 +
2220 +enum
2221 +{
2222 +       DEV0_PhysicalAddress    = 0x18010000,
2223 +       DEV_PhysicalAddress     = DEV0_PhysicalAddress,         // Default
2224 +
2225 +       DEV0_VirtualAddress     = 0xb8010000,
2226 +       DEV_VirtualAddress      = DEV0_VirtualAddress,          // Default
2227 +} ;
2228 +
2229 +typedef struct DEVICE_s
2230 +{
2231 +       U32     devbase ;                       // Device Base
2232 +       U32     devmask ;                       // Device Mask
2233 +       U32     devc ;                          // Device Control
2234 +       U32     devtc ;                         // Device Timing Control
2235 +} volatile *DEVICE_t ;
2236 +
2237 +enum
2238 +{
2239 +       DEV_Count = 3,
2240 +} ;
2241 +
2242 +typedef struct DEV_s
2243 +{
2244 +       struct DEVICE_s dev [DEV_Count] ;
2245 +       U32             btcs ;                  // Bus timeout control / status
2246 +       U32             btcompare ;             // Compare
2247 +       U32             btaddr ;                // Timeout address.
2248 +       U32             devdacs ;               // Decoupled access control.
2249 +       U32             devdaa ;                // Decoupled access address.
2250 +       U32             devdad ;                // Decoupled access address.
2251 +       U32             devspare ;              // spare.
2252 +} volatile *DEV_t ;
2253 +
2254 +enum
2255 +{
2256 +       DEVBASE_baseaddr_b      = 16,
2257 +       DEVBASE_baseaddr_m      = 0xffff0000,
2258 +       DEVMASK_mask_b          = 16,
2259 +       DEVMASK_mask_m          = 0xffff0000,
2260 +
2261 +       DEVC_ds_b               = 0,
2262 +       DEVC_ds_m               = 0x00000003,
2263 +               DEVC_ds_8_v     = 0,            // 8-bit device.
2264 +               DEVC_ds_16_v    = 1,            // reserved
2265 +               DEVC_ds_res_v   = 2,            // reserved.
2266 +               DEVC_ds_res2_v  = 3,            // reserved.
2267 +       DEVC_be_b               = 2,
2268 +       DEVC_be_m               = 0x00000004,
2269 +       DEVC_wp_b               = 3,
2270 +       DEVC_wp_m               = 0x00000008,
2271 +       DEVC_csd_b              = 4,
2272 +       DEVC_csd_m              = 0x000000f0,
2273 +       DEVC_oed_b              = 8,
2274 +       DEVC_oed_m              = 0x00000f00,
2275 +       DEVC_bwd_b              = 12,
2276 +       DEVC_bwd_m              = 0x0000f000,
2277 +       DEVC_rws_b              = 16,
2278 +       DEVC_rws_m              = 0x003f0000,
2279 +       DEVC_wws_b              = 22,
2280 +       DEVC_wws_m              = 0x0fc00000,
2281 +       DEVC_bre_b              = 28,
2282 +       DEVC_bre_m              = 0x10000000,
2283 +       DEVC_bwe_b              = 29,
2284 +       DEVC_bwe_m              = 0x20000000,
2285 +       DEVC_wam_b              = 30,
2286 +       DEVC_wam_m              = 0x40000000,
2287 +
2288 +       DEVTC_prd_b             = 0,
2289 +       DEVTC_prd_m             = 0x0000000f,
2290 +       DEVTC_pwd_b             = 4,
2291 +       DEVTC_pwd_m             = 0x000000f0,
2292 +       DEVTC_wdh_b             = 8,
2293 +       DEVTC_wdh_m             = 0x00000700,
2294 +       DEVTC_csh_b             = 11,
2295 +       DEVTC_csh_m             = 0x00001800,
2296 +
2297 +       BTCS_tt_b               = 0,
2298 +       BTCS_tt_m               = 0x00000001,
2299 +               BTCS_tt_write           = 0,
2300 +               BTCS_tt_read            = 1,
2301 +       BTCS_bto_b              = 1,            // In btcs
2302 +       BTCS_bto_m              = 0x00000002,   // In btcs
2303 +       BTCS_bte_b              = 2,            // In btcs
2304 +       BTCS_bte_m              = 0x00000004,   // In btcs
2305 +
2306 +       BTCOMPARE_compare_b     = 0,            // In btcompare
2307 +       BTCOMPARE_compare_m     = 0x0000ffff,   // In btcompare
2308 +
2309 +       DEVDACS_op_b            = 0,            // In devdacs
2310 +       DEVDACS_op_m            = 0x00000001,   // In devdacs
2311 +               DEVDACS_op_write_v              = 0,
2312 +               DEVDACS_op_read_v               = 1,
2313 +       DEVDACS_size_b          = 1,            // In devdacs
2314 +       DEVDACS_size_m          = 0x00000006,   // In devdacs
2315 +               DEVDACS_size_byte_v             = 0,
2316 +               DEVDACS_size_halfword   = 1,
2317 +               DEVDACS_size_triplebyte = 2,
2318 +               DEVDACS_size_word               = 3,
2319 +       DEVDACS_err_b           = 3,            // In devdacs
2320 +       DEVDACS_err_m           = 0x00000008,   // In devdacs
2321 +       DEVDACS_f_b             = 4,            // In devdacs
2322 +       DEVDACS_f_m             = 0x00000010,   // In devdacs
2323 +} ;
2324 +
2325 +#endif //__IDT_DEV_H__
2326 +
2327 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
2328 --- linux.old/include/asm-mips/rc32434/dma.h    1970-01-01 01:00:00.000000000 +0100
2329 +++ linux.dev/include/asm-mips/rc32434/dma.h    2006-10-11 21:56:38.000000000 +0200
2330 @@ -0,0 +1,202 @@
2331 +#ifndef __IDT_DMA_H__
2332 +#define __IDT_DMA_H__
2333 +
2334 +/*******************************************************************************
2335 + *
2336 + * Copyright 2002 Integrated Device Technology, Inc.
2337 + *             All rights reserved.
2338 + *
2339 + * DMA register definition.
2340 + *
2341 + * File   : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2342 + *
2343 + * Author : ryan.holmQVist@idt.com
2344 + * Date   : 20011005
2345 + * Update :
2346 + *         $Log: dma.h,v $
2347 + *         Revision 1.3  2002/06/06 18:34:03  astichte
2348 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2349 + *
2350 + *         Revision 1.2  2002/06/05 18:30:46  astichte
2351 + *         Removed IDTField
2352 + *
2353 + *         Revision 1.1  2002/05/29 17:33:21  sysarch
2354 + *         jba File moved from vcode/include/idt/acacia
2355 + *
2356 + *
2357 + ******************************************************************************/
2358 +
2359 +#include  <asm/rc32434/types.h>
2360 +enum
2361 +{
2362 +       DMA0_PhysicalAddress    = 0x18040000,
2363 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
2364 +
2365 +       DMA0_VirtualAddress     = 0xb8040000,
2366 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
2367 +} ;
2368 +
2369 +/*
2370 + * DMA descriptor (in physical memory).
2371 + */
2372 +
2373 +typedef struct DMAD_s
2374 +{
2375 +       U32                     control ;       // Control. use DMAD_*
2376 +       U32                     ca ;            // Current Address.
2377 +       U32                     devcs ;         // Device control and status.
2378 +       U32                     link ;          // Next descriptor in chain.
2379 +} volatile *DMAD_t ;
2380 +
2381 +enum
2382 +{
2383 +       DMAD_size               = sizeof (struct DMAD_s),
2384 +       DMAD_count_b            = 0,            // in DMAD_t -> control
2385 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
2386 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
2387 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
2388 +               DMAD_ds_ethRcv_v        = 0,
2389 +               DMAD_ds_ethXmt_v        = 0,
2390 +               DMAD_ds_memToFifo_v     = 0,
2391 +               DMAD_ds_fifoToMem_v     = 0,
2392 +               DMAD_ds_pciToMem_v      = 0,
2393 +               DMAD_ds_memToPci_v      = 0,
2394 +
2395 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
2396 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
2397 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
2398 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
2399 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
2400 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
2401 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
2402 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
2403 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
2404 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
2405 +       DMAD_cof_b              = 25,           // chain on finished
2406 +       DMAD_cof_m              = 0x02000000,   //
2407 +       DMAD_cod_b              = 26,           // chain on done
2408 +       DMAD_cod_m              = 0x04000000,   //
2409 +       DMAD_iof_b              = 27,           // interrupt on finished
2410 +       DMAD_iof_m              = 0x08000000,   //
2411 +       DMAD_iod_b              = 28,           // interrupt on done
2412 +       DMAD_iod_m              = 0x10000000,   //
2413 +       DMAD_t_b                = 29,           // terminated
2414 +       DMAD_t_m                = 0x20000000,   //
2415 +       DMAD_d_b                = 30,           // done
2416 +       DMAD_d_m                = 0x40000000,   //
2417 +       DMAD_f_b                = 31,           // finished
2418 +       DMAD_f_m                = 0x80000000,   //
2419 +} ;
2420 +
2421 +/*
2422 + * DMA register (within Internal Register Map).
2423 + */
2424 +
2425 +struct DMA_Chan_s
2426 +{
2427 +       U32             dmac ;          // Control.
2428 +       U32             dmas ;          // Status.
2429 +       U32             dmasm ;         // Mask.
2430 +       U32             dmadptr ;       // Descriptor pointer.
2431 +       U32             dmandptr ;      // Next descriptor pointer.
2432 +};
2433 +
2434 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
2435 +
2436 +//DMA_Channels   use DMACH_count instead
2437 +
2438 +enum
2439 +{
2440 +       DMAC_run_b      = 0,            //
2441 +       DMAC_run_m      = 0x00000001,   //
2442 +       DMAC_dm_b       = 1,            // done mask
2443 +       DMAC_dm_m       = 0x00000002,   //
2444 +       DMAC_mode_b     = 2,            //
2445 +       DMAC_mode_m     = 0x0000000c,   //
2446 +               DMAC_mode_auto_v        = 0,
2447 +               DMAC_mode_burst_v       = 1,
2448 +               DMAC_mode_transfer_v    = 2, //usually used
2449 +               DMAC_mode_reserved_v    = 3,
2450 +       DMAC_a_b        = 4,            //
2451 +       DMAC_a_m        = 0x00000010,   //
2452 +
2453 +       DMAS_f_b        = 0,            // finished (sticky)
2454 +       DMAS_f_m        = 0x00000001,   //
2455 +       DMAS_d_b        = 1,            // done (sticky)
2456 +       DMAS_d_m        = 0x00000002,   //
2457 +       DMAS_c_b        = 2,            // chain (sticky)
2458 +       DMAS_c_m        = 0x00000004,   //
2459 +       DMAS_e_b        = 3,            // error (sticky)
2460 +       DMAS_e_m        = 0x00000008,   //
2461 +       DMAS_h_b        = 4,            // halt (sticky)
2462 +       DMAS_h_m        = 0x00000010,   //
2463 +
2464 +       DMASM_f_b       = 0,            // finished (1=mask)
2465 +       DMASM_f_m       = 0x00000001,   //
2466 +       DMASM_d_b       = 1,            // done (1=mask)
2467 +       DMASM_d_m       = 0x00000002,   //
2468 +       DMASM_c_b       = 2,            // chain (1=mask)
2469 +       DMASM_c_m       = 0x00000004,   //
2470 +       DMASM_e_b       = 3,            // error (1=mask)
2471 +       DMASM_e_m       = 0x00000008,   //
2472 +       DMASM_h_b       = 4,            // halt (1=mask)
2473 +       DMASM_h_m       = 0x00000010,   //
2474 +} ;
2475 +
2476 +/*
2477 + * DMA channel definitions
2478 + */
2479 +
2480 +enum
2481 +{
2482 +       DMACH_ethRcv = 0,
2483 +       DMACH_ethXmt = 1,
2484 +       DMACH_memToFifo = 2,
2485 +       DMACH_fifoToMem = 3,
2486 +       DMACH_pciToMem = 4,
2487 +       DMACH_memToPci = 5,
2488 +
2489 +       DMACH_count //must be last
2490 +};
2491 +
2492 +
2493 +typedef struct DMAC_s
2494 +{
2495 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
2496 +} volatile *DMA_t ;
2497 +
2498 +
2499 +/*
2500 + * External DMA parameters
2501 +*/
2502 +#if 0
2503 +enum
2504 +{
2505 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
2506 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
2507 +               DMADEVCMD_ts_byte_v     = 0,
2508 +               DMADEVCMD_ts_halfword_v = 1,
2509 +               DMADEVCMD_ts_word_v     = 2,
2510 +               DMADEVCMD_ts_2word_v    = 3,
2511 +               DMADEVCMD_ts_4word_v    = 4,
2512 +               DMADEVCMD_ts_6word_v    = 5,
2513 +               DMADEVCMD_ts_8word_v    = 6,
2514 +               DMADEVCMD_ts_16word_v   = 7
2515 +};
2516 +#endif
2517 +
2518 +#if 1  // aws - Compatibility.
2519 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
2520 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
2521 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
2522 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
2523 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
2524 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
2525 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
2526 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
2527 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
2528 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
2529 +#endif // aws - Compatibility.
2530 +
2531 +#endif // __IDT_DMA_H__
2532 +
2533 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
2534 --- linux.old/include/asm-mips/rc32434/dma_v.h  1970-01-01 01:00:00.000000000 +0100
2535 +++ linux.dev/include/asm-mips/rc32434/dma_v.h  2006-10-11 21:56:38.000000000 +0200
2536 @@ -0,0 +1,73 @@
2537 +#ifndef __IDT_DMA_V_H__
2538 +#define __IDT_DMA_V_H__
2539 +
2540 +/*******************************************************************************
2541 + *
2542 + * Copyright 2002 Integrated Device Technology, Inc.
2543 + *             All rights reserved.
2544 + *
2545 + * DMA register definition.
2546 + *
2547 + * File   : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2548 + *
2549 + * Author : ryan.holmQVist@idt.com
2550 + * Date   : 20011005
2551 + * Update :
2552 + *         $Log: dma.h,v $
2553 + *         Revision 1.3  2002/06/06 18:34:03  astichte
2554 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2555 + *
2556 + *         Revision 1.2  2002/06/05 18:30:46  astichte
2557 + *         Removed IDTField
2558 + *
2559 + *         Revision 1.1  2002/05/29 17:33:21  sysarch
2560 + *         jba File moved from vcode/include/idt/acacia
2561 + *
2562 + *
2563 + ******************************************************************************/
2564 +#include  <asm/rc32434/types.h>
2565 +#include  <asm/rc32434/dma.h>
2566 +#include  <asm/rc32434/rc32434.h>
2567 +#define DMA_CHAN_OFFSET  0x14
2568 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
2569 +#define DMA_COUNT(count)   \
2570 +  ((count) & DMAD_count_m)
2571 +
2572 +#define DMA_HALT_TIMEOUT 500
2573 +
2574 +
2575 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
2576 +{
2577 +       int timeout=1;
2578 +       if (local_readl(&ch->dmac) & DMAC_run_m) {
2579 +               local_writel(0, &ch->dmac);
2580 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2581 +                       if (local_readl(&ch->dmas) & DMAS_h_m) {
2582 +                               local_writel(0, &ch->dmas);
2583 +                               break;
2584 +                       }
2585 +               }
2586 +       }
2587 +
2588 +       return timeout ? 0 : 1;
2589 +}
2590 +
2591 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2592 +{
2593 +       local_writel(0, &ch->dmandptr);
2594 +       local_writel(dma_addr, &ch->dmadptr);
2595 +}
2596 +
2597 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2598 +{
2599 +       local_writel(dma_addr, &ch->dmandptr);
2600 +}
2601 +
2602 +#endif // __IDT_DMA_V_H__
2603 +
2604 +
2605 +
2606 +
2607 +
2608 +
2609 +
2610 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2611 --- linux.old/include/asm-mips/rc32434/eth.h    1970-01-01 01:00:00.000000000 +0100
2612 +++ linux.dev/include/asm-mips/rc32434/eth.h    2006-10-11 21:56:38.000000000 +0200
2613 @@ -0,0 +1,322 @@
2614 +#ifndef        __IDT_ETH_H__
2615 +#define        __IDT_ETH_H__
2616 +
2617 +/*******************************************************************************
2618 + *
2619 + * Copyright 2002 Integrated Device Technology, Inc.
2620 + *             All rights reserved.
2621 + *
2622 + * Ethernet register definition.
2623 + *
2624 + * File   : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2625 + *
2626 + * Author : Allen.Stichter@idt.com
2627 + * Date   : 20020605
2628 + * Update :
2629 + *         $Log: eth.h,v $
2630 + *         Revision 1.3  2002/06/06 18:34:04  astichte
2631 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2632 + *
2633 + *         Revision 1.2  2002/06/05 18:19:46  astichte
2634 + *         Added
2635 + *
2636 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
2637 + *         jba File moved from vcode/include/idt/acacia
2638 + *
2639 + ******************************************************************************/
2640 +
2641 +#include  <asm/rc32434/types.h>
2642 +
2643 +enum
2644 +{
2645 +       ETH0_PhysicalAddress    = 0x18060000,
2646 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
2647 +
2648 +       ETH0_VirtualAddress     = 0xb8060000,
2649 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
2650 +} ;
2651 +
2652 +typedef struct
2653 +{
2654 +       U32 ethintfc            ;
2655 +       U32 ethfifott           ;
2656 +       U32 etharc              ;
2657 +       U32 ethhash0            ;
2658 +       U32 ethhash1            ;
2659 +       U32 ethu0 [4]           ;       // Reserved.
2660 +       U32 ethpfs              ;
2661 +       U32 ethmcp              ;
2662 +       U32 eth_u1 [10]         ;       // Reserved.
2663 +       U32 ethspare            ;
2664 +       U32 eth_u2 [42]         ;       // Reserved.
2665 +       U32 ethsal0             ;
2666 +       U32 ethsah0             ;
2667 +       U32 ethsal1             ;
2668 +       U32 ethsah1             ;
2669 +       U32 ethsal2             ;
2670 +       U32 ethsah2             ;
2671 +       U32 ethsal3             ;
2672 +       U32 ethsah3             ;
2673 +       U32 ethrbc              ;
2674 +       U32 ethrpc              ;
2675 +       U32 ethrupc             ;
2676 +       U32 ethrfc              ;
2677 +       U32 ethtbc              ;
2678 +       U32 ethgpf              ;
2679 +       U32 eth_u9 [50]         ;       // Reserved.
2680 +       U32 ethmac1             ;
2681 +       U32 ethmac2             ;
2682 +       U32 ethipgt             ;
2683 +       U32 ethipgr             ;
2684 +       U32 ethclrt             ;
2685 +       U32 ethmaxf             ;
2686 +       U32 eth_u10             ;       // Reserved.
2687 +       U32 ethmtest            ;
2688 +       U32 miimcfg             ;
2689 +       U32 miimcmd             ;
2690 +       U32 miimaddr            ;
2691 +       U32 miimwtd             ;
2692 +       U32 miimrdd             ;
2693 +       U32 miimind             ;
2694 +       U32 eth_u11             ;       // Reserved.
2695 +       U32 eth_u12             ;       // Reserved.
2696 +       U32 ethcfsa0            ;
2697 +       U32 ethcfsa1            ;
2698 +       U32 ethcfsa2            ;
2699 +} volatile *ETH_t;
2700 +
2701 +enum
2702 +{
2703 +       ETHINTFC_en_b           = 0,
2704 +       ETHINTFC_en_m           = 0x00000001,
2705 +       ETHINTFC_its_b          = 1,
2706 +       ETHINTFC_its_m          = 0x00000002,
2707 +       ETHINTFC_rip_b          = 2,
2708 +       ETHINTFC_rip_m          = 0x00000004,
2709 +       ETHINTFC_jam_b          = 3,
2710 +       ETHINTFC_jam_m          = 0x00000008,
2711 +       ETHINTFC_ovr_b          = 4,
2712 +       ETHINTFC_ovr_m          = 0x00000010,
2713 +       ETHINTFC_und_b          = 5,
2714 +       ETHINTFC_und_m          = 0x00000020,
2715 +       ETHINTFC_iom_b          = 6,
2716 +       ETHINTFC_iom_m          = 0x000000c0,
2717 +
2718 +       ETHFIFOTT_tth_b         = 0,
2719 +       ETHFIFOTT_tth_m         = 0x0000007f,
2720 +
2721 +       ETHARC_pro_b            = 0,
2722 +       ETHARC_pro_m            = 0x00000001,
2723 +       ETHARC_am_b             = 1,
2724 +       ETHARC_am_m             = 0x00000002,
2725 +       ETHARC_afm_b            = 2,
2726 +       ETHARC_afm_m            = 0x00000004,
2727 +       ETHARC_ab_b             = 3,
2728 +       ETHARC_ab_m             = 0x00000008,
2729 +
2730 +       ETHSAL_byte5_b          = 0,
2731 +       ETHSAL_byte5_m          = 0x000000ff,
2732 +       ETHSAL_byte4_b          = 8,
2733 +       ETHSAL_byte4_m          = 0x0000ff00,
2734 +       ETHSAL_byte3_b          = 16,
2735 +       ETHSAL_byte3_m          = 0x00ff0000,
2736 +       ETHSAL_byte2_b          = 24,
2737 +       ETHSAL_byte2_m          = 0xff000000,
2738 +
2739 +       ETHSAH_byte1_b          = 0,
2740 +       ETHSAH_byte1_m          = 0x000000ff,
2741 +       ETHSAH_byte0_b          = 8,
2742 +       ETHSAH_byte0_m          = 0x0000ff00,
2743 +
2744 +       ETHGPF_ptv_b            = 0,
2745 +       ETHGPF_ptv_m            = 0x0000ffff,
2746 +
2747 +       ETHPFS_pfd_b            = 0,
2748 +       ETHPFS_pfd_m            = 0x00000001,
2749 +
2750 +       ETHCFSA0_cfsa4_b        = 0,
2751 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
2752 +       ETHCFSA0_cfsa5_b        = 8,
2753 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
2754 +
2755 +       ETHCFSA1_cfsa2_b        = 0,
2756 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
2757 +       ETHCFSA1_cfsa3_b        = 8,
2758 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
2759 +
2760 +       ETHCFSA2_cfsa0_b        = 0,
2761 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
2762 +       ETHCFSA2_cfsa1_b        = 8,
2763 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
2764 +
2765 +       ETHMAC1_re_b            = 0,
2766 +       ETHMAC1_re_m            = 0x00000001,
2767 +       ETHMAC1_paf_b           = 1,
2768 +       ETHMAC1_paf_m           = 0x00000002,
2769 +       ETHMAC1_rfc_b           = 2,
2770 +       ETHMAC1_rfc_m           = 0x00000004,
2771 +       ETHMAC1_tfc_b           = 3,
2772 +       ETHMAC1_tfc_m           = 0x00000008,
2773 +       ETHMAC1_lb_b            = 4,
2774 +       ETHMAC1_lb_m            = 0x00000010,
2775 +       ETHMAC1_mr_b            = 31,
2776 +       ETHMAC1_mr_m            = 0x80000000,
2777 +
2778 +       ETHMAC2_fd_b            = 0,
2779 +       ETHMAC2_fd_m            = 0x00000001,
2780 +       ETHMAC2_flc_b           = 1,
2781 +       ETHMAC2_flc_m           = 0x00000002,
2782 +       ETHMAC2_hfe_b           = 2,
2783 +       ETHMAC2_hfe_m           = 0x00000004,
2784 +       ETHMAC2_dc_b            = 3,
2785 +       ETHMAC2_dc_m            = 0x00000008,
2786 +       ETHMAC2_cen_b           = 4,
2787 +       ETHMAC2_cen_m           = 0x00000010,
2788 +       ETHMAC2_pe_b            = 5,
2789 +       ETHMAC2_pe_m            = 0x00000020,
2790 +       ETHMAC2_vpe_b           = 6,
2791 +       ETHMAC2_vpe_m           = 0x00000040,
2792 +       ETHMAC2_ape_b           = 7,
2793 +       ETHMAC2_ape_m           = 0x00000080,
2794 +       ETHMAC2_ppe_b           = 8,
2795 +       ETHMAC2_ppe_m           = 0x00000100,
2796 +       ETHMAC2_lpe_b           = 9,
2797 +       ETHMAC2_lpe_m           = 0x00000200,
2798 +       ETHMAC2_nb_b            = 12,
2799 +       ETHMAC2_nb_m            = 0x00001000,
2800 +       ETHMAC2_bp_b            = 13,
2801 +       ETHMAC2_bp_m            = 0x00002000,
2802 +       ETHMAC2_ed_b            = 14,
2803 +       ETHMAC2_ed_m            = 0x00004000,
2804 +
2805 +       ETHIPGT_ipgt_b          = 0,
2806 +       ETHIPGT_ipgt_m          = 0x0000007f,
2807 +
2808 +       ETHIPGR_ipgr2_b         = 0,
2809 +       ETHIPGR_ipgr2_m         = 0x0000007f,
2810 +       ETHIPGR_ipgr1_b         = 8,
2811 +       ETHIPGR_ipgr1_m         = 0x00007f00,
2812 +
2813 +       ETHCLRT_maxret_b        = 0,
2814 +       ETHCLRT_maxret_m        = 0x0000000f,
2815 +       ETHCLRT_colwin_b        = 8,
2816 +       ETHCLRT_colwin_m        = 0x00003f00,
2817 +
2818 +       ETHMAXF_maxf_b          = 0,
2819 +       ETHMAXF_maxf_m          = 0x0000ffff,
2820 +
2821 +       ETHMTEST_tb_b           = 2,
2822 +       ETHMTEST_tb_m           = 0x00000004,
2823 +
2824 +       ETHMCP_div_b            = 0,
2825 +       ETHMCP_div_m            = 0x000000ff,
2826 +
2827 +       MIIMCFG_rsv_b           = 0,
2828 +       MIIMCFG_rsv_m           = 0x0000000c,
2829 +
2830 +       MIIMCMD_rd_b            = 0,
2831 +       MIIMCMD_rd_m            = 0x00000001,
2832 +       MIIMCMD_scn_b           = 1,
2833 +       MIIMCMD_scn_m           = 0x00000002,
2834 +
2835 +       MIIMADDR_regaddr_b      = 0,
2836 +       MIIMADDR_regaddr_m      = 0x0000001f,
2837 +       MIIMADDR_phyaddr_b      = 8,
2838 +       MIIMADDR_phyaddr_m      = 0x00001f00,
2839 +
2840 +       MIIMWTD_wdata_b         = 0,
2841 +       MIIMWTD_wdata_m         = 0x0000ffff,
2842 +
2843 +       MIIMRDD_rdata_b         = 0,
2844 +       MIIMRDD_rdata_m         = 0x0000ffff,
2845 +
2846 +       MIIMIND_bsy_b           = 0,
2847 +       MIIMIND_bsy_m           = 0x00000001,
2848 +       MIIMIND_scn_b           = 1,
2849 +       MIIMIND_scn_m           = 0x00000002,
2850 +       MIIMIND_nv_b            = 2,
2851 +       MIIMIND_nv_m            = 0x00000004,
2852 +
2853 +} ;
2854 +
2855 +/*
2856 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2857 + */
2858 +enum
2859 +{
2860 +       ETHRX_fd_b              = 0,
2861 +       ETHRX_fd_m              = 0x00000001,
2862 +       ETHRX_ld_b              = 1,
2863 +       ETHRX_ld_m              = 0x00000002,
2864 +       ETHRX_rok_b             = 2,
2865 +       ETHRX_rok_m             = 0x00000004,
2866 +       ETHRX_fm_b              = 3,
2867 +       ETHRX_fm_m              = 0x00000008,
2868 +       ETHRX_mp_b              = 4,
2869 +       ETHRX_mp_m              = 0x00000010,
2870 +       ETHRX_bp_b              = 5,
2871 +       ETHRX_bp_m              = 0x00000020,
2872 +       ETHRX_vlt_b             = 6,
2873 +       ETHRX_vlt_m             = 0x00000040,
2874 +       ETHRX_cf_b              = 7,
2875 +       ETHRX_cf_m              = 0x00000080,
2876 +       ETHRX_ovr_b             = 8,
2877 +       ETHRX_ovr_m             = 0x00000100,
2878 +       ETHRX_crc_b             = 9,
2879 +       ETHRX_crc_m             = 0x00000200,
2880 +       ETHRX_cv_b              = 10,
2881 +       ETHRX_cv_m              = 0x00000400,
2882 +       ETHRX_db_b              = 11,
2883 +       ETHRX_db_m              = 0x00000800,
2884 +       ETHRX_le_b              = 12,
2885 +       ETHRX_le_m              = 0x00001000,
2886 +       ETHRX_lor_b             = 13,
2887 +       ETHRX_lor_m             = 0x00002000,
2888 +       ETHRX_ces_b             = 14,
2889 +       ETHRX_ces_m             = 0x00004000,
2890 +       ETHRX_length_b          = 16,
2891 +       ETHRX_length_m          = 0xffff0000,
2892 +
2893 +       ETHTX_fd_b              = 0,
2894 +       ETHTX_fd_m              = 0x00000001,
2895 +       ETHTX_ld_b              = 1,
2896 +       ETHTX_ld_m              = 0x00000002,
2897 +       ETHTX_oen_b             = 2,
2898 +       ETHTX_oen_m             = 0x00000004,
2899 +       ETHTX_pen_b             = 3,
2900 +       ETHTX_pen_m             = 0x00000008,
2901 +       ETHTX_cen_b             = 4,
2902 +       ETHTX_cen_m             = 0x00000010,
2903 +       ETHTX_hen_b             = 5,
2904 +       ETHTX_hen_m             = 0x00000020,
2905 +       ETHTX_tok_b             = 6,
2906 +       ETHTX_tok_m             = 0x00000040,
2907 +       ETHTX_mp_b              = 7,
2908 +       ETHTX_mp_m              = 0x00000080,
2909 +       ETHTX_bp_b              = 8,
2910 +       ETHTX_bp_m              = 0x00000100,
2911 +       ETHTX_und_b             = 9,
2912 +       ETHTX_und_m             = 0x00000200,
2913 +       ETHTX_of_b              = 10,
2914 +       ETHTX_of_m              = 0x00000400,
2915 +       ETHTX_ed_b              = 11,
2916 +       ETHTX_ed_m              = 0x00000800,
2917 +       ETHTX_ec_b              = 12,
2918 +       ETHTX_ec_m              = 0x00001000,
2919 +       ETHTX_lc_b              = 13,
2920 +       ETHTX_lc_m              = 0x00002000,
2921 +       ETHTX_td_b              = 14,
2922 +       ETHTX_td_m              = 0x00004000,
2923 +       ETHTX_crc_b             = 15,
2924 +       ETHTX_crc_m             = 0x00008000,
2925 +       ETHTX_le_b              = 16,
2926 +       ETHTX_le_m              = 0x00010000,
2927 +       ETHTX_cc_b              = 17,
2928 +       ETHTX_cc_m              = 0x001E0000,
2929 +} ;
2930 +
2931 +#endif // __IDT_ETH_H__
2932 +
2933 +
2934 +
2935 +
2936 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2937 --- linux.old/include/asm-mips/rc32434/eth_v.h  1970-01-01 01:00:00.000000000 +0100
2938 +++ linux.dev/include/asm-mips/rc32434/eth_v.h  2006-10-11 21:56:38.000000000 +0200
2939 @@ -0,0 +1,64 @@
2940 +#ifndef        __IDT_ETH_V_H__
2941 +#define        __IDT_ETH_V_H__
2942 +
2943 +/*******************************************************************************
2944 + *
2945 + * Copyright 2002 Integrated Device Technology, Inc.
2946 + *             All rights reserved.
2947 + *
2948 + * Ethernet register definition.
2949 + *
2950 + * File   : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2951 + *
2952 + * Author : Allen.Stichter@idt.com
2953 + * Date   : 20020605
2954 + * Update :
2955 + *         $Log: eth.h,v $
2956 + *         Revision 1.3  2002/06/06 18:34:04  astichte
2957 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2958 + *
2959 + *         Revision 1.2  2002/06/05 18:19:46  astichte
2960 + *         Added
2961 + *
2962 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
2963 + *         jba File moved from vcode/include/idt/acacia
2964 + *
2965 + ******************************************************************************/
2966 +
2967 +#include  <asm/rc32434/types.h>
2968 +#include  <asm/rc32434/eth.h>
2969 +
2970 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
2971 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
2972 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
2973 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
2974 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
2975 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
2976 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
2977 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
2978 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
2979 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
2980 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
2981 +
2982 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
2983 +
2984 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
2985 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
2986 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
2987 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
2988 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
2989 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
2990 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
2991 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
2992 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
2993 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
2994 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
2995 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
2996 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
2997 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
2998 +#endif // __IDT_ETH_V_H__
2999 +
3000 +
3001 +
3002 +
3003 +
3004 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
3005 --- linux.old/include/asm-mips/rc32434/gpio.h   1970-01-01 01:00:00.000000000 +0100
3006 +++ linux.dev/include/asm-mips/rc32434/gpio.h   2006-10-11 21:56:38.000000000 +0200
3007 @@ -0,0 +1,182 @@
3008 +#ifndef __IDT_GPIO_H__
3009 +#define __IDT_GPIO_H__
3010 +
3011 +/*******************************************************************************
3012 + *
3013 + * Copyright 2002 Integrated Device Technology, Inc.
3014 + *             All rights reserved.
3015 + *
3016 + * GPIO register definition.
3017 + *
3018 + * File   : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3019 + *
3020 + * Author : ryan.holmQVist@idt.com
3021 + * Date   : 20011005
3022 + * Update :
3023 + *         $Log: gpio.h,v $
3024 + *         Revision 1.2  2002/06/06 18:34:04  astichte
3025 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
3026 + *
3027 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
3028 + *         jba File moved from vcode/include/idt/acacia
3029 + *
3030 + *
3031 + ******************************************************************************/
3032 +
3033 +#include  <asm/rc32434/types.h>
3034 +enum
3035 +{
3036 +       GPIO0_PhysicalAddress   = 0x18050000,
3037 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
3038 +
3039 +       GPIO0_VirtualAddress    = 0xb8050000,
3040 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
3041 +} ;
3042 +
3043 +typedef struct
3044 +{
3045 +       U32   gpiofunc;   /* GPIO Function Register
3046 +                          * gpiofunc[x]==0 bit = gpio
3047 +                          * func[x]==1  bit = altfunc
3048 +                          */
3049 +       U32   gpiocfg;    /* GPIO Configuration Register
3050 +                          * gpiocfg[x]==0 bit = input
3051 +                          * gpiocfg[x]==1 bit = output
3052 +                          */
3053 +       U32   gpiod;      /* GPIO Data Register
3054 +                          * gpiod[x] read/write gpio pinX status
3055 +                          */
3056 +       U32   gpioilevel; /* GPIO Interrupt Status Register
3057 +                          * interrupt level (see gpioistat)
3058 +                          */
3059 +       U32   gpioistat;  /* Gpio Interrupt Status Register
3060 +                          * istat[x] = (gpiod[x] == level[x])
3061 +                          * cleared in ISR (STICKY bits)
3062 +                          */
3063 +       U32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
3064 +} volatile * GPIO_t ;
3065 +
3066 +typedef enum
3067 +{
3068 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
3069 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
3070 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
3071 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
3072 +       GPIO_pin0_b             = 0,
3073 +       GPIO_pin0_m             = 0x00000001,
3074 +       GPIO_pin1_b             = 1,
3075 +       GPIO_pin1_m             = 0x00000002,
3076 +       GPIO_pin2_b             = 2,
3077 +       GPIO_pin2_m             = 0x00000004,
3078 +       GPIO_pin3_b             = 3,
3079 +       GPIO_pin3_m             = 0x00000008,
3080 +       GPIO_pin4_b             = 4,
3081 +       GPIO_pin4_m             = 0x00000010,
3082 +       GPIO_pin5_b             = 5,
3083 +       GPIO_pin5_m             = 0x00000020,
3084 +       GPIO_pin6_b             = 6,
3085 +       GPIO_pin6_m             = 0x00000040,
3086 +       GPIO_pin7_b             = 7,
3087 +       GPIO_pin7_m             = 0x00000080,
3088 +       GPIO_pin8_b             = 8,
3089 +       GPIO_pin8_m             = 0x00000100,
3090 +       GPIO_pin9_b             = 9,
3091 +       GPIO_pin9_m             = 0x00000200,
3092 +       GPIO_pin10_b            = 10,
3093 +       GPIO_pin10_m            = 0x00000400,
3094 +       GPIO_pin11_b            = 11,
3095 +       GPIO_pin11_m            = 0x00000800,
3096 +       GPIO_pin12_b            = 12,
3097 +       GPIO_pin12_m            = 0x00001000,
3098 +       GPIO_pin13_b            = 13,
3099 +       GPIO_pin13_m            = 0x00002000,
3100 +       GPIO_pin14_b            = 14,
3101 +       GPIO_pin14_m            = 0x00004000,
3102 +       GPIO_pin15_b            = 15,
3103 +       GPIO_pin15_m            = 0x00008000,
3104 +       GPIO_pin16_b            = 16,
3105 +       GPIO_pin16_m            = 0x00010000,
3106 +       GPIO_pin17_b            = 17,
3107 +       GPIO_pin17_m            = 0x00020000,
3108 +       GPIO_pin18_b            = 18,
3109 +       GPIO_pin18_m            = 0x00040000,
3110 +       GPIO_pin19_b            = 19,
3111 +       GPIO_pin19_m            = 0x00080000,
3112 +       GPIO_pin20_b            = 20,
3113 +       GPIO_pin20_m            = 0x00100000,
3114 +       GPIO_pin21_b            = 21,
3115 +       GPIO_pin21_m            = 0x00200000,
3116 +       GPIO_pin22_b            = 22,
3117 +       GPIO_pin22_m            = 0x00400000,
3118 +       GPIO_pin23_b            = 23,
3119 +       GPIO_pin23_m            = 0x00800000,
3120 +       GPIO_pin24_b            = 24,
3121 +       GPIO_pin24_m            = 0x01000000,
3122 +       GPIO_pin25_b            = 25,
3123 +       GPIO_pin25_m            = 0x02000000,
3124 +       GPIO_pin26_b            = 26,
3125 +       GPIO_pin26_m            = 0x04000000,
3126 +       GPIO_pin27_b            = 27,
3127 +       GPIO_pin27_m            = 0x08000000,
3128 +       GPIO_pin28_b            = 28,
3129 +       GPIO_pin28_m            = 0x10000000,
3130 +       GPIO_pin29_b            = 29,
3131 +       GPIO_pin29_m            = 0x20000000,
3132 +       GPIO_pin30_b            = 30,
3133 +       GPIO_pin30_m            = 0x40000000,
3134 +       GPIO_pin31_b            = 31,
3135 +       GPIO_pin31_m            = 0x80000000,
3136 +
3137 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
3138 +
3139 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
3140 +       GPIO_u0sout_m           = GPIO_pin0_m,
3141 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
3142 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
3143 +       GPIO_u0sinp_m   = GPIO_pin1_m,
3144 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
3145 +       GPIO_u0rtsn_b   = GPIO_pin2_b,                  // UART 0 req. to send.
3146 +       GPIO_u0rtsn_m   = GPIO_pin2_m,
3147 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
3148 +       GPIO_u0ctsn_b   = GPIO_pin3_b,                  // UART 0 clear to send.
3149 +       GPIO_u0ctsn_m   = GPIO_pin3_m,
3150 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
3151 +       GPIO_maddr22_b          = GPIO_pin4_b,  // M&P bus bit 22.
3152 +       GPIO_maddr22_m          = GPIO_pin4_m,
3153 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
3154 +
3155 +       GPIO_maddr23_b          = GPIO_pin5_b,  // M&P bus bit 23.
3156 +       GPIO_maddr23_m          = GPIO_pin5_m,
3157 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
3158 +
3159 +       GPIO_maddr24_b          = GPIO_pin6_b,  // M&P bus bit 24.
3160 +       GPIO_maddr24_m          = GPIO_pin6_m,
3161 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
3162 +
3163 +       GPIO_maddr25_b          = GPIO_pin7_b,  // M&P bus bit 25.
3164 +       GPIO_maddr25_m          = GPIO_pin7_m,
3165 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
3166 +
3167 +       GPIO_cpu_b              = GPIO_pin8_b,  // M&P bus bit 25.
3168 +       GPIO_cpu_m              = GPIO_pin8_m,
3169 +               GPIO_cpu_cfg_v  = GPIO_output_v,
3170 +       GPIO_afspare6_b         = GPIO_pin9_b,  // reserved.
3171 +       GPIO_afspare6_m         = GPIO_pin9_m,
3172 +               GPIO_afspare6_cfg_v     = GPIO_input_v,
3173 +       GPIO_afspare4_b         = GPIO_pin10_b,         // reserved.
3174 +       GPIO_afspare4_m         = GPIO_pin10_m,
3175 +               GPIO_afspare4_cfg_v     = GPIO_input_v,
3176 +       GPIO_afspare3_b         = GPIO_pin11_b,         // reserved.
3177 +       GPIO_afspare3_m         = GPIO_pin11_m,
3178 +               GPIO_afspare3_cfg_v     = GPIO_input_v,
3179 +       GPIO_afspare2_b         = GPIO_pin12_b,         // reserved.
3180 +       GPIO_afspare2_m         = GPIO_pin12_m,
3181 +               GPIO_afspare2_cfg_v     = GPIO_input_v,
3182 +       GPIO_pcimuintn_b        = GPIO_pin13_b,         // PCI messaging int.
3183 +       GPIO_pcimuintn_m        = GPIO_pin13_m,
3184 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
3185 +
3186 +} GPIO_DEFS_t;
3187 +
3188 +#endif // __IDT_GPIO_H__
3189 +
3190 diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h
3191 --- linux.old/include/asm-mips/rc32434/i2c.h    1970-01-01 01:00:00.000000000 +0100
3192 +++ linux.dev/include/asm-mips/rc32434/i2c.h    2006-10-11 21:56:38.000000000 +0200
3193 @@ -0,0 +1,147 @@
3194 +#ifndef __IDT_I2C_H__
3195 +#define __IDT_I2C_H__
3196 +
3197 +/*******************************************************************************
3198 + *
3199 + * Copyright 2002 Integrated Device Technology, Inc.
3200 + *             All rights reserved.
3201 + *
3202 + * I2C register definitions.
3203 + *
3204 + * File   : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3205 + *
3206 + * Author : Allen.Stichter@idt.com
3207 + * Date   : 20020120
3208 + * Update :
3209 + *         $Log: i2c.h,v $
3210 + *         Revision 1.2  2002/06/06 18:34:04  astichte
3211 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
3212 + *
3213 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
3214 + *         jba File moved from vcode/include/idt/acacia
3215 + *
3216 + *
3217 + ******************************************************************************/
3218 +
3219 +#include  <asm/rc32434/types.h>
3220 +
3221 +enum
3222 +{
3223 +       I2C0_PhysicalAddress    = 0x18068000,
3224 +       I2C_PhysicalAddress     = I2C0_PhysicalAddress,
3225 +
3226 +       I2C0_VirtualAddress     = 0xb8068000,
3227 +       I2C_VirtualAddress      = I2C0_VirtualAddress,
3228 +} ;
3229 +
3230 +typedef struct
3231 +{
3232 +       U32     i2cc ;
3233 +       U32     i2cdi ;
3234 +       U32     i2cdo ;
3235 +       U32     i2ccp ;         // I2C clk = ICLK / div / 8
3236 +       U32     i2cmcmd ;
3237 +       U32     i2cms ;
3238 +       U32     i2cmsm ;
3239 +       U32     i2css ;
3240 +       U32     i2cssm ;
3241 +       U32     i2csaddr ;
3242 +       U32     i2csack ;
3243 +} volatile * I2C_t ;
3244 +enum
3245 +{
3246 +       I2CC_men_b      = 0,            // In I2C-> i2cc
3247 +       I2CC_men_m      = 0x00000001,
3248 +       I2CC_sen_b      = 1,            // In I2C-> i2cc
3249 +       I2CC_sen_m      = 0x00000002,
3250 +       I2CC_iom_b      = 2,            // In I2C-> i2cc
3251 +       I2CC_iom_m      = 0x00000004,
3252 +
3253 +       I2CDI_data_b    = 0,            // In I2C-> i2cdi
3254 +       I2CDI_data_m    = 0x000000ff,
3255 +
3256 +       I2CDO_data_b    = 0,            // In I2C-> i2cdo
3257 +       I2CDO_data_m    = 0x000000ff,
3258 +
3259 +       I2CCP_div_b     = 0,            // In I2C-> i2ccp
3260 +       I2CCP_div_m     = 0x0000ffff,
3261 +
3262 +       I2CMCMD_cmd_b   = 0,            // In I2C-> i2cmcmd
3263 +       I2CMCMD_cmd_m   = 0x0000000f,
3264 +               I2CMCMD_cmd_nop_v       = 0,
3265 +               I2CMCMD_cmd_start_v     = 1,
3266 +               I2CMCMD_cmd_stop_v      = 2,
3267 +               I2CMCMD_cmd_res3_v      = 3,
3268 +               I2CMCMD_cmd_rd_v        = 4,
3269 +               I2CMCMD_cmd_rdack_v     = 5,
3270 +               I2CMCMD_cmd_wd_v        = 6,
3271 +               I2CMCMD_cmd_wdack_v     = 7,
3272 +               I2CMCMD_cmd_res8_v      = 8,
3273 +               I2CMCMD_cmd_res9_v      = 9,
3274 +               I2CMCMD_cmd_res10_v     = 10,
3275 +               I2CMCMD_cmd_res11_v     = 11,
3276 +               I2CMCMD_cmd_res12_v     = 12,
3277 +               I2CMCMD_cmd_res13_v     = 13,
3278 +               I2CMCMD_cmd_res14_v     = 14,
3279 +               I2CMCMD_cmd_res15_v     = 15,
3280 +
3281 +       I2CMS_d_b       = 0,            // In I2C-> i2cms
3282 +       I2CMS_d_m       = 0x00000001,
3283 +       I2CMS_na_b      = 1,            // In I2C-> i2cms
3284 +       I2CMS_na_m      = 0x00000002,
3285 +       I2CMS_la_b      = 2,            // In I2C-> i2cms
3286 +       I2CMS_la_m      = 0x00000004,
3287 +       I2CMS_err_b     = 3,            // In I2C-> i2cms
3288 +       I2CMS_err_m     = 0x00000008,
3289 +
3290 +       I2CMSM_d_b      = 0,            // In I2C-> i2cmsm
3291 +       I2CMSM_d_m      = 0x00000001,
3292 +       I2CMSM_na_b     = 1,            // In I2C-> i2cmsm
3293 +       I2CMSM_na_m     = 0x00000002,
3294 +       I2CMSM_la_b     = 2,            // In I2C-> i2cmsm
3295 +       I2CMSM_la_m     = 0x00000004,
3296 +       I2CMSM_err_b    = 3,            // In I2C-> i2cmsm
3297 +       I2CMSM_err_m    = 0x00000008,
3298 +
3299 +       I2CSS_rr_b      = 0,            // In I2C-> i2css
3300 +       I2CSS_rr_m      = 0x00000001,
3301 +       I2CSS_wr_b      = 1,            // In I2C-> i2css
3302 +       I2CSS_wr_m      = 0x00000002,
3303 +       I2CSS_sa_b      = 2,            // In I2C-> i2css
3304 +       I2CSS_sa_m      = 0x00000004,
3305 +       I2CSS_tf_b      = 3,            // In I2C-> i2css
3306 +       I2CSS_tf_m      = 0x00000008,
3307 +       I2CSS_gc_b      = 4,            // In I2C-> i2css
3308 +       I2CSS_gc_m      = 0x00000010,
3309 +       I2CSS_na_b      = 5,            // In I2C-> i2css
3310 +       I2CSS_na_m      = 0x00000020,
3311 +       I2CSS_err_b     = 6,            // In I2C-> i2css
3312 +       I2CSS_err_m     = 0x00000040,
3313 +
3314 +       I2CSSM_rr_b     = 0,            // In I2C-> i2cssm
3315 +       I2CSSM_rr_m     = 0x00000001,
3316 +       I2CSSM_wr_b     = 1,            // In I2C-> i2cssm
3317 +       I2CSSM_wr_m     = 0x00000002,
3318 +       I2CSSM_sa_b     = 2,            // In I2C-> i2cssm
3319 +       I2CSSM_sa_m     = 0x00000004,
3320 +       I2CSSM_tf_b     = 3,            // In I2C-> i2cssm
3321 +       I2CSSM_tf_m     = 0x00000008,
3322 +       I2CSSM_gc_b     = 4,            // In I2C-> i2cssm
3323 +       I2CSSM_gc_m     = 0x00000010,
3324 +       I2CSSM_na_b     = 5,            // In I2C-> i2cssm
3325 +       I2CSSM_na_m     = 0x00000020,
3326 +       I2CSSM_err_b    = 6,            // In I2C-> i2cssm
3327 +       I2CSSM_err_m    = 0x00000040,
3328 +
3329 +       I2CSADDR_addr_b = 0,            // In I2C-> i2csaddr
3330 +       I2CSADDR_addr_m = 0x000003ff,
3331 +       I2CSADDR_a_gc_b = 10,           // In I2C-> i2csaddr
3332 +       I2CSADDR_a_gc_m = 0x00000400,
3333 +       I2CSADDR_a10_b  = 11,           // In I2C-> i2csaddr
3334 +       I2CSADDR_a10_m  = 0x00000800,
3335 +
3336 +       I2CSACK_ack_b   = 0,            // In I2C-> i2csack
3337 +       I2CSACK_ack_m   = 0x00000001,
3338 +
3339 +} ;
3340 +#endif // __IDT_I2C_H__
3341 diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h
3342 --- linux.old/include/asm-mips/rc32434/integ.h  1970-01-01 01:00:00.000000000 +0100
3343 +++ linux.dev/include/asm-mips/rc32434/integ.h  2006-10-11 21:56:38.000000000 +0200
3344 @@ -0,0 +1,78 @@
3345 +#ifndef __IDT_INTEG_H__
3346 +#define __IDT_INTEG_H__
3347 +
3348 +/*******************************************************************************
3349 + *
3350 + * Copyright 2002 Integrated Device Technology, Inc.
3351 + *             All rights reserved.
3352 + *
3353 + * System Integrity register definition.
3354 + *
3355 + * File   : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3356 + *
3357 + * Author : ryan.holmQVist@idt.com
3358 + * Date   : 20011005
3359 + * Update :
3360 + *         $Log: integ.h,v $
3361 + *         Revision 1.3  2002/06/06 18:34:04  astichte
3362 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
3363 + *
3364 + *         Revision 1.2  2002/06/05 18:32:33  astichte
3365 + *         Removed IDTField
3366 + *
3367 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
3368 + *         jba File moved from vcode/include/idt/acacia
3369 + *
3370 + ******************************************************************************/
3371 +
3372 +#include  <asm/rc32434/types.h>
3373 +
3374 +enum
3375 +{
3376 +       INTEG0_PhysicalAddress  = 0x18030000,
3377 +       INTEG_PhysicalAddress   = INTEG0_PhysicalAddress,       // Default
3378 +
3379 +       INTEG0_VirtualAddress   = 0xb8030000,
3380 +       INTEG_VirtualAddress    = INTEG0_VirtualAddress,        // Default
3381 +} ;
3382 +
3383 +// if you are looing for CEA, try rst.h
3384 +typedef struct
3385 +{
3386 +       U32 filler [0xc] ;              // 0x30 bytes unused.
3387 +       U32 errcs ;                     // sticky use ERRCS_
3388 +       U32 wtcount ;                   // Watchdog timer count reg.
3389 +       U32 wtcompare ;                 // Watchdog timer timeout value.
3390 +       U32 wtc ;                       // Watchdog timer control. use WTC_
3391 +} volatile *INTEG_t ;
3392 +
3393 +enum
3394 +{
3395 +       ERRCS_wto_b             = 0,            // In INTEG_t -> errcs
3396 +       ERRCS_wto_m             = 0x00000001,
3397 +       ERRCS_wne_b             = 1,            // In INTEG_t -> errcs
3398 +       ERRCS_wne_m             = 0x00000002,
3399 +       ERRCS_ucw_b             = 2,            // In INTEG_t -> errcs
3400 +       ERRCS_ucw_m             = 0x00000004,
3401 +       ERRCS_ucr_b             = 3,            // In INTEG_t -> errcs
3402 +       ERRCS_ucr_m             = 0x00000008,
3403 +       ERRCS_upw_b             = 4,            // In INTEG_t -> errcs
3404 +       ERRCS_upw_m             = 0x00000010,
3405 +       ERRCS_upr_b             = 5,            // In INTEG_t -> errcs
3406 +       ERRCS_upr_m             = 0x00000020,
3407 +       ERRCS_udw_b             = 6,            // In INTEG_t -> errcs
3408 +       ERRCS_udw_m             = 0x00000040,
3409 +       ERRCS_udr_b             = 7,            // In INTEG_t -> errcs
3410 +       ERRCS_udr_m             = 0x00000080,
3411 +       ERRCS_sae_b             = 8,            // In INTEG_t -> errcs
3412 +       ERRCS_sae_m             = 0x00000100,
3413 +       ERRCS_wre_b             = 9,            // In INTEG_t -> errcs
3414 +       ERRCS_wre_m             = 0x00000200,
3415 +
3416 +       WTC_en_b                = 0,            // In INTEG_t -> wtc
3417 +       WTC_en_m                = 0x00000001,
3418 +       WTC_to_b                = 1,            // In INTEG_t -> wtc
3419 +       WTC_to_m                = 0x00000002,
3420 +} ;
3421 +
3422 +#endif // __IDT_INTEG_H__
3423 diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h
3424 --- linux.old/include/asm-mips/rc32434/int.h    1970-01-01 01:00:00.000000000 +0100
3425 +++ linux.dev/include/asm-mips/rc32434/int.h    2006-10-11 21:56:38.000000000 +0200
3426 @@ -0,0 +1,167 @@
3427 +#ifndef __IDT_INT_H__
3428 +#define __IDT_INT_H__
3429 +
3430 +/*******************************************************************************
3431 + *
3432 + * Copyright 2002 Integrated Device Technology, Inc.
3433 + *             All rights reserved.
3434 + *
3435 + * Interrupt Controller register definition.
3436 + *
3437 + * File   : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3438 + *
3439 + * Author : ryan.holmqvist@idt.com
3440 + * Date   : 20011005
3441 + * Update :
3442 + *         $Log: int.h,v $
3443 + *         Revision 1.3  2002/06/06 18:34:04  astichte
3444 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
3445 + *
3446 + *         Revision 1.2  2002/06/05 18:47:33  astichte
3447 + *         Removed IDTField
3448 + *
3449 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
3450 + *         jba File moved from vcode/include/idt/acacia
3451 + *
3452 + *
3453 + ******************************************************************************/
3454 +
3455 +#include  <asm/rc32434/types.h>
3456 +
3457 +enum
3458 +{
3459 +       INT0_PhysicalAddress    = 0x18038000,
3460 +       INT_PhysicalAddress     = INT0_PhysicalAddress,         // Default
3461 +
3462 +       INT0_VirtualAddress     = 0xb8038000,
3463 +       INT_VirtualAddress      = INT0_VirtualAddress,          // Default
3464 +} ;
3465 +
3466 +struct INT_s
3467 +{
3468 +       U32             ipend ;         //Pending interrupts. use INT?_
3469 +       U32             itest ;         //Test bits.            use INT?_
3470 +       U32             imask ;         //Interrupt disabled when set. use INT?_
3471 +} ;
3472 +
3473 +enum
3474 +{
3475 +       IPEND2  = 0,                    // HW 2 interrupt to core. use INT2_
3476 +       IPEND3  = 1,                    // HW 3 interrupt to core. use INT3_
3477 +       IPEND4  = 2,                    // HW 4 interrupt to core. use INT4_
3478 +       IPEND5  = 3,                    // HW 5 interrupt to core. use INT5_
3479 +       IPEND6  = 4,                    // HW 6 interrupt to core. use INT6_
3480 +
3481 +       IPEND_count,                    // must be last (used in loops)
3482 +       IPEND_min       = IPEND2        // min IPEND (used in loops)
3483 +};
3484 +
3485 +typedef struct INTC_s
3486 +{
3487 +       struct INT_s    i [IPEND_count] ;// use i[IPEND?] = INT?_
3488 +       U32             nmips ;         // use NMIPS_
3489 +} volatile *INT_t ;
3490 +
3491 +enum
3492 +{
3493 +       INT2_timer0_b                   = 0,
3494 +       INT2_timer0_m                   = 0x00000001,
3495 +       INT2_timer1_b                   = 1,
3496 +       INT2_timer1_m                   = 0x00000002,
3497 +       INT2_timer2_b                   = 2,
3498 +       INT2_timer2_m                   = 0x00000004,
3499 +       INT2_refresh_b                  = 3,
3500 +       INT2_refresh_m                  = 0x00000008,
3501 +       INT2_watchdogTimeout_b          = 4,
3502 +       INT2_watchdogTimeout_m          = 0x00000010,
3503 +       INT2_undecodedCpuWrite_b        = 5,
3504 +       INT2_undecodedCpuWrite_m        = 0x00000020,
3505 +       INT2_undecodedCpuRead_b         = 6,
3506 +       INT2_undecodedCpuRead_m         = 0x00000040,
3507 +       INT2_undecodedPciWrite_b        = 7,
3508 +       INT2_undecodedPciWrite_m        = 0x00000080,
3509 +       INT2_undecodedPciRead_b         = 8,
3510 +       INT2_undecodedPciRead_m         = 0x00000100,
3511 +       INT2_undecodedDmaWrite_b        = 9,
3512 +       INT2_undecodedDmaWrite_m        = 0x00000200,
3513 +       INT2_undecodedDmaRead_b         = 10,
3514 +       INT2_undecodedDmaRead_m         = 0x00000400,
3515 +       INT2_ipBusSlaveAckError_b       = 11,
3516 +       INT2_ipBusSlaveAckError_m       = 0x00000800,
3517 +
3518 +       INT3_dmaChannel0_b              = 0,
3519 +       INT3_dmaChannel0_m              = 0x00000001,
3520 +       INT3_dmaChannel1_b              = 1,
3521 +       INT3_dmaChannel1_m              = 0x00000002,
3522 +       INT3_dmaChannel2_b              = 2,
3523 +       INT3_dmaChannel2_m              = 0x00000004,
3524 +       INT3_dmaChannel3_b              = 3,
3525 +       INT3_dmaChannel3_m              = 0x00000008,
3526 +       INT3_dmaChannel4_b              = 4,
3527 +       INT3_dmaChannel4_m              = 0x00000010,
3528 +       INT3_dmaChannel5_b              = 5,
3529 +       INT3_dmaChannel5_m              = 0x00000020,
3530 +
3531 +       INT5_uartGeneral0_b             = 0,
3532 +       INT5_uartGeneral0_m             = 0x00000001,
3533 +       INT5_uartTxrdy0_b               = 1,
3534 +       INT5_uartTxrdy0_m               = 0x00000002,
3535 +       INT5_uartRxrdy0_b               = 2,
3536 +       INT5_uartRxrdy0_m               = 0x00000004,
3537 +       INT5_pci_b                      = 3,
3538 +       INT5_pci_m                      = 0x00000008,
3539 +       INT5_pciDecoupled_b             = 4,
3540 +       INT5_pciDecoupled_m             = 0x00000010,
3541 +       INT5_spi_b                      = 5,
3542 +       INT5_spi_m                      = 0x00000020,
3543 +       INT5_deviceDecoupled_b          = 6,
3544 +       INT5_deviceDecoupled_m          = 0x00000040,
3545 +       INT5_i2cMaster_b                = 7,
3546 +       INT5_i2cMaster_m                = 0x00000080,
3547 +       INT5_i2cSlave_b                 = 8,
3548 +       INT5_i2cSlave_m                 = 0x00000100,
3549 +       INT5_ethOvr_b                   = 9,
3550 +       INT5_ethOvr_m                   = 0x00000200,
3551 +       INT5_ethUnd_b                   = 10,
3552 +       INT5_ethUnd_m                   = 0x00000400,
3553 +       INT5_ethPfd_b                   = 11,
3554 +       INT5_ethPfd_m                   = 0x00000800,
3555 +       INT5_nvram_b                    = 12,
3556 +       INT5_nvram_m                    = 0x00001000,
3557 +
3558 +       INT6_gpio0_b                    = 0,
3559 +       INT6_gpio0_m                    = 0x00000001,
3560 +       INT6_gpio1_b                    = 1,
3561 +       INT6_gpio1_m                    = 0x00000002,
3562 +       INT6_gpio2_b                    = 2,
3563 +       INT6_gpio2_m                    = 0x00000004,
3564 +       INT6_gpio3_b                    = 3,
3565 +       INT6_gpio3_m                    = 0x00000008,
3566 +       INT6_gpio4_b                    = 4,
3567 +       INT6_gpio4_m                    = 0x00000010,
3568 +       INT6_gpio5_b                    = 5,
3569 +       INT6_gpio5_m                    = 0x00000020,
3570 +       INT6_gpio6_b                    = 6,
3571 +       INT6_gpio6_m                    = 0x00000040,
3572 +       INT6_gpio7_b                    = 7,
3573 +       INT6_gpio7_m                    = 0x00000080,
3574 +       INT6_gpio8_b                    = 8,
3575 +       INT6_gpio8_m                    = 0x00000100,
3576 +       INT6_gpio9_b                    = 9,
3577 +       INT6_gpio9_m                    = 0x00000200,
3578 +       INT6_gpio10_b                   = 10,
3579 +       INT6_gpio10_m                   = 0x00000400,
3580 +       INT6_gpio11_b                   = 11,
3581 +       INT6_gpio11_m                   = 0x00000800,
3582 +       INT6_gpio12_b                   = 12,
3583 +       INT6_gpio12_m                   = 0x00001000,
3584 +       INT6_gpio13_b                   = 13,
3585 +       INT6_gpio13_m                   = 0x00002000,
3586 +
3587 +       NMIPS_gpio_b                    = 0,
3588 +       NMIPS_gpio_m                    = 0x00000001,
3589 +} ;
3590 +
3591 +#endif // __IDT_INT_H__
3592 +
3593 +
3594 diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h
3595 --- linux.old/include/asm-mips/rc32434/iparb.h  1970-01-01 01:00:00.000000000 +0100
3596 +++ linux.dev/include/asm-mips/rc32434/iparb.h  2006-10-11 21:56:38.000000000 +0200
3597 @@ -0,0 +1,95 @@
3598 +#ifndef __IDT_IPARB_H__
3599 +#define __IDT_IPARB_H__
3600 +
3601 +/*******************************************************************************
3602 + *
3603 + * Copyright 2002 Integrated Device Technology, Inc.
3604 + *             All rights reserved.
3605 + *
3606 + * IP Arbiter register definitions.
3607 + *
3608 + * File   : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3609 + *
3610 + * Author : Allen.Stichter@idt.com
3611 + * Date   : 20020120
3612 + * Update :
3613 + *         $Log: iparb.h,v $
3614 + *         Revision 1.3  2002/06/06 18:34:04  astichte
3615 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
3616 + *
3617 + *         Revision 1.2  2002/06/05 19:01:42  astichte
3618 + *         Removed IDTField
3619 + *
3620 + *         Revision 1.1  2002/05/29 17:33:23  sysarch
3621 + *         jba File moved from vcode/include/idt/acacia
3622 + *
3623 + ******************************************************************************/
3624 +
3625 +#include  <asm/rc32434/types.h>
3626 +
3627 +enum
3628 +{
3629 +       IPARB0_PhysicalAddress  = 0x18048000,
3630 +       IPARB_PhysicalAddress   = IPARB0_PhysicalAddress,       // Default
3631 +
3632 +       IPARB0_VirtualAddress   = 0xb8048000,
3633 +       IPARB_VirtualAddress    = IPARB0_VirtualAddress,        // Default
3634 +} ;
3635 +
3636 +enum
3637 +{
3638 +       IPABMXC_ethernetReceive         = 0,
3639 +       IPABMXC_ethernetTransmit        = 1,
3640 +       IPABMXC_memoryToHoldFifo        = 2,
3641 +       IPABMXC_holdFifoToMemory        = 3,
3642 +       IPABMXC_pciToMemory             = 4,
3643 +       IPABMXC_memoryToPci             = 5,
3644 +       IPABMXC_pciTarget               = 6,
3645 +       IPABMXC_pciTargetStart          = 7,
3646 +       IPABMXC_cpuToIpBus              = 8,
3647 +
3648 +       IPABMXC_Count,                          // Must be last in list !
3649 +       IPABMXC_Min                     = IPABMXC_ethernetReceive,
3650 +
3651 +       IPAPXC_PriorityCount    = 4,            // 3-highest, 0-lowest.
3652 +} ;
3653 +
3654 +typedef struct
3655 +{
3656 +       U32     ipapc [IPAPXC_PriorityCount] ;  // ipapc[IPAPXC_] = IPAPC_
3657 +       U32     ipabmc [IPABMXC_Count] ;        // ipabmc[IPABMXC_] = IPABMC_
3658 +       U32     ipac ;                          // use IPAC_
3659 +       U32     ipaitcc;                        // use IPAITCC_
3660 +       U32     ipaspare ;
3661 +} volatile * IPARB_t ;
3662 +
3663 +enum
3664 +{
3665 +       IPAC_dwm_b                      = 2,
3666 +       IPAC_dwm_m                      = 0x00000004,
3667 +       IPAC_drm_b                      = 3,
3668 +       IPAC_drm_m                      = 0x00000008,
3669 +       IPAC_msk_b                      = 4,
3670 +       IPAC_msk_m                      = 0x00000010,
3671 +
3672 +       IPAPC_ptc_b                     = 0,
3673 +       IPAPC_ptc_m                     = 0x00003fff,
3674 +       IPAPC_mf_b                      = 14,
3675 +       IPAPC_mf_m                      = 0x00004000,
3676 +       IPAPC_cptc_b                    = 16,
3677 +       IPAPC_cptc_m                    = 0x3fff0000,
3678 +
3679 +       IPAITCC_itcc                    = 0,
3680 +       IPAITCC_itcc,                   = 0x000001ff,
3681 +
3682 +       IPABMC_mtc_b                    = 0,
3683 +       IPABMC_mtc_m                    = 0x00000fff,
3684 +       IPABMC_p_b                      = 12,
3685 +       IPABMC_p_m                      = 0x00003000,
3686 +       IPABMC_msk_b                    = 14,
3687 +       IPABMC_msk_m                    = 0x00004000,
3688 +       IPABMC_cmtc_b                   = 16,
3689 +       IPABMC_cmtc_m                   = 0x0fff0000,
3690 +};
3691 +
3692 +#endif // __IDT_IPARB_H__
3693 diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h
3694 --- linux.old/include/asm-mips/rc32434/irm.h    1970-01-01 01:00:00.000000000 +0100
3695 +++ linux.dev/include/asm-mips/rc32434/irm.h    2006-10-11 21:56:38.000000000 +0200
3696 @@ -0,0 +1,55 @@
3697 +#ifndef __IDT_IRM_H__
3698 +#define __IDT_IRM_H__
3699 +
3700 +/*******************************************************************************
3701 + *
3702 + * Copyright 2002 Integrated Device Technology, Inc.
3703 + *             All rights reserved.
3704 + *
3705 + * Internal Register Map
3706 + *
3707 + * File   : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $
3708 + *
3709 + * Author : Allen.Stichter@idt.com
3710 + * Date   : 20020605
3711 + * Update :
3712 + *          $Log: irm.h,v $
3713 + *          Revision 1.2  2002/06/05 14:51:06  astichte
3714 + *          *** empty log message ***
3715 + *
3716 + *          Revision 1.1  2002/05/29 17:33:23  sysarch
3717 + *          jba File moved from vcode/include/idt/acacia
3718 + *
3719 + ******************************************************************************/
3720 +
3721 +/*
3722 + * NOTE --
3723 + *     This file is here for backwards compatibility.
3724 + *     DO NOT USE !!!!
3725 + */
3726 +
3727 +typedef enum
3728 +{
3729 +       IRM_Physical    = 0x18000000,   // Internal Reg. map physical.
3730 +       RST_Offset      = 0x00000000,   // Includes sysid and RST.
3731 +       DEV_Offset      = 0x00010000,   // Device Controller 0.
3732 +       DDR_Offset      = 0x00018000,   // Double-Data-Rate mem. controller.
3733 +       PMARB_Offset    = 0x00020000,   // PM bus arbiter.
3734 +       TIM_Offset      = 0x00028000,   // Counter / timer.
3735 +       INTEG_Offset    = 0x00030000,   // System Integrity.
3736 +       INT_Offset      = 0x00038000,   // Interrupt controller.
3737 +       DMA_Offset      = 0x00040000,   // DMA.
3738 +       IPARB_Offset    = 0x00044000,   // IP bus arbiter.
3739 +       GPIO_Offset     = 0x00050000,   // GPIO.
3740 +       UART_Offset     = 0x00058000,   // UART
3741 +       ETH_Offset      = 0x00060000,   // Ethernet 1.
3742 +       I2C_Offset      = 0x00068000,   // I2C interface.
3743 +       SPI_Offset      = 0x00070000,   // Serial Peripheral Interface.
3744 +       NVRAM_Offset    = 0x00078000,   // NVRAM interface
3745 +       AUTH_Offset     = 0x0007c000,   // Authorization unit
3746 +       PCI_Offset      = 0x00080000,
3747 +       CROM_Offset     = 0x000b8000,   // Configuration ROM.
3748 +       IRM_Size        = 0x00200000,   // Internal Reg. map size.
3749 +} IRM_Offset_t ;
3750 +
3751 +#endif // __IDT_IRM_H__
3752 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
3753 --- linux.old/include/asm-mips/rc32434/irq.h    1970-01-01 01:00:00.000000000 +0100
3754 +++ linux.dev/include/asm-mips/rc32434/irq.h    2006-10-11 21:56:38.000000000 +0200
3755 @@ -0,0 +1,8 @@
3756 +#ifndef __ASM_MACH_MIPS_IRQ_H
3757 +#define __ASM_MACH_MIPS_IRQ_H
3758 +
3759 +#include <linux/config.h>
3760 +
3761 +#define NR_IRQS        256
3762 +
3763 +#endif /* __ASM_MACH_MIPS_IRQ_H */
3764 diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h
3765 --- linux.old/include/asm-mips/rc32434/nvram.h  1970-01-01 01:00:00.000000000 +0100
3766 +++ linux.dev/include/asm-mips/rc32434/nvram.h  2006-10-11 21:56:38.000000000 +0200
3767 @@ -0,0 +1,97 @@
3768 +#ifndef __IDT_NVRAM_H
3769 +#define __IDT_NVRAM_H
3770 +
3771 +/*******************************************************************************
3772 + *
3773 + * Copyright 2002 Integrated Device Technology, Inc.
3774 + *              All rights reserved.
3775 + *
3776 + * IP Arbiter register definitions.
3777 + *
3778 + * File   : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $
3779 + *
3780 + * Author : kiran.rao@idt.com
3781 + * Date   : 20030724
3782 + * Update :
3783 + *          $Log: nvram.h,v $
3784 + *
3785 + *
3786 + ******************************************************************************/
3787 +#include <asm/rc32434/tpes.h>
3788 +
3789 +
3790 +enum
3791 +{
3792 +        NVRAM0_PhysicalAddress    = 0xba000000,
3793 +        NVRAM_PhysicalAddress     = NVRAM0_PhysicalAddress,         // Default
3794 +
3795 +        NVRAM0_VirtualAddress     = 0xba000000,
3796 +        NVRAM_VirtualAddress      = NVRAM0_VirtualAddress,          // Default
3797 +} ;
3798 +
3799 +enum
3800 +{
3801 +       NVRCMD_cmd_b            = 0,
3802 +       NVRCMD_cmd_m            = 0x0000007f,
3803 +
3804 +       NVRS_r_b                = 0,
3805 +       NVRS_r_m                = 0x00000001,
3806 +       NVRS_e_b                = 1,
3807 +       NVRS_e_m                = 0x00000002,
3808 +       NVRS_k_b                = 2,
3809 +       NVRS_k_m                = 0x00000004,
3810 +
3811 +       NVRSM_r_b               = 0,
3812 +       NVRSM_r_m               = 0x00000001,
3813 +       NVRSM_e_b               = 1,
3814 +       NVRSM_e_m               = 0x00000002,
3815 +       NVRSM_k_b               = 2,
3816 +       NVRSM_k_m               = 0x00000004,
3817 +
3818 +       NVRCFG0_pwidth_b        = 0,
3819 +       NVRCFG0_pwidth_m        = 0x00000003,
3820 +       NVRCFG0_nmax_b          = 2,
3821 +       NVRCFG0_nmax_m          = 0x0000000C,
3822 +       NVRCFG0_vppl_b          = 4,
3823 +       NVRCFG0_vppl_m          = 0x000000f0,
3824 +       NVRCFG0_vppm_b          = 8,
3825 +       NVRCFG0_vppm_m          = 0x00000300,
3826 +       NVRCFG0_dvpp_b          = 10,
3827 +       NVRCFG0_dvpp_m          = 0x00000c00,
3828 +       NVRCFG0_x_b             = 12,
3829 +       NVRCFG0_x_m             = 0x00007000,
3830 +
3831 +       NVRCFG1_t1tecc_b        = 0,
3832 +       NVRCFG1_t1tecc_m        = 0x00000003,
3833 +       NVRCFG1_t1mrcl_b        = 2,
3834 +       NVRCFG1_t1mrcl_m        = 0x0000000c,
3835 +       NVRCFG1_t1bias_b        = 4,
3836 +       NVRCFG1_t1bias_m        = 0x00000030,
3837 +       NVRCFG1_t2tecc_b        = 6,
3838 +       NVRCFG1_t2tecc_m        = 0x000000c0,
3839 +       NVRCFG1_t2mrcl_b        = 8,
3840 +       NVRCFG1_t2mrcl_m        = 0x00000300,
3841 +       NVRCFG1_t2bias_b        = 10,
3842 +       NVRCFG1_t2bias_m        = 0x00000c00,
3843 +       NVRCFG1_t3tecc_b        = 12,
3844 +       NVRCFG1_t3tecc_m        = 0x00003000,
3845 +       NVRCFG1_t3mrcl_b        = 14,
3846 +       NVRCFG1_t3mrcl_m        = 0x0000c000,
3847 +       NVRCFG1_t3bias_b        = 16,
3848 +       NVRCFG1_t3bias_m        = 0x00030000,
3849 +       NVRCFG1_t4tecc_b        = 18,
3850 +       NVRCFG1_t4tecc_m        = 0x000c0000,
3851 +       NVRCFG1_t4mrcl_b        = 20,
3852 +       NVRCFG1_t4mrcl_m        = 0x00300000,
3853 +       NVRCFG1_t4bias_b        = 22,
3854 +       NVRCFG1_t4bias_m        = 0x00c00000,
3855 +       NVRCFG1_t5tecc_b        = 24,
3856 +       NVRCFG1_t5tecc_m        = 0x03000000,
3857 +       NVRCFG1_t5mrcl_b        = 26,
3858 +       NVRCFG1_t5mrcl_m        = 0x0c000000,
3859 +       NVRCFG1_t5bias_b        = 28,
3860 +       NVRCFG1_t5bias_m        = 0x30000000,
3861 +}
3862 +
3863 +#endif  // __IDT_NVRAM_H__
3864 +
3865 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
3866 --- linux.old/include/asm-mips/rc32434/pci.h    1970-01-01 01:00:00.000000000 +0100
3867 +++ linux.dev/include/asm-mips/rc32434/pci.h    2006-10-11 21:56:38.000000000 +0200
3868 @@ -0,0 +1,695 @@
3869 +/**************************************************************************
3870 + *
3871 + *  BRIEF MODULE DESCRIPTION
3872 + *   PCI register definitio
3873 + *
3874 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
3875 + *
3876 + *  This program is free software; you can redistribute  it and/or modify it
3877 + *  under  the terms of  the GNU General  Public License as published by the
3878 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3879 + *  option) any later version.
3880 + *
3881 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3882 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3883 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3884 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3885 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3886 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3887 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3888 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3889 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3890 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3891 + *
3892 + *  You should have received a copy of the  GNU General Public License along
3893 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3894 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3895 + *
3896 + *
3897 + **************************************************************************
3898 + * May 2004 rkt, neb.
3899 + *
3900 + * Initial Release
3901 + *
3902 + *
3903 + *
3904 + **************************************************************************
3905 + */
3906 +
3907 +#ifndef __IDT_PCI_H__
3908 +#define __IDT_PCI_H__
3909 +
3910 +enum
3911 +{
3912 +       PCI0_PhysicalAddress    = 0x18080000,
3913 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
3914 +
3915 +       PCI0_VirtualAddress     = 0xB8080000,
3916 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
3917 +} ;
3918 +
3919 +enum
3920 +{
3921 +       PCI_LbaCount    = 4,            // Local base addresses.
3922 +} ;
3923 +
3924 +typedef struct
3925 +{
3926 +       u32     a ;             // Address.
3927 +       u32     c ;             // Control.
3928 +       u32     m ;             // mapping.
3929 +} PCI_Map_s ;
3930 +
3931 +typedef struct
3932 +{
3933 +       u32             pcic ;
3934 +       u32             pcis ;
3935 +       u32             pcism ;
3936 +       u32             pcicfga ;
3937 +       u32             pcicfgd ;
3938 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
3939 +       u32             pcidac ;
3940 +       u32             pcidas ;
3941 +       u32             pcidasm ;
3942 +       u32             pcidad ;
3943 +       u32             pcidma8c ;
3944 +       u32             pcidma9c ;
3945 +       u32             pcitc ;
3946 +} volatile *PCI_t ;
3947 +
3948 +// PCI messaging unit.
3949 +enum
3950 +{
3951 +       PCIM_Count      = 2,
3952 +} ;
3953 +typedef struct
3954 +{
3955 +       u32             pciim [PCIM_Count] ;
3956 +       u32             pciom [PCIM_Count] ;
3957 +       u32             pciid ;
3958 +       u32             pciiic ;
3959 +       u32             pciiim ;
3960 +       u32             pciiod ;
3961 +       u32             pciioic ;
3962 +       u32             pciioim ;
3963 +} volatile *PCIM_t ;
3964 +
3965 +/*******************************************************************************
3966 + *
3967 + * PCI Control Register
3968 + *
3969 + ******************************************************************************/
3970 +enum
3971 +{
3972 +       PCIC_en_b       = 0,
3973 +       PCIC_en_m       = 0x00000001,
3974 +       PCIC_tnr_b      = 1,
3975 +       PCIC_tnr_m      = 0x00000002,
3976 +       PCIC_sce_b      = 2,
3977 +       PCIC_sce_m      = 0x00000004,
3978 +       PCIC_ien_b      = 3,
3979 +       PCIC_ien_m      = 0x00000008,
3980 +       PCIC_aaa_b      = 4,
3981 +       PCIC_aaa_m      = 0x00000010,
3982 +       PCIC_eap_b      = 5,
3983 +       PCIC_eap_m      = 0x00000020,
3984 +       PCIC_pcim_b     = 6,
3985 +       PCIC_pcim_m     = 0x000001c0,
3986 +               PCIC_pcim_disabled_v    = 0,
3987 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
3988 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
3989 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
3990 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
3991 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
3992 +               PCIC_pcim_reserved6_v   = 6,
3993 +               PCIC_pcim_reserved7_v   = 7,
3994 +       PCIC_igm_b      = 9,
3995 +       PCIC_igm_m      = 0x00000200,
3996 +} ;
3997 +
3998 +/*******************************************************************************
3999 + *
4000 + * PCI Status Register
4001 + *
4002 + ******************************************************************************/
4003 +enum {
4004 +       PCIS_eed_b      = 0,
4005 +       PCIS_eed_m      = 0x00000001,
4006 +       PCIS_wr_b       = 1,
4007 +       PCIS_wr_m       = 0x00000002,
4008 +       PCIS_nmi_b      = 2,
4009 +       PCIS_nmi_m      = 0x00000004,
4010 +       PCIS_ii_b       = 3,
4011 +       PCIS_ii_m       = 0x00000008,
4012 +       PCIS_cwe_b      = 4,
4013 +       PCIS_cwe_m      = 0x00000010,
4014 +       PCIS_cre_b      = 5,
4015 +       PCIS_cre_m      = 0x00000020,
4016 +       PCIS_mdpe_b     = 6,
4017 +       PCIS_mdpe_m     = 0x00000040,
4018 +       PCIS_sta_b      = 7,
4019 +       PCIS_sta_m      = 0x00000080,
4020 +       PCIS_rta_b      = 8,
4021 +       PCIS_rta_m      = 0x00000100,
4022 +       PCIS_rma_b      = 9,
4023 +       PCIS_rma_m      = 0x00000200,
4024 +       PCIS_sse_b      = 10,
4025 +       PCIS_sse_m      = 0x00000400,
4026 +       PCIS_ose_b      = 11,
4027 +       PCIS_ose_m      = 0x00000800,
4028 +       PCIS_pe_b       = 12,
4029 +       PCIS_pe_m       = 0x00001000,
4030 +       PCIS_tae_b      = 13,
4031 +       PCIS_tae_m      = 0x00002000,
4032 +       PCIS_rle_b      = 14,
4033 +       PCIS_rle_m      = 0x00004000,
4034 +       PCIS_bme_b      = 15,
4035 +       PCIS_bme_m      = 0x00008000,
4036 +       PCIS_prd_b      = 16,
4037 +       PCIS_prd_m      = 0x00010000,
4038 +       PCIS_rip_b      = 17,
4039 +       PCIS_rip_m      = 0x00020000,
4040 +} ;
4041 +
4042 +/*******************************************************************************
4043 + *
4044 + * PCI Status Mask Register
4045 + *
4046 + ******************************************************************************/
4047 +enum {
4048 +       PCISM_eed_b             = 0,
4049 +       PCISM_eed_m             = 0x00000001,
4050 +       PCISM_wr_b              = 1,
4051 +       PCISM_wr_m              = 0x00000002,
4052 +       PCISM_nmi_b             = 2,
4053 +       PCISM_nmi_m             = 0x00000004,
4054 +       PCISM_ii_b              = 3,
4055 +       PCISM_ii_m              = 0x00000008,
4056 +       PCISM_cwe_b             = 4,
4057 +       PCISM_cwe_m             = 0x00000010,
4058 +       PCISM_cre_b             = 5,
4059 +       PCISM_cre_m             = 0x00000020,
4060 +       PCISM_mdpe_b            = 6,
4061 +       PCISM_mdpe_m            = 0x00000040,
4062 +       PCISM_sta_b             = 7,
4063 +       PCISM_sta_m             = 0x00000080,
4064 +       PCISM_rta_b             = 8,
4065 +       PCISM_rta_m             = 0x00000100,
4066 +       PCISM_rma_b             = 9,
4067 +       PCISM_rma_m             = 0x00000200,
4068 +       PCISM_sse_b             = 10,
4069 +       PCISM_sse_m             = 0x00000400,
4070 +       PCISM_ose_b             = 11,
4071 +       PCISM_ose_m             = 0x00000800,
4072 +       PCISM_pe_b              = 12,
4073 +       PCISM_pe_m              = 0x00001000,
4074 +       PCISM_tae_b             = 13,
4075 +       PCISM_tae_m             = 0x00002000,
4076 +       PCISM_rle_b             = 14,
4077 +       PCISM_rle_m             = 0x00004000,
4078 +       PCISM_bme_b             = 15,
4079 +       PCISM_bme_m             = 0x00008000,
4080 +       PCISM_prd_b             = 16,
4081 +       PCISM_prd_m             = 0x00010000,
4082 +       PCISM_rip_b             = 17,
4083 +       PCISM_rip_m             = 0x00020000,
4084 +} ;
4085 +
4086 +/*******************************************************************************
4087 + *
4088 + * PCI Configuration Address Register
4089 + *
4090 + ******************************************************************************/
4091 +enum {
4092 +       PCICFGA_reg_b           = 2,
4093 +       PCICFGA_reg_m           = 0x000000fc,
4094 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
4095 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
4096 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
4097 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
4098 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
4099 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
4100 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
4101 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
4102 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
4103 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
4104 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
4105 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
4106 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
4107 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
4108 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
4109 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
4110 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
4111 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
4112 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
4113 +       PCICFGA_func_b          = 8,
4114 +       PCICFGA_func_m          = 0x00000700,
4115 +       PCICFGA_dev_b           = 11,
4116 +       PCICFGA_dev_m           = 0x0000f800,
4117 +               PCICFGA_dev_internal_v  = 0,
4118 +       PCICFGA_bus_b           = 16,
4119 +       PCICFGA_bus_m           = 0x00ff0000,
4120 +               PCICFGA_bus_type0_v     = 0,    //local bus
4121 +       PCICFGA_en_b            = 31,           // read only
4122 +       PCICFGA_en_m            = 0x80000000,
4123 +} ;
4124 +
4125 +enum {
4126 +       PCFGID_vendor_b         = 0,
4127 +       PCFGID_vendor_m         = 0x0000ffff,
4128 +               PCFGID_vendor_IDT_v             = 0x111d,
4129 +       PCFGID_device_b         = 16,
4130 +       PCFGID_device_m         = 0xffff0000,
4131 +               PCFGID_device_Korinade_v        = 0x0214,
4132 +
4133 +       PCFG04_command_ioena_b          = 1,
4134 +       PCFG04_command_ioena_m          = 0x00000001,
4135 +       PCFG04_command_memena_b         = 2,
4136 +       PCFG04_command_memena_m         = 0x00000002,
4137 +       PCFG04_command_bmena_b          = 3,
4138 +       PCFG04_command_bmena_m          = 0x00000004,
4139 +       PCFG04_command_mwinv_b          = 5,
4140 +       PCFG04_command_mwinv_m          = 0x00000010,
4141 +       PCFG04_command_parena_b         = 7,
4142 +       PCFG04_command_parena_m         = 0x00000040,
4143 +       PCFG04_command_serrena_b        = 9,
4144 +       PCFG04_command_serrena_m        = 0x00000100,
4145 +       PCFG04_command_fastbbena_b      = 10,
4146 +       PCFG04_command_fastbbena_m      = 0x00000200,
4147 +       PCFG04_status_b                 = 16,
4148 +       PCFG04_status_m                 = 0xffff0000,
4149 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
4150 +       PCFG04_status_66MHz_m           = 0x00200000,
4151 +       PCFG04_status_fbb_b             = 23,
4152 +       PCFG04_status_fbb_m             = 0x00800000,
4153 +       PCFG04_status_mdpe_b            = 24,
4154 +       PCFG04_status_mdpe_m            = 0x01000000,
4155 +       PCFG04_status_dst_b             = 25,
4156 +       PCFG04_status_dst_m             = 0x06000000,
4157 +       PCFG04_status_sta_b             = 27,
4158 +       PCFG04_status_sta_m             = 0x08000000,
4159 +       PCFG04_status_rta_b             = 28,
4160 +       PCFG04_status_rta_m             = 0x10000000,
4161 +       PCFG04_status_rma_b             = 29,
4162 +       PCFG04_status_rma_m             = 0x20000000,
4163 +       PCFG04_status_sse_b             = 30,
4164 +       PCFG04_status_sse_m             = 0x40000000,
4165 +       PCFG04_status_pe_b              = 31,
4166 +       PCFG04_status_pe_m              = 0x40000000,
4167 +
4168 +       PCFG08_revId_b                  = 0,
4169 +       PCFG08_revId_m                  = 0x000000ff,
4170 +       PCFG08_classCode_b              = 0,
4171 +       PCFG08_classCode_m              = 0xffffff00,
4172 +               PCFG08_classCode_bridge_v       = 06,
4173 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
4174 +       PCFG0C_cacheline_b              = 0,
4175 +       PCFG0C_cacheline_m              = 0x000000ff,
4176 +       PCFG0C_masterLatency_b          = 8,
4177 +       PCFG0C_masterLatency_m          = 0x0000ff00,
4178 +       PCFG0C_headerType_b             = 16,
4179 +       PCFG0C_headerType_m             = 0x00ff0000,
4180 +       PCFG0C_bist_b                   = 24,
4181 +       PCFG0C_bist_m                   = 0xff000000,
4182 +
4183 +       PCIPBA_msi_b                    = 0,
4184 +       PCIPBA_msi_m                    = 0x00000001,
4185 +       PCIPBA_p_b                      = 3,
4186 +       PCIPBA_p_m                      = 0x00000004,
4187 +       PCIPBA_baddr_b                  = 8,
4188 +       PCIPBA_baddr_m                  = 0xffffff00,
4189 +
4190 +       PCFGSS_vendorId_b               = 0,
4191 +       PCFGSS_vendorId_m               = 0x0000ffff,
4192 +       PCFGSS_id_b                     = 16,
4193 +       PCFGSS_id_m                     = 0xffff0000,
4194 +
4195 +       PCFG3C_interruptLine_b          = 0,
4196 +       PCFG3C_interruptLine_m          = 0x000000ff,
4197 +       PCFG3C_interruptPin_b           = 8,
4198 +       PCFG3C_interruptPin_m           = 0x0000ff00,
4199 +       PCFG3C_minGrant_b               = 16,
4200 +       PCFG3C_minGrant_m               = 0x00ff0000,
4201 +       PCFG3C_maxLat_b                 = 24,
4202 +       PCFG3C_maxLat_m                 = 0xff000000,
4203 +
4204 +       PCIPBAC_msi_b                   = 0,
4205 +       PCIPBAC_msi_m                   = 0x00000001,
4206 +       PCIPBAC_p_b                     = 1,
4207 +       PCIPBAC_p_m                     = 0x00000002,
4208 +       PCIPBAC_size_b                  = 2,
4209 +       PCIPBAC_size_m                  = 0x0000007c,
4210 +       PCIPBAC_sb_b                    = 7,
4211 +       PCIPBAC_sb_m                    = 0x00000080,
4212 +       PCIPBAC_pp_b                    = 8,
4213 +       PCIPBAC_pp_m                    = 0x00000100,
4214 +       PCIPBAC_mr_b                    = 9,
4215 +       PCIPBAC_mr_m                    = 0x00000600,
4216 +               PCIPBAC_mr_read_v       =0,     //no prefetching
4217 +               PCIPBAC_mr_readLine_v   =1,
4218 +               PCIPBAC_mr_readMult_v   =2,
4219 +       PCIPBAC_mrl_b                   = 11,
4220 +       PCIPBAC_mrl_m                   = 0x00000800,
4221 +       PCIPBAC_mrm_b                   = 12,
4222 +       PCIPBAC_mrm_m                   = 0x00001000,
4223 +       PCIPBAC_trp_b                   = 13,
4224 +       PCIPBAC_trp_m                   = 0x00002000,
4225 +
4226 +       PCFG40_trdyTimeout_b            = 0,
4227 +       PCFG40_trdyTimeout_m            = 0x000000ff,
4228 +       PCFG40_retryLim_b               = 8,
4229 +       PCFG40_retryLim_m               = 0x0000ff00,
4230 +};
4231 +
4232 +/*******************************************************************************
4233 + *
4234 + * PCI Local Base Address [0|1|2|3] Register
4235 + *
4236 + ******************************************************************************/
4237 +enum {
4238 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
4239 +       PCILBA_baddr_m          = 0xffffff00,
4240 +} ;
4241 +/*******************************************************************************
4242 + *
4243 + * PCI Local Base Address Control Register
4244 + *
4245 + ******************************************************************************/
4246 +enum {
4247 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
4248 +       PCILBAC_msi_m           = 0x00000001,
4249 +               PCILBAC_msi_mem_v       = 0,
4250 +               PCILBAC_msi_io_v        = 1,
4251 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
4252 +       PCILBAC_size_m          = 0x0000007c,
4253 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
4254 +       PCILBAC_sb_m            = 0x00000080,
4255 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
4256 +       PCILBAC_rt_m            = 0x00000100,
4257 +               PCILBAC_rt_noprefetch_v = 0, // mem read
4258 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
4259 +} ;
4260 +
4261 +/*******************************************************************************
4262 + *
4263 + * PCI Local Base Address [0|1|2|3] Mapping Register
4264 + *
4265 + ******************************************************************************/
4266 +enum {
4267 +       PCILBAM_maddr_b         = 8,
4268 +       PCILBAM_maddr_m         = 0xffffff00,
4269 +} ;
4270 +
4271 +/*******************************************************************************
4272 + *
4273 + * PCI Decoupled Access Control Register
4274 + *
4275 + ******************************************************************************/
4276 +enum {
4277 +       PCIDAC_den_b            = 0,
4278 +       PCIDAC_den_m            = 0x00000001,
4279 +} ;
4280 +
4281 +/*******************************************************************************
4282 + *
4283 + * PCI Decoupled Access Status Register
4284 + *
4285 + ******************************************************************************/
4286 +enum {
4287 +       PCIDAS_d_b      = 0,
4288 +       PCIDAS_d_m      = 0x00000001,
4289 +       PCIDAS_b_b      = 1,
4290 +       PCIDAS_b_m      = 0x00000002,
4291 +       PCIDAS_e_b      = 2,
4292 +       PCIDAS_e_m      = 0x00000004,
4293 +       PCIDAS_ofe_b    = 3,
4294 +       PCIDAS_ofe_m    = 0x00000008,
4295 +       PCIDAS_off_b    = 4,
4296 +       PCIDAS_off_m    = 0x00000010,
4297 +       PCIDAS_ife_b    = 5,
4298 +       PCIDAS_ife_m    = 0x00000020,
4299 +       PCIDAS_iff_b    = 6,
4300 +       PCIDAS_iff_m    = 0x00000040,
4301 +} ;
4302 +
4303 +/*******************************************************************************
4304 + *
4305 + * PCI DMA Channel 8 Configuration Register
4306 + *
4307 + ******************************************************************************/
4308 +enum
4309 +{
4310 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
4311 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
4312 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
4313 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
4314 +} ;
4315 +
4316 +/*******************************************************************************
4317 + *
4318 + * PCI DMA Channel 9 Configuration Register
4319 + *
4320 + ******************************************************************************/
4321 +enum
4322 +{
4323 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
4324 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
4325 +} ;
4326 +
4327 +/*******************************************************************************
4328 + *
4329 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
4330 + *
4331 + ******************************************************************************/
4332 +enum {
4333 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
4334 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
4335 +               // These are for reads (DMA channel 8)
4336 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
4337 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
4338 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
4339 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
4340 +               // These are for writes (DMA channel 9)
4341 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
4342 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
4343 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
4344 +
4345 +       // Swap byte field applies to both DMA channel 8 and 9
4346 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
4347 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
4348 +} ;
4349 +
4350 +
4351 +/*******************************************************************************
4352 + *
4353 + * PCI Target Control Register
4354 + *
4355 + ******************************************************************************/
4356 +enum
4357 +{
4358 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
4359 +       PCITC_rtimer_m          = 0x000000ff,
4360 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
4361 +       PCITC_dtimer_m          = 0x0000ff00,
4362 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
4363 +       PCITC_rdr_m             = 0x00040000,
4364 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
4365 +       PCITC_ddt_m             = 0x00080000,
4366 +} ;
4367 +/*******************************************************************************
4368 + *
4369 + * PCI messaging unit [applies to both inbound and outbound registers ]
4370 + *
4371 + ******************************************************************************/
4372 +enum
4373 +{
4374 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4375 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
4376 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4377 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
4378 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4379 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
4380 +};
4381 +
4382 +
4383 +
4384 +
4385 +
4386 +
4387 +#define PCI_MSG_VirtualAddress      0xB8088010
4388 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4389 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4390 +
4391 +#define PCIM_SHFT              0x6
4392 +#define PCIM_BIT_LEN           0x7
4393 +#define PCIM_H_EA              0x3
4394 +#define PCIM_H_IA_FIX          0x4
4395 +#define PCIM_H_IA_RR           0x5
4396 +#if 0
4397 +#define PCI_ADDR_START         0x13000000
4398 +#endif
4399 +
4400 +#define PCI_ADDR_START         0x50000000
4401 +
4402 +#define CPUTOPCI_MEM_WIN       0x02000000
4403 +#define CPUTOPCI_IO_WIN                0x00100000
4404 +#define PCILBA_SIZE_SHFT       2
4405 +#define PCILBA_SIZE_MASK       0x1F
4406 +#define SIZE_256MB             0x1C
4407 +#define SIZE_128MB             0x1B
4408 +#define SIZE_64MB               0x1A
4409 +#define SIZE_32MB              0x19
4410 +#define SIZE_16MB               0x18
4411 +#define SIZE_4MB               0x16
4412 +#define SIZE_2MB               0x15
4413 +#define SIZE_1MB               0x14
4414 +#define KORINA_CONFIG0_ADDR    0x80000000
4415 +#define KORINA_CONFIG1_ADDR    0x80000004
4416 +#define KORINA_CONFIG2_ADDR    0x80000008
4417 +#define KORINA_CONFIG3_ADDR    0x8000000C
4418 +#define KORINA_CONFIG4_ADDR    0x80000010
4419 +#define KORINA_CONFIG5_ADDR    0x80000014
4420 +#define KORINA_CONFIG6_ADDR    0x80000018
4421 +#define KORINA_CONFIG7_ADDR    0x8000001C
4422 +#define KORINA_CONFIG8_ADDR    0x80000020
4423 +#define KORINA_CONFIG9_ADDR    0x80000024
4424 +#define KORINA_CONFIG10_ADDR   0x80000028
4425 +#define KORINA_CONFIG11_ADDR   0x8000002C
4426 +#define KORINA_CONFIG12_ADDR   0x80000030
4427 +#define KORINA_CONFIG13_ADDR   0x80000034
4428 +#define KORINA_CONFIG14_ADDR   0x80000038
4429 +#define KORINA_CONFIG15_ADDR   0x8000003C
4430 +#define KORINA_CONFIG16_ADDR   0x80000040
4431 +#define KORINA_CONFIG17_ADDR   0x80000044
4432 +#define KORINA_CONFIG18_ADDR   0x80000048
4433 +#define KORINA_CONFIG19_ADDR   0x8000004C
4434 +#define KORINA_CONFIG20_ADDR   0x80000050
4435 +#define KORINA_CONFIG21_ADDR   0x80000054
4436 +#define KORINA_CONFIG22_ADDR   0x80000058
4437 +#define KORINA_CONFIG23_ADDR   0x8000005C
4438 +#define KORINA_CONFIG24_ADDR   0x80000060
4439 +#define KORINA_CONFIG25_ADDR   0x80000064
4440 +#define KORINA_CMD             (PCFG04_command_ioena_m | \
4441 +                                PCFG04_command_memena_m | \
4442 +                                PCFG04_command_bmena_m | \
4443 +                                PCFG04_command_mwinv_m | \
4444 +                                PCFG04_command_parena_m | \
4445 +                                PCFG04_command_serrena_m )
4446 +
4447 +#define KORINA_STAT            (PCFG04_status_mdpe_m | \
4448 +                                PCFG04_status_sta_m  | \
4449 +                                PCFG04_status_rta_m  | \
4450 +                                PCFG04_status_rma_m  | \
4451 +                                PCFG04_status_sse_m  | \
4452 +                                PCFG04_status_pe_m)
4453 +
4454 +#define KORINA_CNFG1           ((KORINA_STAT<<16)|KORINA_CMD)
4455 +
4456 +#define KORINA_REVID           0
4457 +#define KORINA_CLASS_CODE      0
4458 +#define KORINA_CNFG2           ((KORINA_CLASS_CODE<<8) | \
4459 +                                 KORINA_REVID)
4460 +
4461 +#define KORINA_CACHE_LINE_SIZE 4
4462 +#define KORINA_MASTER_LAT      0x3c
4463 +#define KORINA_HEADER_TYPE     0
4464 +#define KORINA_BIST            0
4465 +
4466 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4467 +                     (KORINA_HEADER_TYPE<<16) | \
4468 +                     (KORINA_MASTER_LAT<<8) | \
4469 +                     KORINA_CACHE_LINE_SIZE )
4470 +
4471 +#define KORINA_BAR0    0x00000008 /* 128 MB Memory */
4472 +#define KORINA_BAR1    0x18800001 /* 1 MB IO */
4473 +#define KORINA_BAR2    0x18000001 /* 2 MB IO window for Korina
4474 +                                       internal Registers */
4475 +#define KORINA_BAR3    0x48000008 /* Spare 128 MB Memory */
4476 +
4477 +#define KORINA_CNFG4   KORINA_BAR0
4478 +#define KORINA_CNFG5    KORINA_BAR1
4479 +#define KORINA_CNFG6   KORINA_BAR2
4480 +#define KORINA_CNFG7   KORINA_BAR3
4481 +
4482 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
4483 +#define KORINA_SUBSYSTEM_ID    0x0214
4484 +#define KORINA_CNFG8           0
4485 +#define KORINA_CNFG9           0
4486 +#define KORINA_CNFG10          0
4487 +#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4488 +                         KORINA_SUBSYSTEM_ID)
4489 +#define KORINA_INT_LINE                1
4490 +#define KORINA_INT_PIN         1
4491 +#define KORINA_MIN_GNT         8
4492 +#define KORINA_MAX_LAT         0x38
4493 +#define KORINA_CNFG12          0
4494 +#define KORINA_CNFG13          0
4495 +#define KORINA_CNFG14          0
4496 +#define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
4497 +                        (KORINA_MIN_GNT<<16) | \
4498 +                        (KORINA_INT_PIN<<8)  | \
4499 +                         KORINA_INT_LINE)
4500 +#define        KORINA_RETRY_LIMIT      0x80
4501 +#define KORINA_TRDY_LIMIT      0x80
4502 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4503 +                       KORINA_TRDY_LIMIT)
4504 +#define PCI_PBAxC_R            0x0
4505 +#define PCI_PBAxC_RL           0x1
4506 +#define PCI_PBAxC_RM           0x2
4507 +#define SIZE_SHFT              2
4508 +
4509 +#if defined(__MIPSEB__)
4510 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4511 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4512 +                         PCIPBAC_pp_m | \
4513 +                         (SIZE_128MB<<SIZE_SHFT) | \
4514 +                          PCIPBAC_p_m)
4515 +#else
4516 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | \
4517 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4518 +                         PCIPBAC_pp_m | \
4519 +                         (SIZE_128MB<<SIZE_SHFT) | \
4520 +                          PCIPBAC_p_m)
4521 +#endif
4522 +#define KORINA_CNFG17  KORINA_PBA0C
4523 +#define KORINA_PBA0M   0x0
4524 +#define KORINA_CNFG18  KORINA_PBA0M
4525 +
4526 +#if defined(__MIPSEB__)
4527 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4528 +                         PCIPBAC_msi_m)
4529 +#else
4530 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | \
4531 +                         PCIPBAC_msi_m)
4532 +#endif
4533 +#define KORINA_CNFG19  KORINA_PBA1C
4534 +#define KORINA_PBA1M   0x0
4535 +#define KORINA_CNFG20  KORINA_PBA1M
4536 +
4537 +#if defined(__MIPSEB__)
4538 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4539 +                         PCIPBAC_msi_m)
4540 +#else
4541 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | \
4542 +                         PCIPBAC_msi_m)
4543 +#endif
4544 +#define KORINA_CNFG21  KORINA_PBA2C
4545 +#define KORINA_PBA2M   0x18000000
4546 +#define KORINA_CNFG22  KORINA_PBA2M
4547 +#define KORINA_PBA3C   0
4548 +#define KORINA_CNFG23  KORINA_PBA3C
4549 +#define KORINA_PBA3M   0
4550 +#define KORINA_CNFG24  KORINA_PBA3M
4551 +
4552 +
4553 +
4554 +#define        PCITC_DTIMER_VAL        8
4555 +#define PCITC_RTIMER_VAL       0x10
4556 +
4557 +
4558 +
4559 +
4560 +#endif // __IDT_PCI_H__
4561 +
4562 +
4563 +
4564 diff -urN linux.old/include/asm-mips/rc32434/pcikorina.h linux.dev/include/asm-mips/rc32434/pcikorina.h
4565 --- linux.old/include/asm-mips/rc32434/pcikorina.h      1970-01-01 01:00:00.000000000 +0100
4566 +++ linux.dev/include/asm-mips/rc32434/pcikorina.h      2006-10-11 21:56:38.000000000 +0200
4567 @@ -0,0 +1,209 @@
4568 +/* $Id: pciacacia.h,v 1.5 2001/05/01 10:09:17 carstenl Exp $
4569 + *
4570 + * This file is subject to the terms and conditions of the GNU General Public
4571 + * License.  See the file "COPYING" in the main directory of this archive
4572 + * for more details.
4573 + */
4574 +#ifndef _PCIKORINA_H
4575 +#define _PCIKORINA_H
4576 +
4577 +
4578 +#define PCI_MSG_VirtualAddress      0xB8088010
4579 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4580 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4581 +
4582 +#define PCIM_SHFT              0x6
4583 +#define PCIM_BIT_LEN           0x7
4584 +#define PCIM_H_EA              0x3
4585 +#define PCIM_H_IA_FIX          0x4
4586 +#define PCIM_H_IA_RR           0x5
4587 +#if 0
4588 +#define PCI_ADDR_START         0x13000000
4589 +#endif
4590 +
4591 +#define PCI_ADDR_START         0x50000000
4592 +
4593 +#define CPUTOPCI_MEM_WIN       0x02000000
4594 +#define CPUTOPCI_IO_WIN                0x00100000
4595 +#define PCILBA_SIZE_SHFT       2
4596 +#define PCILBA_SIZE_MASK       0x1F
4597 +#define SIZE_256MB             0x1C
4598 +#define SIZE_128MB             0x1B
4599 +#define SIZE_64MB               0x1A
4600 +#define SIZE_32MB              0x19
4601 +#define SIZE_16MB               0x18
4602 +#define SIZE_4MB               0x16
4603 +#define SIZE_2MB               0x15
4604 +#define SIZE_1MB               0x14
4605 +#define KORINA_CONFIG0_ADDR    0x80000000
4606 +#define KORINA_CONFIG1_ADDR    0x80000004
4607 +#define KORINA_CONFIG2_ADDR    0x80000008
4608 +#define KORINA_CONFIG3_ADDR    0x8000000C
4609 +#define KORINA_CONFIG4_ADDR    0x80000010
4610 +#define KORINA_CONFIG5_ADDR    0x80000014
4611 +#define KORINA_CONFIG6_ADDR    0x80000018
4612 +#define KORINA_CONFIG7_ADDR    0x8000001C
4613 +#define KORINA_CONFIG8_ADDR    0x80000020
4614 +#define KORINA_CONFIG9_ADDR    0x80000024
4615 +#define KORINA_CONFIG10_ADDR   0x80000028
4616 +#define KORINA_CONFIG11_ADDR   0x8000002C
4617 +#define KORINA_CONFIG12_ADDR   0x80000030
4618 +#define KORINA_CONFIG13_ADDR   0x80000034
4619 +#define KORINA_CONFIG14_ADDR   0x80000038
4620 +#define KORINA_CONFIG15_ADDR   0x8000003C
4621 +#define KORINA_CONFIG16_ADDR   0x80000040
4622 +#define KORINA_CONFIG17_ADDR   0x80000044
4623 +#define KORINA_CONFIG18_ADDR   0x80000048
4624 +#define KORINA_CONFIG19_ADDR   0x8000004C
4625 +#define KORINA_CONFIG20_ADDR   0x80000050
4626 +#define KORINA_CONFIG21_ADDR   0x80000054
4627 +#define KORINA_CONFIG22_ADDR   0x80000058
4628 +#define KORINA_CONFIG23_ADDR   0x8000005C
4629 +#define KORINA_CONFIG24_ADDR   0x80000060
4630 +#define KORINA_CONFIG25_ADDR   0x80000064
4631 +#define KORINA_CMD             (PCFG04_command_ioena_m | \
4632 +                                PCFG04_command_memena_m | \
4633 +                                PCFG04_command_bmena_m | \
4634 +                                PCFG04_command_mwinv_m | \
4635 +                                PCFG04_command_parena_m | \
4636 +                                PCFG04_command_serrena_m )
4637 +
4638 +#define KORINA_STAT            (PCFG04_status_mdpe_m | \
4639 +                                PCFG04_status_sta_m  | \
4640 +                                PCFG04_status_rta_m  | \
4641 +                                PCFG04_status_rma_m  | \
4642 +                                PCFG04_status_sse_m  | \
4643 +                                PCFG04_status_pe_m)
4644 +
4645 +#define KORINA_CNFG1           ((KORINA_STAT<<16)|KORINA_CMD)
4646 +
4647 +#define KORINA_REVID           0
4648 +#define KORINA_CLASS_CODE      0
4649 +#define KORINA_CNFG2           ((KORINA_CLASS_CODE<<8) | \
4650 +                                 KORINA_REVID)
4651 +
4652 +#define KORINA_CACHE_LINE_SIZE 4
4653 +#define KORINA_MASTER_LAT      0x3c
4654 +#define KORINA_HEADER_TYPE     0
4655 +#define KORINA_BIST            0
4656 +
4657 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4658 +                     (KORINA_HEADER_TYPE<<16) | \
4659 +                     (KORINA_MASTER_LAT<<8) | \
4660 +                     KORINA_CACHE_LINE_SIZE )
4661 +
4662 +#define KORINA_BAR0    0x00000008 /* 128 MB Memory */
4663 +#define KORINA_BAR1    0x18800001 /* 1 MB IO */
4664 +#define KORINA_BAR2    0x18000001 /* 2 MB IO window for Acacia
4665 +                                       internal Registers */
4666 +#define KORINA_BAR3    0x48000008 /* Spare 128 MB Memory */
4667 +
4668 +#define KORINA_CNFG4   KORINA_BAR0
4669 +#define KORINA_CNFG5    KORINA_BAR1
4670 +#define KORINA_CNFG6   KORINA_BAR2
4671 +#define KORINA_CNFG7   KORINA_BAR3
4672 +
4673 +#define KORINA_SUBSYS_VENDOR_ID 0
4674 +#define KORINA_SUBSYSTEM_ID    0
4675 +#define KORINA_CNFG8           0
4676 +#define KORINA_CNFG9           0
4677 +#define KORINA_CNFG10          0
4678 +#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4679 +                         KORINA_SUBSYSTEM_ID)
4680 +#define KORINA_INT_LINE                1
4681 +#define KORINA_INT_PIN         1
4682 +#define KORINA_MIN_GNT         8
4683 +#define KORINA_MAX_LAT         0x38
4684 +#define KORINA_CNFG12          0
4685 +#define KORINA_CNFG13          0
4686 +#define KORINA_CNFG14          0
4687 +#define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
4688 +                        (KORINA_MIN_GNT<<16) | \
4689 +                        (KORINA_INT_PIN<<8)  | \
4690 +                         KORINA_INT_LINE)
4691 +#define        KORINA_RETRY_LIMIT      0x80
4692 +#define KORINA_TRDY_LIMIT      0x80
4693 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4694 +                       KORINA_TRDY_LIMIT)
4695 +#define PCI_PBAxC_R            0x0
4696 +#define PCI_PBAxC_RL           0x1
4697 +#define PCI_PBAxC_RM           0x2
4698 +#define SIZE_SHFT              2
4699 +
4700 +#ifdef __MIPSEB__
4701 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m  | PCIPBAC_sb_m | \
4702 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4703 +                         PCIPBAC_pp_m | \
4704 +                         (SIZE_32MB<<SIZE_SHFT) | \
4705 +                          PCIPBAC_p_m)
4706 +#else
4707 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m  | \
4708 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4709 +                         PCIPBAC_pp_m | \
4710 +                         (SIZE_32MB<<SIZE_SHFT) | \
4711 +                          PCIPBAC_p_m)
4712 +#endif
4713 +
4714 +#if 0
4715 +
4716 +#define KORINA_PBA0C   ( PCIPBAC_sb_m | PCIPBAC_pp_m | \
4717 +                         ((PCI_PBAxC_R &0x3) << PCIPBAC_mr_b) | \
4718 +                         (SIZE_128MB<<SIZE_SHFT))
4719 +#endif
4720 +#define KORINA_CNFG17  KORINA_PBA0C
4721 +#define KORINA_PBA0M   0x0
4722 +#define KORINA_CNFG18  KORINA_PBA0M
4723 +
4724 +#ifdef __MIPSEB__
4725 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT)  | PCIPBAC_sb_m | \
4726 +                         PCIPBAC_msi_m)
4727 +#else
4728 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT)  | \
4729 +                         PCIPBAC_msi_m)
4730 +
4731 +#endif
4732 +
4733 +#define KORINA_CNFG19  KORINA_PBA1C
4734 +#define KORINA_PBA1M   0x0
4735 +#define KORINA_CNFG20  KORINA_PBA1M
4736 +
4737 +#ifdef __MIPSEB__
4738 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT)  | PCIPBAC_sb_m | \
4739 +                         PCIPBAC_msi_m)
4740 +#else
4741 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | \
4742 +                         PCIPBAC_msi_m)
4743 +
4744 +#endif
4745 +#define KORINA_CNFG21  KORINA_PBA2C
4746 +#define KORINA_PBA2M   0x18000000
4747 +#define KORINA_CNFG22  KORINA_PBA2M
4748 +#define KORINA_PBA3C   0
4749 +#define KORINA_CNFG23  KORINA_PBA3C
4750 +#define KORINA_PBA3M   0
4751 +#define KORINA_CNFG24  KORINA_PBA3M
4752 +
4753 +
4754 +
4755 +#define        PCITC_DTIMER_VAL        8
4756 +#define PCITC_RTIMER_VAL       0x10
4757 +
4758 +
4759 +#endif /* _PCIKORINA_H */
4760 +
4761 +
4762 +
4763 +
4764 +
4765 +
4766 +
4767 +
4768 +
4769 +
4770 +
4771 +
4772 +
4773 +
4774 +
4775 +
4776 +
4777 diff -urN linux.old/include/asm-mips/rc32434/pci_regs.h linux.dev/include/asm-mips/rc32434/pci_regs.h
4778 --- linux.old/include/asm-mips/rc32434/pci_regs.h       1970-01-01 01:00:00.000000000 +0100
4779 +++ linux.dev/include/asm-mips/rc32434/pci_regs.h       2006-10-11 21:56:38.000000000 +0200
4780 @@ -0,0 +1,8 @@
4781 +/* Override the default address space for this arch
4782 +*/
4783 +
4784 +#include <linux/pci_regs.h>
4785 +
4786 +//#undef PCI_BASE_ADDRESS_SPACE
4787 +//#define PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_MEMORY
4788 +
4789 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
4790 --- linux.old/include/asm-mips/rc32434/rb.h     1970-01-01 01:00:00.000000000 +0100
4791 +++ linux.dev/include/asm-mips/rc32434/rb.h     2006-10-11 21:56:38.000000000 +0200
4792 @@ -0,0 +1,69 @@
4793 +#ifndef __MIPS_RB_H__
4794 +#define __MIPS_RB_H__
4795 +#include <linux/genhd.h>
4796 +
4797 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
4798 +#define DEV0BASE 0x010000
4799 +#define DEV0MASK 0x010004
4800 +#define DEV0C 0x010008
4801 +#define DEV0TC 0x01000C
4802 +#define DEV1BASE 0x010010
4803 +#define DEV1MASK 0x010014
4804 +#define DEV1C 0x010018
4805 +#define DEV1TC 0x01001C
4806 +#define DEV2BASE 0x010020
4807 +#define DEV2MASK 0x010024
4808 +#define DEV2C 0x010028
4809 +#define DEV2TC 0x01002C
4810 +#define DEV3BASE 0x010030
4811 +#define DEV3MASK 0x010034
4812 +#define DEV3C 0x010038
4813 +#define DEV3TC 0x01003C
4814 +#define BTCS 0x010040
4815 +#define BTCOMPARE 0x010044
4816 +#define GPIOFUNC 0x050000
4817 +#define GPIOCFG 0x050004
4818 +#define GPIOD 0x050008
4819 +#define GPIOILEVEL 0x05000C
4820 +#define GPIOISTAT 0x050010
4821 +#define GPIONMIEN 0x050014
4822 +#define IMASK6 0x038038
4823 +
4824 +#define LO_WPX (1 << 0)
4825 +#define LO_ALE (1 << 1)
4826 +#define LO_CLE (1 << 2)
4827 +#define LO_CEX (1 << 3)
4828 +#define LO_FOFF (1 << 5)
4829 +#define LO_SPICS (1 << 6)
4830 +#define LO_ULED (1 << 7)
4831 +
4832 +typedef enum {
4833 +       FUNC = 0x00,
4834 +       CFG = 0x04,
4835 +       DATA = 0x08,
4836 +       ILEVEL = 0x0c,
4837 +       ISTAT = 0x10,
4838 +       NMIEN = 0x14
4839 +} gpio_func;
4840 +
4841 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
4842 +extern unsigned get434Reg(unsigned regOffs);
4843 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
4844 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
4845 +extern u32 gpio_get(gpio_func func);
4846 +
4847 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
4848 +
4849 +struct korina_device {
4850 +       char *name;
4851 +       unsigned char mac[6];
4852 +       struct net_device *dev;
4853 +};
4854 +
4855 +struct cf_device {
4856 +       int gpio_pin;
4857 +       void *dev;
4858 +       struct gendisk *gd;
4859 +};
4860 +
4861 +#endif
4862 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
4863 --- linux.old/include/asm-mips/rc32434/rc32434.h        1970-01-01 01:00:00.000000000 +0100
4864 +++ linux.dev/include/asm-mips/rc32434/rc32434.h        2006-10-11 21:56:38.000000000 +0200
4865 @@ -0,0 +1,126 @@
4866 +/*
4867 + ***************************************************************************
4868 + * Definitions for IDT RC323434 CPU.
4869 + *
4870 + ****************************************************************************
4871 + * Kiran Rao
4872 + *
4873 + * Original form
4874 + ****************************************************************************
4875 + * P. Sadik   Oct 08, 2003
4876 + *
4877 + * Started revision history
4878 + * Made IDT_BUS_FREQ a kernel configuration parameter
4879 + ****************************************************************************
4880 + * P. Sadik   Oct 10, 2003
4881 + *
4882 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
4883 + * idt_cpu_freq is used everywhere
4884 + ****************************************************************************
4885 + * P. Sadik   Oct 20, 2003
4886 + *
4887 + * Removed RC32434_BASE_BAUD
4888 + ****************************************************************************
4889 +*/
4890 +#ifndef _RC32434_H_
4891 +#define _RC32434_H_
4892 +
4893 +#include <linux/config.h>
4894 +#include <linux/delay.h>
4895 +#include <asm/io.h>
4896 +#include <asm/rc32434/timer.h>
4897 +
4898 +#define RC32434_REG_BASE   0x18000000
4899 +
4900 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
4901 +#define timer     ((volatile TIM_t)  TIM0_VirtualAddress)
4902 +#define gpio     ((volatile GPIO_t) GPIO0_VirtualAddress)
4903 +
4904 +#define IDT_CLOCK_MULT 2
4905 +#define MIPS_CPU_TIMER_IRQ 7
4906 +/* Interrupt Controller */
4907 +#define IC_GROUP0_PEND     (RC32434_REG_BASE + 0x38000)
4908 +#define IC_GROUP0_MASK     (RC32434_REG_BASE + 0x38008)
4909 +#define IC_GROUP_OFFSET    0x0C
4910 +
4911 +#define NUM_INTR_GROUPS    5
4912 +/* 16550 UARTs */
4913 +
4914 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
4915 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
4916 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
4917 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
4918 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
4919 +
4920 +
4921 +#ifdef __MIPSEB__
4922 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
4923 +#else
4924 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
4925 +#endif
4926 +
4927 +#define RC32434_UART0_IRQ  GROUP3_IRQ_BASE + 0
4928 +// #define EB434_UART1_IRQ    GROUP4_IRQ_BASE + 11
4929 +
4930 +#define local_readl(addr) __raw_readl(addr)
4931 +#define local_writel(l,addr) __raw_writel(l,addr)
4932 +
4933 +/* cpu pipeline flush */
4934 +static inline void rc32434_sync(void)
4935 +{
4936 +        __asm__ volatile ("sync");
4937 +}
4938 +
4939 +static inline void rc32434_sync_udelay(int us)
4940 +{
4941 +        __asm__ volatile ("sync");
4942 +        udelay(us);
4943 +}
4944 +
4945 +static inline void rc32434_sync_delay(int ms)
4946 +{
4947 +        __asm__ volatile ("sync");
4948 +        mdelay(ms);
4949 +}
4950 +
4951 +/*
4952 + * C access to CLZ and CLO instructions
4953 + * (count leading zeroes/ones).
4954 + */
4955 +static inline int rc32434_clz(unsigned long val)
4956 +{
4957 +       int ret;
4958 +        __asm__ volatile (
4959 +               ".set\tnoreorder\n\t"
4960 +               ".set\tnoat\n\t"
4961 +               ".set\tmips32\n\t"
4962 +               "clz\t%0,%1\n\t"
4963 +                ".set\tmips0\n\t"
4964 +                ".set\tat\n\t"
4965 +                ".set\treorder"
4966 +                : "=r" (ret)
4967 +               : "r" (val));
4968 +
4969 +       return ret;
4970 +}
4971 +static inline int rc32434_clo(unsigned long val)
4972 +{
4973 +       int ret;
4974 +        __asm__ volatile (
4975 +               ".set\tnoreorder\n\t"
4976 +               ".set\tnoat\n\t"
4977 +               ".set\tmips32\n\t"
4978 +               "clo\t%0,%1\n\t"
4979 +                ".set\tmips0\n\t"
4980 +                ".set\tat\n\t"
4981 +                ".set\treorder"
4982 +                : "=r" (ret)
4983 +               : "r" (val));
4984 +
4985 +       return ret;
4986 +}
4987 +
4988 +extern void cons_putc(char c);
4989 +extern void cons_puts(char *s);
4990 +
4991 +#endif /* _RC32434_H_ */
4992 diff -urN linux.old/include/asm-mips/rc32434/rst.h linux.dev/include/asm-mips/rc32434/rst.h
4993 --- linux.old/include/asm-mips/rc32434/rst.h    1970-01-01 01:00:00.000000000 +0100
4994 +++ linux.dev/include/asm-mips/rc32434/rst.h    2006-10-11 21:56:38.000000000 +0200
4995 @@ -0,0 +1,105 @@
4996 +#ifndef __IDT_RST_H__
4997 +#define __IDT_RST_H__
4998 +
4999 +/*******************************************************************************
5000 + *
5001 + * Copyright 2002 Integrated Device Technology, Inc.
5002 + *             All rights reserved.
5003 + *
5004 + * Reset register definitions.
5005 + *
5006 + * File   : $Id: rst.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5007 + *
5008 + * Author : Allen.Stichter@idt.com
5009 + * Date   : 20020118
5010 + * Update :
5011 + *         $Log: rst.h,v $
5012 + *         Revision 1.2  2002/06/06 18:34:05  astichte
5013 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
5014 + *
5015 + *         Revision 1.1  2002/05/29 17:33:24  sysarch
5016 + *         jba File moved from vcode/include/idt/acacia
5017 + *
5018 + *
5019 + ******************************************************************************/
5020 +
5021 +#include  <asm/rc32434/types.h>
5022 +
5023 +enum
5024 +{
5025 +       RST0_PhysicalAddress    = 0x18000000,
5026 +       RST_PhysicalAddress     = RST0_PhysicalAddress,         // Default
5027 +
5028 +       RST0_VirtualAddress     = 0xb8000000,
5029 +       RST_VirtualAddress      = RST0_VirtualAddress,          // Default
5030 +} ;
5031 +
5032 +typedef struct RST_s
5033 +{
5034 +       U32     filler [0x0006] ;
5035 +       U32     sysid ;
5036 +       U32     filler2 [0x2000-8] ;            // Pad out to offset 0x8000
5037 +       U32     reset ;
5038 +       U32     bcv ;
5039 +       U32     cea ;
5040 +} volatile * RST_t ;
5041 +
5042 +enum
5043 +{
5044 +       SYSID_rev_b             = 0,
5045 +       SYSID_rev_m             = 0x000000ff,
5046 +       SYSID_imp_b             = 8,
5047 +       SYSID_imp_m             = 0x000fff00,
5048 +       SYSID_vendor_b          = 20,
5049 +       SYSID_vendor_m          = 0xfff00000,
5050 +
5051 +       BCV_pll_b               = 0,
5052 +       BCV_pll_m               = 0x0000000f,
5053 +               BCV_pll_PLLBypass_v     = 0x0,  // PCLK=1*CLK.
5054 +               BCV_pll_Mul3_v          = 0x1,  // PCLK=3*CLK.
5055 +               BCV_pll_Mul4_v          = 0x2,  // PCLK=4*CLK.
5056 +               BCV_pll_SlowMul5_v      = 0x3,  // PCLK=4*CLK.
5057 +               BCV_pll_Mul5_v          = 0x4,  // PCLK=6*CLK.
5058 +               BCV_pll_SlowMul6_v      = 0x5,  // PCLK=8*CLK.
5059 +               BCV_pll_Mul6_v          = 0x6,  // PCLK=8*CLK.
5060 +               BCV_pll_Mul8_v          = 0x7,  // PCLK=8*CLK.
5061 +               BCV_pll_Mul10_v         = 0x8,  // PCLK=8*CLK.
5062 +               BCV_pll_Res5_v          = 0x9,
5063 +               BCV_pll_Res6_v          = 0xa,
5064 +               BCV_pll_Res7_v          = 0xb,
5065 +               BCV_pll_Res8_v          = 0xc,
5066 +               BCV_pll_Res13_v         = 0xd,
5067 +               BCV_pll_Res14_v         = 0xe,
5068 +               BCV_pll_Res15_v         = 0xf,
5069 +       BCV_clkDiv_b            = 4,
5070 +       BCV_clkDiv_m            = 0x00000030,
5071 +               BCV_clkDiv_Div1_v       = 0x0,
5072 +               BCV_clkDiv_Div2_v       = 0x1,
5073 +               BCV_clkDiv_Div4_v       = 0x2,
5074 +               BCV_clkDiv_Res3_v       = 0x3,
5075 +       BCV_bigEndian_b         = 6,
5076 +       BCV_bigEndian_m         = 0x00000040,
5077 +       BCV_resetFast_b         = 7,
5078 +       BCV_resetFast_m         = 0x00000080,
5079 +       BCV_pciMode_b           = 8,
5080 +       BCV_pciMode_m           = 0x00000100,
5081 +               BCV_pciMode_disabled_v  = 0,    // PCI is disabled.
5082 +               BCV_pciMode_tnr_v       = 1,    // satellite Target Not Ready.
5083 +               BCV_pciMode_suspended_v = 2,    // satellite with suspended CPU.
5084 +               BCV_pciMode_external_v  = 3,    // host, external arbiter.
5085 +               BCV_pciMode_fixed_v     = 4,    // host, fixed priority arbiter.
5086 +               BCV_pciMode_roundRobin_v= 5,    // host, round robin arbiter.
5087 +               BCV_pciMode_res6_v      = 6,
5088 +               BCV_pciMode_res7_v      = 7,
5089 +       BCV_watchDisable_b      = 11,
5090 +       BCV_watchDisable_m      = 0x00000800,
5091 +       BCV_pllTest_b           = 12,
5092 +       BCV_pllTest_m           = 0x00001000,
5093 +       BCV_nvramInit_b         = 13,
5094 +       BCV_nvramInit_m         = 0x00002000,
5095 +       BCV_clksyncTstMd_b      = 14,
5096 +       BCV_clksyncTstMd_m      = 0x00004000,
5097 +       BCV_delayBypass_b       = 15,
5098 +       BCV_delayByPass_m       = 0x00008000,
5099 +} ;
5100 +#endif // __IDT_RST_H__
5101 diff -urN linux.old/include/asm-mips/rc32434/spi.h linux.dev/include/asm-mips/rc32434/spi.h
5102 --- linux.old/include/asm-mips/rc32434/spi.h    1970-01-01 01:00:00.000000000 +0100
5103 +++ linux.dev/include/asm-mips/rc32434/spi.h    2006-10-11 21:56:38.000000000 +0200
5104 @@ -0,0 +1,100 @@
5105 +#ifndef __IDT_SPI_H__
5106 +#define __IDT_SPI_H__
5107 +
5108 +/*******************************************************************************
5109 + *
5110 + * Copyright 2002 Integrated Device Technology, Inc.
5111 + *             All rights reserved.
5112 + *
5113 + * Serial Peripheral Interface register definitions.
5114 + *
5115 + * File   : $Id: spi.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5116 + *
5117 + * Author : ryan.holmQVist@idt.com
5118 + * Date   : 20011005
5119 + * Update :
5120 + *         $Log: spi.h,v $
5121 + *         Revision 1.2  2002/06/06 18:34:05  astichte
5122 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
5123 + *
5124 + *         Revision 1.1  2002/05/29 17:33:25  sysarch
5125 + *         jba File moved from vcode/include/idt/acacia
5126 + *
5127 + *
5128 + ******************************************************************************/
5129 +
5130 +#include  <asm/rc32434/types.h>
5131 +
5132 +enum
5133 +{
5134 +       SPI0_PhysicalAddress    = 0x18070000,
5135 +       SPI_PhysicalAddress     = SPI0_PhysicalAddress,
5136 +
5137 +       SPI0_VirtualAddress     = 0xb8070000,
5138 +       SPI_VirtualAddress      = SPI0_VirtualAddress,
5139 +} ;
5140 +
5141 +typedef struct
5142 +{
5143 +       U32 spcp ;      // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
5144 +       U32 spc ;       // spi control reg use SPC_
5145 +       U32 sps ;       // spi status reg use SPS_
5146 +       U32 spd ;       // spi data reg use SPD_
5147 +       U32 siofunc ;   // serial IO function use SIOFUNC_
5148 +       U32 siocfg ;    // serial IO config use SIOCFG_
5149 +       U32 siod;       // serial IO data use SIOD_
5150 +} volatile *SPI_t ;
5151 +
5152 +enum
5153 +{
5154 +       SPCP_div_b       = 0,
5155 +       SPCP_div_m       = 0x000000ff,
5156 +       SPC_spr_b       = 0,
5157 +       SPC_spr_m       = 0x00000003,
5158 +            SPC_spr_div2_v  = 0,
5159 +            SPC_spr_div4_v  = 1,
5160 +            SPC_spr_div16_v = 2,
5161 +            SPC_spr_div32_v = 3,
5162 +       SPC_cpha_b      = 2,
5163 +       SPC_cpha_m      = 0x00000004,
5164 +       SPC_cpol_b      = 3,
5165 +       SPC_cpol_m      = 0x00000008,
5166 +       SPC_mstr_b      = 4,
5167 +       SPC_mstr_m      = 0x00000010,
5168 +       SPC_spe_b       = 6,
5169 +       SPC_spe_m       = 0x00000040,
5170 +       SPC_spie_b      = 7,
5171 +       SPC_spie_m      = 0x00000080,
5172 +
5173 +       SPS_modf_b      = 4,
5174 +       SPS_modf_m      = 0x00000010,
5175 +       SPS_wcol_b      = 6,
5176 +       SPS_wcol_m      = 0x00000040,
5177 +       SPS_spif_b      = 7,
5178 +       SPS_spif_m      = 0x00000070,
5179 +
5180 +       SPD_data_b      = 0,
5181 +       SPD_data_m      = 0x000000ff,
5182 +
5183 +       SIOFUNC_sdo_b       = 0,
5184 +       SIOFUNC_sdo_m       = 0x00000001,
5185 +       SIOFUNC_sdi_b       = 1,
5186 +       SIOFUNC_sdi_m       = 0x00000002,
5187 +       SIOFUNC_sck_b       = 2,
5188 +       SIOFUNC_sck_m       = 0x00000004,
5189 +
5190 +       SIOCFG_sdo_b       = 0,
5191 +       SIOCFG_sdo_m       = 0x00000001,
5192 +       SIOCFG_sdi_b       = 1,
5193 +       SIOCFG_sdi_m       = 0x00000002,
5194 +       SIOCFG_sck_b       = 2,
5195 +       SIOCFG_sck_m       = 0x00000004,
5196 +
5197 +       SIOD_sdo_b       = 0,
5198 +       SIOD_sdo_m       = 0x00000001,
5199 +       SIOD_sdi_b       = 1,
5200 +       SIOD_sdi_m       = 0x00000002,
5201 +       SIOD_sck_b       = 2,
5202 +       SIOD_sck_m       = 0x00000004,
5203 +} ;
5204 +#endif // __IDT_SPI_H__
5205 diff -urN linux.old/include/asm-mips/rc32434/timer.h linux.dev/include/asm-mips/rc32434/timer.h
5206 --- linux.old/include/asm-mips/rc32434/timer.h  1970-01-01 01:00:00.000000000 +0100
5207 +++ linux.dev/include/asm-mips/rc32434/timer.h  2006-10-11 21:56:38.000000000 +0200
5208 @@ -0,0 +1,91 @@
5209 +/**************************************************************************
5210 + *
5211 + *  BRIEF MODULE DESCRIPTION
5212 + *   Definitions for timer registers
5213 + *
5214 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5215 + *
5216 + *  This program is free software; you can redistribute  it and/or modify it
5217 + *  under  the terms of  the GNU General  Public License as published by the
5218 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5219 + *  option) any later version.
5220 + *
5221 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5222 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5223 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5224 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5225 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5226 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5227 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5228 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5229 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5230 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5231 + *
5232 + *  You should have received a copy of the  GNU General Public License along
5233 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5234 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5235 + *
5236 + *
5237 + **************************************************************************
5238 + * May 2004 rkt,neb.
5239 + *
5240 + * Initial Release
5241 + *
5242 + *
5243 + *
5244 + **************************************************************************
5245 + */
5246 +
5247 +#ifndef __IDT_TIM_H__
5248 +#define __IDT_TIM_H__
5249 +
5250 +enum
5251 +{
5252 +       TIM0_PhysicalAddress    = 0x18028000,
5253 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
5254 +
5255 +       TIM0_VirtualAddress     = 0xb8028000,
5256 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
5257 +} ;
5258 +
5259 +enum
5260 +{
5261 +       TIM_Count = 3,
5262 +} ;
5263 +
5264 +struct TIM_CNTR_s
5265 +{
5266 +  u32 count ;
5267 +  u32 compare ;
5268 +  u32 ctc ;    //use CTC_
5269 +} ;
5270 +
5271 +typedef struct TIM_s
5272 +{
5273 +  struct TIM_CNTR_s    tim [TIM_Count] ;
5274 +  u32                  rcount ;        //use RCOUNT_
5275 +  u32                  rcompare ;      //use RCOMPARE_
5276 +  u32                  rtc ;           //use RTC_
5277 +} volatile * TIM_t ;
5278 +
5279 +enum
5280 +{
5281 +  CTC_en_b     = 0,
5282 +  CTC_en_m     = 0x00000001,
5283 +  CTC_to_b     = 1,
5284 +  CTC_to_m     = 0x00000002,
5285 +
5286 +  RCOUNT_count_b               = 0,
5287 +  RCOUNT_count_m               = 0x0000ffff,
5288 +  RCOMPARE_compare_b   = 0,
5289 +  RCOMPARE_compare_m   = 0x0000ffff,
5290 +  RTC_ce_b             = 0,
5291 +  RTC_ce_m             = 0x00000001,
5292 +  RTC_to_b             = 1,
5293 +  RTC_to_m             = 0x00000002,
5294 +  RTC_rqe_b            = 2,
5295 +  RTC_rqe_m            = 0x00000004,
5296 +
5297 +} ;
5298 +#endif // __IDT_TIM_H__
5299 +
5300 diff -urN linux.old/include/asm-mips/rc32434/tim.h linux.dev/include/asm-mips/rc32434/tim.h
5301 --- linux.old/include/asm-mips/rc32434/tim.h    1970-01-01 01:00:00.000000000 +0100
5302 +++ linux.dev/include/asm-mips/rc32434/tim.h    2006-10-11 21:56:38.000000000 +0200
5303 @@ -0,0 +1,78 @@
5304 +#ifndef __IDT_TIM_H__
5305 +#define __IDT_TIM_H__
5306 +
5307 +/*******************************************************************************
5308 + *
5309 + * Copyright 2002 Integrated Device Technology, Inc.
5310 + *             All rights reserved.
5311 + *
5312 + * Timer register definition.
5313 + *
5314 + * File   : $Id: tim.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5315 + *
5316 + * Author : ryan.holmQVist@idt.com
5317 + * Date   : 20011005
5318 + * Update :
5319 + *         $Log: tim.h,v $
5320 + *         Revision 1.2  2002/06/06 18:34:05  astichte
5321 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
5322 + *
5323 + *         Revision 1.1  2002/05/29 17:33:25  sysarch
5324 + *         jba File moved from vcode/include/idt/acacia
5325 + *
5326 + *
5327 + ******************************************************************************/
5328 +
5329 +
5330 +#include  <asm/rc32434/types.h>
5331 +
5332 +enum
5333 +{
5334 +       TIM0_PhysicalAddress    = 0x18028000,
5335 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
5336 +
5337 +       TIM0_VirtualAddress     = 0xb8028000,
5338 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
5339 +} ;
5340 +
5341 +enum
5342 +{
5343 +       TIM_Count = 3,
5344 +} ;
5345 +
5346 +struct TIM_CNTR_s
5347 +{
5348 +       U32 count ;
5349 +       U32 compare ;
5350 +       U32 ctc ;       //use CTC_
5351 +} ;
5352 +
5353 +typedef struct TIM_s
5354 +{
5355 +       struct TIM_CNTR_s       tim [TIM_Count] ;
5356 +       U32                     rcount ;        //use RCOUNT_
5357 +       U32                     rcompare ;      //use RCOMPARE_
5358 +       U32                     rtc ;           //use RTC_
5359 +} volatile * TIM_t ;
5360 +
5361 +enum
5362 +{
5363 +       CTC_en_b        = 0,
5364 +       CTC_en_m        = 0x00000001,
5365 +       CTC_to_b        = 1,
5366 +       CTC_to_m        = 0x00000002,
5367 +
5368 +       RCOUNT_count_b          = 0,
5369 +       RCOUNT_count_m          = 0x0000ffff,
5370 +       RCOMPARE_compare_b      = 0,
5371 +       RCOMPARE_compare_m      = 0x0000ffff,
5372 +       RTC_ce_b                = 0,
5373 +       RTC_ce_m                = 0x00000001,
5374 +       RTC_to_b                = 1,
5375 +       RTC_to_m                = 0x00000002,
5376 +       RTC_rqe_b               = 2,
5377 +       RTC_rqe_m               = 0x00000004,
5378 +
5379 +} ;
5380 +#endif // __IDT_TIM_H__
5381 +
5382 diff -urN linux.old/include/asm-mips/rc32434/types.h linux.dev/include/asm-mips/rc32434/types.h
5383 --- linux.old/include/asm-mips/rc32434/types.h  1970-01-01 01:00:00.000000000 +0100
5384 +++ linux.dev/include/asm-mips/rc32434/types.h  2006-10-11 21:56:38.000000000 +0200
5385 @@ -0,0 +1,39 @@
5386 +#ifndef __IDT_TYPES_H__
5387 +#define __IDT_TYPES_H__
5388 +
5389 +/*******************************************************************************
5390 + *
5391 + * Copyright 2002 Integrated Device Technology, Inc.
5392 + *             All rights reserved.
5393 + *
5394 + * Common typedefs used in IDT-generated code.
5395 + *
5396 + * File   : $Id: types.h,v 1.1 2002/06/06 16:16:56 astichte Exp $
5397 + *
5398 + * Author : Allen.Stichter@idt.com
5399 + * Date   : 20020606
5400 + * Update :
5401 + *         $Log: types.h,v $
5402 + *         Revision 1.1  2002/06/06 16:16:56  astichte
5403 + *         Added
5404 + *
5405 + *
5406 + ******************************************************************************/
5407 +
5408 +typedef unsigned char          U8 ;
5409 +typedef signed char            S8 ;
5410 +
5411 +typedef unsigned short         U16 ;
5412 +typedef signed short           S16 ;
5413 +
5414 +typedef unsigned int           U32 ;
5415 +typedef signed int             S32 ;
5416 +
5417 +typedef unsigned long long     U64 ;
5418 +typedef signed long long       S64 ;
5419 +
5420 +#ifndef __cplusplus
5421 +       typedef U32             bool ;  // (false == 0), (true is != false)
5422 +#endif // __cplusplus
5423 +
5424 +#endif // __IDT_TYPES_H__
5425 diff -urN linux.old/include/asm-mips/rc32434/uart.h linux.dev/include/asm-mips/rc32434/uart.h
5426 --- linux.old/include/asm-mips/rc32434/uart.h   1970-01-01 01:00:00.000000000 +0100
5427 +++ linux.dev/include/asm-mips/rc32434/uart.h   2006-10-11 21:56:38.000000000 +0200
5428 @@ -0,0 +1,178 @@
5429 +#ifndef __IDT_UART_H__
5430 +#define __IDT_UART_H__
5431 +
5432 +/*******************************************************************************
5433 + *
5434 + * Copyright 2002 Integrated Device Technology, Inc.
5435 + *             All rights reserved.
5436 + *
5437 + * UART register definitions.
5438 + *
5439 + * File   : $Id: uart.h,v 1.3 2002/06/06 18:34:05 astichte Exp $
5440 + *
5441 + * Author : Allen.Stichter@idt.com
5442 + * Date   : 20020118
5443 + * Update :
5444 + *         $Log: uart.h,v $
5445 + *         Revision 1.3  2002/06/06 18:34:05  astichte
5446 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
5447 + *
5448 + *         Revision 1.2  2002/06/04 17:37:52  astichte
5449 + *         Updated register definitions.
5450 + *
5451 + *         Revision 1.1  2002/05/29 17:33:25  sysarch
5452 + *         jba File moved from vcode/include/idt/acacia
5453 + *
5454 + *
5455 + ******************************************************************************/
5456 +
5457 +#include  <asm/rc32434/types.h>
5458 +
5459 +enum
5460 +{
5461 +       UART_PhysicalAddress    = 0x18058000,
5462 +       UART_PhysicalAddress    = UART_PhysicalAddress, // Default
5463 +
5464 +       UART_VirtualAddress     = 0xb8058000,
5465 +       UART_VirtualAddress     = UART_VirtualAddress,          // Default
5466 +} ;
5467 +
5468 +/*
5469 + * Register definitions are in bytes so we can handle endian problems.
5470 + */
5471 +
5472 +typedef struct UART_s
5473 +{
5474 +       union
5475 +       {
5476 +               U32 const       uartrb ;        // 0x00 - DLAB=0, read.
5477 +               U32             uartth ;        // 0x00 - DLAB=0, write.
5478 +               U32             uartdll ;       // 0x00 - DLAB=1, read/write.
5479 +       } ;
5480 +
5481 +       union
5482 +       {
5483 +               U32             uartie ;        // 0x04 - DLAB=0, read/write.
5484 +               U32             uartdlh ;       // 0x04 - DLAB=1, read/write.
5485 +       } ;
5486 +       union
5487 +       {
5488 +               U32 const       uartii ;        // 0x08 - DLAB=0, read.
5489 +               U32             uartfc ;        // 0x08 - DLAB=0, write.
5490 +       } ;
5491 +
5492 +       U32             uartlc ;                // 0x0c
5493 +       U32             uartmc ;                // 0x10
5494 +       U32             uartls ;                // 0x14
5495 +       U32             uartms ;                // 0x18
5496 +       U32             uarts ;                 // 0x1c
5497 +} volatile *UART_t ;
5498 +
5499 +// Reset registers.
5500 +typedef U32    volatile *UARTRR_t ;
5501 +
5502 +enum
5503 +{
5504 +       UARTIE_rda_b    = 0,
5505 +       UARTIE_rda_m    = 0x00000001,
5506 +       UARTIE_the_b    = 1,
5507 +       UARTIE_the_m    = 0x00000002,
5508 +       UARTIE_rls_b    = 2,
5509 +       UARTIE_rls_m    = 0x00000004,
5510 +       UARTIE_ems_b    = 3,
5511 +       UARTIE_ems_m    = 0x00000008,
5512 +
5513 +       UARTII_pi_b     = 0,
5514 +       UARTII_pi_m     = 0x00000001,
5515 +       UARTII_iid_b    = 1,
5516 +       UARTII_iid_m    = 0x0000000e,
5517 +               UARTII_iid_ms_v         = 0,    // Modem stat-CTS,DSR,RI or DCD.
5518 +               UARTII_iid_thre_v       = 1,    // Trans. Holding Reg. empty.
5519 +               UARTII_iid_rda_v        = 2,    // Receive data available
5520 +               UARTII_iid_rls_v        = 3,    // Overrun, parity, etc, error.
5521 +               UARTII_iid_res4_v       = 4,    // reserved.
5522 +               UARTII_iid_res5_v       = 5,    // reserved.
5523 +               UARTII_iid_cto_v        = 6,    // Character timeout.
5524 +               UARTII_iid_res7_v       = 7,    // reserved.
5525 +
5526 +       UARTFC_en_b     = 0,
5527 +       UARTFC_en_m     = 0x00000001,
5528 +       UARTFC_rr_b     = 1,
5529 +       UARTFC_rr_m     = 0x00000002,
5530 +       UARTFC_tr_b     = 2,
5531 +       UARTFC_tr_m     = 0x00000004,
5532 +       UARTFC_dms_b    = 3,
5533 +       UARTFC_dms_m    = 0x00000008,
5534 +       UARTFC_rt_b     = 6,
5535 +       UARTFC_rt_m     = 0x000000c0,
5536 +               UARTFC_rt_1Byte_v       = 0,
5537 +               UARTFC_rt_4Byte_v       = 1,
5538 +               UARTFC_rt_8Byte_v       = 2,
5539 +               UARTFC_rt_14Byte_v      = 3,
5540 +
5541 +       UARTLC_wls_b    = 0,
5542 +       UARTLC_wls_m    = 0x00000003,
5543 +               UARTLC_wls_5Bits_v      = 0,
5544 +               UARTLC_wls_6Bits_v      = 1,
5545 +               UARTLC_wls_7Bits_v      = 2,
5546 +               UARTLC_wls_8Bits_v      = 3,
5547 +       UARTLC_stb_b    = 2,
5548 +       UARTLC_stb_m    = 0x00000004,
5549 +       UARTLC_pen_b    = 3,
5550 +       UARTLC_pen_m    = 0x00000008,
5551 +       UARTLC_eps_b    = 4,
5552 +       UARTLC_eps_m    = 0x00000010,
5553 +       UARTLC_sp_b     = 5,
5554 +       UARTLC_sp_m     = 0x00000020,
5555 +       UARTLC_sb_b     = 6,
5556 +       UARTLC_sb_m     = 0x00000040,
5557 +       UARTLC_dlab_b   = 7,
5558 +       UARTLC_dlab_m   = 0x00000080,
5559 +
5560 +       UARTMC_dtr_b    = 0,
5561 +       UARTMC_dtr_m    = 0x00000001,
5562 +       UARTMC_rts_b    = 1,
5563 +       UARTMC_rts_m    = 0x00000002,
5564 +       UARTMC_o1_b     = 2,
5565 +       UARTMC_o1_m     = 0x00000004,
5566 +       UARTMC_o2_b     = 3,
5567 +       UARTMC_o2_m     = 0x00000008,
5568 +       UARTMC_lp_b     = 4,
5569 +       UARTMC_lp_m     = 0x00000010,
5570 +
5571 +       UARTLS_dr_b     = 0,
5572 +       UARTLS_dr_m     = 0x00000001,
5573 +       UARTLS_oe_b     = 1,
5574 +       UARTLS_oe_m     = 0x00000002,
5575 +       UARTLS_pe_b     = 2,
5576 +       UARTLS_pe_m     = 0x00000004,
5577 +       UARTLS_fe_b     = 3,
5578 +       UARTLS_fe_m     = 0x00000008,
5579 +       UARTLS_bi_b     = 4,
5580 +       UARTLS_bi_m     = 0x00000010,
5581 +       UARTLS_thr_b    = 5,
5582 +       UARTLS_thr_m    = 0x00000020,
5583 +       UARTLS_te_b     = 6,
5584 +       UARTLS_te_m     = 0x00000040,
5585 +       UARTLS_rfe_b    = 7,
5586 +       UARTLS_rfe_m    = 0x00000080,
5587 +
5588 +       UARTMS_dcts_b   = 0,
5589 +       UARTMS_dcts_m   = 0x00000001,
5590 +       UARTMS_ddsr_b   = 1,
5591 +       UARTMS_ddsr_m   = 0x00000002,
5592 +       UARTMS_teri_b   = 2,
5593 +       UARTMS_teri_m   = 0x00000004,
5594 +       UARTMS_ddcd_b   = 3,
5595 +       UARTMS_ddcd_m   = 0x00000008,
5596 +       UARTMS_cts_b    = 4,
5597 +       UARTMS_cts_m    = 0x00000010,
5598 +       UARTMS_dsr_b    = 5,
5599 +       UARTMS_dsr_m    = 0x00000020,
5600 +       UARTMS_ri_b     = 6,
5601 +       UARTMS_ri_m     = 0x00000040,
5602 +       UARTMS_dcd_b    = 7,
5603 +       UARTMS_dcd_m    = 0x00000080,
5604 +} ;
5605 +
5606 +#endif // __IDT_UART_H__