target/linux/ramips/patches-4.3/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch

   1 From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 11:15:12 +0100
   4 Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver
   5
   6 Add the driver needed to make SPI work on Ralink SoC.
   7
   8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   9 Acked-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/spi/Kconfig      |    6 +
  12  drivers/spi/Makefile     |    1 +
  13  drivers/spi/spi-rt2880.c |  530 ++++++++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 537 insertions(+)
  15  create mode 100644 drivers/spi/spi-rt2880.c
  16
  17 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  18 index 4887f31..7c592ce 100644
  19 --- a/drivers/spi/Kconfig
  20 +++ b/drivers/spi/Kconfig
  21 @@ -457,6 +457,12 @@ config SPI_QUP
  22           This driver can also be built as a module.  If so, the module
  23           will be called spi_qup.
  24
  25 +config SPI_RT2880
  26 +       tristate "Ralink RT288x SPI Controller"
  27 +       depends on RALINK
  28 +       help
  29 +         This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  30 +
  31  config SPI_S3C24XX
  32         tristate "Samsung S3C24XX series SPI"
  33         depends on ARCH_S3C24XX
  34 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  35 index 6a7f6f9..3d690ef 100644
  36 --- a/drivers/spi/Makefile
  37 +++ b/drivers/spi/Makefile
  38 @@ -68,6 +68,7 @@ obj-$(CONFIG_SPI_QUP)                 += spi-qup.o
  39  obj-$(CONFIG_SPI_ROCKCHIP)             += spi-rockchip.o
  40  obj-$(CONFIG_SPI_RB4XX)                        += spi-rb4xx.o
  41  obj-$(CONFIG_SPI_RSPI)                 += spi-rspi.o
  42 +obj-$(CONFIG_SPI_RT2880)               += spi-rt2880.o
  43  obj-$(CONFIG_SPI_S3C24XX)              += spi-s3c24xx-hw.o
  44  spi-s3c24xx-hw-y                       := spi-s3c24xx.o
  45  spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
  46 diff --git a/drivers/spi/spi-rt2880.c b/drivers/spi/spi-rt2880.c
  47 new file mode 100644
  48 index 0000000..c286c94
  49 --- /dev/null
  50 +++ b/drivers/spi/spi-rt2880.c
  51 @@ -0,0 +1,530 @@
  52 +/*
  53 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
  54 + *
  55 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  56 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  57 + *
  58 + * Some parts are based on spi-orion.c:
  59 + *   Author: Shadi Ammouri <shadi@marvell.com>
  60 + *   Copyright (C) 2007-2008 Marvell Ltd.
  61 + *
  62 + * This program is free software; you can redistribute it and/or modify
  63 + * it under the terms of the GNU General Public License version 2 as
  64 + * published by the Free Software Foundation.
  65 + */
  66 +
  67 +#include <linux/init.h>
  68 +#include <linux/module.h>
  69 +#include <linux/clk.h>
  70 +#include <linux/err.h>
  71 +#include <linux/delay.h>
  72 +#include <linux/io.h>
  73 +#include <linux/reset.h>
  74 +#include <linux/spi/spi.h>
  75 +#include <linux/platform_device.h>
  76 +#include <linux/gpio.h>
  77 +
  78 +#define DRIVER_NAME                    "spi-rt2880"
  79 +
  80 +#define RAMIPS_SPI_STAT                        0x00
  81 +#define RAMIPS_SPI_CFG                 0x10
  82 +#define RAMIPS_SPI_CTL                 0x14
  83 +#define RAMIPS_SPI_DATA                        0x20
  84 +#define RAMIPS_SPI_ADDR                        0x24
  85 +#define RAMIPS_SPI_BS                  0x28
  86 +#define RAMIPS_SPI_USER                        0x2C
  87 +#define RAMIPS_SPI_TXFIFO              0x30
  88 +#define RAMIPS_SPI_RXFIFO              0x34
  89 +#define RAMIPS_SPI_FIFO_STAT           0x38
  90 +#define RAMIPS_SPI_MODE                        0x3C
  91 +#define RAMIPS_SPI_DEV_OFFSET          0x40
  92 +#define RAMIPS_SPI_DMA                 0x80
  93 +#define RAMIPS_SPI_DMASTAT             0x84
  94 +#define RAMIPS_SPI_ARBITER             0xF0
  95 +
  96 +/* SPISTAT register bit field */
  97 +#define SPISTAT_BUSY                   BIT(0)
  98 +
  99 +/* SPICFG register bit field */
 100 +#define SPICFG_ADDRMODE                        BIT(12)
 101 +#define SPICFG_RXENVDIS                        BIT(11)
 102 +#define SPICFG_RXCAP                   BIT(10)
 103 +#define SPICFG_SPIENMODE               BIT(9)
 104 +#define SPICFG_MSBFIRST                        BIT(8)
 105 +#define SPICFG_SPICLKPOL               BIT(6)
 106 +#define SPICFG_RXCLKEDGE_FALLING       BIT(5)
 107 +#define SPICFG_TXCLKEDGE_FALLING       BIT(4)
 108 +#define SPICFG_HIZSPI                  BIT(3)
 109 +#define SPICFG_SPICLK_PRESCALE_MASK    0x7
 110 +#define SPICFG_SPICLK_DIV2             0
 111 +#define SPICFG_SPICLK_DIV4             1
 112 +#define SPICFG_SPICLK_DIV8             2
 113 +#define SPICFG_SPICLK_DIV16            3
 114 +#define SPICFG_SPICLK_DIV32            4
 115 +#define SPICFG_SPICLK_DIV64            5
 116 +#define SPICFG_SPICLK_DIV128           6
 117 +#define SPICFG_SPICLK_DISABLE          7
 118 +
 119 +/* SPICTL register bit field */
 120 +#define SPICTL_START                   BIT(4)
 121 +#define SPICTL_HIZSDO                  BIT(3)
 122 +#define SPICTL_STARTWR                 BIT(2)
 123 +#define SPICTL_STARTRD                 BIT(1)
 124 +#define SPICTL_SPIENA                  BIT(0)
 125 +
 126 +/* SPIUSER register bit field */
 127 +#define SPIUSER_USERMODE               BIT(21)
 128 +#define SPIUSER_INSTR_PHASE            BIT(20)
 129 +#define SPIUSER_ADDR_PHASE_MASK                0x7
 130 +#define SPIUSER_ADDR_PHASE_OFFSET      17
 131 +#define SPIUSER_MODE_PHASE             BIT(16)
 132 +#define SPIUSER_DUMMY_PHASE_MASK       0x3
 133 +#define SPIUSER_DUMMY_PHASE_OFFSET     14
 134 +#define SPIUSER_DATA_PHASE_MASK                0x3
 135 +#define SPIUSER_DATA_PHASE_OFFSET      12
 136 +#define SPIUSER_DATA_READ              (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
 137 +#define SPIUSER_DATA_WRITE             (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
 138 +#define SPIUSER_ADDR_TYPE_OFFSET       9
 139 +#define SPIUSER_MODE_TYPE_OFFSET       6
 140 +#define SPIUSER_DUMMY_TYPE_OFFSET      3
 141 +#define SPIUSER_DATA_TYPE_OFFSET       0
 142 +#define SPIUSER_TRANSFER_MASK          0x7
 143 +#define SPIUSER_TRANSFER_SINGLE                BIT(0)
 144 +#define SPIUSER_TRANSFER_DUAL          BIT(1)
 145 +#define SPIUSER_TRANSFER_QUAD          BIT(2)
 146 +
 147 +#define SPIUSER_TRANSFER_TYPE(type) ( \
 148 +       (type << SPIUSER_ADDR_TYPE_OFFSET) | \
 149 +       (type << SPIUSER_MODE_TYPE_OFFSET) | \
 150 +       (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
 151 +       (type << SPIUSER_DATA_TYPE_OFFSET) \
 152 +)
 153 +
 154 +/* SPIFIFOSTAT register bit field */
 155 +#define SPIFIFOSTAT_TXEMPTY            BIT(19)
 156 +#define SPIFIFOSTAT_RXEMPTY            BIT(18)
 157 +#define SPIFIFOSTAT_TXFULL             BIT(17)
 158 +#define SPIFIFOSTAT_RXFULL             BIT(16)
 159 +#define SPIFIFOSTAT_FIFO_MASK          0xff
 160 +#define SPIFIFOSTAT_TX_OFFSET          8
 161 +#define SPIFIFOSTAT_RX_OFFSET          0
 162 +
 163 +#define SPI_FIFO_DEPTH                 16
 164 +
 165 +/* SPIMODE register bit field */
 166 +#define SPIMODE_MODE_OFFSET            24
 167 +#define SPIMODE_DUMMY_OFFSET           0
 168 +
 169 +/* SPIARB register bit field */
 170 +#define SPICTL_ARB_EN                  BIT(31)
 171 +#define SPICTL_CSCTL1                  BIT(16)
 172 +#define SPI1_POR                       BIT(1)
 173 +#define SPI0_POR                       BIT(0)
 174 +
 175 +#define RT2880_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
 176 +               SPI_CS_HIGH)
 177 +
 178 +static atomic_t hw_reset_count = ATOMIC_INIT(0);
 179 +
 180 +struct rt2880_spi {
 181 +       struct spi_master       *master;
 182 +       void __iomem            *base;
 183 +       u32                     speed;
 184 +       u16                     wait_loops;
 185 +       u16                     mode;
 186 +       struct clk              *clk;
 187 +};
 188 +
 189 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
 190 +{
 191 +       return spi_master_get_devdata(spi->master);
 192 +}
 193 +
 194 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
 195 +{
 196 +       return ioread32(rs->base + reg);
 197 +}
 198 +
 199 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
 200 +               const u32 val)
 201 +{
 202 +       iowrite32(val, rs->base + reg);
 203 +}
 204 +
 205 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 206 +{
 207 +       void __iomem *addr = rs->base + reg;
 208 +
 209 +       iowrite32((ioread32(addr) | mask), addr);
 210 +}
 211 +
 212 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 213 +{
 214 +       void __iomem *addr = rs->base + reg;
 215 +
 216 +       iowrite32((ioread32(addr) & ~mask), addr);
 217 +}
 218 +
 219 +static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
 220 +{
 221 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 222 +       u32 rate;
 223 +       u32 prescale;
 224 +
 225 +       /*
 226 +        * the supported rates are: 2, 4, 8, ... 128
 227 +        * round up as we look for equal or less speed
 228 +        */
 229 +       rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
 230 +       rate = roundup_pow_of_two(rate);
 231 +
 232 +       /* Convert the rate to SPI clock divisor value. */
 233 +       prescale = ilog2(rate / 2);
 234 +
 235 +       /* some tolerance. double and add 100 */
 236 +       rs->wait_loops = (8 * HZ * loops_per_jiffy) /
 237 +               (clk_get_rate(rs->clk) / rate);
 238 +       rs->wait_loops = (rs->wait_loops << 1) + 100;
 239 +       rs->speed = speed;
 240 +
 241 +       dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
 242 +                       clk_get_rate(rs->clk) / rate, speed, rate, prescale,
 243 +                       rs->wait_loops);
 244 +
 245 +       return prescale;
 246 +}
 247 +
 248 +static u32 get_arbiter_offset(struct spi_master *master)
 249 +{
 250 +       u32 offset;
 251 +
 252 +       offset = RAMIPS_SPI_ARBITER;
 253 +       if (master->bus_num == 1)
 254 +               offset -= RAMIPS_SPI_DEV_OFFSET;
 255 +
 256 +       return offset;
 257 +}
 258 +
 259 +static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)
 260 +{
 261 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 262 +
 263 +       if (enable)
 264 +               rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 265 +       else
 266 +               rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 267 +}
 268 +
 269 +static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
 270 +{
 271 +       int loop = rs->wait_loops * len;
 272 +
 273 +       while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
 274 +               cpu_relax();
 275 +
 276 +       if (loop)
 277 +               return 0;
 278 +
 279 +       return -ETIMEDOUT;
 280 +}
 281 +
 282 +static void rt2880_dump_reg(struct spi_master *master)
 283 +{
 284 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 285 +
 286 +       dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \
 287 +                       "data: %08x, arb: %08x\n",
 288 +                       rt2880_spi_read(rs, RAMIPS_SPI_STAT),
 289 +                       rt2880_spi_read(rs, RAMIPS_SPI_CFG),
 290 +                       rt2880_spi_read(rs, RAMIPS_SPI_CTL),
 291 +                       rt2880_spi_read(rs, RAMIPS_SPI_DATA),
 292 +                       rt2880_spi_read(rs, get_arbiter_offset(master)));
 293 +}
 294 +
 295 +static int rt2880_spi_transfer_one(struct spi_master *master,
 296 +               struct spi_device *spi, struct spi_transfer *xfer)
 297 +{
 298 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 299 +       unsigned len;
 300 +       const u8 *tx = xfer->tx_buf;
 301 +       u8 *rx = xfer->rx_buf;
 302 +       int err = 0;
 303 +
 304 +       /* change clock speed  */
 305 +       if (unlikely(rs->speed != xfer->speed_hz)) {
 306 +               u32 reg;
 307 +               reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
 308 +               reg &= ~SPICFG_SPICLK_PRESCALE_MASK;
 309 +               reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);
 310 +               rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
 311 +       }
 312 +
 313 +       if (tx) {
 314 +               len = xfer->len;
 315 +               while (len-- > 0) {
 316 +                       rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);
 317 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
 318 +                       err = rt2880_spi_wait_ready(rs, 1);
 319 +                       if (err) {
 320 +                               dev_err(&spi->dev, "TX failed, err=%d\n", err);
 321 +                               goto out;
 322 +                       }
 323 +               }
 324 +       }
 325 +
 326 +       if (rx) {
 327 +               len = xfer->len;
 328 +               while (len-- > 0) {
 329 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
 330 +                       err = rt2880_spi_wait_ready(rs, 1);
 331 +                       if (err) {
 332 +                               dev_err(&spi->dev, "RX failed, err=%d\n", err);
 333 +                               goto out;
 334 +                       }
 335 +                       *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
 336 +               }
 337 +       }
 338 +
 339 +out:
 340 +       return err;
 341 +}
 342 +
 343 +/* copy from spi.c */
 344 +static void spi_set_cs(struct spi_device *spi, bool enable)
 345 +{
 346 +       if (spi->mode & SPI_CS_HIGH)
 347 +               enable = !enable;
 348 +
 349 +       if (spi->cs_gpio >= 0)
 350 +               gpio_set_value(spi->cs_gpio, !enable);
 351 +       else if (spi->master->set_cs)
 352 +               spi->master->set_cs(spi, !enable);
 353 +}
 354 +
 355 +static int rt2880_spi_setup(struct spi_device *spi)
 356 +{
 357 +       struct spi_master *master = spi->master;
 358 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 359 +       u32 reg, old_reg, arbit_off;
 360 +
 361 +       if ((spi->max_speed_hz > master->max_speed_hz) ||
 362 +                       (spi->max_speed_hz < master->min_speed_hz)) {
 363 +               dev_err(&spi->dev, "invalide requested speed %d Hz\n",
 364 +                               spi->max_speed_hz);
 365 +               return -EINVAL;
 366 +       }
 367 +
 368 +       if (!(master->bits_per_word_mask &
 369 +                               BIT(spi->bits_per_word - 1))) {
 370 +               dev_err(&spi->dev, "invalide bits_per_word %d\n",
 371 +                               spi->bits_per_word);
 372 +               return -EINVAL;
 373 +       }
 374 +
 375 +       /* the hardware seems can't work on mode0 force it to mode3 */
 376 +       if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
 377 +               dev_warn(&spi->dev, "force spi mode3\n");
 378 +               spi->mode |= SPI_MODE_3;
 379 +       }
 380 +
 381 +       /* chip polarity */
 382 +       arbit_off = get_arbiter_offset(master);
 383 +       reg = old_reg = rt2880_spi_read(rs, arbit_off);
 384 +       if (spi->mode & SPI_CS_HIGH) {
 385 +               switch (master->bus_num) {
 386 +               case 1:
 387 +                       reg |= SPI1_POR;
 388 +                       break;
 389 +               default:
 390 +                       reg |= SPI0_POR;
 391 +                       break;
 392 +               }
 393 +       } else {
 394 +               switch (master->bus_num) {
 395 +               case 1:
 396 +                       reg &= ~SPI1_POR;
 397 +                       break;
 398 +               default:
 399 +                       reg &= ~SPI0_POR;
 400 +                       break;
 401 +               }
 402 +       }
 403 +
 404 +       /* enable spi1 */
 405 +       if (master->bus_num == 1)
 406 +               reg |= SPICTL_ARB_EN;
 407 +
 408 +       if (reg != old_reg)
 409 +               rt2880_spi_write(rs, arbit_off, reg);
 410 +
 411 +       /* deselected the spi device */
 412 +       spi_set_cs(spi, false);
 413 +
 414 +       rt2880_dump_reg(master);
 415 +
 416 +       return 0;
 417 +}
 418 +
 419 +static int rt2880_spi_prepare_message(struct spi_master *master,
 420 +               struct spi_message *msg)
 421 +{
 422 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 423 +       struct spi_device *spi = msg->spi;
 424 +       u32 reg;
 425 +
 426 +       if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
 427 +               return 0;
 428 +
 429 +#if 0
 430 +       /* set spido to tri-state */
 431 +       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
 432 +#endif
 433 +
 434 +       reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
 435 +
 436 +       reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
 437 +                       SPICFG_RXCLKEDGE_FALLING |
 438 +                       SPICFG_TXCLKEDGE_FALLING |
 439 +                       SPICFG_SPICLK_PRESCALE_MASK);
 440 +
 441 +       /* MSB */
 442 +       if (!(spi->mode & SPI_LSB_FIRST))
 443 +               reg |= SPICFG_MSBFIRST;
 444 +
 445 +       /* spi mode */
 446 +       switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
 447 +       case SPI_MODE_0:
 448 +               reg |= SPICFG_TXCLKEDGE_FALLING;
 449 +               break;
 450 +       case SPI_MODE_1:
 451 +               reg |= SPICFG_RXCLKEDGE_FALLING;
 452 +               break;
 453 +       case SPI_MODE_2:
 454 +               reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
 455 +               break;
 456 +       case SPI_MODE_3:
 457 +               reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
 458 +               break;
 459 +       }
 460 +       rs->mode = spi->mode;
 461 +
 462 +#if 0
 463 +       /* set spiclk and spiena to tri-state */
 464 +       reg |= SPICFG_HIZSPI;
 465 +#endif
 466 +
 467 +       /* clock divide */
 468 +       reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
 469 +
 470 +       rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
 471 +
 472 +       return 0;
 473 +}
 474 +
 475 +static int rt2880_spi_probe(struct platform_device *pdev)
 476 +{
 477 +       struct spi_master *master;
 478 +       struct rt2880_spi *rs;
 479 +       void __iomem *base;
 480 +       struct resource *r;
 481 +       struct clk *clk;
 482 +       int ret;
 483 +
 484 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 485 +       base = devm_ioremap_resource(&pdev->dev, r);
 486 +       if (IS_ERR(base))
 487 +               return PTR_ERR(base);
 488 +
 489 +       clk = devm_clk_get(&pdev->dev, NULL);
 490 +       if (IS_ERR(clk)) {
 491 +               dev_err(&pdev->dev, "unable to get SYS clock\n");
 492 +               return PTR_ERR(clk);
 493 +       }
 494 +
 495 +       ret = clk_prepare_enable(clk);
 496 +       if (ret)
 497 +               goto err_clk;
 498 +
 499 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 500 +       if (master == NULL) {
 501 +               dev_dbg(&pdev->dev, "master allocation failed\n");
 502 +               ret = -ENOMEM;
 503 +               goto err_clk;
 504 +       }
 505 +
 506 +       master->dev.of_node = pdev->dev.of_node;
 507 +       master->mode_bits = RT2880_SPI_MODE_BITS;
 508 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 509 +       master->min_speed_hz = clk_get_rate(clk) / 128;
 510 +       master->max_speed_hz = clk_get_rate(clk) / 2;
 511 +       master->flags = SPI_MASTER_HALF_DUPLEX;
 512 +       master->setup = rt2880_spi_setup;
 513 +       master->prepare_message = rt2880_spi_prepare_message;
 514 +       master->set_cs = rt2880_spi_set_cs;
 515 +       master->transfer_one = rt2880_spi_transfer_one,
 516 +
 517 +       dev_set_drvdata(&pdev->dev, master);
 518 +
 519 +       rs = spi_master_get_devdata(master);
 520 +       rs->master = master;
 521 +       rs->base = base;
 522 +       rs->clk = clk;
 523 +
 524 +       if (atomic_inc_return(&hw_reset_count) == 1)
 525 +               device_reset(&pdev->dev);
 526 +
 527 +       ret = devm_spi_register_master(&pdev->dev, master);
 528 +       if (ret < 0) {
 529 +               dev_err(&pdev->dev, "devm_spi_register_master error.\n");
 530 +               goto err_master;
 531 +       }
 532 +
 533 +       return ret;
 534 +
 535 +err_master:
 536 +       spi_master_put(master);
 537 +       kfree(master);
 538 +err_clk:
 539 +       clk_disable_unprepare(clk);
 540 +
 541 +       return ret;
 542 +}
 543 +
 544 +static int rt2880_spi_remove(struct platform_device *pdev)
 545 +{
 546 +       struct spi_master *master;
 547 +       struct rt2880_spi *rs;
 548 +
 549 +       master = dev_get_drvdata(&pdev->dev);
 550 +       rs = spi_master_get_devdata(master);
 551 +
 552 +       clk_disable_unprepare(rs->clk);
 553 +       atomic_dec(&hw_reset_count);
 554 +
 555 +       return 0;
 556 +}
 557 +
 558 +MODULE_ALIAS("platform:" DRIVER_NAME);
 559 +
 560 +static const struct of_device_id rt2880_spi_match[] = {
 561 +       { .compatible = "ralink,rt2880-spi" },
 562 +       {},
 563 +};
 564 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 565 +
 566 +static struct platform_driver rt2880_spi_driver = {
 567 +       .driver = {
 568 +               .name = DRIVER_NAME,
 569 +               .owner = THIS_MODULE,
 570 +               .of_match_table = rt2880_spi_match,
 571 +       },
 572 +       .probe = rt2880_spi_probe,
 573 +       .remove = rt2880_spi_remove,
 574 +};
 575 +
 576 +module_platform_driver(rt2880_spi_driver);
 577 +
 578 +MODULE_DESCRIPTION("Ralink SPI driver");
 579 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
 580 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 581 +MODULE_LICENSE("GPL");
 582 --
 583 1.7.10.4
 584