ramips: fix ethernet stability issue introduced by recent kernel upgrade
[openwrt.git] / target / linux / ramips / patches-3.9 / 0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From 12ea1efe1496e936d1cecc4de97ee55321aceee9 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 159/164] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10  .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
11  arch/mips/ralink/rt305x.c                          |    1 +
12  drivers/net/ethernet/Kconfig                       |    1 +
13  drivers/net/ethernet/Makefile                      |    1 +
14  drivers/net/ethernet/ralink/Kconfig                |   31 +
15  drivers/net/ethernet/ralink/Makefile               |   18 +
16  drivers/net/ethernet/ralink/esw_rt3052.c           | 1463 ++++++++++++++++++++
17  drivers/net/ethernet/ralink/esw_rt3052.h           |   32 +
18  drivers/net/ethernet/ralink/gsw_mt7620a.c          | 1027 ++++++++++++++
19  drivers/net/ethernet/ralink/gsw_mt7620a.h          |   29 +
20  drivers/net/ethernet/ralink/mdio.c                 |  245 ++++
21  drivers/net/ethernet/ralink/mdio.h                 |   29 +
22  drivers/net/ethernet/ralink/mdio_rt2880.c          |  163 +++
23  drivers/net/ethernet/ralink/mdio_rt2880.h          |   25 +
24  drivers/net/ethernet/ralink/ralink_soc_eth.c       |  759 ++++++++++
25  drivers/net/ethernet/ralink/ralink_soc_eth.h       |  372 +++++
26  drivers/net/ethernet/ralink/soc_mt7620.c           |  111 ++
27  drivers/net/ethernet/ralink/soc_rt2880.c           |   51 +
28  drivers/net/ethernet/ralink/soc_rt305x.c           |  102 ++
29  drivers/net/ethernet/ralink/soc_rt3883.c           |   59 +
30  20 files changed, 4546 insertions(+)
31  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
32  create mode 100644 drivers/net/ethernet/ralink/Kconfig
33  create mode 100644 drivers/net/ethernet/ralink/Makefile
34  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
35  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
36  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
37  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
38  create mode 100644 drivers/net/ethernet/ralink/mdio.c
39  create mode 100644 drivers/net/ethernet/ralink/mdio.h
40  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
41  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
42  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
43  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
44  create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
45  create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
46  create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
47  create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
48
49 Index: linux-3.9.6/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
50 ===================================================================
51 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
52 +++ linux-3.9.6/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h 2013-06-24 14:12:43.500180312 +0200
53 @@ -0,0 +1,27 @@
54 +/*
55 + *  Ralink RT305x SoC platform device registration
56 + *
57 + *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
58 + *
59 + *  This program is free software; you can redistribute it and/or modify it
60 + *  under the terms of the GNU General Public License version 2 as published
61 + *  by the Free Software Foundation.
62 + */
63 +
64 +#ifndef _RT305X_ESW_PLATFORM_H
65 +#define _RT305X_ESW_PLATFORM_H
66 +
67 +enum {
68 +       RT305X_ESW_VLAN_CONFIG_NONE = 0,
69 +       RT305X_ESW_VLAN_CONFIG_LLLLW,
70 +       RT305X_ESW_VLAN_CONFIG_WLLLL,
71 +};
72 +
73 +struct rt305x_esw_platform_data
74 +{
75 +       u8 vlan_config;
76 +       u32 reg_initval_fct2;
77 +       u32 reg_initval_fpa2;
78 +};
79 +
80 +#endif /* _RT305X_ESW_PLATFORM_H */
81 Index: linux-3.9.6/arch/mips/ralink/rt305x.c
82 ===================================================================
83 --- linux-3.9.6.orig/arch/mips/ralink/rt305x.c  2013-06-24 14:12:42.560180272 +0200
84 +++ linux-3.9.6/arch/mips/ralink/rt305x.c       2013-06-24 14:12:43.504180312 +0200
85 @@ -221,6 +221,7 @@
86         }
87  
88         ralink_clk_add("cpu", cpu_rate);
89 +       ralink_clk_add("sys", sys_rate);
90         ralink_clk_add("10000b00.spi", sys_rate);
91         ralink_clk_add("10000100.timer", wdt_rate);
92         ralink_clk_add("10000120.watchdog", wdt_rate);
93 Index: linux-3.9.6/drivers/net/ethernet/Kconfig
94 ===================================================================
95 --- linux-3.9.6.orig/drivers/net/ethernet/Kconfig       2013-06-13 19:52:08.000000000 +0200
96 +++ linux-3.9.6/drivers/net/ethernet/Kconfig    2013-06-24 14:12:43.504180312 +0200
97 @@ -135,6 +135,7 @@
98  source "drivers/net/ethernet/packetengines/Kconfig"
99  source "drivers/net/ethernet/pasemi/Kconfig"
100  source "drivers/net/ethernet/qlogic/Kconfig"
101 +source "drivers/net/ethernet/ralink/Kconfig"
102  source "drivers/net/ethernet/realtek/Kconfig"
103  source "drivers/net/ethernet/renesas/Kconfig"
104  source "drivers/net/ethernet/rdc/Kconfig"
105 Index: linux-3.9.6/drivers/net/ethernet/Makefile
106 ===================================================================
107 --- linux-3.9.6.orig/drivers/net/ethernet/Makefile      2013-06-13 19:52:08.000000000 +0200
108 +++ linux-3.9.6/drivers/net/ethernet/Makefile   2013-06-24 14:12:43.504180312 +0200
109 @@ -53,6 +53,7 @@
110  obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
111  obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
112  obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
113 +obj-$(CONFIG_NET_RALINK) += ralink/
114  obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
115  obj-$(CONFIG_SH_ETH) += renesas/
116  obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
117 Index: linux-3.9.6/drivers/net/ethernet/ralink/Kconfig
118 ===================================================================
119 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
120 +++ linux-3.9.6/drivers/net/ethernet/ralink/Kconfig     2013-06-24 14:12:43.504180312 +0200
121 @@ -0,0 +1,31 @@
122 +config NET_RALINK
123 +       tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
124 +       depends on RALINK
125 +       help
126 +         This driver supports the ethernet mac inside the ralink wisocs
127 +
128 +if NET_RALINK
129 +
130 +config NET_RALINK_MDIO
131 +       def_bool NET_RALINK
132 +       depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
133 +       select PHYLIB
134 +
135 +config NET_RALINK_MDIO_RT2880
136 +       def_bool NET_RALINK
137 +       depends on (SOC_RT288X || SOC_RT3883)
138 +       select NET_RALINK_MDIO
139 +
140 +config NET_RALINK_ESW_RT3052
141 +       def_bool NET_RALINK
142 +       depends on SOC_RT305X
143 +       select PHYLIB
144 +       select SWCONFIG
145 +
146 +config NET_RALINK_GSW_MT7620
147 +       def_bool NET_RALINK
148 +       depends on SOC_MT7620
149 +       select NET_RALINK_MDIO
150 +       select PHYLIB
151 +       select SWCONFIG
152 +endif
153 Index: linux-3.9.6/drivers/net/ethernet/ralink/Makefile
154 ===================================================================
155 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
156 +++ linux-3.9.6/drivers/net/ethernet/ralink/Makefile    2013-06-24 14:12:43.504180312 +0200
157 @@ -0,0 +1,18 @@
158 +#
159 +# Makefile for the Ralink SoCs built-in ethernet macs
160 +#
161 +
162 +ralink-eth-y                                   += ralink_soc_eth.o
163 +
164 +ralink-eth-$(CONFIG_NET_RALINK_MDIO)           += mdio.o
165 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880)    += mdio_rt2880.o
166 +
167 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052)     += esw_rt3052.o
168 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620)     += gsw_mt7620a.o
169 +
170 +ralink-eth-$(CONFIG_SOC_RT288X)                        += soc_rt2880.o
171 +ralink-eth-$(CONFIG_SOC_RT305X)                        += soc_rt305x.o
172 +ralink-eth-$(CONFIG_SOC_RT3883)                        += soc_rt3883.o
173 +ralink-eth-$(CONFIG_SOC_MT7620)                        += soc_mt7620.o
174 +
175 +obj-$(CONFIG_NET_RALINK)                       += ralink-eth.o
176 Index: linux-3.9.6/drivers/net/ethernet/ralink/esw_rt3052.c
177 ===================================================================
178 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
179 +++ linux-3.9.6/drivers/net/ethernet/ralink/esw_rt3052.c        2013-06-24 14:12:43.508180313 +0200
180 @@ -0,0 +1,1463 @@
181 +/*
182 + *   This program is free software; you can redistribute it and/or modify
183 + *   it under the terms of the GNU General Public License as published by
184 + *   the Free Software Foundation; version 2 of the License
185 + *
186 + *   This program is distributed in the hope that it will be useful,
187 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
188 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
189 + *   GNU General Public License for more details.
190 + *
191 + *   You should have received a copy of the GNU General Public License
192 + *   along with this program; if not, write to the Free Software
193 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
194 + *
195 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
196 + */
197 +
198 +#include <linux/module.h>
199 +#include <linux/kernel.h>
200 +#include <linux/types.h>
201 +#include <linux/dma-mapping.h>
202 +#include <linux/init.h>
203 +#include <linux/skbuff.h>
204 +#include <linux/etherdevice.h>
205 +#include <linux/ethtool.h>
206 +#include <linux/platform_device.h>
207 +#include <linux/of_device.h>
208 +#include <linux/clk.h>
209 +#include <linux/of_net.h>
210 +#include <linux/of_mdio.h>
211 +
212 +#include <asm/mach-ralink/ralink_regs.h>
213 +
214 +#include "ralink_soc_eth.h"
215 +
216 +#include <linux/ioport.h>
217 +#include <linux/switch.h>
218 +#include <linux/mii.h>
219 +
220 +#include <ralink_regs.h>
221 +#include <asm/mach-ralink/rt305x.h>
222 +#include <asm/mach-ralink/rt305x_esw_platform.h>
223 +
224 +/*
225 + * HW limitations for this switch:
226 + * - No large frame support (PKT_MAX_LEN at most 1536)
227 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
228 + *   though this might be possible using the undocumented PPE.
229 + */
230 +
231 +#define RT305X_ESW_REG_ISR             0x00
232 +#define RT305X_ESW_REG_IMR             0x04
233 +#define RT305X_ESW_REG_FCT0            0x08
234 +#define RT305X_ESW_REG_PFC1            0x14
235 +#define RT305X_ESW_REG_ATS             0x24
236 +#define RT305X_ESW_REG_ATS0            0x28
237 +#define RT305X_ESW_REG_ATS1            0x2c
238 +#define RT305X_ESW_REG_ATS2            0x30
239 +#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
240 +#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
241 +#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
242 +#define RT305X_ESW_REG_POA             0x80
243 +#define RT305X_ESW_REG_FPA             0x84
244 +#define RT305X_ESW_REG_SOCPC           0x8c
245 +#define RT305X_ESW_REG_POC0            0x90
246 +#define RT305X_ESW_REG_POC1            0x94
247 +#define RT305X_ESW_REG_POC2            0x98
248 +#define RT305X_ESW_REG_SGC             0x9c
249 +#define RT305X_ESW_REG_STRT            0xa0
250 +#define RT305X_ESW_REG_PCR0            0xc0
251 +#define RT305X_ESW_REG_PCR1            0xc4
252 +#define RT305X_ESW_REG_FPA2            0xc8
253 +#define RT305X_ESW_REG_FCT2            0xcc
254 +#define RT305X_ESW_REG_SGC2            0xe4
255 +#define RT305X_ESW_REG_P0LED           0xa4
256 +#define RT305X_ESW_REG_P1LED           0xa8
257 +#define RT305X_ESW_REG_P2LED           0xac
258 +#define RT305X_ESW_REG_P3LED           0xb0
259 +#define RT305X_ESW_REG_P4LED           0xb4
260 +#define RT305X_ESW_REG_PXPC(_x)                (0xe8 + (4 * _x))
261 +#define RT305X_ESW_REG_P1PC            0xec
262 +#define RT305X_ESW_REG_P2PC            0xf0
263 +#define RT305X_ESW_REG_P3PC            0xf4
264 +#define RT305X_ESW_REG_P4PC            0xf8
265 +#define RT305X_ESW_REG_P5PC            0xfc
266 +
267 +#define RT305X_ESW_LED_LINK            0
268 +#define RT305X_ESW_LED_100M            1
269 +#define RT305X_ESW_LED_DUPLEX          2
270 +#define RT305X_ESW_LED_ACTIVITY                3
271 +#define RT305X_ESW_LED_COLLISION       4
272 +#define RT305X_ESW_LED_LINKACT         5
273 +#define RT305X_ESW_LED_DUPLCOLL                6
274 +#define RT305X_ESW_LED_10MACT          7
275 +#define RT305X_ESW_LED_100MACT         8
276 +/* Additional led states not in datasheet: */
277 +#define RT305X_ESW_LED_BLINK           10
278 +#define RT305X_ESW_LED_ON              12
279 +
280 +#define RT305X_ESW_LINK_S              25
281 +#define RT305X_ESW_DUPLEX_S            9
282 +#define RT305X_ESW_SPD_S               0
283 +
284 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
285 +#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
286 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
287 +
288 +#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
289 +
290 +#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
291 +#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
292 +
293 +#define RT305X_ESW_PVIDC_PVID_M                0xfff
294 +#define RT305X_ESW_PVIDC_PVID_S                12
295 +
296 +#define RT305X_ESW_VLANI_VID_M         0xfff
297 +#define RT305X_ESW_VLANI_VID_S         12
298 +
299 +#define RT305X_ESW_VMSC_MSC_M          0xff
300 +#define RT305X_ESW_VMSC_MSC_S          8
301 +
302 +#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
303 +#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
304 +#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
305 +#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
306 +
307 +#define RT305X_ESW_POC0_EN_BP_S                0
308 +#define RT305X_ESW_POC0_EN_FC_S                8
309 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
310 +#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
311 +#define RT305X_ESW_POC0_DIS_PORT_S     23
312 +
313 +#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
314 +#define RT305X_ESW_POC2_UNTAG_EN_S     0
315 +#define RT305X_ESW_POC2_ENAGING_S      8
316 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
317 +
318 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
319 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
320 +#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
321 +#define RT305X_ESW_SGC2_LAN_PMAP_S     24
322 +
323 +#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
324 +#define RT305X_ESW_PFC1_EN_VLAN_S      16
325 +#define RT305X_ESW_PFC1_EN_TOS_S       24
326 +
327 +#define RT305X_ESW_VLAN_NONE           0xfff
328 +
329 +#define RT305X_ESW_GSC_BC_STROM_MASK   0x3
330 +#define RT305X_ESW_GSC_BC_STROM_SHIFT  4
331 +
332 +#define RT305X_ESW_GSC_LED_FREQ_MASK   0x3
333 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT  23
334 +
335 +#define RT305X_ESW_POA_LINK_MASK       0x1f
336 +#define RT305X_ESW_POA_LINK_SHIFT      25
337 +
338 +#define RT305X_ESW_PORT_ST_CHG         BIT(26)
339 +#define RT305X_ESW_PORT0               0
340 +#define RT305X_ESW_PORT1               1
341 +#define RT305X_ESW_PORT2               2
342 +#define RT305X_ESW_PORT3               3
343 +#define RT305X_ESW_PORT4               4
344 +#define RT305X_ESW_PORT5               5
345 +#define RT305X_ESW_PORT6               6
346 +
347 +#define RT305X_ESW_PORTS_NONE          0
348 +
349 +#define RT305X_ESW_PMAP_LLLLLL         0x3f
350 +#define RT305X_ESW_PMAP_LLLLWL         0x2f
351 +#define RT305X_ESW_PMAP_WLLLLL         0x3e
352 +
353 +#define RT305X_ESW_PORTS_INTERNAL                                      \
354 +               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
355 +                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
356 +                BIT(RT305X_ESW_PORT4))
357 +
358 +#define RT305X_ESW_PORTS_NOCPU                                         \
359 +               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
360 +
361 +#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
362 +
363 +#define RT305X_ESW_PORTS_ALL                                           \
364 +               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
365 +
366 +#define RT305X_ESW_NUM_VLANS           16
367 +#define RT305X_ESW_NUM_VIDS            4096
368 +#define RT305X_ESW_NUM_PORTS           7
369 +#define RT305X_ESW_NUM_LANWAN          6
370 +#define RT305X_ESW_NUM_LEDS            5
371 +
372 +#define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
373 +#define RT5350_EWS_REG_LED_POLARITY    0x168
374 +#define RT5350_RESET_EPHY              BIT(24)
375 +#define SYSC_REG_RESET_CTRL            0x34
376 +
377 +enum {
378 +       /* Global attributes. */
379 +       RT305X_ESW_ATTR_ENABLE_VLAN,
380 +       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
381 +       RT305X_ESW_ATTR_BC_STATUS,
382 +       RT305X_ESW_ATTR_LED_FREQ,
383 +       /* Port attributes. */
384 +       RT305X_ESW_ATTR_PORT_DISABLE,
385 +       RT305X_ESW_ATTR_PORT_DOUBLETAG,
386 +       RT305X_ESW_ATTR_PORT_UNTAG,
387 +       RT305X_ESW_ATTR_PORT_LED,
388 +       RT305X_ESW_ATTR_PORT_LAN,
389 +       RT305X_ESW_ATTR_PORT_RECV_BAD,
390 +       RT305X_ESW_ATTR_PORT_RECV_GOOD,
391 +       RT5350_ESW_ATTR_PORT_TR_BAD,
392 +       RT5350_ESW_ATTR_PORT_TR_GOOD,
393 +};
394 +
395 +struct esw_port {
396 +       bool    disable;
397 +       bool    doubletag;
398 +       bool    untag;
399 +       u8      led;
400 +       u16     pvid;
401 +};
402 +
403 +struct esw_vlan {
404 +       u8      ports;
405 +       u16     vid;
406 +};
407 +
408 +struct rt305x_esw {
409 +       struct device           *dev;
410 +       void __iomem            *base;
411 +       int                     irq;
412 +       const struct rt305x_esw_platform_data *pdata;
413 +       /* Protects against concurrent register rmw operations. */
414 +       spinlock_t              reg_rw_lock;
415 +
416 +       unsigned char           port_map;
417 +       unsigned int            reg_initval_fct2;
418 +       unsigned int            reg_initval_fpa2;
419 +       unsigned int            reg_led_polarity;
420 +
421 +
422 +       struct switch_dev       swdev;
423 +       bool                    global_vlan_enable;
424 +       bool                    alt_vlan_disable;
425 +       int                     bc_storm_protect;
426 +       int                     led_frequency;
427 +       struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
428 +       struct esw_port ports[RT305X_ESW_NUM_PORTS];
429 +
430 +};
431 +
432 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
433 +{
434 +       __raw_writel(val, esw->base + reg);
435 +}
436 +
437 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
438 +{
439 +       return __raw_readl(esw->base + reg);
440 +}
441 +
442 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
443 +                  unsigned long val)
444 +{
445 +       unsigned long t;
446 +
447 +       t = __raw_readl(esw->base + reg) & ~mask;
448 +       __raw_writel(t | val, esw->base + reg);
449 +}
450 +
451 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
452 +              unsigned long val)
453 +{
454 +       unsigned long flags;
455 +
456 +       spin_lock_irqsave(&esw->reg_rw_lock, flags);
457 +       esw_rmw_raw(esw, reg, mask, val);
458 +       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
459 +}
460 +
461 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
462 +                u32 write_data)
463 +{
464 +       unsigned long t_start = jiffies;
465 +       int ret = 0;
466 +
467 +       while (1) {
468 +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
469 +                     RT305X_ESW_PCR1_WT_DONE))
470 +                       break;
471 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
472 +                       ret = 1;
473 +                       goto out;
474 +               }
475 +       }
476 +
477 +       write_data &= 0xffff;
478 +       esw_w32(esw,
479 +                     (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
480 +                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
481 +                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
482 +                     RT305X_ESW_REG_PCR0);
483 +
484 +       t_start = jiffies;
485 +       while (1) {
486 +               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
487 +                   RT305X_ESW_PCR1_WT_DONE)
488 +                       break;
489 +
490 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
491 +                       ret = 1;
492 +                       break;
493 +               }
494 +       }
495 +out:
496 +       if (ret)
497 +               printk(KERN_ERR "ramips_eth: MDIO timeout\n");
498 +       return ret;
499 +}
500 +
501 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
502 +{
503 +       unsigned s;
504 +       unsigned val;
505 +
506 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
507 +       val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
508 +       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
509 +
510 +       return val;
511 +}
512 +
513 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
514 +{
515 +       unsigned s;
516 +
517 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
518 +       esw_rmw(esw,
519 +                      RT305X_ESW_REG_VLANI(vlan / 2),
520 +                      RT305X_ESW_VLANI_VID_M << s,
521 +                      (vid & RT305X_ESW_VLANI_VID_M) << s);
522 +}
523 +
524 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
525 +{
526 +       unsigned s, val;
527 +
528 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
529 +       val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
530 +       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
531 +}
532 +
533 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
534 +{
535 +       unsigned s;
536 +
537 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
538 +       esw_rmw(esw,
539 +                      RT305X_ESW_REG_PVIDC(port / 2),
540 +                      RT305X_ESW_PVIDC_PVID_M << s,
541 +                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
542 +}
543 +
544 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
545 +{
546 +       unsigned s, val;
547 +
548 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
549 +       val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
550 +       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
551 +
552 +       return val;
553 +}
554 +
555 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
556 +{
557 +       unsigned s;
558 +
559 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
560 +       esw_rmw(esw,
561 +                      RT305X_ESW_REG_VMSC(vlan / 4),
562 +                      RT305X_ESW_VMSC_MSC_M << s,
563 +                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
564 +}
565 +
566 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
567 +{
568 +       unsigned reg;
569 +       reg = esw_r32(esw, RT305X_ESW_REG_POC0);
570 +       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
571 +              RT305X_ESW_POC0_DIS_PORT_M;
572 +}
573 +
574 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
575 +{
576 +       unsigned old_mask;
577 +       unsigned enable_mask;
578 +       unsigned changed;
579 +       int i;
580 +
581 +       old_mask = esw_get_port_disable(esw);
582 +       changed = old_mask ^ disable_mask;
583 +       enable_mask = old_mask & disable_mask;
584 +
585 +       /* enable before writing to MII */
586 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
587 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
588 +                       RT305X_ESW_POC0_DIS_PORT_S),
589 +                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
590 +
591 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
592 +               if (!(changed & (1 << i)))
593 +                       continue;
594 +               if (disable_mask & (1 << i)) {
595 +                       /* disable */
596 +                       rt305x_mii_write(esw, i, MII_BMCR,
597 +                                        BMCR_PDOWN);
598 +               } else {
599 +                       /* enable */
600 +                       rt305x_mii_write(esw, i, MII_BMCR,
601 +                                        BMCR_FULLDPLX |
602 +                                        BMCR_ANENABLE |
603 +                                        BMCR_ANRESTART |
604 +                                        BMCR_SPEED100);
605 +               }
606 +       }
607 +
608 +       /* disable after writing to MII */
609 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
610 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
611 +                       RT305X_ESW_POC0_DIS_PORT_S),
612 +                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
613 +}
614 +
615 +static void esw_set_gsc(struct rt305x_esw *esw)
616 +{
617 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
618 +               RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
619 +               esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
620 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
621 +               RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
622 +               esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
623 +}
624 +
625 +static int esw_apply_config(struct switch_dev *dev);
626 +
627 +static void esw_hw_init(struct rt305x_esw *esw)
628 +{
629 +       int i;
630 +       u8 port_disable = 0;
631 +       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
632 +
633 +       /* vodoo from original driver */
634 +       esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
635 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
636 +       /* Port priority 1 for all ports, vlan enabled. */
637 +       esw_w32(esw, 0x00005555 |
638 +                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
639 +                     RT305X_ESW_REG_PFC1);
640 +
641 +       /* Enable Back Pressure, and Flow Control */
642 +       esw_w32(esw,
643 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
644 +                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
645 +                     RT305X_ESW_REG_POC0);
646 +
647 +       /* Enable Aging, and VLAN TAG removal */
648 +       esw_w32(esw,
649 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
650 +                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
651 +                     RT305X_ESW_REG_POC2);
652 +
653 +       if (esw->reg_initval_fct2)
654 +               esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
655 +       else
656 +               esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
657 +
658 +       /*
659 +        * 300s aging timer, max packet len 1536, broadcast storm prevention
660 +        * disabled, disable collision abort, mac xor48 hash, 10 packet back
661 +        * pressure jam, GMII disable was_transmit, back pressure disabled,
662 +        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
663 +        * ports.
664 +        */
665 +       esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
666 +
667 +       /* Setup SoC Port control register */
668 +       esw_w32(esw,
669 +                     (RT305X_ESW_SOCPC_CRC_PADDING |
670 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
671 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
672 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
673 +                     RT305X_ESW_REG_SOCPC);
674 +
675 +       if (esw->reg_initval_fpa2)
676 +               esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
677 +       else
678 +               esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
679 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
680 +
681 +       /* Force Link/Activity on ports */
682 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
683 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
684 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
685 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
686 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
687 +
688 +       /* Copy disabled port configuration from bootloader setup */
689 +       port_disable = esw_get_port_disable(esw);
690 +       for (i = 0; i < 6; i++)
691 +               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
692 +
693 +       if (soc_is_rt3352()) {
694 +               /* reset EPHY */
695 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
696 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
697 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
698 +
699 +               rt305x_mii_write(esw, 0, 31, 0x8000);
700 +               for (i = 0; i < 5; i++) {
701 +                       if (esw->ports[i].disable) {
702 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
703 +                       } else {
704 +                               rt305x_mii_write(esw, i, MII_BMCR,
705 +                                        BMCR_FULLDPLX |
706 +                                        BMCR_ANENABLE |
707 +                                        BMCR_SPEED100);
708 +                       }
709 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
710 +                       rt305x_mii_write(esw, i, 26, 0x1601);
711 +                       /* TX100/TX10 AD/DA current bias */
712 +                       rt305x_mii_write(esw, i, 29, 0x7016);
713 +                       /* TX100 slew rate control */
714 +                       rt305x_mii_write(esw, i, 30, 0x0038);
715 +               }
716 +
717 +               /* select global register */
718 +               rt305x_mii_write(esw, 0, 31, 0x0);
719 +               /* enlarge agcsel threshold 3 and threshold 2 */
720 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
721 +               /* enlarge agcsel threshold 5 and threshold 4 */
722 +               rt305x_mii_write(esw, 0, 2, 0x6254);
723 +               /* enlarge agcsel threshold  */
724 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
725 +               rt305x_mii_write(esw, 0,12, 0x7eaa);
726 +               /* longer TP_IDL tail length */
727 +               rt305x_mii_write(esw, 0, 14, 0x65);
728 +               /* increased squelch pulse count threshold. */
729 +               rt305x_mii_write(esw, 0, 16, 0x0684);
730 +               /* set TX10 signal amplitude threshold to minimum */
731 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
732 +               /* set squelch amplitude to higher threshold */
733 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
734 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
735 +               rt305x_mii_write(esw, 0, 22, 0x253f);
736 +               /* set PLL/Receive bias current are calibrated */
737 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
738 +               /* change PLL/Receive bias current to internal(RT3350) */
739 +               rt305x_mii_write(esw, 0, 28, 0xc410);
740 +               /* change PLL bias current to internal(RT3052_MP3) */
741 +               rt305x_mii_write(esw, 0, 29, 0x598b);
742 +               /* select local register */
743 +               rt305x_mii_write(esw, 0, 31, 0x8000);
744 +       } else if (soc_is_rt5350()) {
745 +               /* reset EPHY */
746 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
747 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
748 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
749 +
750 +               /* set the led polarity */
751 +               esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
752 +
753 +               /* local registers */
754 +               rt305x_mii_write(esw, 0, 31, 0x8000);
755 +               for (i = 0; i < 5; i++) {
756 +                       if (esw->ports[i].disable) {
757 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
758 +                       } else {
759 +                               rt305x_mii_write(esw, i, MII_BMCR,
760 +                                        BMCR_FULLDPLX |
761 +                                        BMCR_ANENABLE |
762 +                                        BMCR_SPEED100);
763 +                       }
764 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
765 +                       rt305x_mii_write(esw, i, 26, 0x1601);
766 +                       /* TX100/TX10 AD/DA current bias */
767 +                       rt305x_mii_write(esw, i, 29, 0x7015);
768 +                       /* TX100 slew rate control */
769 +                       rt305x_mii_write(esw, i, 30, 0x0038);
770 +               }
771 +
772 +               /* global registers */
773 +               rt305x_mii_write(esw, 0, 31, 0x0);
774 +               /* enlarge agcsel threshold 3 and threshold 2 */
775 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
776 +               /* enlarge agcsel threshold 5 and threshold 4 */
777 +               rt305x_mii_write(esw, 0, 2, 0x6254);
778 +               /* enlarge agcsel threshold 6 */
779 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
780 +               rt305x_mii_write(esw, 0, 12, 0x7eaa);
781 +               /* longer TP_IDL tail length */
782 +               rt305x_mii_write(esw, 0, 14, 0x65);
783 +               /* increased squelch pulse count threshold. */
784 +               rt305x_mii_write(esw, 0, 16, 0x0684);
785 +               /* set TX10 signal amplitude threshold to minimum */
786 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
787 +               /* set squelch amplitude to higher threshold */
788 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
789 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
790 +               rt305x_mii_write(esw, 0, 22, 0x253f);
791 +               /* set PLL/Receive bias current are calibrated */
792 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
793 +               /* change PLL/Receive bias current to internal(RT3350) */
794 +               rt305x_mii_write(esw, 0, 28, 0xc410);
795 +               /* change PLL bias current to internal(RT3052_MP3) */
796 +               rt305x_mii_write(esw, 0, 29, 0x598b);
797 +               /* select local register */
798 +               rt305x_mii_write(esw, 0, 31, 0x8000);
799 +       } else {
800 +               rt305x_mii_write(esw, 0, 31, 0x8000);
801 +               for (i = 0; i < 5; i++) {
802 +                       if (esw->ports[i].disable) {
803 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
804 +                       } else {
805 +                               rt305x_mii_write(esw, i, MII_BMCR,
806 +                                        BMCR_FULLDPLX |
807 +                                        BMCR_ANENABLE |
808 +                                        BMCR_SPEED100);
809 +                       }
810 +                       /* TX10 waveform coefficient */
811 +                       rt305x_mii_write(esw, i, 26, 0x1601);
812 +                       /* TX100/TX10 AD/DA current bias */
813 +                       rt305x_mii_write(esw, i, 29, 0x7058);
814 +                       /* TX100 slew rate control */
815 +                       rt305x_mii_write(esw, i, 30, 0x0018);
816 +               }
817 +
818 +               /* PHY IOT */
819 +               /* select global register */
820 +               rt305x_mii_write(esw, 0, 31, 0x0);
821 +               /* tune TP_IDL tail and head waveform */
822 +               rt305x_mii_write(esw, 0, 22, 0x052f);
823 +               /* set TX10 signal amplitude threshold to minimum */
824 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
825 +               /* set squelch amplitude to higher threshold */
826 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
827 +               /* longer TP_IDL tail length */
828 +               rt305x_mii_write(esw, 0, 14, 0x65);
829 +               /* select local register */
830 +               rt305x_mii_write(esw, 0, 31, 0x8000);
831 +       }
832 +
833 +       if (esw->port_map)
834 +               port_map = esw->port_map;
835 +       else
836 +               port_map = RT305X_ESW_PMAP_LLLLLL;
837 +
838 +       /*
839 +        * Unused HW feature, but still nice to be consistent here...
840 +        * This is also exported to userspace ('lan' attribute) so it's
841 +        * conveniently usable to decide which ports go into the wan vlan by
842 +        * default.
843 +        */
844 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
845 +                      RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
846 +                      port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
847 +
848 +       /* make the switch leds blink */
849 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
850 +               esw->ports[i].led = 0x05;
851 +
852 +       /* Apply the empty config. */
853 +       esw_apply_config(&esw->swdev);
854 +
855 +       /* Only unmask the port change interrupt */
856 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
857 +}
858 +
859 +static irqreturn_t esw_interrupt(int irq, void *_esw)
860 +{
861 +       struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
862 +       u32 status;
863 +
864 +       status = esw_r32(esw, RT305X_ESW_REG_ISR);
865 +       if (status & RT305X_ESW_PORT_ST_CHG) {
866 +               u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
867 +               link >>= RT305X_ESW_POA_LINK_SHIFT;
868 +               link &= RT305X_ESW_POA_LINK_MASK;
869 +               dev_info(esw->dev, "link changed 0x%02X\n", link);
870 +       }
871 +       esw_w32(esw, status, RT305X_ESW_REG_ISR);
872 +
873 +       return IRQ_HANDLED;
874 +}
875 +
876 +static int esw_apply_config(struct switch_dev *dev)
877 +{
878 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
879 +       int i;
880 +       u8 disable = 0;
881 +       u8 doubletag = 0;
882 +       u8 en_vlan = 0;
883 +       u8 untag = 0;
884 +
885 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
886 +               u32 vid, vmsc;
887 +               if (esw->global_vlan_enable) {
888 +                       vid = esw->vlans[i].vid;
889 +                       vmsc = esw->vlans[i].ports;
890 +               } else {
891 +                       vid = RT305X_ESW_VLAN_NONE;
892 +                       vmsc = RT305X_ESW_PORTS_NONE;
893 +               }
894 +               esw_set_vlan_id(esw, i, vid);
895 +               esw_set_vmsc(esw, i, vmsc);
896 +       }
897 +
898 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
899 +               u32 pvid;
900 +               disable |= esw->ports[i].disable << i;
901 +               if (esw->global_vlan_enable) {
902 +                       doubletag |= esw->ports[i].doubletag << i;
903 +                       en_vlan   |= 1                       << i;
904 +                       untag     |= esw->ports[i].untag     << i;
905 +                       pvid       = esw->ports[i].pvid;
906 +               } else {
907 +                       int x = esw->alt_vlan_disable ? 0 : 1;
908 +                       doubletag |= x << i;
909 +                       en_vlan   |= x << i;
910 +                       untag     |= x << i;
911 +                       pvid       = 0;
912 +               }
913 +               esw_set_pvid(esw, i, pvid);
914 +               if (i < RT305X_ESW_NUM_LEDS)
915 +                       esw_w32(esw, esw->ports[i].led,
916 +                                     RT305X_ESW_REG_P0LED + 4*i);
917 +       }
918 +
919 +       esw_set_gsc(esw);
920 +       esw_set_port_disable(esw, disable);
921 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
922 +                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
923 +                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
924 +                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
925 +       esw_rmw(esw, RT305X_ESW_REG_PFC1,
926 +                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
927 +                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
928 +       esw_rmw(esw, RT305X_ESW_REG_POC2,
929 +                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
930 +                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
931 +
932 +       if (!esw->global_vlan_enable) {
933 +               /*
934 +                * Still need to put all ports into vlan 0 or they'll be
935 +                * isolated.
936 +                * NOTE: vlan 0 is special, no vlan tag is prepended
937 +                */
938 +               esw_set_vlan_id(esw, 0, 0);
939 +               esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
940 +       }
941 +
942 +       return 0;
943 +}
944 +
945 +static int esw_reset_switch(struct switch_dev *dev)
946 +{
947 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
948 +
949 +       esw->global_vlan_enable = 0;
950 +       memset(esw->ports, 0, sizeof(esw->ports));
951 +       memset(esw->vlans, 0, sizeof(esw->vlans));
952 +       esw_hw_init(esw);
953 +
954 +       return 0;
955 +}
956 +
957 +static int esw_get_vlan_enable(struct switch_dev *dev,
958 +                          const struct switch_attr *attr,
959 +                          struct switch_val *val)
960 +{
961 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
962 +
963 +       val->value.i = esw->global_vlan_enable;
964 +
965 +       return 0;
966 +}
967 +
968 +static int esw_set_vlan_enable(struct switch_dev *dev,
969 +                          const struct switch_attr *attr,
970 +                          struct switch_val *val)
971 +{
972 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
973 +
974 +       esw->global_vlan_enable = val->value.i != 0;
975 +
976 +       return 0;
977 +}
978 +
979 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
980 +                               const struct switch_attr *attr,
981 +                               struct switch_val *val)
982 +{
983 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
984 +
985 +       val->value.i = esw->alt_vlan_disable;
986 +
987 +       return 0;
988 +}
989 +
990 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
991 +                               const struct switch_attr *attr,
992 +                               struct switch_val *val)
993 +{
994 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
995 +
996 +       esw->alt_vlan_disable = val->value.i != 0;
997 +
998 +       return 0;
999 +}
1000 +
1001 +static int
1002 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1003 +                       const struct switch_attr *attr,
1004 +                       struct switch_val *val)
1005 +{
1006 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1007 +
1008 +       esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1009 +
1010 +       return 0;
1011 +}
1012 +
1013 +static int
1014 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1015 +                       const struct switch_attr *attr,
1016 +                       struct switch_val *val)
1017 +{
1018 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1019 +
1020 +       val->value.i = esw->bc_storm_protect;
1021 +
1022 +       return 0;
1023 +}
1024 +
1025 +static int
1026 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1027 +                       const struct switch_attr *attr,
1028 +                       struct switch_val *val)
1029 +{
1030 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1031 +
1032 +       esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1033 +
1034 +       return 0;
1035 +}
1036 +
1037 +static int
1038 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1039 +                       const struct switch_attr *attr,
1040 +                       struct switch_val *val)
1041 +{
1042 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1043 +
1044 +       val->value.i = esw->led_frequency;
1045 +
1046 +       return 0;
1047 +}
1048 +
1049 +static int esw_get_port_link(struct switch_dev *dev,
1050 +                        int port,
1051 +                        struct switch_port_link *link)
1052 +{
1053 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1054 +       u32 speed, poa;
1055 +
1056 +       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1057 +               return -EINVAL;
1058 +
1059 +       poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1060 +
1061 +       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1062 +       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1063 +       if (port < RT305X_ESW_NUM_LEDS) {
1064 +               speed = (poa >> RT305X_ESW_SPD_S) & 1;
1065 +       } else {
1066 +               if (port == RT305X_ESW_NUM_PORTS - 1)
1067 +                       poa >>= 1;
1068 +               speed = (poa >> RT305X_ESW_SPD_S) & 3;
1069 +       }
1070 +       switch (speed) {
1071 +       case 0:
1072 +               link->speed = SWITCH_PORT_SPEED_10;
1073 +               break;
1074 +       case 1:
1075 +               link->speed = SWITCH_PORT_SPEED_100;
1076 +               break;
1077 +       case 2:
1078 +       case 3: /* forced gige speed can be 2 or 3 */
1079 +               link->speed = SWITCH_PORT_SPEED_1000;
1080 +               break;
1081 +       default:
1082 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1083 +               break;
1084 +       }
1085 +
1086 +       return 0;
1087 +}
1088 +
1089 +static int esw_get_port_bool(struct switch_dev *dev,
1090 +                        const struct switch_attr *attr,
1091 +                        struct switch_val *val)
1092 +{
1093 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1094 +       int idx = val->port_vlan;
1095 +       u32 x, reg, shift;
1096 +
1097 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1098 +               return -EINVAL;
1099 +
1100 +       switch (attr->id) {
1101 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1102 +               reg = RT305X_ESW_REG_POC0;
1103 +               shift = RT305X_ESW_POC0_DIS_PORT_S;
1104 +               break;
1105 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1106 +               reg = RT305X_ESW_REG_SGC2;
1107 +               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1108 +               break;
1109 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1110 +               reg = RT305X_ESW_REG_POC2;
1111 +               shift = RT305X_ESW_POC2_UNTAG_EN_S;
1112 +               break;
1113 +       case RT305X_ESW_ATTR_PORT_LAN:
1114 +               reg = RT305X_ESW_REG_SGC2;
1115 +               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1116 +               if (idx >= RT305X_ESW_NUM_LANWAN)
1117 +                       return -EINVAL;
1118 +               break;
1119 +       default:
1120 +               return -EINVAL;
1121 +       }
1122 +
1123 +       x = esw_r32(esw, reg);
1124 +       val->value.i = (x >> (idx + shift)) & 1;
1125 +
1126 +       return 0;
1127 +}
1128 +
1129 +static int esw_set_port_bool(struct switch_dev *dev,
1130 +                        const struct switch_attr *attr,
1131 +                        struct switch_val *val)
1132 +{
1133 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1134 +       int idx = val->port_vlan;
1135 +
1136 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1137 +           val->value.i < 0 || val->value.i > 1)
1138 +               return -EINVAL;
1139 +
1140 +       switch (attr->id) {
1141 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1142 +               esw->ports[idx].disable = val->value.i;
1143 +               break;
1144 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1145 +               esw->ports[idx].doubletag = val->value.i;
1146 +               break;
1147 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1148 +               esw->ports[idx].untag = val->value.i;
1149 +               break;
1150 +       default:
1151 +               return -EINVAL;
1152 +       }
1153 +
1154 +       return 0;
1155 +}
1156 +
1157 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1158 +                                const struct switch_attr *attr,
1159 +                                struct switch_val *val)
1160 +{
1161 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1162 +       int idx = val->port_vlan;
1163 +       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1164 +       u32 reg;
1165 +
1166 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1167 +               return -EINVAL;
1168 +       reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1169 +       val->value.i = (reg >> shift) & 0xffff;
1170 +
1171 +       return 0;
1172 +}
1173 +
1174 +static int
1175 +esw_get_port_tr_badgood(struct switch_dev *dev,
1176 +                                const struct switch_attr *attr,
1177 +                                struct switch_val *val)
1178 +{
1179 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1180 +
1181 +       int idx = val->port_vlan;
1182 +       int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1183 +       u32 reg;
1184 +
1185 +       if (!soc_is_rt5350())
1186 +               return -EINVAL;
1187 +
1188 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1189 +               return -EINVAL;
1190 +
1191 +       reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1192 +       val->value.i = (reg >> shift) & 0xffff;
1193 +
1194 +       return 0;
1195 +}
1196 +
1197 +static int esw_get_port_led(struct switch_dev *dev,
1198 +                       const struct switch_attr *attr,
1199 +                       struct switch_val *val)
1200 +{
1201 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1202 +       int idx = val->port_vlan;
1203 +
1204 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1205 +           idx >= RT305X_ESW_NUM_LEDS)
1206 +               return -EINVAL;
1207 +
1208 +       val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1209 +
1210 +       return 0;
1211 +}
1212 +
1213 +static int esw_set_port_led(struct switch_dev *dev,
1214 +                       const struct switch_attr *attr,
1215 +                       struct switch_val *val)
1216 +{
1217 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1218 +       int idx = val->port_vlan;
1219 +
1220 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1221 +               return -EINVAL;
1222 +
1223 +       esw->ports[idx].led = val->value.i;
1224 +
1225 +       return 0;
1226 +}
1227 +
1228 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1229 +{
1230 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1231 +
1232 +       if (port >= RT305X_ESW_NUM_PORTS)
1233 +               return -EINVAL;
1234 +
1235 +       *val = esw_get_pvid(esw, port);
1236 +
1237 +       return 0;
1238 +}
1239 +
1240 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1241 +{
1242 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1243 +
1244 +       if (port >= RT305X_ESW_NUM_PORTS)
1245 +               return -EINVAL;
1246 +
1247 +       esw->ports[port].pvid = val;
1248 +
1249 +       return 0;
1250 +}
1251 +
1252 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1253 +{
1254 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1255 +       u32 vmsc, poc2;
1256 +       int vlan_idx = -1;
1257 +       int i;
1258 +
1259 +       val->len = 0;
1260 +
1261 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1262 +               return -EINVAL;
1263 +
1264 +       /* valid vlan? */
1265 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1266 +               if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1267 +                   esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1268 +                       vlan_idx = i;
1269 +                       break;
1270 +               }
1271 +       }
1272 +
1273 +       if (vlan_idx == -1)
1274 +               return -EINVAL;
1275 +
1276 +       vmsc = esw_get_vmsc(esw, vlan_idx);
1277 +       poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1278 +
1279 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1280 +               struct switch_port *p;
1281 +               int port_mask = 1 << i;
1282 +
1283 +               if (!(vmsc & port_mask))
1284 +                       continue;
1285 +
1286 +               p = &val->value.ports[val->len++];
1287 +               p->id = i;
1288 +               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1289 +                       p->flags = 0;
1290 +               else
1291 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1292 +       }
1293 +
1294 +       return 0;
1295 +}
1296 +
1297 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1298 +{
1299 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1300 +       int ports;
1301 +       int vlan_idx = -1;
1302 +       int i;
1303 +
1304 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1305 +           val->len > RT305X_ESW_NUM_PORTS)
1306 +               return -EINVAL;
1307 +
1308 +       /* one of the already defined vlans? */
1309 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1310 +               if (esw->vlans[i].vid == val->port_vlan &&
1311 +                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1312 +                       vlan_idx = i;
1313 +                       break;
1314 +               }
1315 +       }
1316 +
1317 +       /* select a free slot */
1318 +       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1319 +               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1320 +                       vlan_idx = i;
1321 +       }
1322 +
1323 +       /* bail if all slots are in use */
1324 +       if (vlan_idx == -1)
1325 +               return -EINVAL;
1326 +
1327 +       ports = RT305X_ESW_PORTS_NONE;
1328 +       for (i = 0; i < val->len; i++) {
1329 +               struct switch_port *p = &val->value.ports[i];
1330 +               int port_mask = 1 << p->id;
1331 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1332 +
1333 +               if (p->id >= RT305X_ESW_NUM_PORTS)
1334 +                       return -EINVAL;
1335 +
1336 +               ports |= port_mask;
1337 +               esw->ports[p->id].untag = untagged;
1338 +       }
1339 +       esw->vlans[vlan_idx].ports = ports;
1340 +       if (ports == RT305X_ESW_PORTS_NONE)
1341 +               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1342 +       else
1343 +               esw->vlans[vlan_idx].vid = val->port_vlan;
1344 +
1345 +       return 0;
1346 +}
1347 +
1348 +static const struct switch_attr esw_global[] = {
1349 +       {
1350 +               .type = SWITCH_TYPE_INT,
1351 +               .name = "enable_vlan",
1352 +               .description = "VLAN mode (1:enabled)",
1353 +               .max = 1,
1354 +               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1355 +               .get = esw_get_vlan_enable,
1356 +               .set = esw_set_vlan_enable,
1357 +       },
1358 +       {
1359 +               .type = SWITCH_TYPE_INT,
1360 +               .name = "alternate_vlan_disable",
1361 +               .description = "Use en_vlan instead of doubletag to disable"
1362 +                               " VLAN mode",
1363 +               .max = 1,
1364 +               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1365 +               .get = esw_get_alt_vlan_disable,
1366 +               .set = esw_set_alt_vlan_disable,
1367 +       },
1368 +       {
1369 +               .type = SWITCH_TYPE_INT,
1370 +               .name = "bc_storm_protect",
1371 +               .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1372 +               .max = 3,
1373 +               .id = RT305X_ESW_ATTR_BC_STATUS,
1374 +               .get = rt305x_esw_get_bc_status,
1375 +               .set = rt305x_esw_set_bc_status,
1376 +       },
1377 +       {
1378 +               .type = SWITCH_TYPE_INT,
1379 +               .name = "led_frequency",
1380 +               .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1381 +               .max = 3,
1382 +               .id = RT305X_ESW_ATTR_LED_FREQ,
1383 +               .get = rt305x_esw_get_led_freq,
1384 +               .set = rt305x_esw_set_led_freq,
1385 +       }
1386 +};
1387 +
1388 +static const struct switch_attr esw_port[] = {
1389 +       {
1390 +               .type = SWITCH_TYPE_INT,
1391 +               .name = "disable",
1392 +               .description = "Port state (1:disabled)",
1393 +               .max = 1,
1394 +               .id = RT305X_ESW_ATTR_PORT_DISABLE,
1395 +               .get = esw_get_port_bool,
1396 +               .set = esw_set_port_bool,
1397 +       },
1398 +       {
1399 +               .type = SWITCH_TYPE_INT,
1400 +               .name = "doubletag",
1401 +               .description = "Double tagging for incoming vlan packets "
1402 +                               "(1:enabled)",
1403 +               .max = 1,
1404 +               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1405 +               .get = esw_get_port_bool,
1406 +               .set = esw_set_port_bool,
1407 +       },
1408 +       {
1409 +               .type = SWITCH_TYPE_INT,
1410 +               .name = "untag",
1411 +               .description = "Untag (1:strip outgoing vlan tag)",
1412 +               .max = 1,
1413 +               .id = RT305X_ESW_ATTR_PORT_UNTAG,
1414 +               .get = esw_get_port_bool,
1415 +               .set = esw_set_port_bool,
1416 +       },
1417 +       {
1418 +               .type = SWITCH_TYPE_INT,
1419 +               .name = "led",
1420 +               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1421 +                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1422 +                               " 8:100mact, 10:blink, 11:off, 12:on)",
1423 +               .max = 15,
1424 +               .id = RT305X_ESW_ATTR_PORT_LED,
1425 +               .get = esw_get_port_led,
1426 +               .set = esw_set_port_led,
1427 +       },
1428 +       {
1429 +               .type = SWITCH_TYPE_INT,
1430 +               .name = "lan",
1431 +               .description = "HW port group (0:wan, 1:lan)",
1432 +               .max = 1,
1433 +               .id = RT305X_ESW_ATTR_PORT_LAN,
1434 +               .get = esw_get_port_bool,
1435 +       },
1436 +       {
1437 +               .type = SWITCH_TYPE_INT,
1438 +               .name = "recv_bad",
1439 +               .description = "Receive bad packet counter",
1440 +               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1441 +               .get = esw_get_port_recv_badgood,
1442 +       },
1443 +       {
1444 +               .type = SWITCH_TYPE_INT,
1445 +               .name = "recv_good",
1446 +               .description = "Receive good packet counter",
1447 +               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1448 +               .get = esw_get_port_recv_badgood,
1449 +       },
1450 +       {
1451 +               .type = SWITCH_TYPE_INT,
1452 +               .name = "tr_bad",
1453 +
1454 +               .description = "Transmit bad packet counter. rt5350 only",
1455 +               .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1456 +               .get = esw_get_port_tr_badgood,
1457 +       },
1458 +       {
1459 +               .type = SWITCH_TYPE_INT,
1460 +               .name = "tr_good",
1461 +
1462 +               .description = "Transmit good packet counter. rt5350 only",
1463 +               .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1464 +               .get = esw_get_port_tr_badgood,
1465 +       },
1466 +};
1467 +
1468 +static const struct switch_attr esw_vlan[] = {
1469 +};
1470 +
1471 +static const struct switch_dev_ops esw_ops = {
1472 +       .attr_global = {
1473 +               .attr = esw_global,
1474 +               .n_attr = ARRAY_SIZE(esw_global),
1475 +       },
1476 +       .attr_port = {
1477 +               .attr = esw_port,
1478 +               .n_attr = ARRAY_SIZE(esw_port),
1479 +       },
1480 +       .attr_vlan = {
1481 +               .attr = esw_vlan,
1482 +               .n_attr = ARRAY_SIZE(esw_vlan),
1483 +       },
1484 +       .get_vlan_ports = esw_get_vlan_ports,
1485 +       .set_vlan_ports = esw_set_vlan_ports,
1486 +       .get_port_pvid = esw_get_port_pvid,
1487 +       .set_port_pvid = esw_set_port_pvid,
1488 +       .get_port_link = esw_get_port_link,
1489 +       .apply_config = esw_apply_config,
1490 +       .reset_switch = esw_reset_switch,
1491 +};
1492 +
1493 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1494 +       /* All ports are LAN ports. */
1495 +       .vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
1496 +       .reg_initval_fct2       = 0x00d6500c,
1497 +       /*
1498 +        * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1499 +        * turbo mii off, rgmi 3.3v off
1500 +        * port5: disabled
1501 +        * port6: enabled, gige, full-duplex, rx/tx-flow-control
1502 +        */
1503 +       .reg_initval_fpa2       = 0x3f502b28,
1504 +};
1505 +
1506 +static const struct of_device_id ralink_esw_match[] = {
1507 +       { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1508 +       {},
1509 +};
1510 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1511 +
1512 +static int esw_probe(struct platform_device *pdev)
1513 +{
1514 +       struct device_node *np = pdev->dev.of_node;
1515 +       const struct rt305x_esw_platform_data *pdata;
1516 +       const __be32 *port_map, *reg_init;
1517 +       struct rt305x_esw *esw;
1518 +       struct switch_dev *swdev;
1519 +       struct resource *res, *irq;
1520 +       int err;
1521 +
1522 +       pdata = pdev->dev.platform_data;
1523 +       if (!pdata) {
1524 +               const struct of_device_id *match;
1525 +               match = of_match_device(ralink_esw_match, &pdev->dev);
1526 +               if (match)
1527 +                       pdata = (struct rt305x_esw_platform_data *) match->data;
1528 +       }
1529 +       if (!pdata)
1530 +               return -EINVAL;
1531 +
1532 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1533 +       if (!res) {
1534 +               dev_err(&pdev->dev, "no memory resource found\n");
1535 +               return -ENOMEM;
1536 +       }
1537 +
1538 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1539 +       if (!irq) {
1540 +               dev_err(&pdev->dev, "no irq resource found\n");
1541 +               return -ENOMEM;
1542 +       }
1543 +
1544 +       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1545 +       if (!esw) {
1546 +               dev_err(&pdev->dev, "no memory for private data\n");
1547 +               return -ENOMEM;
1548 +       }
1549 +
1550 +       esw->dev = &pdev->dev;
1551 +       esw->irq = irq->start;
1552 +       esw->base = ioremap(res->start, resource_size(res));
1553 +       if (!esw->base) {
1554 +               dev_err(&pdev->dev, "ioremap failed\n");
1555 +               err = -ENOMEM;
1556 +               goto free_esw;
1557 +       }
1558 +
1559 +       port_map = of_get_property(np, "ralink,portmap", NULL);
1560 +        if (port_map)
1561 +               esw->port_map = be32_to_cpu(*port_map);
1562 +
1563 +       reg_init = of_get_property(np, "ralink,fct2", NULL);
1564 +        if (reg_init)
1565 +               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1566 +
1567 +       reg_init = of_get_property(np, "ralink,fpa2", NULL);
1568 +        if (reg_init)
1569 +               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1570 +
1571 +       reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1572 +        if (reg_init)
1573 +               esw->reg_led_polarity = be32_to_cpu(*reg_init);
1574 +
1575 +       swdev = &esw->swdev;
1576 +       swdev->of_node = pdev->dev.of_node;
1577 +       swdev->name = "rt305x-esw";
1578 +       swdev->alias = "rt305x";
1579 +       swdev->cpu_port = RT305X_ESW_PORT6;
1580 +       swdev->ports = RT305X_ESW_NUM_PORTS;
1581 +       swdev->vlans = RT305X_ESW_NUM_VIDS;
1582 +       swdev->ops = &esw_ops;
1583 +
1584 +       err = register_switch(swdev, NULL);
1585 +       if (err < 0) {
1586 +               dev_err(&pdev->dev, "register_switch failed\n");
1587 +               goto unmap_base;
1588 +       }
1589 +
1590 +       platform_set_drvdata(pdev, esw);
1591 +
1592 +       esw->pdata = pdata;
1593 +       spin_lock_init(&esw->reg_rw_lock);
1594 +
1595 +       esw_hw_init(esw);
1596 +
1597 +       esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1598 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1599 +       request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1600 +
1601 +       return 0;
1602 +
1603 +unmap_base:
1604 +       iounmap(esw->base);
1605 +free_esw:
1606 +       kfree(esw);
1607 +       return err;
1608 +}
1609 +
1610 +static int esw_remove(struct platform_device *pdev)
1611 +{
1612 +       struct rt305x_esw *esw;
1613 +
1614 +       esw = platform_get_drvdata(pdev);
1615 +       if (esw) {
1616 +               unregister_switch(&esw->swdev);
1617 +               platform_set_drvdata(pdev, NULL);
1618 +               iounmap(esw->base);
1619 +               kfree(esw);
1620 +       }
1621 +
1622 +       return 0;
1623 +}
1624 +
1625 +static struct platform_driver esw_driver = {
1626 +       .probe = esw_probe,
1627 +       .remove = esw_remove,
1628 +       .driver = {
1629 +               .name = "rt305x-esw",
1630 +               .owner = THIS_MODULE,
1631 +               .of_match_table = ralink_esw_match,
1632 +       },
1633 +};
1634 +
1635 +int __init rtesw_init(void)
1636 +{
1637 +       return platform_driver_register(&esw_driver);
1638 +}
1639 +
1640 +void rtesw_exit(void)
1641 +{
1642 +       platform_driver_unregister(&esw_driver);
1643 +}
1644 Index: linux-3.9.6/drivers/net/ethernet/ralink/esw_rt3052.h
1645 ===================================================================
1646 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1647 +++ linux-3.9.6/drivers/net/ethernet/ralink/esw_rt3052.h        2013-06-24 14:12:43.508180313 +0200
1648 @@ -0,0 +1,32 @@
1649 +/*
1650 + *   This program is free software; you can redistribute it and/or modify
1651 + *   it under the terms of the GNU General Public License as published by
1652 + *   the Free Software Foundation; version 2 of the License
1653 + *
1654 + *   This program is distributed in the hope that it will be useful,
1655 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1656 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1657 + *   GNU General Public License for more details.
1658 + *
1659 + *   You should have received a copy of the GNU General Public License
1660 + *   along with this program; if not, write to the Free Software
1661 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1662 + *
1663 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1664 + */
1665 +
1666 +#ifndef _RALINK_ESW_RT3052_H__
1667 +#define _RALINK_ESW_RT3052_H__
1668 +
1669 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1670 +
1671 +int __init rtesw_init(void);
1672 +void rtesw_exit(void);
1673 +
1674 +#else
1675 +
1676 +static inline int __init rtesw_init(void) { return 0; }
1677 +static inline void rtesw_exit(void) { }
1678 +
1679 +#endif
1680 +#endif
1681 Index: linux-3.9.6/drivers/net/ethernet/ralink/gsw_mt7620a.c
1682 ===================================================================
1683 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1684 +++ linux-3.9.6/drivers/net/ethernet/ralink/gsw_mt7620a.c       2013-06-24 14:12:43.508180313 +0200
1685 @@ -0,0 +1,1027 @@
1686 +/*
1687 + *   This program is free software; you can redistribute it and/or modify
1688 + *   it under the terms of the GNU General Public License as published by
1689 + *   the Free Software Foundation; version 2 of the License
1690 + *
1691 + *   This program is distributed in the hope that it will be useful,
1692 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1693 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1694 + *   GNU General Public License for more details.
1695 + *
1696 + *   You should have received a copy of the GNU General Public License
1697 + *   along with this program; if not, write to the Free Software
1698 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1699 + *
1700 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1701 + */
1702 +
1703 +#include <linux/module.h>
1704 +#include <linux/kernel.h>
1705 +#include <linux/types.h>
1706 +#include <linux/dma-mapping.h>
1707 +#include <linux/init.h>
1708 +#include <linux/skbuff.h>
1709 +#include <linux/etherdevice.h>
1710 +#include <linux/ethtool.h>
1711 +#include <linux/platform_device.h>
1712 +#include <linux/of_device.h>
1713 +#include <linux/clk.h>
1714 +#include <linux/of_net.h>
1715 +#include <linux/of_mdio.h>
1716 +#include <linux/of_irq.h>
1717 +#include <linux/of_address.h>
1718 +#include <linux/switch.h>
1719 +
1720 +#include <asm/mach-ralink/ralink_regs.h>
1721 +
1722 +#include "ralink_soc_eth.h"
1723 +
1724 +#include <linux/ioport.h>
1725 +#include <linux/switch.h>
1726 +#include <linux/mii.h>
1727 +
1728 +#include <ralink_regs.h>
1729 +#include <asm/mach-ralink/mt7620.h>
1730 +
1731 +#include "ralink_soc_eth.h"
1732 +#include "gsw_mt7620a.h"
1733 +#include "mdio.h"
1734 +
1735 +#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
1736 +
1737 +#define MT7620A_GSW_REG_PIAC   0x7004
1738 +
1739 +#define GSW_NUM_VLANS          16
1740 +#define GSW_NUM_VIDS           4096
1741 +#define GSW_NUM_PORTS          7
1742 +#define GSW_PORT6              6
1743 +
1744 +#define GSW_MDIO_ACCESS                BIT(31)
1745 +#define GSW_MDIO_READ          BIT(19)
1746 +#define GSW_MDIO_WRITE         BIT(18)
1747 +#define GSW_MDIO_START         BIT(16)
1748 +#define GSW_MDIO_ADDR_SHIFT    20
1749 +#define GSW_MDIO_REG_SHIFT     25
1750 +
1751 +#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
1752 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1753 +#define GSW_REG_SMACCR0                0x3fE4
1754 +#define GSW_REG_SMACCR1                0x3fE8
1755 +#define GSW_REG_CKGCR          0x3ff0
1756 +
1757 +#define GSW_REG_IMR            0x7008
1758 +#define GSW_REG_ISR            0x700c
1759 +
1760 +#define SYSC_REG_CFG1          0x14
1761 +
1762 +#define PORT_IRQ_ST_CHG                0x7f
1763 +
1764 +#define GSW_VLAN_VTCR          0x90
1765 +#define GSW_VLAN_VTCR_VID_M    0xfff
1766 +#define GSW_VLAN_ID(_x)                (0x100 + (4 * (_x)))
1767 +#define GSW_VLAN_ID_VID_S      12
1768 +#define GSW_VLAN_ID_VID_M      0xfff
1769 +
1770 +#define GSW_VAWD1              0x94
1771 +#define GSW_VAWD1_VTAG_EN      BIT(28)
1772 +#define GSW_VAWD1_PORTM_S      16
1773 +#define GSW_VAWD1_PORTM_M      0xff
1774 +
1775 +#define GSW_VAWD2              0x98
1776 +#define GSW_VAWD2_PORTT_S      16
1777 +#define GSW_VAWD2_PORTT_M      0xff
1778 +
1779 +#define GSW_VTIM(_x)           (0x100 + (4 * (_x)))
1780 +#define GSW_VTIM_M             0xfff
1781 +#define GSW_VTIM_S             12
1782 +
1783 +#define GSW_REG_PCR(x)         (0x2004 + (x * 0x100))
1784 +#define GSW_REG_PCR_EG_TAG_S   28
1785 +#define GSW_REG_PCR_EG_TAG_M   0x3
1786 +
1787 +#define SYSCFG1                        0x14
1788 +
1789 +#define ESW_PHY_POLLING                0x7000
1790 +
1791 +#define        PMCR_IPG                BIT(18)
1792 +#define        PMCR_MAC_MODE           BIT(16)
1793 +#define        PMCR_FORCE              BIT(15)
1794 +#define        PMCR_TX_EN              BIT(14)
1795 +#define        PMCR_RX_EN              BIT(13)
1796 +#define        PMCR_BACKOFF            BIT(9)
1797 +#define        PMCR_BACKPRES           BIT(8)
1798 +#define        PMCR_RX_FC              BIT(5)
1799 +#define        PMCR_TX_FC              BIT(4)
1800 +#define        PMCR_SPEED(_x)          (_x << 2)
1801 +#define        PMCR_DUPLEX             BIT(1)
1802 +#define        PMCR_LINK               BIT(0)
1803 +
1804 +#define PHY_AN_EN              BIT(31)
1805 +#define PHY_PRE_EN             BIT(30)
1806 +#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
1807 +
1808 +enum {
1809 +       /* Global attributes. */
1810 +       GSW_ATTR_ENABLE_VLAN,
1811 +       /* Port attributes. */
1812 +       GSW_ATTR_PORT_UNTAG,
1813 +};
1814 +
1815 +enum {
1816 +       PORT4_EPHY = 0,
1817 +       PORT4_EXT,
1818 +};
1819 +
1820 +struct gsw_port {
1821 +       bool    disable;
1822 +       bool    untag;
1823 +       u16     pvid;
1824 +};
1825 +
1826 +struct gsw_vlan {
1827 +       u8      ports;
1828 +       u16     vid;
1829 +};
1830 +
1831 +struct mt7620_gsw {
1832 +       struct device           *dev;
1833 +       void __iomem            *base;
1834 +       int                     irq;
1835 +
1836 +       struct switch_dev       swdev;
1837 +       bool                    global_vlan_enable;
1838 +       struct gsw_vlan         vlans[GSW_NUM_VLANS];
1839 +       struct gsw_port         ports[GSW_NUM_PORTS];
1840 +       long unsigned int       autopoll;
1841 +       int                     port4;
1842 +};
1843 +
1844 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1845 +{
1846 +       iowrite32(val, gsw->base + reg);
1847 +}
1848 +
1849 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1850 +{
1851 +       return ioread32(gsw->base + reg);
1852 +}
1853 +
1854 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1855 +{
1856 +       unsigned long t_start = jiffies;
1857 +
1858 +       while (1) {
1859 +               if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1860 +                       return 0;
1861 +               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1862 +                       break;
1863 +               }
1864 +       }
1865 +
1866 +       printk(KERN_ERR "mdio: MDIO timeout\n");
1867 +       return -1;
1868 +}
1869 +
1870 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1871 +                               u32 write_data)
1872 +{
1873 +       if (mt7620_mii_busy_wait(gsw))
1874 +               return -1;
1875 +
1876 +       write_data &= 0xffff;
1877 +
1878 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1879 +               (phy_register << GSW_MDIO_REG_SHIFT) |
1880 +               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1881 +               MT7620A_GSW_REG_PIAC);
1882 +
1883 +       if (mt7620_mii_busy_wait(gsw))
1884 +               return -1;
1885 +
1886 +       return 0;
1887 +}
1888 +
1889 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1890 +{
1891 +       struct fe_priv *priv = bus->priv;
1892 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1893 +
1894 +       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1895 +}
1896 +
1897 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1898 +{
1899 +       struct fe_priv *priv = bus->priv;
1900 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1901 +       u32 d;
1902 +
1903 +       if (mt7620_mii_busy_wait(gsw))
1904 +               return 0xffff;
1905 +
1906 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1907 +               (phy_reg << GSW_MDIO_REG_SHIFT) |
1908 +               (phy_addr << GSW_MDIO_ADDR_SHIFT),
1909 +               MT7620A_GSW_REG_PIAC);
1910 +
1911 +       if (mt7620_mii_busy_wait(gsw))
1912 +               return 0xffff;
1913 +
1914 +       d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1915 +
1916 +       return d;
1917 +}
1918 +
1919 +static unsigned char *fe_speed_str(int speed)
1920 +{
1921 +       switch (speed) {
1922 +       case 2:
1923 +       case SPEED_1000:
1924 +               return "1000";
1925 +       case 1:
1926 +       case SPEED_100:
1927 +               return "100";
1928 +       case 0:
1929 +       case SPEED_10:
1930 +               return "10";
1931 +       }
1932 +
1933 +       return "? ";
1934 +}
1935 +
1936 +int mt7620a_has_carrier(struct fe_priv *priv)
1937 +{
1938 +        struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1939 +       int i;
1940 +
1941 +       for (i = 0; i < GSW_PORT6; i++)
1942 +               if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1943 +                       return 1;
1944 +       return 0;
1945 +}
1946 +
1947 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1948 +{
1949 +       if (!priv->phy)
1950 +               return;
1951 +
1952 +       if (mt7620a_has_carrier(priv))
1953 +               netif_carrier_on(priv->netdev);
1954 +       else
1955 +               netif_carrier_off(priv->netdev);
1956 +}
1957 +
1958 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1959 +{
1960 +       if (priv->link[port])
1961 +               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1962 +                       port, fe_speed_str(priv->phy->speed[port]),
1963 +                       (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1964 +       else
1965 +               netdev_info(priv->netdev, "port %d link down\n", port);
1966 +       mt7620a_handle_carrier(priv);
1967 +}
1968 +
1969 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1970 +{
1971 +       struct fe_priv *priv = (struct fe_priv *) _priv;
1972 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1973 +       u32 status;
1974 +       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1975 +
1976 +       status = gsw_r32(gsw, GSW_REG_ISR);
1977 +       if (status & PORT_IRQ_ST_CHG)
1978 +               for (i = 0; i <= max; i++) {
1979 +                       u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1980 +                       int link = status & 0x1;
1981 +
1982 +                       if (link != priv->link[i]) {
1983 +                               if (link)
1984 +                                       netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1985 +                                                       i, fe_speed_str((status >> 2) & 3),
1986 +                                                       (status & 0x2) ? "Full" : "Half");
1987 +                               else
1988 +                                       netdev_info(priv->netdev, "port %d link down\n", i);
1989 +                       }
1990 +
1991 +                       priv->link[i] = link;
1992 +               }
1993 +       mt7620a_handle_carrier(priv);
1994 +
1995 +       gsw_w32(gsw, status, GSW_REG_ISR);
1996 +
1997 +       return IRQ_HANDLED;
1998 +}
1999 +
2000 +static int mt7620_is_bga(void)
2001 +{
2002 +       u32 bga = rt_sysc_r32(0x0c);
2003 +
2004 +       return (bga >> 16) & 1;
2005 +}
2006 +
2007 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
2008 +{
2009 +       int phy;
2010 +       int lsb = -1, msb = 0;
2011 +
2012 +       for_each_set_bit(phy, &gsw->autopoll, 32) {
2013 +               if (lsb < 0)
2014 +                       lsb = phy;
2015 +               msb = phy;
2016 +       }
2017 +
2018 +       gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
2019 +}
2020 +
2021 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
2022 +{
2023 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2024 +       const __be32 *_id = of_get_property(np, "reg", NULL);
2025 +       int phy_mode, size, id;
2026 +       int shift = 12;
2027 +       u32 val, mask = 0;
2028 +       int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2029 +
2030 +       if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2031 +               if (_id)
2032 +                       pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2033 +               else
2034 +                       pr_err("%s: invalid port id\n", np->name);
2035 +               return;
2036 +       }
2037 +
2038 +       id = be32_to_cpu(*_id);
2039 +
2040 +       if (id == 4)
2041 +               shift = 14;
2042 +
2043 +       priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2044 +       if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2045 +               pr_err("%s: invalid fixed link property\n", np->name);
2046 +               priv->phy->phy_fixed[id] = NULL;
2047 +               return;
2048 +       }
2049 +
2050 +       phy_mode = of_get_phy_mode(np);
2051 +       switch (phy_mode) {
2052 +       case PHY_INTERFACE_MODE_RGMII:
2053 +               mask = 0;
2054 +               break;
2055 +       case PHY_INTERFACE_MODE_MII:
2056 +               mask = 1;
2057 +               break;
2058 +       case PHY_INTERFACE_MODE_RMII:
2059 +               mask = 2;
2060 +               break;
2061 +       default:
2062 +               dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[id]);
2063 +               return;
2064 +       }
2065 +
2066 +       priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2067 +       if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2068 +               return;
2069 +
2070 +       val = rt_sysc_r32(SYSCFG1);
2071 +       val &= ~(3 << shift);
2072 +       val |= mask << shift;
2073 +       rt_sysc_w32(val, SYSCFG1);
2074 +
2075 +       if (priv->phy->phy_fixed[id]) {
2076 +               const __be32 *link = priv->phy->phy_fixed[id];
2077 +               int tx_fc = be32_to_cpup(link++);
2078 +               int rx_fc = be32_to_cpup(link++);
2079 +               u32 val = 0;
2080 +
2081 +               priv->phy->speed[id] = be32_to_cpup(link++);
2082 +               priv->phy->duplex[id] = be32_to_cpup(link++);
2083 +               priv->link[id] = 1;
2084 +
2085 +               switch (priv->phy->speed[id]) {
2086 +               case SPEED_10:
2087 +                       val = 0;
2088 +                       break;
2089 +               case SPEED_100:
2090 +                       val = 1;
2091 +                       break;
2092 +               case SPEED_1000:
2093 +                       val = 2;
2094 +                       break;
2095 +               default:
2096 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2097 +                       priv->phy->phy_fixed[id] = 0;
2098 +                       return;
2099 +               }
2100 +               val = PMCR_SPEED(val);
2101 +               val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2102 +                       PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2103 +               if (tx_fc)
2104 +                       val |= PMCR_TX_FC;
2105 +               if (rx_fc)
2106 +                       val |= PMCR_RX_FC;
2107 +               if (priv->phy->duplex[id])
2108 +                       val |= PMCR_DUPLEX;
2109 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2110 +               dev_info(priv->device, "using fixed link parameters\n");
2111 +               return;
2112 +       }
2113 +
2114 +       if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2115 +               u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2116 +                       PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
2117 +
2118 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2119 +               fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2120 +               gsw->autopoll |= BIT(id);
2121 +               gsw_auto_poll(gsw);
2122 +               return;
2123 +       }
2124 +}
2125 +
2126 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2127 +{
2128 +       u32 is_BGA = mt7620_is_bga();
2129 +
2130 +       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2131 +       gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2132 +
2133 +       /*correct  PHY  setting L3.0 BGA*/
2134 +       _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2135 +
2136 +       _mt7620_mii_write(gsw, 1, 17, 0x7444);
2137 +       if (is_BGA)
2138 +               _mt7620_mii_write(gsw, 1, 19, 0x0114);
2139 +       else
2140 +               _mt7620_mii_write(gsw, 1, 19, 0x0117);
2141 +
2142 +       _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2143 +       _mt7620_mii_write(gsw, 1, 25, 0x6212);
2144 +       _mt7620_mii_write(gsw, 1, 26, 0x0777);
2145 +       _mt7620_mii_write(gsw, 1, 29, 0x4000);
2146 +       _mt7620_mii_write(gsw, 1, 28, 0xc077);
2147 +       _mt7620_mii_write(gsw, 1, 24, 0x0000);
2148 +
2149 +       _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2150 +       _mt7620_mii_write(gsw, 1, 17, 0x4838);
2151 +
2152 +       _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2153 +       if (is_BGA) {
2154 +               _mt7620_mii_write(gsw, 1, 21, 0x0515);
2155 +               _mt7620_mii_write(gsw, 1, 22, 0x0053);
2156 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2157 +               _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2158 +               _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2159 +               _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2160 +       } else {
2161 +               _mt7620_mii_write(gsw, 1, 21, 0x0517);
2162 +               _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2163 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2164 +               _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2165 +               _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2166 +               _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2167 +       }
2168 +       _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2169 +       _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2170 +
2171 +       _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2172 +       _mt7620_mii_write(gsw, 0, 30, 0xa000);
2173 +       _mt7620_mii_write(gsw, 1, 30, 0xa000);
2174 +       _mt7620_mii_write(gsw, 2, 30, 0xa000);
2175 +       _mt7620_mii_write(gsw, 3, 30, 0xa000);
2176 +
2177 +       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2178 +       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2179 +       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2180 +       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2181 +       _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2182 +       _mt7620_mii_write(gsw, 0, 16, 0x1111);
2183 +       _mt7620_mii_write(gsw, 1, 16, 0x1010);
2184 +       _mt7620_mii_write(gsw, 2, 16, 0x1515);
2185 +       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2186 +
2187 +       /* CPU Port6 Force Link 1G, FC ON */
2188 +       gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2189 +       /* Set Port6 CPU Port */
2190 +       gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2191 +
2192 +//     GSW_VAWD2
2193 +
2194 +       /* setup port 4 */
2195 +       if (gsw->port4 == PORT4_EPHY) {
2196 +               u32 val = rt_sysc_r32(SYSCFG1);
2197 +               val |= 3 << 14;
2198 +               rt_sysc_w32(val, SYSCFG1);
2199 +               _mt7620_mii_write(gsw, 4, 30, 0xa000);
2200 +               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2201 +               _mt7620_mii_write(gsw, 4, 16, 0x1313);
2202 +               pr_info("gsw: setting port4 to ephy mode\n");
2203 +       }
2204 +}
2205 +
2206 +static int gsw_reset_switch(struct switch_dev *dev)
2207 +{
2208 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2209 +
2210 +       gsw->global_vlan_enable = 0;
2211 +       memset(gsw->ports, 0, sizeof(gsw->ports));
2212 +       memset(gsw->vlans, 0, sizeof(gsw->vlans));
2213 +       gsw_hw_init(gsw);
2214 +
2215 +       return 0;
2216 +}
2217 +
2218 +static int gsw_get_vlan_enable(struct switch_dev *dev,
2219 +                          const struct switch_attr *attr,
2220 +                          struct switch_val *val)
2221 +{
2222 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2223 +
2224 +       val->value.i = gsw->global_vlan_enable;
2225 +
2226 +       return 0;
2227 +}
2228 +
2229 +static int gsw_set_vlan_enable(struct switch_dev *dev,
2230 +                          const struct switch_attr *attr,
2231 +                          struct switch_val *val)
2232 +{
2233 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2234 +
2235 +       gsw->global_vlan_enable = val->value.i != 0;
2236 +
2237 +       return 0;
2238 +}
2239 +
2240 +static unsigned gsw_get_pvid(struct mt7620_gsw *gsw, unsigned port)
2241 +{
2242 +       unsigned s, val;
2243 +
2244 +       s = GSW_VTIM_S * (port % 2);
2245 +       val = gsw_r32(gsw, GSW_VTIM(port / 2));
2246 +
2247 +       return (val >> s) & GSW_VTIM_M;
2248 +}
2249 +
2250 +static void gsw_set_pvid(struct mt7620_gsw *gsw, unsigned port, unsigned pvid)
2251 +{
2252 +       unsigned s, val;
2253 +
2254 +       s = GSW_VTIM_S * (port % 2);
2255 +       val = gsw_r32(gsw, GSW_VTIM(port / 2));
2256 +       val &= ~(GSW_VTIM_M << s);
2257 +       val |= (pvid && GSW_VTIM_M) << s;
2258 +       gsw_w32(gsw, val, GSW_VTIM(port / 2));
2259 +}
2260 +
2261 +static int gsw_get_port_bool(struct switch_dev *dev,
2262 +                        const struct switch_attr *attr,
2263 +                        struct switch_val *val)
2264 +{
2265 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2266 +       int idx = val->port_vlan;
2267 +
2268 +       if (idx < 0 || idx >= GSW_NUM_PORTS)
2269 +               return -EINVAL;
2270 +
2271 +       switch (attr->id) {
2272 +       case GSW_ATTR_PORT_UNTAG:
2273 +               return gsw->ports[idx].untag;
2274 +       }
2275 +
2276 +       return -EINVAL;
2277 +}
2278 +
2279 +static int gsw_get_port_pvid(struct switch_dev *dev, int port, int *val)
2280 +{
2281 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2282 +
2283 +       if (port >= GSW_NUM_PORTS)
2284 +               return -EINVAL;
2285 +
2286 +       *val = gsw_get_pvid(gsw, port);
2287 +
2288 +       return 0;
2289 +}
2290 +
2291 +static int gsw_set_port_pvid(struct switch_dev *dev, int port, int val)
2292 +{
2293 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2294 +
2295 +       if (port >= GSW_NUM_PORTS)
2296 +               return -EINVAL;
2297 +
2298 +       gsw->ports[port].pvid = val;
2299 +
2300 +       return 0;
2301 +}
2302 +
2303 +static void gsw_set_vtcr(struct switch_dev *dev, u32 vid)
2304 +{
2305 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2306 +       int retry = 1000;
2307 +
2308 +       gsw_w32(gsw, 0x80000000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2309 +       while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2310 +               ;
2311 +}
2312 +
2313 +static void gsw_apply_vtcr(struct switch_dev *dev, u32 vid)
2314 +{
2315 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2316 +       int retry = 1000;
2317 +
2318 +       gsw_w32(gsw, 0x80001000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2319 +       while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2320 +               ;
2321 +}
2322 +
2323 +static unsigned gsw_get_vlan_id(struct mt7620_gsw *gsw, unsigned vlan)
2324 +{
2325 +       unsigned s;
2326 +       unsigned val;
2327 +
2328 +       s = GSW_VLAN_ID_VID_S * (vlan % 2);
2329 +       val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2330 +       val = (val >> s) & GSW_VLAN_ID_VID_M;
2331 +
2332 +       return val;
2333 +}
2334 +
2335 +static void gsw_set_vlan_id(struct mt7620_gsw *gsw, unsigned vlan, unsigned vid)
2336 +{
2337 +       unsigned s;
2338 +       unsigned val;
2339 +
2340 +       s = GSW_VLAN_ID_VID_S * (vlan % 2);
2341 +       val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2342 +       val &= ~(GSW_VLAN_ID_VID_M << s);
2343 +       val |= (vid << s);
2344 +       gsw_w32(gsw, val, GSW_VLAN_ID(vlan / 2));
2345 +}
2346 +
2347 +static void gsw_vlan_tagging_enable(struct mt7620_gsw *gsw, unsigned vlan, unsigned enable)
2348 +{
2349 +       unsigned val;
2350 +
2351 +       val = gsw_r32(gsw, GSW_VAWD1);
2352 +       if (enable)
2353 +               val |= GSW_VAWD1_VTAG_EN;
2354 +       else
2355 +               val &= ~GSW_VAWD1_VTAG_EN;
2356 +       gsw_w32(gsw, val, GSW_VAWD1);
2357 +}
2358 +
2359 +static unsigned gsw_get_port_member(struct mt7620_gsw *gsw, unsigned vlan)
2360 +{
2361 +       unsigned val;
2362 +
2363 +       gsw_set_vtcr(&gsw->swdev, vlan);
2364 +
2365 +       val = gsw_r32(gsw, GSW_VAWD1);
2366 +       val = (val >> GSW_VAWD1_PORTM_S) & GSW_VAWD1_PORTM_M;
2367 +
2368 +       return val;
2369 +}
2370 +
2371 +static void gsw_set_port_member(struct mt7620_gsw *gsw, unsigned vlan, unsigned member)
2372 +{
2373 +       unsigned val;
2374 +
2375 +       val = gsw_r32(gsw, GSW_VAWD1);
2376 +       val = ~(GSW_VAWD1_PORTM_M << GSW_VAWD1_PORTM_S);
2377 +       val |= (member & GSW_VAWD1_PORTM_M) << GSW_VAWD1_PORTM_S;
2378 +        gsw_w32(gsw, val, GSW_VAWD1);
2379 +}
2380 +
2381 +static unsigned gsw_get_port_tag(struct mt7620_gsw *gsw, unsigned port)
2382 +{
2383 +       unsigned val;
2384 +
2385 +       val = gsw_r32(gsw, GSW_REG_PCR(port));
2386 +       val >>= GSW_REG_PCR_EG_TAG_S;
2387 +       val &= GSW_REG_PCR_EG_TAG_M;
2388 +
2389 +       return !!val;
2390 +}
2391 +
2392 +static void gsw_set_port_untag(struct mt7620_gsw *gsw, unsigned port, unsigned untag)
2393 +{
2394 +       unsigned val;
2395 +
2396 +       val = gsw_r32(gsw, GSW_REG_PCR(port));
2397 +       if (!untag)
2398 +               untag = 0x2;
2399 +       else
2400 +               untag = 0;
2401 +       val &= ~(GSW_REG_PCR_EG_TAG_M << GSW_REG_PCR_EG_TAG_S);
2402 +       val |= (untag & GSW_REG_PCR_EG_TAG_M) << GSW_REG_PCR_EG_TAG_S;
2403 +       gsw_w32(gsw, val, GSW_REG_PCR(port));
2404 +}
2405 +
2406 +static int gsw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2407 +{
2408 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2409 +       int vlan_idx = -1;
2410 +       u32 member;
2411 +       int i;
2412 +
2413 +       val->len = 0;
2414 +
2415 +       if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS)
2416 +               return -EINVAL;
2417 +
2418 +       /* valid vlan? */
2419 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2420 +               if (gsw_get_vlan_id(gsw, i) != val->port_vlan)
2421 +                       continue;
2422 +               member = gsw_get_port_member(gsw, i);
2423 +               vlan_idx = i;
2424 +               break;
2425 +       }
2426 +
2427 +       if (vlan_idx == -1)
2428 +               return -EINVAL;
2429 +
2430 +       for (i = 0; i < GSW_NUM_PORTS; i++) {
2431 +               struct switch_port *p;
2432 +               int port_mask = 1 << i;
2433 +
2434 +               if (!(member & port_mask))
2435 +                       continue;
2436 +
2437 +               p = &val->value.ports[val->len++];
2438 +               p->id = i;
2439 +               if (gsw_get_port_tag(gsw, i))
2440 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
2441 +               else
2442 +                       p->flags = 0;
2443 +       }
2444 +
2445 +       return 0;
2446 +}
2447 +
2448 +static int gsw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2449 +{
2450 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2451 +       int ports;
2452 +       int vlan_idx = -1;
2453 +       int i;
2454 +
2455 +       if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS ||
2456 +                       val->len > GSW_NUM_PORTS)
2457 +               return -EINVAL;
2458 +
2459 +       /* one of the already defined vlans? */
2460 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2461 +               if (gsw->vlans[i].vid == val->port_vlan &&
2462 +                   gsw->vlans[i].ports) {
2463 +                       vlan_idx = i;
2464 +                       break;
2465 +               }
2466 +       }
2467 +
2468 +       /* select a free slot */
2469 +       for (i = 0; vlan_idx == -1 && i < GSW_NUM_VLANS; i++) {
2470 +               if (!gsw->vlans[i].ports)
2471 +                       vlan_idx = i;
2472 +       }
2473 +
2474 +       /* bail if all slots are in use */
2475 +       if (vlan_idx == -1)
2476 +               return -EINVAL;
2477 +
2478 +       ports = 0;
2479 +       for (i = 0; i < val->len; i++) {
2480 +               struct switch_port *p = &val->value.ports[i];
2481 +               int port_mask = 1 << p->id;
2482 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
2483 +
2484 +               if (p->id >= GSW_NUM_PORTS)
2485 +                       return -EINVAL;
2486 +
2487 +               ports |= port_mask;
2488 +               gsw->ports[p->id].untag = untagged;
2489 +       }
2490 +       gsw->vlans[vlan_idx].ports = ports;
2491 +       if (!ports)
2492 +               gsw->vlans[vlan_idx].vid = 0xfff;
2493 +       else
2494 +               gsw->vlans[vlan_idx].vid = val->port_vlan;
2495 +
2496 +       return 0;
2497 +}
2498 +
2499 +static int gsw_apply_config(struct switch_dev *dev)
2500 +{
2501 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2502 +       int i;
2503 +
2504 +       for (i = 0; i < GSW_NUM_VLANS; i++) {
2505 +               gsw_set_vtcr(&gsw->swdev, i);
2506 +               if (gsw->global_vlan_enable) {
2507 +                       gsw_set_vlan_id(gsw, i, gsw->vlans[i].vid);
2508 +                       gsw_set_port_member(gsw, i, gsw->vlans[i].ports);
2509 +                       gsw_vlan_tagging_enable(gsw, i, 1);
2510 +               } else {
2511 +                       gsw_set_vlan_id(gsw, i, 0xfff);
2512 +                       gsw_set_port_member(gsw, i, 0);
2513 +                       gsw_vlan_tagging_enable(gsw, i, 0);
2514 +               }
2515 +               gsw_apply_vtcr(&gsw->swdev, i);
2516 +       }
2517 +
2518 +       for (i = 0; i < GSW_NUM_PORTS; i++) {
2519 +               if (gsw->global_vlan_enable) {
2520 +                       gsw_set_port_untag(gsw, i, !gsw->ports[i].untag);
2521 +                       gsw_set_pvid(gsw, i, gsw->ports[i].pvid);
2522 +               } else {
2523 +                       gsw_set_port_untag(gsw, i, 0);
2524 +                       gsw_set_pvid(gsw, i, 0);
2525 +               }
2526 +       }
2527 +
2528 +       if (!gsw->global_vlan_enable)
2529 +               gsw_set_vlan_id(gsw, 0, 0);
2530 +
2531 +       return 0;
2532 +}
2533 +
2534 +static int gsw_get_port_link(struct switch_dev *dev,
2535 +                        int port,
2536 +                        struct switch_port_link *link)
2537 +{
2538 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2539 +       u32 status;
2540 +
2541 +       if (port < 0 || port >= GSW_NUM_PORTS)
2542 +               return -EINVAL;
2543 +
2544 +       status = gsw_r32(gsw, GSW_REG_PORT_STATUS(port));
2545 +       link->link = status & 0x1;
2546 +       link->duplex = (status >> 1) & 1;
2547 +
2548 +       switch ((status >> 2) & 0x3) {
2549 +       case 0:
2550 +               link->speed = SWITCH_PORT_SPEED_10;
2551 +               break;
2552 +       case 1:
2553 +               link->speed = SWITCH_PORT_SPEED_100;
2554 +               break;
2555 +       case 2:
2556 +       case 3: // forced gige speed can be 2 or 3
2557 +               link->speed = SWITCH_PORT_SPEED_1000;
2558 +               break;
2559 +       }
2560 +
2561 +       return 0;
2562 +}
2563 +
2564 +static int gsw_set_port_bool(struct switch_dev *dev,
2565 +                        const struct switch_attr *attr,
2566 +                        struct switch_val *val)
2567 +{
2568 +       struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2569 +       int idx = val->port_vlan;
2570 +
2571 +       if (idx < 0 || idx >= GSW_NUM_PORTS ||
2572 +           val->value.i < 0 || val->value.i > 1)
2573 +               return -EINVAL;
2574 +
2575 +       switch (attr->id) {
2576 +       case GSW_ATTR_PORT_UNTAG:
2577 +               gsw->ports[idx].untag = val->value.i;
2578 +               break;
2579 +       default:
2580 +               return -EINVAL;
2581 +       }
2582 +
2583 +       return 0;
2584 +}
2585 +
2586 +static const struct switch_attr gsw_global[] = {
2587 +       {
2588 +               .type = SWITCH_TYPE_INT,
2589 +               .name = "enable_vlan",
2590 +               .description = "VLAN mode (1:enabled)",
2591 +               .max = 1,
2592 +               .id = GSW_ATTR_ENABLE_VLAN,
2593 +               .get = gsw_get_vlan_enable,
2594 +               .set = gsw_set_vlan_enable,
2595 +       },
2596 +};
2597 +
2598 +static const struct switch_attr gsw_port[] = {
2599 +       {
2600 +               .type = SWITCH_TYPE_INT,
2601 +               .name = "untag",
2602 +               .description = "Untag (1:strip outgoing vlan tag)",
2603 +               .max = 1,
2604 +               .id = GSW_ATTR_PORT_UNTAG,
2605 +               .get = gsw_get_port_bool,
2606 +               .set = gsw_set_port_bool,
2607 +       },
2608 +};
2609 +
2610 +static const struct switch_attr gsw_vlan[] = {
2611 +};
2612 +
2613 +static const struct switch_dev_ops gsw_ops = {
2614 +       .attr_global = {
2615 +               .attr = gsw_global,
2616 +               .n_attr = ARRAY_SIZE(gsw_global),
2617 +       },
2618 +       .attr_port = {
2619 +               .attr = gsw_port,
2620 +               .n_attr = ARRAY_SIZE(gsw_port),
2621 +       },
2622 +       .attr_vlan = {
2623 +               .attr = gsw_vlan,
2624 +               .n_attr = ARRAY_SIZE(gsw_vlan),
2625 +       },
2626 +       .get_vlan_ports = gsw_get_vlan_ports,
2627 +       .set_vlan_ports = gsw_set_vlan_ports,
2628 +       .get_port_pvid = gsw_get_port_pvid,
2629 +       .set_port_pvid = gsw_set_port_pvid,
2630 +       .get_port_link = gsw_get_port_link,
2631 +       .apply_config = gsw_apply_config,
2632 +       .reset_switch = gsw_reset_switch,
2633 +};
2634 +
2635 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2636 +{
2637 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2638 +       unsigned long flags;
2639 +
2640 +       spin_lock_irqsave(&priv->page_lock, flags);
2641 +       gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2642 +       gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2643 +               GSW_REG_SMACCR0);
2644 +       spin_unlock_irqrestore(&priv->page_lock, flags);
2645 +}
2646 +
2647 +static struct of_device_id gsw_match[] = {
2648 +       { .compatible = "ralink,mt7620a-gsw" },
2649 +       {}
2650 +};
2651 +
2652 +int mt7620_gsw_probe(struct fe_priv *priv)
2653 +{
2654 +       struct mt7620_gsw *gsw;
2655 +       struct device_node *np;
2656 +       struct switch_dev *swdev;
2657 +       const char *port4 = NULL;
2658 +
2659 +       np = of_find_matching_node(NULL, gsw_match);
2660 +       if (!np) {
2661 +               dev_err(priv->device, "no gsw node found\n");
2662 +               return -EINVAL;
2663 +       }
2664 +       np = of_node_get(np);
2665 +
2666 +       gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2667 +       if (!gsw) {
2668 +               dev_err(priv->device, "no gsw memory for private data\n");
2669 +               return -ENOMEM;
2670 +       }
2671 +
2672 +       gsw->irq = irq_of_parse_and_map(np, 0);
2673 +       if (!gsw->irq) {
2674 +               dev_err(priv->device, "no gsw irq resource found\n");
2675 +               return -ENOMEM;
2676 +       }
2677 +
2678 +       gsw->base = of_iomap(np, 0);
2679 +       if (!gsw->base) {
2680 +               dev_err(priv->device, "gsw ioremap failed\n");
2681 +       }
2682 +
2683 +       gsw->dev = priv->device;
2684 +       priv->soc->swpriv = gsw;
2685 +
2686 +       swdev = &gsw->swdev;
2687 +       swdev->of_node = np;
2688 +       swdev->name = "mt7620a-gsw";
2689 +       swdev->alias = "mt7620x";
2690 +       swdev->cpu_port = GSW_PORT6;
2691 +       swdev->ports = GSW_NUM_PORTS;
2692 +       swdev->vlans = GSW_NUM_VLANS;
2693 +       swdev->ops = &gsw_ops;
2694 +
2695 +       if (register_switch(swdev, NULL))
2696 +               dev_err(priv->device, "register_switch failed\n");
2697 +
2698 +       of_property_read_string(np, "ralink,port4", &port4);
2699 +       if (port4 && !strcmp(port4, "ephy"))
2700 +               gsw->port4 = PORT4_EPHY;
2701 +       else if (port4 && !strcmp(port4, "gmac"))
2702 +               gsw->port4 = PORT4_EXT;
2703 +       else
2704 +               WARN_ON(port4);
2705 +
2706 +       gsw_hw_init(gsw);
2707 +
2708 +       gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2709 +       request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2710 +
2711 +       return 0;
2712 +}
2713 Index: linux-3.9.6/drivers/net/ethernet/ralink/gsw_mt7620a.h
2714 ===================================================================
2715 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2716 +++ linux-3.9.6/drivers/net/ethernet/ralink/gsw_mt7620a.h       2013-06-24 14:12:43.508180313 +0200
2717 @@ -0,0 +1,29 @@
2718 +/*
2719 + *   This program is free software; you can redistribute it and/or modify
2720 + *   it under the terms of the GNU General Public License as published by
2721 + *   the Free Software Foundation; version 2 of the License
2722 + *
2723 + *   This program is distributed in the hope that it will be useful,
2724 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2725 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2726 + *   GNU General Public License for more details.
2727 + *
2728 + *   You should have received a copy of the GNU General Public License
2729 + *   along with this program; if not, write to the Free Software
2730 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2731 + *
2732 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2733 + */
2734 +
2735 +#ifndef _RALINK_GSW_MT7620_H__
2736 +#define _RALINK_GSW_MT7620_H__
2737 +
2738 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2739 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2740 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2741 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2742 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2743 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2744 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2745 +
2746 +#endif
2747 Index: linux-3.9.6/drivers/net/ethernet/ralink/mdio.c
2748 ===================================================================
2749 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2750 +++ linux-3.9.6/drivers/net/ethernet/ralink/mdio.c      2013-06-24 14:12:43.508180313 +0200
2751 @@ -0,0 +1,245 @@
2752 +/*
2753 + *   This program is free software; you can redistribute it and/or modify
2754 + *   it under the terms of the GNU General Public License as published by
2755 + *   the Free Software Foundation; version 2 of the License
2756 + *
2757 + *   This program is distributed in the hope that it will be useful,
2758 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2759 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2760 + *   GNU General Public License for more details.
2761 + *
2762 + *   You should have received a copy of the GNU General Public License
2763 + *   along with this program; if not, write to the Free Software
2764 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2765 + *
2766 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2767 + */
2768 +
2769 +#include <linux/module.h>
2770 +#include <linux/kernel.h>
2771 +#include <linux/types.h>
2772 +#include <linux/dma-mapping.h>
2773 +#include <linux/init.h>
2774 +#include <linux/skbuff.h>
2775 +#include <linux/etherdevice.h>
2776 +#include <linux/ethtool.h>
2777 +#include <linux/platform_device.h>
2778 +#include <linux/phy.h>
2779 +#include <linux/of_device.h>
2780 +#include <linux/clk.h>
2781 +#include <linux/of_net.h>
2782 +#include <linux/of_mdio.h>
2783 +
2784 +#include "ralink_soc_eth.h"
2785 +#include "mdio.h"
2786 +
2787 +static int fe_mdio_reset(struct mii_bus *bus)
2788 +{
2789 +       /* TODO */
2790 +       return 0;
2791 +}
2792 +
2793 +static void fe_phy_link_adjust(struct net_device *dev)
2794 +{
2795 +       struct fe_priv *priv = netdev_priv(dev);
2796 +       unsigned long flags;
2797 +       int i;
2798 +
2799 +       spin_lock_irqsave(&priv->phy->lock, flags);
2800 +       for (i = 0; i < 8; i++) {
2801 +               if (priv->phy->phy_node[i]) {
2802 +                       struct phy_device *phydev = priv->phy->phy[i];
2803 +                       int status_change = 0;
2804 +
2805 +                       if (phydev->link)
2806 +                               if (priv->phy->duplex[i] != phydev->duplex ||
2807 +                                               priv->phy->speed[i] != phydev->speed)
2808 +                                       status_change = 1;
2809 +
2810 +                       if (phydev->link != priv->link[i])
2811 +                               status_change = 1;
2812 +
2813 +                       switch (phydev->speed) {
2814 +                       case SPEED_1000:
2815 +                       case SPEED_100:
2816 +                       case SPEED_10:
2817 +                               priv->link[i] = phydev->link;
2818 +                               priv->phy->duplex[i] = phydev->duplex;
2819 +                               priv->phy->speed[i] = phydev->speed;
2820 +
2821 +                               if (status_change && priv->soc->mdio_adjust_link)
2822 +                                       priv->soc->mdio_adjust_link(priv, i);
2823 +                               break;
2824 +                       }
2825 +               }
2826 +       }
2827 +       spin_unlock_irqrestore(&priv->phy->lock, flags);
2828 +}
2829 +
2830 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2831 +{
2832 +       const __be32 *_port = NULL;
2833 +       struct phy_device *phydev;
2834 +       int phy_mode, port;
2835 +
2836 +       _port = of_get_property(phy_node, "reg", NULL);
2837 +
2838 +       if (!_port || (be32_to_cpu(*_port) >= 8)) {
2839 +               pr_err("%s: invalid port id\n", phy_node->name);
2840 +               return -EINVAL;
2841 +       }
2842 +       port = be32_to_cpu(*_port);
2843 +       phy_mode = of_get_phy_mode(phy_node);
2844 +       if (phy_mode < 0) {
2845 +               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2846 +               priv->phy->phy_node[port] = NULL;
2847 +               return -EINVAL;
2848 +       }
2849 +
2850 +       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2851 +                               0, phy_mode);
2852 +       if (IS_ERR(phydev)) {
2853 +               dev_err(priv->device, "could not connect to PHY\n");
2854 +               priv->phy->phy_node[port] = NULL;
2855 +               return PTR_ERR(phydev);
2856 +       }
2857 +
2858 +       phydev->supported &= PHY_GBIT_FEATURES;
2859 +       phydev->advertising = phydev->supported;
2860 +       phydev->no_auto_carrier_off = 1;
2861 +
2862 +       dev_info(priv->device,
2863 +                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2864 +                port, dev_name(&phydev->dev), phydev->phy_id,
2865 +                phydev->drv->name);
2866 +
2867 +       priv->phy->phy[port] = phydev;
2868 +       priv->link[port] = 0;
2869 +
2870 +       return 0;
2871 +}
2872 +
2873 +static int fe_phy_connect(struct fe_priv *priv)
2874 +{
2875 +       return 0;
2876 +}
2877 +
2878 +static void fe_phy_disconnect(struct fe_priv *priv)
2879 +{
2880 +       unsigned long flags;
2881 +       int i;
2882 +
2883 +       for (i = 0; i < 8; i++)
2884 +               if (priv->phy->phy_fixed[i]) {
2885 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2886 +                       priv->link[i] = 0;
2887 +                       if (priv->soc->mdio_adjust_link)
2888 +                               priv->soc->mdio_adjust_link(priv, i);
2889 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2890 +               } else if (priv->phy->phy[i]) {
2891 +                       phy_disconnect(priv->phy->phy[i]);
2892 +               }
2893 +}
2894 +
2895 +static void fe_phy_start(struct fe_priv *priv)
2896 +{
2897 +       unsigned long flags;
2898 +       int i;
2899 +
2900 +       for (i = 0; i < 8; i++) {
2901 +               if (priv->phy->phy_fixed[i]) {
2902 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2903 +                       priv->link[i] = 1;
2904 +                       if (priv->soc->mdio_adjust_link)
2905 +                               priv->soc->mdio_adjust_link(priv, i);
2906 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2907 +               } else if (priv->phy->phy[i]) {
2908 +                       phy_start(priv->phy->phy[i]);
2909 +               }
2910 +       }
2911 +}
2912 +
2913 +static void fe_phy_stop(struct fe_priv *priv)
2914 +{
2915 +       unsigned long flags;
2916 +       int i;
2917 +
2918 +       for (i = 0; i < 8; i++)
2919 +               if (priv->phy->phy_fixed[i]) {
2920 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2921 +                       priv->link[i] = 0;
2922 +                       if (priv->soc->mdio_adjust_link)
2923 +                               priv->soc->mdio_adjust_link(priv, i);
2924 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2925 +               } else if (priv->phy->phy[i]) {
2926 +                       phy_stop(priv->phy->phy[i]);
2927 +               }
2928 +}
2929 +
2930 +static struct fe_phy phy_ralink = {
2931 +       .connect = fe_phy_connect,
2932 +       .disconnect = fe_phy_disconnect,
2933 +       .start = fe_phy_start,
2934 +       .stop = fe_phy_stop,
2935 +};
2936 +
2937 +int fe_mdio_init(struct fe_priv *priv)
2938 +{
2939 +       struct device_node *mii_np;
2940 +       int err;
2941 +
2942 +       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2943 +               return 0;
2944 +