target/linux/ramips/patches-3.9/0150-PCI-MIPS-adds-rt3883-pci-support.patch

   1 From 9e3707ddded9895aa47e11b42125a94f04f8bd9d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 17:34:08 +0100
   4 Subject: [PATCH 150/164] PCI: MIPS: adds rt3883 pci support
   5
   6 Add support for the pcie found on the rt3883 SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/pci/Makefile     |    1 +
  11  arch/mips/pci/pci-rt3883.c |  640 ++++++++++++++++++++++++++++++++++++++++++++
  12  arch/mips/ralink/Kconfig   |    1 +
  13  3 files changed, 642 insertions(+)
  14  create mode 100644 arch/mips/pci/pci-rt3883.c
  15
  16 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
  17 index 77974ba..3cbfd9b 100644
  18 --- a/arch/mips/pci/Makefile
  19 +++ b/arch/mips/pci/Makefile
  20 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops-sni.o
  21  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  22  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  23  obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
  24 +obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  25  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  26  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
  27  obj-$(CONFIG_TANBAC_TB0287)    += fixup-tb0287.o
  28 diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
  29 new file mode 100644
  30 index 0000000..212c90b
  31 --- /dev/null
  32 +++ b/arch/mips/pci/pci-rt3883.c
  33 @@ -0,0 +1,640 @@
  34 +/*
  35 + *  Ralink RT3662/RT3883 SoC PCI support
  36 + *
  37 + *  Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  38 + *
  39 + *  Parts of this file are based on Ralink's 2.6.21 BSP
  40 + *
  41 + *  This program is free software; you can redistribute it and/or modify it
  42 + *  under the terms of the GNU General Public License version 2 as published
  43 + *  by the Free Software Foundation.
  44 + */
  45 +
  46 +#include <linux/types.h>
  47 +#include <linux/pci.h>
  48 +#include <linux/io.h>
  49 +#include <linux/init.h>
  50 +#include <linux/delay.h>
  51 +#include <linux/interrupt.h>
  52 +#include <linux/module.h>
  53 +#include <linux/of.h>
  54 +#include <linux/of_irq.h>
  55 +#include <linux/of_pci.h>
  56 +#include <linux/platform_device.h>
  57 +
  58 +#include <asm/mach-ralink/rt3883.h>
  59 +#include <asm/mach-ralink/ralink_regs.h>
  60 +
  61 +#define RT3883_MEMORY_BASE             0x00000000
  62 +#define RT3883_MEMORY_SIZE             0x02000000
  63 +
  64 +#define RT3883_PCI_REG_PCICFG          0x00
  65 +#define   RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
  66 +#define   RT3883_PCICFG_P2P_BR_DEVNUM_S 16
  67 +#define   RT3883_PCICFG_PCIRST         BIT(1)
  68 +#define RT3883_PCI_REG_PCIRAW          0x04
  69 +#define RT3883_PCI_REG_PCIINT          0x08
  70 +#define RT3883_PCI_REG_PCIENA          0x0c
  71 +
  72 +#define RT3883_PCI_REG_CFGADDR         0x20
  73 +#define RT3883_PCI_REG_CFGDATA         0x24
  74 +#define RT3883_PCI_REG_MEMBASE         0x28
  75 +#define RT3883_PCI_REG_IOBASE          0x2c
  76 +#define RT3883_PCI_REG_ARBCTL          0x80
  77 +
  78 +#define RT3883_PCI_REG_BASE(_x)                (0x1000 + (_x) * 0x1000)
  79 +#define RT3883_PCI_REG_BAR0SETUP(_x)   (RT3883_PCI_REG_BASE((_x)) + 0x10)
  80 +#define RT3883_PCI_REG_IMBASEBAR0(_x)  (RT3883_PCI_REG_BASE((_x)) + 0x18)
  81 +#define RT3883_PCI_REG_ID(_x)          (RT3883_PCI_REG_BASE((_x)) + 0x30)
  82 +#define RT3883_PCI_REG_CLASS(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x34)
  83 +#define RT3883_PCI_REG_SUBID(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x38)
  84 +#define RT3883_PCI_REG_STATUS(_x)      (RT3883_PCI_REG_BASE((_x)) + 0x50)
  85 +
  86 +#define RT3883_PCI_MODE_NONE   0
  87 +#define RT3883_PCI_MODE_PCI    BIT(0)
  88 +#define RT3883_PCI_MODE_PCIE   BIT(1)
  89 +#define RT3883_PCI_MODE_BOTH   (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
  90 +
  91 +#define RT3883_PCI_IRQ_COUNT   32
  92 +
  93 +#define RT3883_P2P_BR_DEVNUM   1
  94 +
  95 +struct rt3883_pci_controller {
  96 +       void __iomem *base;
  97 +       spinlock_t lock;
  98 +
  99 +       struct irq_domain *irq_domain;
 100 +
 101 +       struct pci_controller pci_controller;
 102 +       struct resource io_res;
 103 +       struct resource mem_res;
 104 +
 105 +       bool pcie_ready;
 106 +       unsigned char p2p_devnum;
 107 +};
 108 +
 109 +static inline struct rt3883_pci_controller *
 110 +pci_bus_to_rt3883_controller(struct pci_bus *bus)
 111 +{
 112 +       struct pci_controller *hose;
 113 +
 114 +       hose = (struct pci_controller *) bus->sysdata;
 115 +       return container_of(hose, struct rt3883_pci_controller, pci_controller);
 116 +}
 117 +
 118 +static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
 119 +                                unsigned reg)
 120 +{
 121 +       return ioread32(rpc->base + reg);
 122 +}
 123 +
 124 +static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
 125 +                                 u32 val, unsigned reg)
 126 +{
 127 +       iowrite32(val, rpc->base + reg);
 128 +}
 129 +
 130 +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 131 +                                        unsigned int func, unsigned int where)
 132 +{
 133 +       return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
 134 +               0x80000000);
 135 +}
 136 +
 137 +static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
 138 +                              unsigned bus, unsigned slot,
 139 +                              unsigned func, unsigned reg)
 140 +{
 141 +       unsigned long flags;
 142 +       u32 address;
 143 +       u32 ret;
 144 +
 145 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 146 +
 147 +       spin_lock_irqsave(&rpc->lock, flags);
 148 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 149 +       ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 150 +       spin_unlock_irqrestore(&rpc->lock, flags);
 151 +
 152 +       return ret;
 153 +}
 154 +
 155 +static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
 156 +                                unsigned bus, unsigned slot,
 157 +                                unsigned func, unsigned reg, u32 val)
 158 +{
 159 +       unsigned long flags;
 160 +       u32 address;
 161 +
 162 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 163 +
 164 +       spin_lock_irqsave(&rpc->lock, flags);
 165 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 166 +       rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
 167 +       spin_unlock_irqrestore(&rpc->lock, flags);
 168 +}
 169 +
 170 +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 171 +{
 172 +       struct rt3883_pci_controller *rpc;
 173 +       u32 pending;
 174 +
 175 +       rpc = irq_get_handler_data(irq);
 176 +
 177 +       pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
 178 +                 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 179 +
 180 +       if (!pending) {
 181 +               spurious_interrupt();
 182 +               return;
 183 +       }
 184 +
 185 +       while (pending) {
 186 +               unsigned bit = __ffs(pending);
 187 +
 188 +               irq = irq_find_mapping(rpc->irq_domain, bit);
 189 +               generic_handle_irq(irq);
 190 +
 191 +               pending &= ~BIT(bit);
 192 +       }
 193 +}
 194 +
 195 +static void rt3883_pci_irq_unmask(struct irq_data *d)
 196 +{
 197 +       struct rt3883_pci_controller *rpc;
 198 +       u32 t;
 199 +
 200 +       rpc = irq_data_get_irq_chip_data(d);
 201 +
 202 +       t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 203 +       rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 204 +       /* flush write */
 205 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 206 +}
 207 +
 208 +static void rt3883_pci_irq_mask(struct irq_data *d)
 209 +{
 210 +       struct rt3883_pci_controller *rpc;
 211 +       u32 t;
 212 +
 213 +       rpc = irq_data_get_irq_chip_data(d);
 214 +
 215 +       t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 216 +       rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 217 +       /* flush write */
 218 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 219 +}
 220 +
 221 +static struct irq_chip rt3883_pci_irq_chip = {
 222 +       .name           = "RT3883 PCI",
 223 +       .irq_mask       = rt3883_pci_irq_mask,
 224 +       .irq_unmask     = rt3883_pci_irq_unmask,
 225 +       .irq_mask_ack   = rt3883_pci_irq_mask,
 226 +};
 227 +
 228 +static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
 229 +                             irq_hw_number_t hw)
 230 +{
 231 +       irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
 232 +       irq_set_chip_data(irq, d->host_data);
 233 +
 234 +       return 0;
 235 +}
 236 +
 237 +static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
 238 +       .map = rt3883_pci_irq_map,
 239 +       .xlate = irq_domain_xlate_onecell,
 240 +};
 241 +
 242 +static int rt3883_pci_irq_init(struct device *dev,
 243 +                              struct rt3883_pci_controller *rpc)
 244 +{
 245 +       struct device_node *np = dev->of_node;
 246 +       struct device_node *intc_np;
 247 +       int irq;
 248 +       int err;
 249 +
 250 +       intc_np = of_get_child_by_name(np, "interrupt-controller");
 251 +       if (!intc_np) {
 252 +               dev_err(dev, "no %s child node found", "interrupt-controller");
 253 +               return -ENODEV;
 254 +       }
 255 +
 256 +       irq = irq_of_parse_and_map(intc_np, 0);
 257 +       if (irq == 0) {
 258 +               dev_err(dev, "%s has no IRQ", of_node_full_name(intc_np));
 259 +               err = -EINVAL;
 260 +               goto err_put_intc;
 261 +       }
 262 +
 263 +       /* disable all interrupts */
 264 +       rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
 265 +
 266 +       rpc->irq_domain =
 267 +               irq_domain_add_linear(intc_np, RT3883_PCI_IRQ_COUNT,
 268 +                                     &rt3883_pci_irq_domain_ops,
 269 +                                     rpc);
 270 +       if (!rpc->irq_domain) {
 271 +               dev_err(dev, "unable to add IRQ domain\n");
 272 +               err = -ENODEV;
 273 +               goto err_put_intc;
 274 +       }
 275 +
 276 +       irq_set_handler_data(irq, rpc);
 277 +       irq_set_chained_handler(irq, rt3883_pci_irq_handler);
 278 +
 279 +       return 0;
 280 +
 281 +err_put_intc:
 282 +       of_node_put(intc_np);
 283 +       return err;
 284 +}
 285 +
 286 +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 287 +                                 int where, int size, u32 *val)
 288 +{
 289 +       struct rt3883_pci_controller *rpc;
 290 +       unsigned long flags;
 291 +       u32 address;
 292 +       u32 data;
 293 +
 294 +       rpc = pci_bus_to_rt3883_controller(bus);
 295 +
 296 +       if (!rpc->pcie_ready && bus->number == 1)
 297 +               return PCIBIOS_DEVICE_NOT_FOUND;
 298 +
 299 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 300 +                                        PCI_FUNC(devfn), where);
 301 +
 302 +       spin_lock_irqsave(&rpc->lock, flags);
 303 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 304 +       data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 305 +       spin_unlock_irqrestore(&rpc->lock, flags);
 306 +
 307 +       switch (size) {
 308 +       case 1:
 309 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 310 +               break;
 311 +       case 2:
 312 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 313 +               break;
 314 +       case 4:
 315 +               *val = data;
 316 +               break;
 317 +       }
 318 +
 319 +       return PCIBIOS_SUCCESSFUL;
 320 +}
 321 +
 322 +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 323 +                                  int where, int size, u32 val)
 324 +{
 325 +       struct rt3883_pci_controller *rpc;
 326 +       unsigned long flags;
 327 +       u32 address;
 328 +       u32 data;
 329 +
 330 +       rpc = pci_bus_to_rt3883_controller(bus);
 331 +
 332 +       if (!rpc->pcie_ready && bus->number == 1)
 333 +               return PCIBIOS_DEVICE_NOT_FOUND;
 334 +
 335 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 336 +                                        PCI_FUNC(devfn), where);
 337 +
 338 +       spin_lock_irqsave(&rpc->lock, flags);
 339 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 340 +       data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 341 +
 342 +       switch (size) {
 343 +       case 1:
 344 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 345 +                      (val << ((where & 3) << 3));
 346 +               break;
 347 +       case 2:
 348 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 349 +                      (val << ((where & 3) << 3));
 350 +               break;
 351 +       case 4:
 352 +               data = val;
 353 +               break;
 354 +       }
 355 +
 356 +       rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
 357 +       spin_unlock_irqrestore(&rpc->lock, flags);
 358 +
 359 +       return PCIBIOS_SUCCESSFUL;
 360 +}
 361 +
 362 +static struct pci_ops rt3883_pci_ops = {
 363 +       .read   = rt3883_pci_config_read,
 364 +       .write  = rt3883_pci_config_write,
 365 +};
 366 +
 367 +static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
 368 +{
 369 +       u32 syscfg1;
 370 +       u32 rstctrl;
 371 +       u32 clkcfg1;
 372 +       u32 t;
 373 +
 374 +       rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 375 +       syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
 376 +       clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 377 +
 378 +       if (mode & RT3883_PCI_MODE_PCIE) {
 379 +               rstctrl |= RT3883_RSTCTRL_PCIE;
 380 +               rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 381 +
 382 +               /* setup PCI PAD drive mode */
 383 +               syscfg1 &= ~(0x30);
 384 +               syscfg1 |= (2 << 4);
 385 +               rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 386 +
 387 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 388 +               t &= ~BIT(31);
 389 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 390 +
 391 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 392 +               t &= 0x80ffffff;
 393 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 394 +
 395 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 396 +               t |= 0xa << 24;
 397 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 398 +
 399 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 400 +               t |= BIT(31);
 401 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 402 +
 403 +               msleep(50);
 404 +
 405 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 406 +               rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 407 +       }
 408 +
 409 +       syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
 410 +
 411 +       clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
 412 +
 413 +       if (mode & RT3883_PCI_MODE_PCI) {
 414 +               clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
 415 +               rstctrl &= ~RT3883_RSTCTRL_PCI;
 416 +       }
 417 +
 418 +       if (mode & RT3883_PCI_MODE_PCIE) {
 419 +               clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
 420 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 421 +       }
 422 +
 423 +       rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 424 +       rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 425 +       rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 426 +
 427 +       msleep(500);
 428 +
 429 +       /*
 430 +        * setup the device number of the P2P bridge
 431 +        * and de-assert the reset line
 432 +        */
 433 +       t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
 434 +       rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
 435 +
 436 +       /* flush write */
 437 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
 438 +       msleep(500);
 439 +
 440 +       if (mode & RT3883_PCI_MODE_PCIE) {
 441 +               msleep(500);
 442 +
 443 +               t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
 444 +
 445 +               rpc->pcie_ready = t & BIT(0);
 446 +
 447 +               if (!rpc->pcie_ready) {
 448 +                       /* reset the PCIe block */
 449 +                       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 450 +                       t |= RT3883_RSTCTRL_PCIE;
 451 +                       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 452 +                       t &= ~RT3883_RSTCTRL_PCIE;
 453 +                       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 454 +
 455 +                       /* turn off PCIe clock */
 456 +                       t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 457 +                       t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
 458 +                       rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
 459 +
 460 +                       t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 461 +                       t &= ~0xf000c080;
 462 +                       rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 463 +               }
 464 +       }
 465 +
 466 +       /* enable PCI arbiter */
 467 +       rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
 468 +}
 469 +
 470 +static inline void
 471 +rt3883_dump_pci_config(struct rt3883_pci_controller *rpc,
 472 +                      int bus, int slot)
 473 +{
 474 +       int i;
 475 +
 476 +       for (i = 0; i < 16; i++) {
 477 +               u32 val;
 478 +
 479 +               val = rt3883_pci_read_cfg32(rpc, bus, slot, 0, i << 2);
 480 +               pr_info("pci %02x:%02x.0 0x%02x = %08x\n",
 481 +                       bus, slot, i << 2, val);
 482 +       }
 483 +}
 484 +
 485 +static int rt3883_pci_probe(struct platform_device *pdev)
 486 +{
 487 +       struct rt3883_pci_controller *rpc;
 488 +       struct device *dev = &pdev->dev;
 489 +       struct device_node *np = dev->of_node;
 490 +       struct resource *res;
 491 +       struct device_node *child;
 492 +       u32 val;
 493 +       int err;
 494 +       int mode;
 495 +
 496 +       rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
 497 +       if (!rpc)
 498 +               return -ENOMEM;
 499 +
 500 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 501 +       if (!res)
 502 +               return -EINVAL;
 503 +
 504 +       rpc->base = devm_ioremap_resource(dev, res);
 505 +       if (IS_ERR(rpc->base))
 506 +               return PTR_ERR(rpc->base);
 507 +
 508 +       rpc->pci_controller.of_node = of_get_child_by_name(np, "host-bridge");
 509 +       if (!rpc->pci_controller.of_node) {
 510 +               dev_err(dev, "no %s child node found", "host-bridge");
 511 +               return -ENODEV;
 512 +       }
 513 +
 514 +       mode = RT3883_PCI_MODE_NONE;
 515 +       for_each_child_of_node(rpc->pci_controller.of_node, child) {
 516 +               u32 slot;
 517 +
 518 +               if (!of_device_is_available(child))
 519 +                       continue;
 520 +
 521 +               if (of_property_read_u32(child, "ralink,pci-slot",
 522 +                                        &slot)) {
 523 +                       dev_err(dev, "no '%s' property found for %s\n",
 524 +                               "ralink,pci-slot",
 525 +                               of_node_full_name(child));
 526 +                       continue;
 527 +               }
 528 +
 529 +               switch (slot) {
 530 +               case 1:
 531 +                       mode |= RT3883_PCI_MODE_PCIE;
 532 +                       break;
 533 +
 534 +               case 17:
 535 +               case 18:
 536 +                       mode |= RT3883_PCI_MODE_PCI;
 537 +                       break;
 538 +               }
 539 +       }
 540 +
 541 +       if (mode == RT3883_PCI_MODE_NONE) {
 542 +               dev_err(dev, "unable to determine PCI mode\n");
 543 +               err = -EINVAL;
 544 +               goto err_put_hb_node;
 545 +       }
 546 +
 547 +       dev_info(dev, "mode:%s%s\n",
 548 +                (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
 549 +                (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
 550 +
 551 +       rt3883_pci_preinit(rpc, mode);
 552 +
 553 +       rpc->pci_controller.pci_ops = &rt3883_pci_ops;
 554 +       rpc->pci_controller.io_resource = &rpc->io_res;
 555 +       rpc->pci_controller.mem_resource = &rpc->mem_res;
 556 +
 557 +       /* Load PCI I/O and memory resources from DT */
 558 +       pci_load_of_ranges(&rpc->pci_controller,
 559 +                          rpc->pci_controller.of_node);
 560 +
 561 +       rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
 562 +       rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
 563 +
 564 +       ioport_resource.start = rpc->io_res.start;
 565 +       ioport_resource.end = rpc->io_res.end;
 566 +
 567 +       /* PCI */
 568 +       rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
 569 +       rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
 570 +       rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
 571 +       rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
 572 +       rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
 573 +
 574 +       /* PCIe */
 575 +       rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
 576 +       rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
 577 +       rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
 578 +       rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
 579 +       rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
 580 +
 581 +       err = rt3883_pci_irq_init(dev, rpc);
 582 +       if (err)
 583 +               goto err_put_hb_node;
 584 +
 585 +       /* PCIe */
 586 +       val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
 587 +       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 588 +       rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
 589 +
 590 +       /* PCI */
 591 +       val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
 592 +       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 593 +       rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
 594 +
 595 +       if (mode == RT3883_PCI_MODE_PCIE) {
 596 +               rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
 597 +               rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
 598 +
 599 +               rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 600 +                                      PCI_BASE_ADDRESS_0,
 601 +                                      RT3883_MEMORY_BASE);
 602 +               /* flush write */
 603 +               rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 604 +                                     PCI_BASE_ADDRESS_0);
 605 +       } else {
 606 +               rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 607 +                                      PCI_IO_BASE, 0x00000101);
 608 +       }
 609 +
 610 +       register_pci_controller(&rpc->pci_controller);
 611 +
 612 +       return 0;
 613 +
 614 +err_put_hb_node:
 615 +       of_node_put(rpc->pci_controller.of_node);
 616 +       return err;
 617 +}
 618 +
 619 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 620 +{
 621 +       struct rt3883_pci_controller *rpc;
 622 +       struct of_irq dev_irq;
 623 +       int err;
 624 +       int irq;
 625 +
 626 +       rpc = pci_bus_to_rt3883_controller(dev->bus);
 627 +       err = of_irq_map_pci(dev, &dev_irq);
 628 +       if (err) {
 629 +               pr_err("pci %s: unable to get irq map, err=%d\n",
 630 +                      pci_name((struct pci_dev *) dev), err);
 631 +               return 0;
 632 +       }
 633 +
 634 +       irq = irq_create_of_mapping(dev_irq.controller,
 635 +                                   dev_irq.specifier,
 636 +                                   dev_irq.size);
 637 +
 638 +       if (irq == 0)
 639 +               pr_crit("pci %s: no irq found for pin %u\n",
 640 +                       pci_name((struct pci_dev *) dev), pin);
 641 +       else
 642 +               pr_info("pci %s: using irq %d for pin %u\n",
 643 +                       pci_name((struct pci_dev *) dev), irq, pin);
 644 +
 645 +       return irq;
 646 +}
 647 +
 648 +int pcibios_plat_dev_init(struct pci_dev *dev)
 649 +{
 650 +       return 0;
 651 +}
 652 +
 653 +static const struct of_device_id rt3883_pci_ids[] = {
 654 +       { .compatible = "ralink,rt3883-pci" },
 655 +       {},
 656 +};
 657 +MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
 658 +
 659 +static struct platform_driver rt3883_pci_driver = {
 660 +       .probe = rt3883_pci_probe,
 661 +       .driver = {
 662 +               .name = "rt3883-pci",
 663 +               .owner = THIS_MODULE,
 664 +               .of_match_table = of_match_ptr(rt3883_pci_ids),
 665 +       },
 666 +};
 667 +
 668 +static int __init rt3883_pci_init(void)
 669 +{
 670 +       return platform_driver_register(&rt3883_pci_driver);
 671 +}
 672 +
 673 +postcore_initcall(rt3883_pci_init);
 674 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
 675 index c0ac93a..2fbe93c 100644
 676 --- a/arch/mips/ralink/Kconfig
 677 +++ b/arch/mips/ralink/Kconfig
 678 @@ -21,6 +21,7 @@ choice
 679                 bool "RT3883"
 680                 select USB_ARCH_HAS_OHCI
 681                 select USB_ARCH_HAS_EHCI
 682 +               select HW_HAS_PCI
 683
 684         config SOC_MT7620
 685                 bool "MT7620"
 686 --
 687 1.7.10.4
 688