target/linux/ramips/patches-3.9/0126-MIPS-ralink-add-memory-definition-for-MT7620.patch

   1 From 0c6c7304e33f3decff3293739076f29314ce535e Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 14 Apr 2013 09:55:29 +0200
   4 Subject: [PATCH 126/164] MIPS: ralink: add memory definition for MT7620
   5
   6 Populate struct soc_info with the data that describes our RAM window.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 Patchwork: http://patchwork.linux-mips.org/patch/5183/
  10 ---
  11  arch/mips/include/asm/mach-ralink/mt7620.h |    8 ++++++++
  12  arch/mips/ralink/mt7620.c                  |   20 ++++++++++++++++++++
  13  2 files changed, 28 insertions(+)
  14
  15 diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
  16 index b272649..9809972 100644
  17 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
  18 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  19 @@ -50,6 +50,14 @@
  20  #define SYSCFG0_DRAM_TYPE_DDR1         1
  21  #define SYSCFG0_DRAM_TYPE_DDR2         2
  22
  23 +#define MT7620_DRAM_BASE               0x0
  24 +#define MT7620_SDRAM_SIZE_MIN          2
  25 +#define MT7620_SDRAM_SIZE_MAX          64
  26 +#define MT7620_DDR1_SIZE_MIN           32
  27 +#define MT7620_DDR1_SIZE_MAX           128
  28 +#define MT7620_DDR2_SIZE_MIN           32
  29 +#define MT7620_DDR2_SIZE_MAX           256
  30 +
  31  #define MT7620_GPIO_MODE_I2C           BIT(0)
  32  #define MT7620_GPIO_MODE_UART0_SHIFT   2
  33  #define MT7620_GPIO_MODE_UART0_MASK    0x7
  34 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
  35 index eb00ab8..98ddb93 100644
  36 --- a/arch/mips/ralink/mt7620.c
  37 +++ b/arch/mips/ralink/mt7620.c
  38 @@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
  39
  40         cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
  41         dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
  42 +
  43 +       switch (dram_type) {
  44 +       case SYSCFG0_DRAM_TYPE_SDRAM:
  45 +               soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
  46 +               soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
  47 +               break;
  48 +
  49 +       case SYSCFG0_DRAM_TYPE_DDR1:
  50 +               soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
  51 +               soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
  52 +               break;
  53 +
  54 +       case SYSCFG0_DRAM_TYPE_DDR2:
  55 +               soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
  56 +               soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
  57 +               break;
  58 +       default:
  59 +               BUG();
  60 +       }
  61 +       soc_info->mem_base = MT7620_DRAM_BASE;
  62  }
  63 --
  64 1.7.10.4
  65