target/linux/ramips/patches-3.8/0136-NET-MIPS-add-ralink-SoC-ethernet-driver.patch

   1 From 34fc7d26c01ba594be347aefcc31f55b36c06a72 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 22 Apr 2013 23:20:03 +0200
   4 Subject: [PATCH 136/137] NET: MIPS: add ralink SoC ethernet driver
   5
   6 Add support for Ralink FE and ESW.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
  11  arch/mips/ralink/rt305x.c                          |    1 +
  12  drivers/net/ethernet/Kconfig                       |    1 +
  13  drivers/net/ethernet/Makefile                      |    1 +
  14  drivers/net/ethernet/ramips/Kconfig                |   18 +
  15  drivers/net/ethernet/ramips/Makefile               |    9 +
  16  drivers/net/ethernet/ramips/ramips_debugfs.c       |  127 ++
  17  drivers/net/ethernet/ramips/ramips_esw.c           | 1221 +++++++++++++++++++
  18  drivers/net/ethernet/ramips/ramips_eth.h           |  375 ++++++
  19  drivers/net/ethernet/ramips/ramips_main.c          | 1281 ++++++++++++++++++++
  20  10 files changed, 3061 insertions(+)
  21  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  22  create mode 100644 drivers/net/ethernet/ramips/Kconfig
  23  create mode 100644 drivers/net/ethernet/ramips/Makefile
  24  create mode 100644 drivers/net/ethernet/ramips/ramips_debugfs.c
  25  create mode 100644 drivers/net/ethernet/ramips/ramips_esw.c
  26  create mode 100644 drivers/net/ethernet/ramips/ramips_eth.h
  27  create mode 100644 drivers/net/ethernet/ramips/ramips_main.c
  28
  29 Index: linux-3.8.11/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  30 ===================================================================
  31 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  32 +++ linux-3.8.11/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h        2013-05-06 12:43:38.148652601 +0200
  33 @@ -0,0 +1,27 @@
  34 +/*
  35 + *  Ralink RT305x SoC platform device registration
  36 + *
  37 + *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  38 + *
  39 + *  This program is free software; you can redistribute it and/or modify it
  40 + *  under the terms of the GNU General Public License version 2 as published
  41 + *  by the Free Software Foundation.
  42 + */
  43 +
  44 +#ifndef _RT305X_ESW_PLATFORM_H
  45 +#define _RT305X_ESW_PLATFORM_H
  46 +
  47 +enum {
  48 +       RT305X_ESW_VLAN_CONFIG_NONE = 0,
  49 +       RT305X_ESW_VLAN_CONFIG_LLLLW,
  50 +       RT305X_ESW_VLAN_CONFIG_WLLLL,
  51 +};
  52 +
  53 +struct rt305x_esw_platform_data
  54 +{
  55 +       u8 vlan_config;
  56 +       u32 reg_initval_fct2;
  57 +       u32 reg_initval_fpa2;
  58 +};
  59 +
  60 +#endif /* _RT305X_ESW_PLATFORM_H */
  61 Index: linux-3.8.11/arch/mips/ralink/rt305x.c
  62 ===================================================================
  63 --- linux-3.8.11.orig/arch/mips/ralink/rt305x.c 2013-05-06 12:43:38.016652594 +0200
  64 +++ linux-3.8.11/arch/mips/ralink/rt305x.c      2013-05-06 12:43:38.148652601 +0200
  65 @@ -221,6 +221,7 @@
  66         }
  67
  68         ralink_clk_add("cpu", cpu_rate);
  69 +       ralink_clk_add("sys", sys_rate);
  70         ralink_clk_add("10000b00.spi", sys_rate);
  71         ralink_clk_add("10000100.timer", wdt_rate);
  72         ralink_clk_add("10000120.watchdog", wdt_rate);
  73 Index: linux-3.8.11/drivers/net/ethernet/Kconfig
  74 ===================================================================
  75 --- linux-3.8.11.orig/drivers/net/ethernet/Kconfig      2013-05-01 18:56:10.000000000 +0200
  76 +++ linux-3.8.11/drivers/net/ethernet/Kconfig   2013-05-06 12:43:38.148652601 +0200
  77 @@ -136,6 +136,7 @@
  78  source "drivers/net/ethernet/pasemi/Kconfig"
  79  source "drivers/net/ethernet/qlogic/Kconfig"
  80  source "drivers/net/ethernet/racal/Kconfig"
  81 +source "drivers/net/ethernet/ramips/Kconfig"
  82  source "drivers/net/ethernet/realtek/Kconfig"
  83  source "drivers/net/ethernet/renesas/Kconfig"
  84  source "drivers/net/ethernet/rdc/Kconfig"
  85 Index: linux-3.8.11/drivers/net/ethernet/Makefile
  86 ===================================================================
  87 --- linux-3.8.11.orig/drivers/net/ethernet/Makefile     2013-05-01 18:56:10.000000000 +0200
  88 +++ linux-3.8.11/drivers/net/ethernet/Makefile  2013-05-06 12:43:38.148652601 +0200
  89 @@ -54,6 +54,7 @@
  90  obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
  91  obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
  92  obj-$(CONFIG_NET_VENDOR_RACAL) += racal/
  93 +obj-$(CONFIG_NET_RAMIPS) += ramips/
  94  obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
  95  obj-$(CONFIG_SH_ETH) += renesas/
  96  obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
  97 Index: linux-3.8.11/drivers/net/ethernet/ramips/Kconfig
  98 ===================================================================
  99 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 100 +++ linux-3.8.11/drivers/net/ethernet/ramips/Kconfig    2013-05-06 12:43:38.148652601 +0200
 101 @@ -0,0 +1,18 @@
 102 +config NET_RAMIPS
 103 +       tristate "Ralink RT288X/RT3X5X/RT3662/RT3883 ethernet driver"
 104 +       depends on RALINK
 105 +       select PHYLIB if (SOC_RT288X || SOC_RT3883)
 106 +       select SWCONFIG if SOC_RT305X
 107 +       help
 108 +         This driver supports the etehrnet mac inside the ralink wisocs
 109 +
 110 +if NET_RAMIPS
 111 +
 112 +config NET_RAMIPS_DEBUG
 113 +       bool "Enable debug messages in the Ralink ethernet driver"
 114 +
 115 +config NET_RAMIPS_DEBUG_FS
 116 +       bool "Enable debugfs support for the Ralink ethernet driver"
 117 +       depends on DEBUG_FS
 118 +
 119 +endif
 120 Index: linux-3.8.11/drivers/net/ethernet/ramips/Makefile
 121 ===================================================================
 122 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 123 +++ linux-3.8.11/drivers/net/ethernet/ramips/Makefile   2013-05-06 12:43:38.148652601 +0200
 124 @@ -0,0 +1,9 @@
 125 +#
 126 +# Makefile for the Ramips SoCs built-in ethernet macs
 127 +#
 128 +
 129 +ramips-y       += ramips_main.o
 130 +
 131 +ramips-$(CONFIG_NET_RAMIPS_DEBUG_FS)   += ramips_debugfs.o
 132 +
 133 +obj-$(CONFIG_NET_RAMIPS)       += ramips.o
 134 Index: linux-3.8.11/drivers/net/ethernet/ramips/ramips_debugfs.c
 135 ===================================================================
 136 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 137 +++ linux-3.8.11/drivers/net/ethernet/ramips/ramips_debugfs.c   2013-05-06 12:43:38.148652601 +0200
 138 @@ -0,0 +1,127 @@
 139 +/*
 140 + *  Ralink SoC ethernet driver debugfs code
 141 + *
 142 + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
 143 + *
 144 + *  This program is free software; you can redistribute it and/or modify it
 145 + *  under the terms of the GNU General Public License version 2 as published
 146 + *  by the Free Software Foundation.
 147 + */
 148 +
 149 +#include <linux/debugfs.h>
 150 +#include <linux/module.h>
 151 +#include <linux/phy.h>
 152 +
 153 +#include "ramips_eth.h"
 154 +
 155 +static struct dentry *raeth_debugfs_root;
 156 +
 157 +static int raeth_debugfs_generic_open(struct inode *inode, struct file *file)
 158 +{
 159 +       file->private_data = inode->i_private;
 160 +       return 0;
 161 +}
 162 +
 163 +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status)
 164 +{
 165 +       re->debug.int_stats.total += !!status;
 166 +
 167 +       re->debug.int_stats.rx_delayed += !!(status & RAMIPS_RX_DLY_INT);
 168 +       re->debug.int_stats.rx_done0 += !!(status & RAMIPS_RX_DONE_INT0);
 169 +       re->debug.int_stats.rx_coherent += !!(status & RAMIPS_RX_COHERENT);
 170 +
 171 +       re->debug.int_stats.tx_delayed += !!(status & RAMIPS_TX_DLY_INT);
 172 +       re->debug.int_stats.tx_done0 += !!(status & RAMIPS_TX_DONE_INT0);
 173 +       re->debug.int_stats.tx_done1 += !!(status & RAMIPS_TX_DONE_INT1);
 174 +       re->debug.int_stats.tx_done2 += !!(status & RAMIPS_TX_DONE_INT2);
 175 +       re->debug.int_stats.tx_done3 += !!(status & RAMIPS_TX_DONE_INT3);
 176 +       re->debug.int_stats.tx_coherent += !!(status & RAMIPS_TX_COHERENT);
 177 +
 178 +       re->debug.int_stats.pse_fq_empty += !!(status & RAMIPS_PSE_FQ_EMPTY);
 179 +       re->debug.int_stats.pse_p0_fc += !!(status & RAMIPS_PSE_P0_FC);
 180 +       re->debug.int_stats.pse_p1_fc += !!(status & RAMIPS_PSE_P1_FC);
 181 +       re->debug.int_stats.pse_p2_fc += !!(status & RAMIPS_PSE_P2_FC);
 182 +       re->debug.int_stats.pse_buf_drop += !!(status & RAMIPS_PSE_BUF_DROP);
 183 +}
 184 +
 185 +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
 186 +                                  size_t count, loff_t *ppos)
 187 +{
 188 +#define PR_INT_STAT(_label, _field)                                    \
 189 +       len += snprintf(buf + len, sizeof(buf) - len,                   \
 190 +               "%-18s: %10lu\n", _label, re->debug.int_stats._field);
 191 +
 192 +       struct raeth_priv *re = file->private_data;
 193 +       char buf[512];
 194 +       unsigned int len = 0;
 195 +       unsigned long flags;
 196 +
 197 +       spin_lock_irqsave(&re->page_lock, flags);
 198 +
 199 +       PR_INT_STAT("RX Delayed", rx_delayed);
 200 +       PR_INT_STAT("RX Done 0", rx_done0);
 201 +       PR_INT_STAT("RX Coherent", rx_coherent);
 202 +
 203 +       PR_INT_STAT("TX Delayed", tx_delayed);
 204 +       PR_INT_STAT("TX Done 0", tx_done0);
 205 +       PR_INT_STAT("TX Done 1", tx_done1);
 206 +       PR_INT_STAT("TX Done 2", tx_done2);
 207 +       PR_INT_STAT("TX Done 3", tx_done3);
 208 +       PR_INT_STAT("TX Coherent", tx_coherent);
 209 +
 210 +       PR_INT_STAT("PSE FQ empty", pse_fq_empty);
 211 +       PR_INT_STAT("CDMA Flow control", pse_p0_fc);
 212 +       PR_INT_STAT("GDMA1 Flow control", pse_p1_fc);
 213 +       PR_INT_STAT("GDMA2 Flow control", pse_p2_fc);
 214 +       PR_INT_STAT("PSE discard", pse_buf_drop);
 215 +
 216 +       len += snprintf(buf + len, sizeof(buf) - len, "\n");
 217 +       PR_INT_STAT("Total", total);
 218 +
 219 +       spin_unlock_irqrestore(&re->page_lock, flags);
 220 +
 221 +       return simple_read_from_buffer(user_buf, count, ppos, buf, len);
 222 +#undef PR_INT_STAT
 223 +}
 224 +
 225 +static const struct file_operations raeth_fops_int_stats = {
 226 +       .open   = raeth_debugfs_generic_open,
 227 +       .read   = read_file_int_stats,
 228 +       .owner  = THIS_MODULE
 229 +};
 230 +
 231 +void raeth_debugfs_exit(struct raeth_priv *re)
 232 +{
 233 +       debugfs_remove_recursive(re->debug.debugfs_dir);
 234 +}
 235 +
 236 +int raeth_debugfs_init(struct raeth_priv *re)
 237 +{
 238 +       re->debug.debugfs_dir = debugfs_create_dir(re->netdev->name,
 239 +                                                  raeth_debugfs_root);
 240 +       if (!re->debug.debugfs_dir)
 241 +               return -ENOMEM;
 242 +
 243 +       debugfs_create_file("int_stats", S_IRUGO, re->debug.debugfs_dir,
 244 +                           re, &raeth_fops_int_stats);
 245 +
 246 +       return 0;
 247 +}
 248 +
 249 +int raeth_debugfs_root_init(void)
 250 +{
 251 +       if (raeth_debugfs_root)
 252 +               return -EBUSY;
 253 +
 254 +       raeth_debugfs_root = debugfs_create_dir("raeth", NULL);
 255 +       if (!raeth_debugfs_root)
 256 +               return -ENOENT;
 257 +
 258 +       return 0;
 259 +}
 260 +
 261 +void raeth_debugfs_root_exit(void)
 262 +{
 263 +       debugfs_remove(raeth_debugfs_root);
 264 +       raeth_debugfs_root = NULL;
 265 +}
 266 Index: linux-3.8.11/drivers/net/ethernet/ramips/ramips_esw.c
 267 ===================================================================
 268 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 269 +++ linux-3.8.11/drivers/net/ethernet/ramips/ramips_esw.c       2013-05-06 12:43:38.148652601 +0200
 270 @@ -0,0 +1,1221 @@
 271 +#include <linux/ioport.h>
 272 +#include <linux/switch.h>
 273 +#include <linux/mii.h>
 274 +
 275 +#include <ralink_regs.h>
 276 +#include <rt305x.h>
 277 +#include <rt305x_esw_platform.h>
 278 +
 279 +/*
 280 + * HW limitations for this switch:
 281 + * - No large frame support (PKT_MAX_LEN at most 1536)
 282 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
 283 + *   though this might be possible using the undocumented PPE.
 284 + */
 285 +
 286 +#define RT305X_ESW_REG_ISR             0x00
 287 +#define RT305X_ESW_REG_IMR             0x04
 288 +#define RT305X_ESW_REG_FCT0            0x08
 289 +#define RT305X_ESW_REG_PFC1            0x14
 290 +#define RT305X_ESW_REG_ATS             0x24
 291 +#define RT305X_ESW_REG_ATS0            0x28
 292 +#define RT305X_ESW_REG_ATS1            0x2c
 293 +#define RT305X_ESW_REG_ATS2            0x30
 294 +#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
 295 +#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 296 +#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 297 +#define RT305X_ESW_REG_POA             0x80
 298 +#define RT305X_ESW_REG_FPA             0x84
 299 +#define RT305X_ESW_REG_SOCPC           0x8c
 300 +#define RT305X_ESW_REG_POC0            0x90
 301 +#define RT305X_ESW_REG_POC1            0x94
 302 +#define RT305X_ESW_REG_POC2            0x98
 303 +#define RT305X_ESW_REG_SGC             0x9c
 304 +#define RT305X_ESW_REG_STRT            0xa0
 305 +#define RT305X_ESW_REG_PCR0            0xc0
 306 +#define RT305X_ESW_REG_PCR1            0xc4
 307 +#define RT305X_ESW_REG_FPA2            0xc8
 308 +#define RT305X_ESW_REG_FCT2            0xcc
 309 +#define RT305X_ESW_REG_SGC2            0xe4
 310 +#define RT305X_ESW_REG_P0LED           0xa4
 311 +#define RT305X_ESW_REG_P1LED           0xa8
 312 +#define RT305X_ESW_REG_P2LED           0xac
 313 +#define RT305X_ESW_REG_P3LED           0xb0
 314 +#define RT305X_ESW_REG_P4LED           0xb4
 315 +#define RT305X_ESW_REG_P0PC            0xe8
 316 +#define RT305X_ESW_REG_P1PC            0xec
 317 +#define RT305X_ESW_REG_P2PC            0xf0
 318 +#define RT305X_ESW_REG_P3PC            0xf4
 319 +#define RT305X_ESW_REG_P4PC            0xf8
 320 +#define RT305X_ESW_REG_P5PC            0xfc
 321 +
 322 +#define RT305X_ESW_LED_LINK            0
 323 +#define RT305X_ESW_LED_100M            1
 324 +#define RT305X_ESW_LED_DUPLEX          2
 325 +#define RT305X_ESW_LED_ACTIVITY                3
 326 +#define RT305X_ESW_LED_COLLISION       4
 327 +#define RT305X_ESW_LED_LINKACT         5
 328 +#define RT305X_ESW_LED_DUPLCOLL                6
 329 +#define RT305X_ESW_LED_10MACT          7
 330 +#define RT305X_ESW_LED_100MACT         8
 331 +/* Additional led states not in datasheet: */
 332 +#define RT305X_ESW_LED_BLINK           10
 333 +#define RT305X_ESW_LED_ON              12
 334 +
 335 +#define RT305X_ESW_LINK_S              25
 336 +#define RT305X_ESW_DUPLEX_S            9
 337 +#define RT305X_ESW_SPD_S               0
 338 +
 339 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
 340 +#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
 341 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
 342 +
 343 +#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
 344 +
 345 +#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
 346 +#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 347 +
 348 +#define RT305X_ESW_PVIDC_PVID_M                0xfff
 349 +#define RT305X_ESW_PVIDC_PVID_S                12
 350 +
 351 +#define RT305X_ESW_VLANI_VID_M         0xfff
 352 +#define RT305X_ESW_VLANI_VID_S         12
 353 +
 354 +#define RT305X_ESW_VMSC_MSC_M          0xff
 355 +#define RT305X_ESW_VMSC_MSC_S          8
 356 +
 357 +#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
 358 +#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
 359 +#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
 360 +#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
 361 +
 362 +#define RT305X_ESW_POC0_EN_BP_S                0
 363 +#define RT305X_ESW_POC0_EN_FC_S                8
 364 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
 365 +#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
 366 +#define RT305X_ESW_POC0_DIS_PORT_S     23
 367 +
 368 +#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
 369 +#define RT305X_ESW_POC2_UNTAG_EN_S     0
 370 +#define RT305X_ESW_POC2_ENAGING_S      8
 371 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
 372 +
 373 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
 374 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
 375 +#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
 376 +#define RT305X_ESW_SGC2_LAN_PMAP_S     24
 377 +
 378 +#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
 379 +#define RT305X_ESW_PFC1_EN_VLAN_S      16
 380 +#define RT305X_ESW_PFC1_EN_TOS_S       24
 381 +
 382 +#define RT305X_ESW_VLAN_NONE           0xfff
 383 +
 384 +#define RT305X_ESW_POA_LINK_MASK       0x1f
 385 +#define RT305X_ESW_POA_LINK_SHIFT      25
 386 +
 387 +#define RT305X_ESW_PORT_ST_CHG         BIT(26)
 388 +#define RT305X_ESW_PORT0               0
 389 +#define RT305X_ESW_PORT1               1
 390 +#define RT305X_ESW_PORT2               2
 391 +#define RT305X_ESW_PORT3               3
 392 +#define RT305X_ESW_PORT4               4
 393 +#define RT305X_ESW_PORT5               5
 394 +#define RT305X_ESW_PORT6               6
 395 +
 396 +#define RT305X_ESW_PORTS_NONE          0
 397 +
 398 +#define RT305X_ESW_PMAP_LLLLLL         0x3f
 399 +#define RT305X_ESW_PMAP_LLLLWL         0x2f
 400 +#define RT305X_ESW_PMAP_WLLLLL         0x3e
 401 +
 402 +#define RT305X_ESW_PORTS_INTERNAL                                      \
 403 +               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
 404 +                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
 405 +                BIT(RT305X_ESW_PORT4))
 406 +
 407 +#define RT305X_ESW_PORTS_NOCPU                                         \
 408 +               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
 409 +
 410 +#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
 411 +
 412 +#define RT305X_ESW_PORTS_ALL                                           \
 413 +               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
 414 +
 415 +#define RT305X_ESW_NUM_VLANS           16
 416 +#define RT305X_ESW_NUM_VIDS            4096
 417 +#define RT305X_ESW_NUM_PORTS           7
 418 +#define RT305X_ESW_NUM_LANWAN          6
 419 +#define RT305X_ESW_NUM_LEDS            5
 420 +
 421 +enum {
 422 +       /* Global attributes. */
 423 +       RT305X_ESW_ATTR_ENABLE_VLAN,
 424 +       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 425 +       /* Port attributes. */
 426 +       RT305X_ESW_ATTR_PORT_DISABLE,
 427 +       RT305X_ESW_ATTR_PORT_DOUBLETAG,
 428 +       RT305X_ESW_ATTR_PORT_UNTAG,
 429 +       RT305X_ESW_ATTR_PORT_LED,
 430 +       RT305X_ESW_ATTR_PORT_LAN,
 431 +       RT305X_ESW_ATTR_PORT_RECV_BAD,
 432 +       RT305X_ESW_ATTR_PORT_RECV_GOOD,
 433 +};
 434 +
 435 +struct rt305x_esw_port {
 436 +       bool    disable;
 437 +       bool    doubletag;
 438 +       bool    untag;
 439 +       u8      led;
 440 +       u16     pvid;
 441 +};
 442 +
 443 +struct rt305x_esw_vlan {
 444 +       u8      ports;
 445 +       u16     vid;
 446 +};
 447 +
 448 +struct rt305x_esw {
 449 +       struct device           *dev;
 450 +       void __iomem            *base;
 451 +       int                     irq;
 452 +       const struct rt305x_esw_platform_data *pdata;
 453 +       /* Protects against concurrent register rmw operations. */
 454 +       spinlock_t              reg_rw_lock;
 455 +
 456 +       unsigned char           port_map;
 457 +       unsigned int            reg_initval_fct2;
 458 +       unsigned int            reg_initval_fpa2;
 459 +
 460 +
 461 +       struct switch_dev       swdev;
 462 +       bool                    global_vlan_enable;
 463 +       bool                    alt_vlan_disable;
 464 +       struct rt305x_esw_vlan vlans[RT305X_ESW_NUM_VLANS];
 465 +       struct rt305x_esw_port ports[RT305X_ESW_NUM_PORTS];
 466 +
 467 +};
 468 +
 469 +static inline void
 470 +rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
 471 +{
 472 +       __raw_writel(val, esw->base + reg);
 473 +}
 474 +
 475 +static inline u32
 476 +rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
 477 +{
 478 +       return __raw_readl(esw->base + reg);
 479 +}
 480 +
 481 +static inline void
 482 +rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 483 +                  unsigned long val)
 484 +{
 485 +       unsigned long t;
 486 +
 487 +       t = __raw_readl(esw->base + reg) & ~mask;
 488 +       __raw_writel(t | val, esw->base + reg);
 489 +}
 490 +
 491 +static void
 492 +rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 493 +              unsigned long val)
 494 +{
 495 +       unsigned long flags;
 496 +
 497 +       spin_lock_irqsave(&esw->reg_rw_lock, flags);
 498 +       rt305x_esw_rmw_raw(esw, reg, mask, val);
 499 +       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 500 +}
 501 +
 502 +static u32
 503 +rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 504 +                u32 write_data)
 505 +{
 506 +       unsigned long t_start = jiffies;
 507 +       int ret = 0;
 508 +
 509 +       while (1) {
 510 +               if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 511 +                     RT305X_ESW_PCR1_WT_DONE))
 512 +                       break;
 513 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 514 +                       ret = 1;
 515 +                       goto out;
 516 +               }
 517 +       }
 518 +
 519 +       write_data &= 0xffff;
 520 +       rt305x_esw_wr(esw,
 521 +                     (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 522 +                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 523 +                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 524 +                     RT305X_ESW_REG_PCR0);
 525 +
 526 +       t_start = jiffies;
 527 +       while (1) {
 528 +               if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 529 +                   RT305X_ESW_PCR1_WT_DONE)
 530 +                       break;
 531 +
 532 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 533 +                       ret = 1;
 534 +                       break;
 535 +               }
 536 +       }
 537 +out:
 538 +       if (ret)
 539 +               printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 540 +       return ret;
 541 +}
 542 +
 543 +static unsigned
 544 +rt305x_esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
 545 +{
 546 +       unsigned s;
 547 +       unsigned val;
 548 +
 549 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 550 +       val = rt305x_esw_rr(esw, RT305X_ESW_REG_VLANI(vlan / 2));
 551 +       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
 552 +
 553 +       return val;
 554 +}
 555 +
 556 +static void
 557 +rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 558 +{
 559 +       unsigned s;
 560 +
 561 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 562 +       rt305x_esw_rmw(esw,
 563 +                      RT305X_ESW_REG_VLANI(vlan / 2),
 564 +                      RT305X_ESW_VLANI_VID_M << s,
 565 +                      (vid & RT305X_ESW_VLANI_VID_M) << s);
 566 +}
 567 +
 568 +static unsigned
 569 +rt305x_esw_get_pvid(struct rt305x_esw *esw, unsigned port)
 570 +{
 571 +       unsigned s, val;
 572 +
 573 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 574 +       val = rt305x_esw_rr(esw, RT305X_ESW_REG_PVIDC(port / 2));
 575 +       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
 576 +}
 577 +
 578 +static void
 579 +rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 580 +{
 581 +       unsigned s;
 582 +
 583 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 584 +       rt305x_esw_rmw(esw,
 585 +                      RT305X_ESW_REG_PVIDC(port / 2),
 586 +                      RT305X_ESW_PVIDC_PVID_M << s,
 587 +                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 588 +}
 589 +
 590 +static unsigned
 591 +rt305x_esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
 592 +{
 593 +       unsigned s, val;
 594 +
 595 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 596 +       val = rt305x_esw_rr(esw, RT305X_ESW_REG_VMSC(vlan / 4));
 597 +       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
 598 +
 599 +       return val;
 600 +}
 601 +
 602 +static void
 603 +rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 604 +{
 605 +       unsigned s;
 606 +
 607 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 608 +       rt305x_esw_rmw(esw,
 609 +                      RT305X_ESW_REG_VMSC(vlan / 4),
 610 +                      RT305X_ESW_VMSC_MSC_M << s,
 611 +                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
 612 +}
 613 +
 614 +static unsigned
 615 +rt305x_esw_get_port_disable(struct rt305x_esw *esw)
 616 +{
 617 +       unsigned reg;
 618 +       reg = rt305x_esw_rr(esw, RT305X_ESW_REG_POC0);
 619 +       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
 620 +              RT305X_ESW_POC0_DIS_PORT_M;
 621 +}
 622 +
 623 +static void
 624 +rt305x_esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
 625 +{
 626 +       unsigned old_mask;
 627 +       unsigned enable_mask;
 628 +       unsigned changed;
 629 +       int i;
 630 +
 631 +       old_mask = rt305x_esw_get_port_disable(esw);
 632 +       changed = old_mask ^ disable_mask;
 633 +       enable_mask = old_mask & disable_mask;
 634 +
 635 +       /* enable before writing to MII */
 636 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
 637 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 638 +                       RT305X_ESW_POC0_DIS_PORT_S),
 639 +                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 640 +
 641 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
 642 +               if (!(changed & (1 << i)))
 643 +                       continue;
 644 +               if (disable_mask & (1 << i)) {
 645 +                       /* disable */
 646 +                       rt305x_mii_write(esw, i, MII_BMCR,
 647 +                                        BMCR_PDOWN);
 648 +               } else {
 649 +                       /* enable */
 650 +                       rt305x_mii_write(esw, i, MII_BMCR,
 651 +                                        BMCR_FULLDPLX |
 652 +                                        BMCR_ANENABLE |
 653 +                                        BMCR_ANRESTART |
 654 +                                        BMCR_SPEED100);
 655 +               }
 656 +       }
 657 +
 658 +       /* disable after writing to MII */
 659 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
 660 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 661 +                       RT305X_ESW_POC0_DIS_PORT_S),
 662 +                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 663 +}
 664 +
 665 +static int
 666 +rt305x_esw_apply_config(struct switch_dev *dev);
 667 +
 668 +static void
 669 +rt305x_esw_hw_init(struct rt305x_esw *esw)
 670 +{
 671 +       int i;
 672 +       u8 port_disable = 0;
 673 +       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
 674 +
 675 +       /* vodoo from original driver */
 676 +       rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 677 +       rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 678 +       /* Port priority 1 for all ports, vlan enabled. */
 679 +       rt305x_esw_wr(esw, 0x00005555 |
 680 +                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
 681 +                     RT305X_ESW_REG_PFC1);
 682 +
 683 +       /* Enable Back Pressure, and Flow Control */
 684 +       rt305x_esw_wr(esw,
 685 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
 686 +                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
 687 +                     RT305X_ESW_REG_POC0);
 688 +
 689 +       /* Enable Aging, and VLAN TAG removal */
 690 +       rt305x_esw_wr(esw,
 691 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
 692 +                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
 693 +                     RT305X_ESW_REG_POC2);
 694 +
 695 +       if (esw->reg_initval_fct2)
 696 +               rt305x_esw_wr(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 697 +       else
 698 +               rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 699 +
 700 +       /*
 701 +        * 300s aging timer, max packet len 1536, broadcast storm prevention
 702 +        * disabled, disable collision abort, mac xor48 hash, 10 packet back
 703 +        * pressure jam, GMII disable was_transmit, back pressure disabled,
 704 +        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
 705 +        * ports.
 706 +        */
 707 +       rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 708 +
 709 +       /* Setup SoC Port control register */
 710 +       rt305x_esw_wr(esw,
 711 +                     (RT305X_ESW_SOCPC_CRC_PADDING |
 712 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 713 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 714 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 715 +                     RT305X_ESW_REG_SOCPC);
 716 +
 717 +       if (esw->reg_initval_fpa2)
 718 +               rt305x_esw_wr(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 719 +       else
 720 +               rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 721 +       rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
 722 +
 723 +       /* Force Link/Activity on ports */
 724 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED);
 725 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED);
 726 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED);
 727 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED);
 728 +       rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED);
 729 +
 730 +       /* Copy disabled port configuration from bootloader setup */
 731 +       port_disable = rt305x_esw_get_port_disable(esw);
 732 +       for (i = 0; i < 6; i++)
 733 +               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
 734 +
 735 +       rt305x_mii_write(esw, 0, 31, 0x8000);
 736 +       for (i = 0; i < 5; i++) {
 737 +               if (esw->ports[i].disable) {
 738 +                       rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 739 +               } else {
 740 +                       rt305x_mii_write(esw, i, MII_BMCR,
 741 +                                        BMCR_FULLDPLX |
 742 +                                        BMCR_ANENABLE |
 743 +                                        BMCR_SPEED100);
 744 +               }
 745 +               /* TX10 waveform coefficient */
 746 +               rt305x_mii_write(esw, i, 26, 0x1601);
 747 +               /* TX100/TX10 AD/DA current bias */
 748 +               rt305x_mii_write(esw, i, 29, 0x7058);
 749 +               /* TX100 slew rate control */
 750 +               rt305x_mii_write(esw, i, 30, 0x0018);
 751 +       }
 752 +
 753 +       /* PHY IOT */
 754 +       /* select global register */
 755 +       rt305x_mii_write(esw, 0, 31, 0x0);
 756 +       /* tune TP_IDL tail and head waveform */
 757 +       rt305x_mii_write(esw, 0, 22, 0x052f);
 758 +       /* set TX10 signal amplitude threshold to minimum */
 759 +       rt305x_mii_write(esw, 0, 17, 0x0fe0);
 760 +       /* set squelch amplitude to higher threshold */
 761 +       rt305x_mii_write(esw, 0, 18, 0x40ba);
 762 +       /* longer TP_IDL tail length */
 763 +       rt305x_mii_write(esw, 0, 14, 0x65);
 764 +       /* select local register */
 765 +       rt305x_mii_write(esw, 0, 31, 0x8000);
 766 +
 767 +       if (esw->port_map)
 768 +               port_map = esw->port_map;
 769 +       else
 770 +               port_map = RT305X_ESW_PMAP_LLLLLL;
 771 +
 772 +       /*
 773 +        * Unused HW feature, but still nice to be consistent here...
 774 +        * This is also exported to userspace ('lan' attribute) so it's
 775 +        * conveniently usable to decide which ports go into the wan vlan by
 776 +        * default.
 777 +        */
 778 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
 779 +                      RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
 780 +                      port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
 781 +
 782 +       /* make the switch leds blink */
 783 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
 784 +               esw->ports[i].led = 0x05;
 785 +
 786 +       /* Apply the empty config. */
 787 +       rt305x_esw_apply_config(&esw->swdev);
 788 +}
 789 +
 790 +static irqreturn_t
 791 +rt305x_esw_interrupt(int irq, void *_esw)
 792 +{
 793 +       struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
 794 +       u32 status;
 795 +
 796 +       status = rt305x_esw_rr(esw, RT305X_ESW_REG_ISR);
 797 +       if (status & RT305X_ESW_PORT_ST_CHG) {
 798 +               u32 link = rt305x_esw_rr(esw, RT305X_ESW_REG_POA);
 799 +               link >>= RT305X_ESW_POA_LINK_SHIFT;
 800 +               link &= RT305X_ESW_POA_LINK_MASK;
 801 +               dev_info(esw->dev, "link changed 0x%02X\n", link);
 802 +       }
 803 +       rt305x_esw_wr(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
 804 +
 805 +       return IRQ_HANDLED;
 806 +}
 807 +
 808 +static void
 809 +rt305x_esw_request_irq(struct rt305x_esw *esw)
 810 +{
 811 +       /* Only unmask the port change interrupt */
 812 +       rt305x_esw_wr(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
 813 +
 814 +       /* request the irq handler */
 815 +       request_irq(esw->irq, rt305x_esw_interrupt, 0, "esw", esw);
 816 +}
 817 +
 818 +static int
 819 +rt305x_esw_apply_config(struct switch_dev *dev)
 820 +{
 821 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 822 +       int i;
 823 +       u8 disable = 0;
 824 +       u8 doubletag = 0;
 825 +       u8 en_vlan = 0;
 826 +       u8 untag = 0;
 827 +
 828 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 829 +               u32 vid, vmsc;
 830 +               if (esw->global_vlan_enable) {
 831 +                       vid = esw->vlans[i].vid;
 832 +                       vmsc = esw->vlans[i].ports;
 833 +               } else {
 834 +                       vid = RT305X_ESW_VLAN_NONE;
 835 +                       vmsc = RT305X_ESW_PORTS_NONE;
 836 +               }
 837 +               rt305x_esw_set_vlan_id(esw, i, vid);
 838 +               rt305x_esw_set_vmsc(esw, i, vmsc);
 839 +       }
 840 +
 841 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 842 +               u32 pvid;
 843 +               disable |= esw->ports[i].disable << i;
 844 +               if (esw->global_vlan_enable) {
 845 +                       doubletag |= esw->ports[i].doubletag << i;
 846 +                       en_vlan   |= 1                       << i;
 847 +                       untag     |= esw->ports[i].untag     << i;
 848 +                       pvid       = esw->ports[i].pvid;
 849 +               } else {
 850 +                       int x = esw->alt_vlan_disable ? 0 : 1;
 851 +                       doubletag |= x << i;
 852 +                       en_vlan   |= x << i;
 853 +                       untag     |= x << i;
 854 +                       pvid       = 0;
 855 +               }
 856 +               rt305x_esw_set_pvid(esw, i, pvid);
 857 +               if (i < RT305X_ESW_NUM_LEDS)
 858 +                       rt305x_esw_wr(esw, esw->ports[i].led,
 859 +                                     RT305X_ESW_REG_P0LED + 4*i);
 860 +       }
 861 +
 862 +       rt305x_esw_set_port_disable(esw, disable);
 863 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
 864 +                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
 865 +                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
 866 +                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
 867 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1,
 868 +                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
 869 +                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
 870 +       rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2,
 871 +                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
 872 +                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
 873 +
 874 +       if (!esw->global_vlan_enable) {
 875 +               /*
 876 +                * Still need to put all ports into vlan 0 or they'll be
 877 +                * isolated.
 878 +                * NOTE: vlan 0 is special, no vlan tag is prepended
 879 +                */
 880 +               rt305x_esw_set_vlan_id(esw, 0, 0);
 881 +               rt305x_esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
 882 +       }
 883 +
 884 +       return 0;
 885 +}
 886 +
 887 +static int
 888 +rt305x_esw_reset_switch(struct switch_dev *dev)
 889 +{
 890 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 891 +       esw->global_vlan_enable = 0;
 892 +       memset(esw->ports, 0, sizeof(esw->ports));
 893 +       memset(esw->vlans, 0, sizeof(esw->vlans));
 894 +       rt305x_esw_hw_init(esw);
 895 +
 896 +       return 0;
 897 +}
 898 +
 899 +static int
 900 +rt305x_esw_get_vlan_enable(struct switch_dev *dev,
 901 +                          const struct switch_attr *attr,
 902 +                          struct switch_val *val)
 903 +{
 904 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 905 +
 906 +       val->value.i = esw->global_vlan_enable;
 907 +
 908 +       return 0;
 909 +}
 910 +
 911 +static int
 912 +rt305x_esw_set_vlan_enable(struct switch_dev *dev,
 913 +                          const struct switch_attr *attr,
 914 +                          struct switch_val *val)
 915 +{
 916 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 917 +
 918 +       esw->global_vlan_enable = val->value.i != 0;
 919 +
 920 +       return 0;
 921 +}
 922 +
 923 +static int
 924 +rt305x_esw_get_alt_vlan_disable(struct switch_dev *dev,
 925 +                               const struct switch_attr *attr,
 926 +                               struct switch_val *val)
 927 +{
 928 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 929 +
 930 +       val->value.i = esw->alt_vlan_disable;
 931 +
 932 +       return 0;
 933 +}
 934 +
 935 +static int
 936 +rt305x_esw_set_alt_vlan_disable(struct switch_dev *dev,
 937 +                               const struct switch_attr *attr,
 938 +                               struct switch_val *val)
 939 +{
 940 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 941 +
 942 +       esw->alt_vlan_disable = val->value.i != 0;
 943 +
 944 +       return 0;
 945 +}
 946 +
 947 +static int
 948 +rt305x_esw_get_port_link(struct switch_dev *dev,
 949 +                        int port,
 950 +                        struct switch_port_link *link)
 951 +{
 952 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 953 +       u32 speed, poa;
 954 +
 955 +       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
 956 +               return -EINVAL;
 957 +
 958 +       poa = rt305x_esw_rr(esw, RT305X_ESW_REG_POA) >> port;
 959 +
 960 +       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
 961 +       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
 962 +       if (port < RT305X_ESW_NUM_LEDS) {
 963 +               speed = (poa >> RT305X_ESW_SPD_S) & 1;
 964 +       } else {
 965 +               if (port == RT305X_ESW_NUM_PORTS - 1)
 966 +                       poa >>= 1;
 967 +               speed = (poa >> RT305X_ESW_SPD_S) & 3;
 968 +       }
 969 +       switch (speed) {
 970 +       case 0:
 971 +               link->speed = SWITCH_PORT_SPEED_10;
 972 +               break;
 973 +       case 1:
 974 +               link->speed = SWITCH_PORT_SPEED_100;
 975 +               break;
 976 +       case 2:
 977 +       case 3: /* forced gige speed can be 2 or 3 */
 978 +               link->speed = SWITCH_PORT_SPEED_1000;
 979 +               break;
 980 +       default:
 981 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 982 +               break;
 983 +       }
 984 +
 985 +       return 0;
 986 +}
 987 +
 988 +static int
 989 +rt305x_esw_get_port_bool(struct switch_dev *dev,
 990 +                        const struct switch_attr *attr,
 991 +                        struct switch_val *val)
 992 +{
 993 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 994 +       int idx = val->port_vlan;
 995 +       u32 x, reg, shift;
 996 +
 997 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
 998 +               return -EINVAL;
 999 +
1000 +       switch (attr->id) {
1001 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1002 +               reg = RT305X_ESW_REG_POC0;
1003 +               shift = RT305X_ESW_POC0_DIS_PORT_S;
1004 +               break;
1005 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1006 +               reg = RT305X_ESW_REG_SGC2;
1007 +               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1008 +               break;
1009 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1010 +               reg = RT305X_ESW_REG_POC2;
1011 +               shift = RT305X_ESW_POC2_UNTAG_EN_S;
1012 +               break;
1013 +       case RT305X_ESW_ATTR_PORT_LAN:
1014 +               reg = RT305X_ESW_REG_SGC2;
1015 +               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1016 +               if (idx >= RT305X_ESW_NUM_LANWAN)
1017 +                       return -EINVAL;
1018 +               break;
1019 +       default:
1020 +               return -EINVAL;
1021 +       }
1022 +
1023 +       x = rt305x_esw_rr(esw, reg);
1024 +       val->value.i = (x >> (idx + shift)) & 1;
1025 +
1026 +       return 0;
1027 +}
1028 +
1029 +static int
1030 +rt305x_esw_set_port_bool(struct switch_dev *dev,
1031 +                        const struct switch_attr *attr,
1032 +                        struct switch_val *val)
1033 +{
1034 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1035 +       int idx = val->port_vlan;
1036 +
1037 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1038 +           val->value.i < 0 || val->value.i > 1)
1039 +               return -EINVAL;
1040 +
1041 +       switch (attr->id) {
1042 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1043 +               esw->ports[idx].disable = val->value.i;
1044 +               break;
1045 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1046 +               esw->ports[idx].doubletag = val->value.i;
1047 +               break;
1048 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1049 +               esw->ports[idx].untag = val->value.i;
1050 +               break;
1051 +       default:
1052 +               return -EINVAL;
1053 +       }
1054 +
1055 +       return 0;
1056 +}
1057 +
1058 +static int
1059 +rt305x_esw_get_port_recv_badgood(struct switch_dev *dev,
1060 +                                const struct switch_attr *attr,
1061 +                                struct switch_val *val)
1062 +{
1063 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1064 +       int idx = val->port_vlan;
1065 +       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1066 +       u32 reg;
1067 +
1068 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1069 +               return -EINVAL;
1070 +
1071 +       reg = rt305x_esw_rr(esw, RT305X_ESW_REG_P0PC + 4*idx);
1072 +       val->value.i = (reg >> shift) & 0xffff;
1073 +
1074 +       return 0;
1075 +}
1076 +
1077 +static int
1078 +rt305x_esw_get_port_led(struct switch_dev *dev,
1079 +                       const struct switch_attr *attr,
1080 +                       struct switch_val *val)
1081 +{
1082 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1083 +       int idx = val->port_vlan;
1084 +
1085 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1086 +           idx >= RT305X_ESW_NUM_LEDS)
1087 +               return -EINVAL;
1088 +
1089 +       val->value.i = rt305x_esw_rr(esw, RT305X_ESW_REG_P0LED + 4*idx);
1090 +
1091 +       return 0;
1092 +}
1093 +
1094 +static int
1095 +rt305x_esw_set_port_led(struct switch_dev *dev,
1096 +                       const struct switch_attr *attr,
1097 +                       struct switch_val *val)
1098 +{
1099 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1100 +       int idx = val->port_vlan;
1101 +
1102 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1103 +               return -EINVAL;
1104 +
1105 +       esw->ports[idx].led = val->value.i;
1106 +
1107 +       return 0;
1108 +}
1109 +
1110 +static int
1111 +rt305x_esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1112 +{
1113 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1114 +
1115 +       if (port >= RT305X_ESW_NUM_PORTS)
1116 +               return -EINVAL;
1117 +
1118 +       *val = rt305x_esw_get_pvid(esw, port);
1119 +
1120 +       return 0;
1121 +}
1122 +
1123 +static int
1124 +rt305x_esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1125 +{
1126 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1127 +
1128 +       if (port >= RT305X_ESW_NUM_PORTS)
1129 +               return -EINVAL;
1130 +
1131 +       esw->ports[port].pvid = val;
1132 +
1133 +       return 0;
1134 +}
1135 +
1136 +static int
1137 +rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1138 +{
1139 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1140 +       u32 vmsc, poc2;
1141 +       int vlan_idx = -1;
1142 +       int i;
1143 +
1144 +       val->len = 0;
1145 +
1146 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1147 +               return -EINVAL;
1148 +
1149 +       /* valid vlan? */
1150 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1151 +               if (rt305x_esw_get_vlan_id(esw, i) == val->port_vlan &&
1152 +                   rt305x_esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1153 +                       vlan_idx = i;
1154 +                       break;
1155 +               }
1156 +       }
1157 +
1158 +       if (vlan_idx == -1)
1159 +               return -EINVAL;
1160 +
1161 +       vmsc = rt305x_esw_get_vmsc(esw, vlan_idx);
1162 +       poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2);
1163 +
1164 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1165 +               struct switch_port *p;
1166 +               int port_mask = 1 << i;
1167 +
1168 +               if (!(vmsc & port_mask))
1169 +                       continue;
1170 +
1171 +               p = &val->value.ports[val->len++];
1172 +               p->id = i;
1173 +               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1174 +                       p->flags = 0;
1175 +               else
1176 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1177 +       }
1178 +
1179 +       return 0;
1180 +}
1181 +
1182 +static int
1183 +rt305x_esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1184 +{
1185 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1186 +       int ports;
1187 +       int vlan_idx = -1;
1188 +       int i;
1189 +
1190 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1191 +           val->len > RT305X_ESW_NUM_PORTS)
1192 +               return -EINVAL;
1193 +
1194 +       /* one of the already defined vlans? */
1195 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1196 +               if (esw->vlans[i].vid == val->port_vlan &&
1197 +                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1198 +                       vlan_idx = i;
1199 +                       break;
1200 +               }
1201 +       }
1202 +
1203 +       /* select a free slot */
1204 +       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1205 +               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1206 +                       vlan_idx = i;
1207 +       }
1208 +
1209 +       /* bail if all slots are in use */
1210 +       if (vlan_idx == -1)
1211 +               return -EINVAL;
1212 +
1213 +       ports = RT305X_ESW_PORTS_NONE;
1214 +       for (i = 0; i < val->len; i++) {
1215 +               struct switch_port *p = &val->value.ports[i];
1216 +               int port_mask = 1 << p->id;
1217 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1218 +
1219 +               if (p->id >= RT305X_ESW_NUM_PORTS)
1220 +                       return -EINVAL;
1221 +
1222 +               ports |= port_mask;
1223 +               esw->ports[p->id].untag = untagged;
1224 +       }
1225 +       esw->vlans[vlan_idx].ports = ports;
1226 +       if (ports == RT305X_ESW_PORTS_NONE)
1227 +               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1228 +       else
1229 +               esw->vlans[vlan_idx].vid = val->port_vlan;
1230 +
1231 +       return 0;
1232 +}
1233 +
1234 +static const struct switch_attr rt305x_esw_global[] = {
1235 +       {
1236 +               .type = SWITCH_TYPE_INT,
1237 +               .name = "enable_vlan",
1238 +               .description = "VLAN mode (1:enabled)",
1239 +               .max = 1,
1240 +               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1241 +               .get = rt305x_esw_get_vlan_enable,
1242 +               .set = rt305x_esw_set_vlan_enable,
1243 +       },
1244 +       {
1245 +               .type = SWITCH_TYPE_INT,
1246 +               .name = "alternate_vlan_disable",
1247 +               .description = "Use en_vlan instead of doubletag to disable"
1248 +                               " VLAN mode",
1249 +               .max = 1,
1250 +               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1251 +               .get = rt305x_esw_get_alt_vlan_disable,
1252 +               .set = rt305x_esw_set_alt_vlan_disable,
1253 +       },
1254 +};
1255 +
1256 +static const struct switch_attr rt305x_esw_port[] = {
1257 +       {
1258 +               .type = SWITCH_TYPE_INT,
1259 +               .name = "disable",
1260 +               .description = "Port state (1:disabled)",
1261 +               .max = 1,
1262 +               .id = RT305X_ESW_ATTR_PORT_DISABLE,
1263 +               .get = rt305x_esw_get_port_bool,
1264 +               .set = rt305x_esw_set_port_bool,
1265 +       },
1266 +       {
1267 +               .type = SWITCH_TYPE_INT,
1268 +               .name = "doubletag",
1269 +               .description = "Double tagging for incoming vlan packets "
1270 +                               "(1:enabled)",
1271 +               .max = 1,
1272 +               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1273 +               .get = rt305x_esw_get_port_bool,
1274 +               .set = rt305x_esw_set_port_bool,
1275 +       },
1276 +       {
1277 +               .type = SWITCH_TYPE_INT,
1278 +               .name = "untag",
1279 +               .description = "Untag (1:strip outgoing vlan tag)",
1280 +               .max = 1,
1281 +               .id = RT305X_ESW_ATTR_PORT_UNTAG,
1282 +               .get = rt305x_esw_get_port_bool,
1283 +               .set = rt305x_esw_set_port_bool,
1284 +       },
1285 +       {
1286 +               .type = SWITCH_TYPE_INT,
1287 +               .name = "led",
1288 +               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1289 +                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1290 +                               " 8:100mact, 10:blink, 12:on)",
1291 +               .max = 15,
1292 +               .id = RT305X_ESW_ATTR_PORT_LED,
1293 +               .get = rt305x_esw_get_port_led,
1294 +               .set = rt305x_esw_set_port_led,
1295 +       },
1296 +       {
1297 +               .type = SWITCH_TYPE_INT,
1298 +               .name = "lan",
1299 +               .description = "HW port group (0:wan, 1:lan)",
1300 +               .max = 1,
1301 +               .id = RT305X_ESW_ATTR_PORT_LAN,
1302 +               .get = rt305x_esw_get_port_bool,
1303 +       },
1304 +       {
1305 +               .type = SWITCH_TYPE_INT,
1306 +               .name = "recv_bad",
1307 +               .description = "Receive bad packet counter",
1308 +               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1309 +               .get = rt305x_esw_get_port_recv_badgood,
1310 +       },
1311 +       {
1312 +               .type = SWITCH_TYPE_INT,
1313 +               .name = "recv_good",
1314 +               .description = "Receive good packet counter",
1315 +               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1316 +               .get = rt305x_esw_get_port_recv_badgood,
1317 +       },
1318 +};
1319 +
1320 +static const struct switch_attr rt305x_esw_vlan[] = {
1321 +};
1322 +
1323 +static const struct switch_dev_ops rt305x_esw_ops = {
1324 +       .attr_global = {
1325 +               .attr = rt305x_esw_global,
1326 +               .n_attr = ARRAY_SIZE(rt305x_esw_global),
1327 +       },
1328 +       .attr_port = {
1329 +               .attr = rt305x_esw_port,
1330 +               .n_attr = ARRAY_SIZE(rt305x_esw_port),
1331 +       },
1332 +       .attr_vlan = {
1333 +               .attr = rt305x_esw_vlan,
1334 +               .n_attr = ARRAY_SIZE(rt305x_esw_vlan),
1335 +       },
1336 +       .get_vlan_ports = rt305x_esw_get_vlan_ports,
1337 +       .set_vlan_ports = rt305x_esw_set_vlan_ports,
1338 +       .get_port_pvid = rt305x_esw_get_port_pvid,
1339 +       .set_port_pvid = rt305x_esw_set_port_pvid,
1340 +       .get_port_link = rt305x_esw_get_port_link,
1341 +       .apply_config = rt305x_esw_apply_config,
1342 +       .reset_switch = rt305x_esw_reset_switch,
1343 +};
1344 +
1345 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1346 +       /* All ports are LAN ports. */
1347 +       .vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
1348 +       .reg_initval_fct2       = 0x00d6500c,
1349 +       /*
1350 +        * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1351 +        * turbo mii off, rgmi 3.3v off
1352 +        * port5: disabled
1353 +        * port6: enabled, gige, full-duplex, rx/tx-flow-control
1354 +        */
1355 +       .reg_initval_fpa2       = 0x3f502b28,
1356 +};
1357 +
1358 +static const struct of_device_id ralink_esw_match[] = {
1359 +       { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1360 +       {},
1361 +};
1362 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1363 +
1364 +static int
1365 +rt305x_esw_probe(struct platform_device *pdev)
1366 +{
1367 +       struct device_node *np = pdev->dev.of_node;
1368 +       const struct rt305x_esw_platform_data *pdata;
1369 +       const __be32 *port_map, *reg_init;
1370 +       struct rt305x_esw *esw;
1371 +       struct switch_dev *swdev;
1372 +       struct resource *res, *irq;
1373 +       int err;
1374 +
1375 +       pdata = pdev->dev.platform_data;
1376 +       if (!pdata) {
1377 +               const struct of_device_id *match;
1378 +               match = of_match_device(ralink_esw_match, &pdev->dev);
1379 +               if (match)
1380 +                       pdata = (struct rt305x_esw_platform_data *) match->data;
1381 +       }
1382 +       if (!pdata)
1383 +               return -EINVAL;
1384 +
1385 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386 +       if (!res) {
1387 +               dev_err(&pdev->dev, "no memory resource found\n");
1388 +               return -ENOMEM;
1389 +       }
1390 +
1391 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1392 +       if (!irq) {
1393 +               dev_err(&pdev->dev, "no irq resource found\n");
1394 +               return -ENOMEM;
1395 +       }
1396 +
1397 +       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1398 +       if (!esw) {
1399 +               dev_err(&pdev->dev, "no memory for private data\n");
1400 +               return -ENOMEM;
1401 +       }
1402 +
1403 +       esw->dev = &pdev->dev;
1404 +       esw->irq = irq->start;
1405 +       esw->base = ioremap(res->start, resource_size(res));
1406 +       if (!esw->base) {
1407 +               dev_err(&pdev->dev, "ioremap failed\n");
1408 +               err = -ENOMEM;
1409 +               goto free_esw;
1410 +       }
1411 +
1412 +       port_map = of_get_property(np, "ralink,portmap", NULL);
1413 +        if (port_map)
1414 +               esw->port_map = be32_to_cpu(*port_map);
1415 +
1416 +       reg_init = of_get_property(np, "ralink,fct2", NULL);
1417 +        if (reg_init)
1418 +               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1419 +
1420 +       reg_init = of_get_property(np, "ralink,fpa2", NULL);
1421 +        if (reg_init)
1422 +               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1423 +
1424 +       swdev = &esw->swdev;
1425 +       swdev->of_node = pdev->dev.of_node;
1426 +       swdev->name = "rt305x-esw";
1427 +       swdev->alias = "rt305x";
1428 +       swdev->cpu_port = RT305X_ESW_PORT6;
1429 +       swdev->ports = RT305X_ESW_NUM_PORTS;
1430 +       swdev->vlans = RT305X_ESW_NUM_VIDS;
1431 +       swdev->ops = &rt305x_esw_ops;
1432 +
1433 +       err = register_switch(swdev, NULL);
1434 +       if (err < 0) {
1435 +               dev_err(&pdev->dev, "register_switch failed\n");
1436 +               goto unmap_base;
1437 +       }
1438 +
1439 +       platform_set_drvdata(pdev, esw);
1440 +
1441 +       esw->pdata = pdata;
1442 +       spin_lock_init(&esw->reg_rw_lock);
1443 +       rt305x_esw_hw_init(esw);
1444 +       rt305x_esw_request_irq(esw);
1445 +
1446 +       return 0;
1447 +
1448 +unmap_base:
1449 +       iounmap(esw->base);
1450 +free_esw:
1451 +       kfree(esw);
1452 +       return err;
1453 +}
1454 +
1455 +static int
1456 +rt305x_esw_remove(struct platform_device *pdev)
1457 +{
1458 +       struct rt305x_esw *esw;
1459 +
1460 +       esw = platform_get_drvdata(pdev);
1461 +       if (esw) {
1462 +               unregister_switch(&esw->swdev);
1463 +               platform_set_drvdata(pdev, NULL);
1464 +               iounmap(esw->base);
1465 +               kfree(esw);
1466 +       }
1467 +
1468 +       return 0;
1469 +}
1470 +
1471 +static struct platform_driver rt305x_esw_driver = {
1472 +       .probe = rt305x_esw_probe,
1473 +       .remove = rt305x_esw_remove,
1474 +       .driver = {
1475 +               .name = "rt305x-esw",
1476 +               .owner = THIS_MODULE,
1477 +               .of_match_table = ralink_esw_match,
1478 +       },
1479 +};
1480 +
1481 +static int __init
1482 +rt305x_esw_init(void)
1483 +{
1484 +       return platform_driver_register(&rt305x_esw_driver);
1485 +}
1486 +
1487 +static void
1488 +rt305x_esw_exit(void)
1489 +{
1490 +       platform_driver_unregister(&rt305x_esw_driver);
1491 +}
1492 Index: linux-3.8.11/drivers/net/ethernet/ramips/ramips_eth.h
1493 ===================================================================
1494 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1495 +++ linux-3.8.11/drivers/net/ethernet/ramips/ramips_eth.h       2013-05-06 12:43:38.152652600 +0200
1496 @@ -0,0 +1,375 @@
1497 +/*
1498 + *   This program is free software; you can redistribute it and/or modify
1499 + *   it under the terms of the GNU General Public License as published by
1500 + *   the Free Software Foundation; version 2 of the License
1501 + *
1502 + *   This program is distributed in the hope that it will be useful,
1503 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1504 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1505 + *   GNU General Public License for more details.
1506 + *
1507 + *   You should have received a copy of the GNU General Public License
1508 + *   along with this program; if not, write to the Free Software
1509 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1510 + *
1511 + *   based on Ralink SDK3.3
1512 + *   Copyright (C) 2009 John Crispin <blogic@openwrt.org>
1513 + */
1514 +
1515 +#ifndef RAMIPS_ETH_H
1516 +#define RAMIPS_ETH_H
1517 +
1518 +#include <linux/mii.h>
1519 +#include <linux/interrupt.h>
1520 +#include <linux/netdevice.h>
1521 +#include <linux/dma-mapping.h>
1522 +
1523 +#define NUM_RX_DESC     256
1524 +#define NUM_TX_DESC     256
1525 +
1526 +#define RAMIPS_DELAY_EN_INT            0x80
1527 +#define RAMIPS_DELAY_MAX_INT           0x04
1528 +#define RAMIPS_DELAY_MAX_TOUT          0x04
1529 +#define RAMIPS_DELAY_CHAN              (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT)
1530 +#define RAMIPS_DELAY_INIT              ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN)
1531 +#define RAMIPS_PSE_FQFC_CFG_INIT       0x80504000
1532 +
1533 +/* interrupt bits */
1534 +#define RAMIPS_CNT_PPE_AF              BIT(31)
1535 +#define RAMIPS_CNT_GDM_AF              BIT(29)
1536 +#define RAMIPS_PSE_P2_FC               BIT(26)
1537 +#define RAMIPS_PSE_BUF_DROP            BIT(24)
1538 +#define RAMIPS_GDM_OTHER_DROP          BIT(23)
1539 +#define RAMIPS_PSE_P1_FC               BIT(22)
1540 +#define RAMIPS_PSE_P0_FC               BIT(21)
1541 +#define RAMIPS_PSE_FQ_EMPTY            BIT(20)
1542 +#define RAMIPS_GE1_STA_CHG             BIT(18)
1543 +#define RAMIPS_TX_COHERENT             BIT(17)
1544 +#define RAMIPS_RX_COHERENT             BIT(16)
1545 +#define RAMIPS_TX_DONE_INT3            BIT(11)
1546 +#define RAMIPS_TX_DONE_INT2            BIT(10)
1547 +#define RAMIPS_TX_DONE_INT1            BIT(9)
1548 +#define RAMIPS_TX_DONE_INT0            BIT(8)
1549 +#define RAMIPS_RX_DONE_INT0            BIT(2)
1550 +#define RAMIPS_TX_DLY_INT              BIT(1)
1551 +#define RAMIPS_RX_DLY_INT              BIT(0)
1552 +
1553 +#define RT5350_RX_DLY_INT              BIT(30)
1554 +#define RT5350_TX_DLY_INT              BIT(28)
1555 +
1556 +/* registers */
1557 +#define RAMIPS_FE_OFFSET               0x0000
1558 +#define RAMIPS_GDMA_OFFSET             0x0020
1559 +#define RAMIPS_PSE_OFFSET              0x0040
1560 +#define RAMIPS_GDMA2_OFFSET            0x0060
1561 +#define RAMIPS_CDMA_OFFSET             0x0080
1562 +#define RAMIPS_PDMA_OFFSET             0x0100
1563 +#define RAMIPS_PPE_OFFSET              0x0200
1564 +#define RAMIPS_CMTABLE_OFFSET          0x0400
1565 +#define RAMIPS_POLICYTABLE_OFFSET      0x1000
1566 +
1567 +#define RT5350_PDMA_OFFSET             0x0800
1568 +#define RT5350_SDM_OFFSET              0x0c00
1569 +
1570 +#define RAMIPS_MDIO_ACCESS             (RAMIPS_FE_OFFSET + 0x00)
1571 +#define RAMIPS_MDIO_CFG                        (RAMIPS_FE_OFFSET + 0x04)
1572 +#define RAMIPS_FE_GLO_CFG              (RAMIPS_FE_OFFSET + 0x08)
1573 +#define RAMIPS_FE_RST_GL               (RAMIPS_FE_OFFSET + 0x0C)
1574 +#define RAMIPS_FE_INT_STATUS           (RAMIPS_FE_OFFSET + 0x10)
1575 +#define RAMIPS_FE_INT_ENABLE           (RAMIPS_FE_OFFSET + 0x14)
1576 +#define RAMIPS_MDIO_CFG2               (RAMIPS_FE_OFFSET + 0x18)
1577 +#define RAMIPS_FOC_TS_T                        (RAMIPS_FE_OFFSET + 0x1C)
1578 +
1579 +#define        RAMIPS_GDMA1_FWD_CFG            (RAMIPS_GDMA_OFFSET + 0x00)
1580 +#define RAMIPS_GDMA1_SCH_CFG           (RAMIPS_GDMA_OFFSET + 0x04)
1581 +#define RAMIPS_GDMA1_SHPR_CFG          (RAMIPS_GDMA_OFFSET + 0x08)
1582 +#define RAMIPS_GDMA1_MAC_ADRL          (RAMIPS_GDMA_OFFSET + 0x0C)
1583 +#define RAMIPS_GDMA1_MAC_ADRH          (RAMIPS_GDMA_OFFSET + 0x10)
1584 +
1585 +#define        RAMIPS_GDMA2_FWD_CFG            (RAMIPS_GDMA2_OFFSET + 0x00)
1586 +#define RAMIPS_GDMA2_SCH_CFG           (RAMIPS_GDMA2_OFFSET + 0x04)
1587 +#define RAMIPS_GDMA2_SHPR_CFG          (RAMIPS_GDMA2_OFFSET + 0x08)
1588 +#define RAMIPS_GDMA2_MAC_ADRL          (RAMIPS_GDMA2_OFFSET + 0x0C)
1589 +#define RAMIPS_GDMA2_MAC_ADRH          (RAMIPS_GDMA2_OFFSET + 0x10)
1590 +
1591 +#define RAMIPS_PSE_FQ_CFG              (RAMIPS_PSE_OFFSET + 0x00)
1592 +#define RAMIPS_CDMA_FC_CFG             (RAMIPS_PSE_OFFSET + 0x04)
1593 +#define RAMIPS_GDMA1_FC_CFG            (RAMIPS_PSE_OFFSET + 0x08)
1594 +#define RAMIPS_GDMA2_FC_CFG            (RAMIPS_PSE_OFFSET + 0x0C)
1595 +
1596 +#define RAMIPS_CDMA_CSG_CFG            (RAMIPS_CDMA_OFFSET + 0x00)
1597 +#define RAMIPS_CDMA_SCH_CFG            (RAMIPS_CDMA_OFFSET + 0x04)
1598 +
1599 +#define RT5350_TX_BASE_PTR0            (RT5350_PDMA_OFFSET + 0x00)
1600 +#define RT5350_TX_MAX_CNT0             (RT5350_PDMA_OFFSET + 0x04)
1601 +#define RT5350_TX_CTX_IDX0             (RT5350_PDMA_OFFSET + 0x08)
1602 +#define RT5350_TX_DTX_IDX0             (RT5350_PDMA_OFFSET + 0x0C)
1603 +#define RT5350_TX_BASE_PTR1            (RT5350_PDMA_OFFSET + 0x10)
1604 +#define RT5350_TX_MAX_CNT1             (RT5350_PDMA_OFFSET + 0x14)
1605 +#define RT5350_TX_CTX_IDX1             (RT5350_PDMA_OFFSET + 0x18)
1606 +#define RT5350_TX_DTX_IDX1             (RT5350_PDMA_OFFSET + 0x1C)
1607 +#define RT5350_TX_BASE_PTR2            (RT5350_PDMA_OFFSET + 0x20)
1608 +#define RT5350_TX_MAX_CNT2             (RT5350_PDMA_OFFSET + 0x24)
1609 +#define RT5350_TX_CTX_IDX2             (RT5350_PDMA_OFFSET + 0x28)
1610 +#define RT5350_TX_DTX_IDX2             (RT5350_PDMA_OFFSET + 0x2C)
1611 +#define RT5350_TX_BASE_PTR3            (RT5350_PDMA_OFFSET + 0x30)
1612 +#define RT5350_TX_MAX_CNT3             (RT5350_PDMA_OFFSET + 0x34)
1613 +#define RT5350_TX_CTX_IDX3             (RT5350_PDMA_OFFSET + 0x38)
1614 +#define RT5350_TX_DTX_IDX3             (RT5350_PDMA_OFFSET + 0x3C)
1615 +#define RT5350_RX_BASE_PTR0            (RT5350_PDMA_OFFSET + 0x100)
1616 +#define RT5350_RX_MAX_CNT0             (RT5350_PDMA_OFFSET + 0x104)
1617 +#define RT5350_RX_CALC_IDX0            (RT5350_PDMA_OFFSET + 0x108)
1618 +#define RT5350_RX_DRX_IDX0             (RT5350_PDMA_OFFSET + 0x10C)
1619 +#define RT5350_RX_BASE_PTR1            (RT5350_PDMA_OFFSET + 0x110)
1620 +#define RT5350_RX_MAX_CNT1             (RT5350_PDMA_OFFSET + 0x114)
1621 +#define RT5350_RX_CALC_IDX1            (RT5350_PDMA_OFFSET + 0x118)
1622 +#define RT5350_RX_DRX_IDX1             (RT5350_PDMA_OFFSET + 0x11C)
1623 +#define RT5350_PDMA_GLO_CFG            (RT5350_PDMA_OFFSET + 0x204)
1624 +#define RT5350_PDMA_RST_CFG            (RT5350_PDMA_OFFSET + 0x208)
1625 +#define RT5350_DLY_INT_CFG             (RT5350_PDMA_OFFSET + 0x20c)
1626 +#define RT5350_FE_INT_STATUS           (RT5350_PDMA_OFFSET + 0x220)
1627 +#define RT5350_FE_INT_ENABLE           (RT5350_PDMA_OFFSET + 0x228)
1628 +#define RT5350_PDMA_SCH_CFG            (RT5350_PDMA_OFFSET + 0x280)
1629 +
1630 +
1631 +#define RAMIPS_PDMA_GLO_CFG            (RAMIPS_PDMA_OFFSET + 0x00)
1632 +#define RAMIPS_PDMA_RST_CFG            (RAMIPS_PDMA_OFFSET + 0x04)
1633 +#define RAMIPS_PDMA_SCH_CFG            (RAMIPS_PDMA_OFFSET + 0x08)
1634 +#define RAMIPS_DLY_INT_CFG             (RAMIPS_PDMA_OFFSET + 0x0C)
1635 +#define RAMIPS_TX_BASE_PTR0            (RAMIPS_PDMA_OFFSET + 0x10)
1636 +#define RAMIPS_TX_MAX_CNT0             (RAMIPS_PDMA_OFFSET + 0x14)
1637 +#define RAMIPS_TX_CTX_IDX0             (RAMIPS_PDMA_OFFSET + 0x18)
1638 +#define RAMIPS_TX_DTX_IDX0             (RAMIPS_PDMA_OFFSET + 0x1C)
1639 +#define RAMIPS_TX_BASE_PTR1            (RAMIPS_PDMA_OFFSET + 0x20)
1640 +#define RAMIPS_TX_MAX_CNT1             (RAMIPS_PDMA_OFFSET + 0x24)
1641 +#define RAMIPS_TX_CTX_IDX1             (RAMIPS_PDMA_OFFSET + 0x28)
1642 +#define RAMIPS_TX_DTX_IDX1             (RAMIPS_PDMA_OFFSET + 0x2C)
1643 +#define RAMIPS_RX_BASE_PTR0            (RAMIPS_PDMA_OFFSET + 0x30)
1644 +#define RAMIPS_RX_MAX_CNT0             (RAMIPS_PDMA_OFFSET + 0x34)
1645 +#define RAMIPS_RX_CALC_IDX0            (RAMIPS_PDMA_OFFSET + 0x38)
1646 +#define RAMIPS_RX_DRX_IDX0             (RAMIPS_PDMA_OFFSET + 0x3C)
1647 +#define RAMIPS_TX_BASE_PTR2            (RAMIPS_PDMA_OFFSET + 0x40)
1648 +#define RAMIPS_TX_MAX_CNT2             (RAMIPS_PDMA_OFFSET + 0x44)
1649 +#define RAMIPS_TX_CTX_IDX2             (RAMIPS_PDMA_OFFSET + 0x48)
1650 +#define RAMIPS_TX_DTX_IDX2             (RAMIPS_PDMA_OFFSET + 0x4C)
1651 +#define RAMIPS_TX_BASE_PTR3            (RAMIPS_PDMA_OFFSET + 0x50)
1652 +#define RAMIPS_TX_MAX_CNT3             (RAMIPS_PDMA_OFFSET + 0x54)
1653 +#define RAMIPS_TX_CTX_IDX3             (RAMIPS_PDMA_OFFSET + 0x58)
1654 +#define RAMIPS_TX_DTX_IDX3             (RAMIPS_PDMA_OFFSET + 0x5C)
1655 +#define RAMIPS_RX_BASE_PTR1            (RAMIPS_PDMA_OFFSET + 0x60)
1656 +#define RAMIPS_RX_MAX_CNT1             (RAMIPS_PDMA_OFFSET + 0x64)
1657 +#define RAMIPS_RX_CALC_IDX1            (RAMIPS_PDMA_OFFSET + 0x68)
1658 +#define RAMIPS_RX_DRX_IDX1             (RAMIPS_PDMA_OFFSET + 0x6C)
1659 +
1660 +#define RT5350_SDM_CFG                 (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
1661 +#define RT5350_SDM_RRING               (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
1662 +#define RT5350_SDM_TRING               (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
1663 +#define RT5350_SDM_MAC_ADRL            (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
1664 +#define RT5350_SDM_MAC_ADRH            (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
1665 +#define RT5350_SDM_TPCNT               (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
1666 +#define RT5350_SDM_TBCNT               (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
1667 +#define RT5350_SDM_RPCNT               (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
1668 +#define RT5350_SDM_RBCNT               (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
1669 +#define RT5350_SDM_CS_ERR              (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
1670 +
1671 +#define RT5350_SDM_ICS_EN              BIT(16)
1672 +#define RT5350_SDM_TCS_EN              BIT(17)
1673 +#define RT5350_SDM_UCS_EN              BIT(18)
1674 +
1675 +
1676 +/* MDIO_CFG register bits */
1677 +#define RAMIPS_MDIO_CFG_AUTO_POLL_EN   BIT(29)
1678 +#define RAMIPS_MDIO_CFG_GP1_BP_EN      BIT(16)
1679 +#define RAMIPS_MDIO_CFG_GP1_FRC_EN     BIT(15)
1680 +#define RAMIPS_MDIO_CFG_GP1_SPEED_10   (0 << 13)
1681 +#define RAMIPS_MDIO_CFG_GP1_SPEED_100  (1 << 13)
1682 +#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
1683 +#define RAMIPS_MDIO_CFG_GP1_DUPLEX     BIT(12)
1684 +#define RAMIPS_MDIO_CFG_GP1_FC_TX      BIT(11)
1685 +#define RAMIPS_MDIO_CFG_GP1_FC_RX      BIT(10)
1686 +#define RAMIPS_MDIO_CFG_GP1_LNK_DWN    BIT(9)
1687 +#define RAMIPS_MDIO_CFG_GP1_AN_FAIL    BIT(8)
1688 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1  (0 << 6)
1689 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2  (1 << 6)
1690 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4  (2 << 6)
1691 +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8  (3 << 6)
1692 +#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5)
1693 +#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4)
1694 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0  (0 << 2)
1695 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200        (1 << 2)
1696 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400        (2 << 2)
1697 +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV        (3 << 2)
1698 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0  0
1699 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200        1
1700 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400        2
1701 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV        3
1702 +
1703 +/* uni-cast port */
1704 +#define RAMIPS_GDM1_ICS_EN             BIT(22)
1705 +#define RAMIPS_GDM1_TCS_EN             BIT(21)
1706 +#define RAMIPS_GDM1_UCS_EN             BIT(20)
1707 +#define RAMIPS_GDM1_JMB_EN             BIT(19)
1708 +#define RAMIPS_GDM1_STRPCRC            BIT(16)
1709 +#define RAMIPS_GDM1_UFRC_P_CPU         (0 << 12)
1710 +#define RAMIPS_GDM1_UFRC_P_GDMA1       (1 << 12)
1711 +#define RAMIPS_GDM1_UFRC_P_PPE         (6 << 12)
1712 +
1713 +/* checksums */
1714 +#define RAMIPS_ICS_GEN_EN              BIT(2)
1715 +#define RAMIPS_UCS_GEN_EN              BIT(1)
1716 +#define RAMIPS_TCS_GEN_EN              BIT(0)
1717 +
1718 +/* dma ring */
1719 +#define RAMIPS_PST_DRX_IDX0            BIT(16)
1720 +#define RAMIPS_PST_DTX_IDX3            BIT(3)
1721 +#define RAMIPS_PST_DTX_IDX2            BIT(2)
1722 +#define RAMIPS_PST_DTX_IDX1            BIT(1)
1723 +#define RAMIPS_PST_DTX_IDX0            BIT(0)
1724 +
1725 +#define RAMIPS_TX_WB_DDONE             BIT(6)
1726 +#define RAMIPS_RX_DMA_BUSY             BIT(3)
1727 +#define RAMIPS_TX_DMA_BUSY             BIT(1)
1728 +#define RAMIPS_RX_DMA_EN               BIT(2)
1729 +#define RAMIPS_TX_DMA_EN               BIT(0)
1730 +
1731 +#define RAMIPS_PDMA_SIZE_4DWORDS       (0 << 4)
1732 +#define RAMIPS_PDMA_SIZE_8DWORDS       (1 << 4)
1733 +#define RAMIPS_PDMA_SIZE_16DWORDS      (2 << 4)
1734 +
1735 +#define RAMIPS_US_CYC_CNT_MASK         0xff
1736 +#define RAMIPS_US_CYC_CNT_SHIFT                0x8
1737 +#define RAMIPS_US_CYC_CNT_DIVISOR      1000000
1738 +
1739 +#define RX_DMA_PLEN0(_x)               (((_x) >> 16) & 0x3fff)
1740 +#define RX_DMA_LSO                     BIT(30)
1741 +#define RX_DMA_DONE                    BIT(31)
1742 +
1743 +struct ramips_rx_dma {
1744 +       unsigned int rxd1;
1745 +       unsigned int rxd2;
1746 +       unsigned int rxd3;
1747 +       unsigned int rxd4;
1748 +} __packed __aligned(4);
1749 +
1750 +#define TX_DMA_PLEN0_MASK              ((0x3fff) << 16)
1751 +#define TX_DMA_PLEN0(_x)               (((_x) & 0x3fff) << 16)
1752 +#define TX_DMA_LSO                     BIT(30)
1753 +#define TX_DMA_DONE                    BIT(31)
1754 +#define TX_DMA_QN(_x)                  ((_x) << 16)
1755 +#define TX_DMA_PN(_x)                  ((_x) << 24)
1756 +#define TX_DMA_QN_MASK                 TX_DMA_QN(0x7)
1757 +#define TX_DMA_PN_MASK                 TX_DMA_PN(0x7)
1758 +
1759 +struct ramips_tx_dma {
1760 +       unsigned int txd1;
1761 +       unsigned int txd2;
1762 +       unsigned int txd3;
1763 +       unsigned int txd4;
1764 +} __packed __aligned(4);
1765 +
1766 +struct raeth_tx_info {
1767 +       struct ramips_tx_dma    *tx_desc;
1768 +       struct sk_buff          *tx_skb;
1769 +};
1770 +
1771 +struct raeth_rx_info {
1772 +       struct ramips_rx_dma    *rx_desc;
1773 +       struct sk_buff          *rx_skb;
1774 +       dma_addr_t              rx_dma;
1775 +       unsigned int            pad;
1776 +};
1777 +
1778 +struct raeth_int_stats {
1779 +       unsigned long           rx_delayed;
1780 +       unsigned long           tx_delayed;
1781 +       unsigned long           rx_done0;
1782 +       unsigned long           tx_done0;
1783 +       unsigned long           tx_done1;
1784 +       unsigned long           tx_done2;
1785 +       unsigned long           tx_done3;
1786 +       unsigned long           rx_coherent;
1787 +       unsigned long           tx_coherent;
1788 +
1789 +       unsigned long           pse_fq_empty;
1790 +       unsigned long           pse_p0_fc;
1791 +       unsigned long           pse_p1_fc;
1792 +       unsigned long           pse_p2_fc;
1793 +       unsigned long           pse_buf_drop;
1794 +
1795 +       unsigned long           total;
1796 +};
1797 +
1798 +struct raeth_debug {
1799 +       struct dentry           *debugfs_dir;
1800 +
1801 +       struct raeth_int_stats  int_stats;
1802 +};
1803 +
1804 +struct raeth_priv
1805 +{
1806 +       struct device_node      *of_node;
1807 +
1808 +       struct raeth_rx_info    *rx_info;
1809 +       dma_addr_t              rx_desc_dma;
1810 +       struct tasklet_struct   rx_tasklet;
1811 +       struct ramips_rx_dma    *rx;
1812 +
1813 +       struct raeth_tx_info    *tx_info;
1814 +       dma_addr_t              tx_desc_dma;
1815 +       struct tasklet_struct   tx_housekeeping_tasklet;
1816 +       struct ramips_tx_dma    *tx;
1817 +
1818 +       unsigned int            skb_free_idx;
1819 +
1820 +       spinlock_t              page_lock;
1821 +       struct net_device       *netdev;
1822 +       struct device           *parent;
1823 +
1824 +       int                     link;
1825 +       int                     speed;
1826 +       int                     duplex;
1827 +       int                     tx_fc;
1828 +       int                     rx_fc;
1829 +
1830 +       struct mii_bus          *mii_bus;
1831 +       int                     mii_irq[PHY_MAX_ADDR];
1832 +       struct phy_device       *phy_dev;
1833 +       spinlock_t              phy_lock;
1834 +       unsigned long           sys_freq;
1835 +
1836 +       unsigned char           mac[6];
1837 +       void                    (*reset_fe)(void);
1838 +       int                     min_pkt_len;
1839 +
1840 +       u32                     phy_mask;
1841 +       phy_interface_t         phy_if_mode;
1842 +
1843 +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS
1844 +       struct raeth_debug      debug;
1845 +#endif
1846 +};
1847 +
1848 +struct ramips_soc_data
1849 +{
1850 +       unsigned char mac[6];
1851 +       void (*reset_fe)(void);
1852 +       int min_pkt_len;
1853 +};
1854 +
1855 +
1856 +#ifdef CONFIG_NET_RAMIPS_DEBUG_FS
1857 +int raeth_debugfs_root_init(void);
1858 +void raeth_debugfs_root_exit(void);
1859 +int raeth_debugfs_init(struct raeth_priv *re);
1860 +void raeth_debugfs_exit(struct raeth_priv *re);
1861 +void raeth_debugfs_update_int_stats(struct raeth_priv *re, u32 status);
1862 +#else
1863 +static inline int raeth_debugfs_root_init(void) { return 0; }
1864 +static inline void raeth_debugfs_root_exit(void) {}
1865 +static inline int raeth_debugfs_init(struct raeth_priv *re) { return 0; }
1866 +static inline void raeth_debugfs_exit(struct raeth_priv *re) {}
1867 +static inline void raeth_debugfs_update_int_stats(struct raeth_priv *re,
1868 +                                                 u32 status) {}
1869 +#endif /* CONFIG_NET_RAMIPS_DEBUG_FS */
1870 +
1871 +#endif /* RAMIPS_ETH_H */
1872 Index: linux-3.8.11/drivers/net/ethernet/ramips/ramips_main.c
1873 ===================================================================
1874 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1875 +++ linux-3.8.11/drivers/net/ethernet/ramips/ramips_main.c      2013-05-06 13:55:12.572838852 +0200
1876 @@ -0,0 +1,1281 @@
1877 +/*
1878 + *   This program is free software; you can redistribute it and/or modify
1879 + *   it under the terms of the GNU General Public License as published by
1880 + *   the Free Software Foundation; version 2 of the License
1881 + *
1882 + *   This program is distributed in the hope that it will be useful,
1883 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1884 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1885 + *   GNU General Public License for more details.
1886 + *
1887 + *   You should have received a copy of the GNU General Public License
1888 + *   along with this program; if not, write to the Free Software
1889 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1890 + *
1891 + *   Copyright (C) 2009 John Crispin <blogic@openwrt.org>
1892 + */
1893 +
1894 +#include <linux/module.h>
1895 +#include <linux/kernel.h>
1896 +#include <linux/types.h>
1897 +#include <linux/dma-mapping.h>
1898 +#include <linux/init.h>
1899 +#include <linux/skbuff.h>
1900 +#include <linux/etherdevice.h>
1901 +#include <linux/ethtool.h>
1902 +#include <linux/platform_device.h>
1903 +#include <linux/phy.h>
1904 +#include <linux/of_device.h>
1905 +#include <linux/clk.h>
1906 +#include <linux/of_net.h>
1907 +#include <linux/of_mdio.h>
1908 +
1909 +#include "ramips_eth.h"
1910 +
1911 +#define TX_TIMEOUT (20 * HZ / 100)
1912 +#define        MAX_RX_LENGTH   1600
1913 +
1914 +#ifdef CONFIG_SOC_RT305X
1915 +#include <rt305x.h>
1916 +#include "ramips_esw.c"
1917 +#else
1918 +#include <asm/mach-ralink/ralink_regs.h>
1919 +static inline int rt305x_esw_init(void) { return 0; }
1920 +static inline void rt305x_esw_exit(void) { }
1921 +static inline int soc_is_rt5350(void) { return 0; }
1922 +#endif
1923 +
1924 +#define phys_to_bus(a)  (a & 0x1FFFFFFF)
1925 +
1926 +#ifdef CONFIG_NET_RAMIPS_DEBUG
1927 +#define RADEBUG(fmt, args...)  printk(KERN_DEBUG fmt, ## args)
1928 +#else
1929 +#define RADEBUG(fmt, args...)  do {} while (0)
1930 +#endif
1931 +
1932 +#define RX_DLY_INT ((soc_is_rt5350())?(RT5350_RX_DLY_INT):(RAMIPS_RX_DLY_INT))
1933 +#define TX_DLY_INT ((soc_is_rt5350())?(RT5350_TX_DLY_INT):(RAMIPS_TX_DLY_INT))
1934 +
1935 +enum raeth_reg {
1936 +       RAETH_REG_PDMA_GLO_CFG = 0,
1937 +       RAETH_REG_PDMA_RST_CFG,
1938 +       RAETH_REG_DLY_INT_CFG,
1939 +       RAETH_REG_TX_BASE_PTR0,
1940 +       RAETH_REG_TX_MAX_CNT0,
1941 +       RAETH_REG_TX_CTX_IDX0,
1942 +       RAETH_REG_RX_BASE_PTR0,
1943 +       RAETH_REG_RX_MAX_CNT0,
1944 +       RAETH_REG_RX_CALC_IDX0,
1945 +       RAETH_REG_FE_INT_ENABLE,
1946 +       RAETH_REG_FE_INT_STATUS,
1947 +       RAETH_REG_COUNT
1948 +};
1949 +
1950 +static const u32 ramips_reg_table[RAETH_REG_COUNT] = {
1951 +       [RAETH_REG_PDMA_GLO_CFG] = RAMIPS_PDMA_GLO_CFG,
1952 +       [RAETH_REG_PDMA_RST_CFG] = RAMIPS_PDMA_RST_CFG,
1953 +       [RAETH_REG_DLY_INT_CFG] = RAMIPS_DLY_INT_CFG,
1954 +       [RAETH_REG_TX_BASE_PTR0] = RAMIPS_TX_BASE_PTR0,
1955 +       [RAETH_REG_TX_MAX_CNT0] = RAMIPS_TX_MAX_CNT0,
1956 +       [RAETH_REG_TX_CTX_IDX0] = RAMIPS_TX_CTX_IDX0,
1957 +       [RAETH_REG_RX_BASE_PTR0] = RAMIPS_RX_BASE_PTR0,
1958 +       [RAETH_REG_RX_MAX_CNT0] = RAMIPS_RX_MAX_CNT0,
1959 +       [RAETH_REG_RX_CALC_IDX0] = RAMIPS_RX_CALC_IDX0,
1960 +       [RAETH_REG_FE_INT_ENABLE] = RAMIPS_FE_INT_ENABLE,
1961 +       [RAETH_REG_FE_INT_STATUS] = RAMIPS_FE_INT_STATUS,
1962 +};
1963 +
1964 +static const u32 rt5350_reg_table[RAETH_REG_COUNT] = {
1965 +       [RAETH_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
1966 +       [RAETH_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
1967 +       [RAETH_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
1968 +       [RAETH_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
1969 +       [RAETH_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
1970 +       [RAETH_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
1971 +       [RAETH_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
1972 +       [RAETH_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
1973 +       [RAETH_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
1974 +       [RAETH_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
1975 +       [RAETH_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
1976 +};
1977 +
1978 +static struct net_device * ramips_dev;
1979 +static void __iomem *ramips_fe_base = 0;
1980 +
1981 +static inline u32 get_reg_offset(enum raeth_reg reg)
1982 +{
1983 +       const u32 *table;
1984 +
1985 +       if (soc_is_rt5350())
1986 +               table = rt5350_reg_table;
1987 +       else
1988 +               table = ramips_reg_table;
1989 +
1990 +       return table[reg];
1991 +}
1992 +
1993 +static inline void
1994 +ramips_fe_wr(u32 val, unsigned reg)
1995 +{
1996 +       __raw_writel(val, ramips_fe_base + reg);
1997 +}
1998 +
1999 +static inline u32
2000 +ramips_fe_rr(unsigned reg)
2001 +{
2002 +       return __raw_readl(ramips_fe_base + reg);
2003 +}
2004 +
2005 +static inline void
2006 +ramips_fe_twr(u32 val, enum raeth_reg reg)
2007 +{
2008 +       ramips_fe_wr(val, get_reg_offset(reg));
2009 +}
2010 +
2011 +static inline u32
2012 +ramips_fe_trr(enum raeth_reg reg)
2013 +{
2014 +       return ramips_fe_rr(get_reg_offset(reg));
2015 +}
2016 +
2017 +static inline void
2018 +ramips_fe_int_disable(u32 mask)
2019 +{
2020 +       ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) & ~mask,
2021 +                    RAETH_REG_FE_INT_ENABLE);
2022 +       /* flush write */
2023 +       ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2024 +}
2025 +
2026 +static inline void
2027 +ramips_fe_int_enable(u32 mask)
2028 +{
2029 +       ramips_fe_twr(ramips_fe_trr(RAETH_REG_FE_INT_ENABLE) | mask,
2030 +                    RAETH_REG_FE_INT_ENABLE);
2031 +       /* flush write */
2032 +       ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2033 +}
2034 +
2035 +static inline void
2036 +ramips_hw_set_macaddr(unsigned char *mac)
2037 +{
2038 +       if (soc_is_rt5350()) {
2039 +               ramips_fe_wr((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
2040 +               ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2041 +                            RT5350_SDM_MAC_ADRL);
2042 +       } else {
2043 +               ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH);
2044 +               ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2045 +                            RAMIPS_GDMA1_MAC_ADRL);
2046 +       }
2047 +}
2048 +
2049 +static struct sk_buff *
2050 +ramips_alloc_skb(struct raeth_priv *re)
2051 +{
2052 +       struct sk_buff *skb;
2053 +
2054 +       skb = netdev_alloc_skb(re->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
2055 +       if (!skb)
2056 +               return NULL;
2057 +
2058 +       skb_reserve(skb, NET_IP_ALIGN);
2059 +
2060 +       return skb;
2061 +}
2062 +
2063 +static void
2064 +ramips_ring_setup(struct raeth_priv *re)
2065 +{
2066 +       int len;
2067 +       int i;
2068 +
2069 +       memset(re->tx_info, 0, NUM_TX_DESC * sizeof(struct raeth_tx_info));
2070 +
2071 +       len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2072 +       memset(re->tx, 0, len);
2073 +
2074 +       for (i = 0; i < NUM_TX_DESC; i++) {
2075 +               struct raeth_tx_info *txi;
2076 +               struct ramips_tx_dma *txd;
2077 +
2078 +               txd = &re->tx[i];
2079 +               txd->txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
2080 +               txd->txd2 = TX_DMA_LSO | TX_DMA_DONE;
2081 +
2082 +               txi = &re->tx_info[i];
2083 +               txi->tx_desc = txd;
2084 +               if (txi->tx_skb != NULL) {
2085 +                       netdev_warn(re->netdev,
2086 +                                   "dirty skb for TX desc %d\n", i);
2087 +                       txi->tx_skb = NULL;
2088 +               }
2089 +       }
2090 +
2091 +       len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2092 +       memset(re->rx, 0, len);
2093 +
2094 +       for (i = 0; i < NUM_RX_DESC; i++) {
2095 +               struct raeth_rx_info *rxi;
2096 +               struct ramips_rx_dma *rxd;
2097 +               dma_addr_t dma_addr;
2098 +
2099 +               rxd = &re->rx[i];
2100 +               rxi = &re->rx_info[i];
2101 +               BUG_ON(rxi->rx_skb == NULL);
2102 +               dma_addr = dma_map_single(&re->netdev->dev, rxi->rx_skb->data,
2103 +                                         MAX_RX_LENGTH, DMA_FROM_DEVICE);
2104 +               rxi->rx_dma = dma_addr;
2105 +               rxi->rx_desc = rxd;
2106 +
2107 +               rxd->rxd1 = (unsigned int) dma_addr;
2108 +               rxd->rxd2 = RX_DMA_LSO;
2109 +       }
2110 +
2111 +       /* flush descriptors */
2112 +       wmb();
2113 +}
2114 +
2115 +static void
2116 +ramips_ring_cleanup(struct raeth_priv *re)
2117 +{
2118 +       int i;
2119 +
2120 +       for (i = 0; i < NUM_RX_DESC; i++) {
2121 +               struct raeth_rx_info *rxi;
2122 +
2123 +               rxi = &re->rx_info[i];
2124 +               if (rxi->rx_skb)
2125 +                       dma_unmap_single(&re->netdev->dev, rxi->rx_dma,
2126 +                                        MAX_RX_LENGTH, DMA_FROM_DEVICE);
2127 +       }
2128 +
2129 +       for (i = 0; i < NUM_TX_DESC; i++) {
2130 +               struct raeth_tx_info *txi;
2131 +
2132 +               txi = &re->tx_info[i];
2133 +               if (txi->tx_skb) {
2134 +                       dev_kfree_skb_any(txi->tx_skb);
2135 +                       txi->tx_skb = NULL;
2136 +               }
2137 +       }
2138 +
2139 +       netdev_reset_queue(re->netdev);
2140 +}
2141 +
2142 +#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT3883)
2143 +
2144 +#define RAMIPS_MDIO_RETRY      1000
2145 +
2146 +static unsigned char *ramips_speed_str(struct raeth_priv *re)
2147 +{
2148 +       switch (re->speed) {
2149 +       case SPEED_1000:
2150 +               return "1000";
2151 +       case SPEED_100:
2152 +               return "100";
2153 +       case SPEED_10:
2154 +               return "10";
2155 +       }
2156 +
2157 +       return "?";
2158 +}
2159 +
2160 +static void ramips_link_adjust(struct raeth_priv *re)
2161 +{
2162 +       u32 mdio_cfg;
2163 +
2164 +       if (!re->link) {
2165 +               netif_carrier_off(re->netdev);
2166 +               netdev_info(re->netdev, "link down\n");
2167 +               return;
2168 +       }
2169 +
2170 +       mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
2171 +                  RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 |
2172 +                  RAMIPS_MDIO_CFG_GP1_FRC_EN;
2173 +
2174 +       if (re->duplex == DUPLEX_FULL)
2175 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX;
2176 +
2177 +       if (re->tx_fc)
2178 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX;
2179 +
2180 +       if (re->rx_fc)
2181 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX;
2182 +
2183 +       switch (re->speed) {
2184 +       case SPEED_10:
2185 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10;
2186 +               break;
2187 +       case SPEED_100:
2188 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100;
2189 +               break;
2190 +       case SPEED_1000:
2191 +               mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000;
2192 +               break;
2193 +       default:
2194 +               BUG();
2195 +       }
2196 +
2197 +       ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG);
2198 +
2199 +       netif_carrier_on(re->netdev);
2200 +       netdev_info(re->netdev, "link up (%sMbps/%s duplex)\n",
2201 +                   ramips_speed_str(re),
2202 +                   (DUPLEX_FULL == re->duplex) ? "Full" : "Half");
2203 +}
2204 +
2205 +static int
2206 +ramips_mdio_wait_ready(struct raeth_priv *re)
2207 +{
2208 +       int retries;
2209 +
2210 +       retries = RAMIPS_MDIO_RETRY;
2211 +       while (1) {
2212 +               u32 t;
2213 +
2214 +               t = ramips_fe_rr(RAMIPS_MDIO_ACCESS);
2215 +               if ((t & (0x1 << 31)) == 0)
2216 +                       return 0;
2217 +
2218 +               if (retries-- == 0)
2219 +                       break;
2220 +
2221 +               udelay(1);
2222 +       }
2223 +
2224 +       dev_err(re->parent, "MDIO operation timed out\n");
2225 +       return -ETIMEDOUT;
2226 +}
2227 +
2228 +static int
2229 +ramips_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2230 +{
2231 +       struct raeth_priv *re = bus->priv;
2232 +       int err;
2233 +       u32 t;
2234 +
2235 +       err = ramips_mdio_wait_ready(re);
2236 +       if (err)
2237 +               return 0xffff;
2238 +
2239 +       t = (phy_addr << 24) | (phy_reg << 16);
2240 +       ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2241 +       t |= (1 << 31);
2242 +       ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2243 +
2244 +       err = ramips_mdio_wait_ready(re);
2245 +       if (err)
2246 +               return 0xffff;
2247 +
2248 +       RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2249 +               phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
2250 +
2251 +       return ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff;
2252 +}
2253 +
2254 +static int
2255 +ramips_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2256 +{
2257 +       struct raeth_priv *re = bus->priv;
2258 +       int err;
2259 +       u32 t;
2260 +
2261 +       RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2262 +               phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
2263 +
2264 +       err = ramips_mdio_wait_ready(re);
2265 +       if (err)
2266 +               return err;
2267 +
2268 +       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2269 +       ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2270 +       t |= (1 << 31);
2271 +       ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
2272 +
2273 +       return ramips_mdio_wait_ready(re);
2274 +}
2275 +
2276 +static int
2277 +ramips_mdio_reset(struct mii_bus *bus)
2278 +{
2279 +       /* TODO */
2280 +       return 0;
2281 +}
2282 +
2283 +static int
2284 +ramips_mdio_init(struct raeth_priv *re)
2285 +{
2286 +       struct device_node *mii_np;
2287 +       int err;
2288 +
2289 +       mii_np = of_get_child_by_name(re->of_node, "mdio-bus");
2290 +       if (!mii_np) {
2291 +               dev_err(re->parent, "no %s child node found", "mdio-bus");
2292 +               return -ENODEV;
2293 +       }
2294 +
2295 +       if (!of_device_is_available(mii_np)) {
2296 +               err = 0;
2297 +               goto err_put_node;
2298 +       }
2299 +
2300 +       re->mii_bus = mdiobus_alloc();
2301 +       if (re->mii_bus == NULL) {
2302 +               err = -ENOMEM;
2303 +               goto err_put_node;
2304 +       }
2305 +
2306 +       re->mii_bus->name = "ramips_mdio";
2307 +       re->mii_bus->read = ramips_mdio_read;
2308 +       re->mii_bus->write = ramips_mdio_write;
2309 +       re->mii_bus->reset = ramips_mdio_reset;
2310 +       re->mii_bus->irq = re->mii_irq;
2311 +       re->mii_bus->priv = re;
2312 +       re->mii_bus->parent = re->parent;
2313 +
2314 +       snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio");
2315 +       err = of_mdiobus_register(re->mii_bus, mii_np);
2316 +       if (err)
2317 +               goto err_free_bus;
2318 +
2319 +       return 0;
2320 +
2321 +err_free_bus:
2322 +       kfree(re->mii_bus);
2323 +err_put_node:
2324 +       of_node_put(mii_np);
2325 +       re->mii_bus = NULL;
2326 +       return err;
2327 +}
2328 +
2329 +static void
2330 +ramips_mdio_cleanup(struct raeth_priv *re)
2331 +{
2332 +       if (!re->mii_bus)
2333 +               return;
2334 +
2335 +       mdiobus_unregister(re->mii_bus);
2336 +       of_node_put(re->mii_bus->dev.of_node);
2337 +       kfree(re->mii_bus);
2338 +}
2339 +
2340 +static void
2341 +ramips_phy_link_adjust(struct net_device *dev)
2342 +{
2343 +       struct raeth_priv *re = netdev_priv(dev);
2344 +       struct phy_device *phydev = re->phy_dev;
2345 +       unsigned long flags;
2346 +       int status_change = 0;
2347 +
2348 +       spin_lock_irqsave(&re->phy_lock, flags);
2349 +
2350 +       if (phydev->link)
2351 +               if (re->duplex != phydev->duplex ||
2352 +                   re->speed != phydev->speed)
2353 +                       status_change = 1;
2354 +
2355 +       if (phydev->link != re->link)
2356 +               status_change = 1;
2357 +
2358 +       re->link = phydev->link;
2359 +       re->duplex = phydev->duplex;
2360 +       re->speed = phydev->speed;
2361 +
2362 +       if (status_change)
2363 +               ramips_link_adjust(re);
2364 +
2365 +       spin_unlock_irqrestore(&re->phy_lock, flags);
2366 +}
2367 +
2368 +static int
2369 +ramips_phy_connect_by_node(struct raeth_priv *re, struct device_node *phy_node)
2370 +{
2371 +       struct phy_device *phydev;
2372 +       int phy_mode;
2373 +
2374 +       phy_mode = of_get_phy_mode(re->of_node);
2375 +       if (phy_mode < 0) {
2376 +               dev_err(re->parent, "incorrect phy-mode\n");
2377 +               return -EINVAL;
2378 +       }
2379 +
2380 +       phydev = of_phy_connect(re->netdev, phy_node, ramips_phy_link_adjust,
2381 +                               0, phy_mode);
2382 +       if (IS_ERR(phydev)) {
2383 +               dev_err(re->parent, "could not connect to PHY\n");
2384 +               return PTR_ERR(re->phy_dev);
2385 +       }
2386 +
2387 +       phydev->supported &= PHY_GBIT_FEATURES;
2388 +       phydev->advertising = phydev->supported;
2389 +
2390 +       dev_info(re->parent,
2391 +                "connected to PHY at %s [uid=%08x, driver=%s]\n",
2392 +                dev_name(&phydev->dev), phydev->phy_id,
2393 +                phydev->drv->name);
2394 +
2395 +       re->phy_dev = phydev;
2396 +       re->link = 0;
2397 +       re->speed = 0;
2398 +       re->duplex = -1;
2399 +       re->rx_fc = 0;
2400 +       re->tx_fc = 0;
2401 +
2402 +       return 0;
2403 +}
2404 +
2405 +static int
2406 +ramips_phy_connect_fixed(struct raeth_priv *re, const __be32 *link, int size)
2407 +{
2408 +       if (size != (4 * sizeof(*link))) {
2409 +               dev_err(re->parent, "invalid fixed-link property\n");
2410 +               return -EINVAL;
2411 +       }
2412 +
2413 +       re->speed = be32_to_cpup(link++);
2414 +       re->duplex = be32_to_cpup(link++);
2415 +       re->tx_fc = be32_to_cpup(link++);
2416 +       re->rx_fc = be32_to_cpup(link++);
2417 +
2418 +       switch (re->speed) {
2419 +       case SPEED_10:
2420 +       case SPEED_100:
2421 +       case SPEED_1000:
2422 +               break;
2423 +       default:
2424 +               dev_err(re->parent, "invalid link speed: %d\n", re->speed);
2425 +               return -EINVAL;
2426 +       }
2427 +
2428 +       dev_info(re->parent, "using fixed link parameters\n");
2429 +       return 0;
2430 +}
2431 +
2432 +static int
2433 +ramips_phy_connect(struct raeth_priv *re)
2434 +{
2435 +       struct device_node *phy_node;
2436 +       const __be32 *p32;
2437 +       int size;
2438 +
2439 +       phy_node = of_parse_phandle(re->of_node, "phy-handle", 0);
2440 +       if (phy_node)
2441 +               return ramips_phy_connect_by_node(re, phy_node);
2442 +
2443 +       p32 = of_get_property(re->of_node, "ralink,fixed-link", &size);
2444 +       if (p32)
2445 +               return ramips_phy_connect_fixed(re, p32, size);
2446 +
2447 +       dev_err(re->parent, "unable to get connection type\n");
2448 +       return -EINVAL;
2449 +}
2450 +
2451 +static void
2452 +ramips_phy_disconnect(struct raeth_priv *re)
2453 +{
2454 +       if (re->phy_dev)
2455 +               phy_disconnect(re->phy_dev);
2456 +}
2457 +
2458 +static void
2459 +ramips_phy_start(struct raeth_priv *re)
2460 +{
2461 +       unsigned long flags;
2462 +
2463 +       if (re->phy_dev) {
2464 +               phy_start(re->phy_dev);
2465 +       } else {
2466 +               spin_lock_irqsave(&re->phy_lock, flags);
2467 +               re->link = 1;
2468 +               ramips_link_adjust(re);
2469 +               spin_unlock_irqrestore(&re->phy_lock, flags);
2470 +       }
2471 +}
2472 +
2473 +static void
2474 +ramips_phy_stop(struct raeth_priv *re)
2475 +{
2476 +       unsigned long flags;
2477 +
2478 +       if (re->phy_dev)
2479 +               phy_stop(re->phy_dev);
2480 +
2481 +       spin_lock_irqsave(&re->phy_lock, flags);
2482 +       re->link = 0;
2483 +       ramips_link_adjust(re);
2484 +       spin_unlock_irqrestore(&re->phy_lock, flags);
2485 +}
2486 +#else
2487 +static inline int
2488 +ramips_mdio_init(struct raeth_priv *re)
2489 +{
2490 +       return 0;
2491 +}
2492 +
2493 +static inline void
2494 +ramips_mdio_cleanup(struct raeth_priv *re)
2495 +{
2496 +}
2497 +
2498 +static inline int
2499 +ramips_phy_connect(struct raeth_priv *re)
2500 +{
2501 +       return 0;
2502 +}
2503 +
2504 +static inline void
2505 +ramips_phy_disconnect(struct raeth_priv *re)
2506 +{
2507 +}
2508 +
2509 +static inline void
2510 +ramips_phy_start(struct raeth_priv *re)
2511 +{
2512 +}
2513 +
2514 +static inline void
2515 +ramips_phy_stop(struct raeth_priv *re)
2516 +{
2517 +}
2518 +#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT3883 */
2519 +
2520 +static void
2521 +ramips_ring_free(struct raeth_priv *re)
2522 +{
2523 +       int len;
2524 +       int i;
2525 +
2526 +       if (re->rx_info) {
2527 +               for (i = 0; i < NUM_RX_DESC; i++) {
2528 +                       struct raeth_rx_info *rxi;
2529 +
2530 +                       rxi = &re->rx_info[i];
2531 +                       if (rxi->rx_skb)
2532 +                               dev_kfree_skb_any(rxi->rx_skb);
2533 +               }
2534 +               kfree(re->rx_info);
2535 +       }
2536 +
2537 +       if (re->rx) {
2538 +               len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2539 +               dma_free_coherent(&re->netdev->dev, len, re->rx,
2540 +                                 re->rx_desc_dma);
2541 +       }
2542 +
2543 +       if (re->tx) {
2544 +               len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2545 +               dma_free_coherent(&re->netdev->dev, len, re->tx,
2546 +                                 re->tx_desc_dma);
2547 +       }
2548 +
2549 +       kfree(re->tx_info);
2550 +}
2551 +
2552 +static int
2553 +ramips_ring_alloc(struct raeth_priv *re)
2554 +{
2555 +       int len;
2556 +       int err = -ENOMEM;
2557 +       int i;
2558 +
2559 +       re->tx_info = kzalloc(NUM_TX_DESC * sizeof(struct raeth_tx_info),
2560 +                             GFP_ATOMIC);
2561 +       if (!re->tx_info)
2562 +               goto err_cleanup;
2563 +
2564 +       re->rx_info = kzalloc(NUM_RX_DESC * sizeof(struct raeth_rx_info),
2565 +                             GFP_ATOMIC);
2566 +       if (!re->rx_info)
2567 +               goto err_cleanup;
2568 +
2569 +       /* allocate tx ring */
2570 +       len = NUM_TX_DESC * sizeof(struct ramips_tx_dma);
2571 +       re->tx = dma_alloc_coherent(&re->netdev->dev, len,
2572 +                                         &re->tx_desc_dma, GFP_ATOMIC);
2573 +       if (!re->tx)
2574 +               goto err_cleanup;
2575 +
2576 +       /* allocate rx ring */
2577 +       len = NUM_RX_DESC * sizeof(struct ramips_rx_dma);
2578 +       re->rx = dma_alloc_coherent(&re->netdev->dev, len,
2579 +                                   &re->rx_desc_dma, GFP_ATOMIC);
2580 +       if (!re->rx)
2581 +               goto err_cleanup;
2582 +
2583 +       for (i = 0; i < NUM_RX_DESC; i++) {
2584 +               struct sk_buff *skb;
2585 +
2586 +               skb = ramips_alloc_skb(re);
2587 +               if (!skb)
2588 +                       goto err_cleanup;
2589 +
2590 +               re->rx_info[i].rx_skb = skb;
2591 +       }
2592 +
2593 +       return 0;
2594 +
2595 +err_cleanup:
2596 +       ramips_ring_free(re);
2597 +       return err;
2598 +}
2599 +
2600 +static void
2601 +ramips_setup_dma(struct raeth_priv *re)
2602 +{
2603 +       ramips_fe_twr(re->tx_desc_dma, RAETH_REG_TX_BASE_PTR0);
2604 +       ramips_fe_twr(NUM_TX_DESC, RAETH_REG_TX_MAX_CNT0);
2605 +       ramips_fe_twr(0, RAETH_REG_TX_CTX_IDX0);
2606 +       ramips_fe_twr(RAMIPS_PST_DTX_IDX0, RAETH_REG_PDMA_RST_CFG);
2607 +
2608 +       ramips_fe_twr(re->rx_desc_dma, RAETH_REG_RX_BASE_PTR0);
2609 +       ramips_fe_twr(NUM_RX_DESC, RAETH_REG_RX_MAX_CNT0);
2610 +       ramips_fe_twr((NUM_RX_DESC - 1), RAETH_REG_RX_CALC_IDX0);
2611 +       ramips_fe_twr(RAMIPS_PST_DRX_IDX0, RAETH_REG_PDMA_RST_CFG);
2612 +}
2613 +
2614 +static int
2615 +ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
2616 +{
2617 +       struct raeth_priv *re = netdev_priv(dev);
2618 +       struct raeth_tx_info *txi, *txi_next;
2619 +       struct ramips_tx_dma *txd, *txd_next;
2620 +       unsigned long tx;
2621 +       unsigned int tx_next;
2622 +       dma_addr_t mapped_addr;
2623 +
2624 +       if (re->min_pkt_len) {
2625 +               if (skb->len < re->min_pkt_len) {
2626 +                       if (skb_padto(skb, re->min_pkt_len)) {
2627 +                               printk(KERN_ERR
2628 +                                      "ramips_eth: skb_padto failed\n");
2629 +                               kfree_skb(skb);
2630 +                               return 0;
2631 +                       }
2632 +                       skb_put(skb, re->min_pkt_len - skb->len);
2633 +               }
2634 +       }
2635 +
2636 +       dev->trans_start = jiffies;
2637 +       mapped_addr = dma_map_single(&re->netdev->dev, skb->data, skb->len,
2638 +                                    DMA_TO_DEVICE);
2639 +
2640 +       spin_lock(&re->page_lock);
2641 +       tx = ramips_fe_trr(RAETH_REG_TX_CTX_IDX0);
2642 +       tx_next = (tx + 1) % NUM_TX_DESC;
2643 +
2644 +       txi = &re->tx_info[tx];
2645 +       txd = txi->tx_desc;
2646 +       txi_next = &re->tx_info[tx_next];
2647 +       txd_next = txi_next->tx_desc;
2648 +
2649 +       if ((txi->tx_skb) || (txi_next->tx_skb) ||
2650 +           !(txd->txd2 & TX_DMA_DONE) ||
2651 +           !(txd_next->txd2 & TX_DMA_DONE))
2652 +               goto out;
2653 +
2654 +       txi->tx_skb = skb;
2655 +
2656 +       txd->txd1 = (unsigned int) mapped_addr;
2657 +       wmb();
2658 +       txd->txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
2659 +       dev->stats.tx_packets++;
2660 +       dev->stats.tx_bytes += skb->len;
2661 +       ramips_fe_twr(tx_next, RAETH_REG_TX_CTX_IDX0);
2662 +       netdev_sent_queue(dev, skb->len);
2663 +       spin_unlock(&re->page_lock);
2664 +       return NETDEV_TX_OK;
2665 +
2666 + out:
2667 +       spin_unlock(&re->page_lock);
2668 +       dev->stats.tx_dropped++;
2669 +       kfree_skb(skb);
2670 +       return NETDEV_TX_OK;
2671 +}
2672 +
2673 +static void
2674 +ramips_eth_rx_hw(unsigned long ptr)
2675 +{
2676 +       struct net_device *dev = (struct net_device *) ptr;
2677 +       struct raeth_priv *re = netdev_priv(dev);
2678 +       int rx;
2679 +       int max_rx = 16;
2680 +
2681 +       rx = ramips_fe_trr(RAETH_REG_RX_CALC_IDX0);
2682 +
2683 +       while (max_rx) {
2684 +               struct raeth_rx_info *rxi;
2685 +               struct ramips_rx_dma *rxd;
2686 +               struct sk_buff *rx_skb, *new_skb;
2687 +               int pktlen;
2688 +
2689 +               rx = (rx + 1) % NUM_RX_DESC;
2690 +
2691 +               rxi = &re->rx_info[rx];
2692 +               rxd = rxi->rx_desc;
2693 +               if (!(rxd->rxd2 & RX_DMA_DONE))
2694 +                       break;
2695 +
2696 +               rx_skb = rxi->rx_skb;
2697 +               pktlen = RX_DMA_PLEN0(rxd->rxd2);
2698 +
2699 +               new_skb = ramips_alloc_skb(re);
2700 +               /* Reuse the buffer on allocation failures */
2701 +               if (new_skb) {
2702 +                       dma_addr_t dma_addr;
2703 +
2704 +                       dma_unmap_single(&re->netdev->dev, rxi->rx_dma,
2705 +                                        MAX_RX_LENGTH, DMA_FROM_DEVICE);
2706 +
2707 +                       skb_put(rx_skb, pktlen);
2708 +                       rx_skb->dev = dev;
2709 +                       rx_skb->protocol = eth_type_trans(rx_skb, dev);
2710 +                       rx_skb->ip_summed = CHECKSUM_NONE;
2711 +                       dev->stats.rx_packets++;
2712 +                       dev->stats.rx_bytes += pktlen;
2713 +                       netif_rx(rx_skb);
2714 +
2715 +                       rxi->rx_skb = new_skb;
2716 +
2717 +                       dma_addr = dma_map_single(&re->netdev->dev,
2718 +                                                 new_skb->data,
2719 +                                                 MAX_RX_LENGTH,
2720 +                                                 DMA_FROM_DEVICE);
2721 +                       rxi->rx_dma = dma_addr;
2722 +                       rxd->rxd1 = (unsigned int) dma_addr;
2723 +                       wmb();
2724 +               } else {
2725 +                       dev->stats.rx_dropped++;
2726 +               }
2727 +
2728 +               rxd->rxd2 = RX_DMA_LSO;
2729 +               ramips_fe_twr(rx, RAETH_REG_RX_CALC_IDX0);
2730 +               max_rx--;
2731 +       }
2732 +
2733 +       if (max_rx == 0)
2734 +               tasklet_schedule(&re->rx_tasklet);
2735 +       else
2736 +               ramips_fe_int_enable(RX_DLY_INT);
2737 +}
2738 +
2739 +static void
2740 +ramips_eth_tx_housekeeping(unsigned long ptr)
2741 +{
2742 +       struct net_device *dev = (struct net_device*)ptr;
2743 +       struct raeth_priv *re = netdev_priv(dev);
2744 +       unsigned int bytes_compl = 0, pkts_compl = 0;
2745 +
2746 +       spin_lock(&re->page_lock);
2747 +       while (1) {
2748 +               struct raeth_tx_info *txi;
2749 +               struct ramips_tx_dma *txd;
2750 +
2751 +               txi = &re->tx_info[re->skb_free_idx];
2752 +               txd = txi->tx_desc;
2753 +
2754 +               if (!(txd->txd2 & TX_DMA_DONE) || !(txi->tx_skb))
2755 +                       break;
2756 +
2757 +               pkts_compl++;
2758 +               bytes_compl += txi->tx_skb->len;
2759 +
2760 +               dev_kfree_skb_irq(txi->tx_skb);
2761 +               txi->tx_skb = NULL;
2762 +               re->skb_free_idx++;
2763 +               if (re->skb_free_idx >= NUM_TX_DESC)
2764 +                       re->skb_free_idx = 0;
2765 +       }
2766 +       netdev_completed_queue(dev, pkts_compl, bytes_compl);
2767 +       spin_unlock(&re->page_lock);
2768 +
2769 +       ramips_fe_int_enable(TX_DLY_INT);
2770 +}
2771 +
2772 +static void
2773 +ramips_eth_timeout(struct net_device *dev)
2774 +{
2775 +       struct raeth_priv *re = netdev_priv(dev);
2776 +
2777 +       tasklet_schedule(&re->tx_housekeeping_tasklet);
2778 +}
2779 +
2780 +static irqreturn_t
2781 +ramips_eth_irq(int irq, void *dev)
2782 +{
2783 +       struct raeth_priv *re = netdev_priv(dev);
2784 +       unsigned int status;
2785 +
2786 +       status = ramips_fe_trr(RAETH_REG_FE_INT_STATUS);
2787 +       status &= ramips_fe_trr(RAETH_REG_FE_INT_ENABLE);
2788 +
2789 +       if (!status)
2790 +               return IRQ_NONE;
2791 +
2792 +       ramips_fe_twr(status, RAETH_REG_FE_INT_STATUS);
2793 +
2794 +       if (status & RX_DLY_INT) {
2795 +               ramips_fe_int_disable(RX_DLY_INT);
2796 +               tasklet_schedule(&re->rx_tasklet);
2797 +       }
2798 +
2799 +       if (status & TX_DLY_INT) {
2800 +               ramips_fe_int_disable(TX_DLY_INT);
2801 +               tasklet_schedule(&re->tx_housekeeping_tasklet);
2802 +       }
2803 +
2804 +       raeth_debugfs_update_int_stats(re, status);
2805 +
2806 +       return IRQ_HANDLED;
2807 +}
2808 +
2809 +static int
2810 +ramips_eth_hw_init(struct net_device *dev)
2811 +{
2812 +       struct raeth_priv *re = netdev_priv(dev);
2813 +       int err;
2814 +
2815 +       err = request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED,
2816 +                         dev_name(re->parent), dev);
2817 +       if (err)
2818 +               return err;
2819 +
2820 +       err = ramips_ring_alloc(re);
2821 +       if (err)
2822 +               goto err_free_irq;
2823 +
2824 +       ramips_ring_setup(re);
2825 +       ramips_hw_set_macaddr(dev->dev_addr);
2826 +
2827 +       ramips_setup_dma(re);
2828 +       ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) &
2829 +               ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) |
2830 +               ((re->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT),
2831 +               RAMIPS_FE_GLO_CFG);
2832 +
2833 +       tasklet_init(&re->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping,
2834 +                    (unsigned long)dev);
2835 +       tasklet_init(&re->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev);
2836 +
2837 +
2838 +       ramips_fe_twr(RAMIPS_DELAY_INIT, RAETH_REG_DLY_INT_CFG);
2839 +       ramips_fe_twr(TX_DLY_INT | RX_DLY_INT, RAETH_REG_FE_INT_ENABLE);
2840 +       if (soc_is_rt5350()) {
2841 +               ramips_fe_wr(ramips_fe_rr(RT5350_SDM_CFG) &
2842 +                       ~(RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN | 0xffff),
2843 +                       RT5350_SDM_CFG);
2844 +       } else {
2845 +               ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
2846 +                       ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff),
2847 +                       RAMIPS_GDMA1_FWD_CFG);
2848 +               ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) &
2849 +                       ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN),
2850 +                       RAMIPS_CDMA_CSG_CFG);
2851 +               ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG);
2852 +       }
2853 +       ramips_fe_wr(1, RAMIPS_FE_RST_GL);
2854 +       ramips_fe_wr(0, RAMIPS_FE_RST_GL);
2855 +
2856 +       return 0;
2857 +
2858 +err_free_irq:
2859 +       free_irq(dev->irq, dev);
2860 +       return err;
2861 +}
2862 +
2863 +static int
2864 +ramips_eth_open(struct net_device *dev)
2865 +{
2866 +       struct raeth_priv *re = netdev_priv(dev);
2867 +
2868 +       ramips_fe_twr((ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) & 0xff) |
2869 +               (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN |
2870 +               RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS),
2871 +               RAETH_REG_PDMA_GLO_CFG);
2872 +       ramips_phy_start(re);
2873 +       netif_start_queue(dev);
2874 +       return 0;
2875 +}
2876 +
2877 +static int
2878 +ramips_eth_stop(struct net_device *dev)
2879 +{
2880 +       struct raeth_priv *re = netdev_priv(dev);
2881 +
2882 +       ramips_fe_twr(ramips_fe_trr(RAETH_REG_PDMA_GLO_CFG) &
2883 +                    ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN),
2884 +                    RAETH_REG_PDMA_GLO_CFG);
2885 +
2886 +       netif_stop_queue(dev);
2887 +       ramips_phy_stop(re);
2888 +       RADEBUG("ramips_eth: stopped\n");
2889 +       return 0;
2890 +}
2891 +
2892 +static int __init
2893 +ramips_eth_probe(struct net_device *dev)
2894 +{
2895 +       struct raeth_priv *re = netdev_priv(dev);
2896 +       int err;
2897 +
2898 +       BUG_ON(!re->reset_fe);
2899 +       re->reset_fe();
2900 +       net_srandom(jiffies);
2901 +       memcpy(dev->dev_addr, re->mac, ETH_ALEN);
2902 +       of_get_mac_address_mtd(re->of_node, dev->dev_addr);
2903 +       ether_setup(dev);
2904 +       dev->mtu = 1500;
2905 +       dev->watchdog_timeo = TX_TIMEOUT;
2906 +       spin_lock_init(&re->page_lock);
2907 +       spin_lock_init(&re->phy_lock);
2908 +
2909 +       err = ramips_mdio_init(re);
2910 +       if (err)
2911 +               return err;
2912 +
2913 +       err = ramips_phy_connect(re);
2914 +       if (err)
2915 +               goto err_mdio_cleanup;
2916 +
2917 +       err = raeth_debugfs_init(re);
2918 +       if (err)
2919 +               goto err_phy_disconnect;
2920 +
2921 +       err = ramips_eth_hw_init(dev);
2922 +       if (err)
2923 +               goto err_debugfs;
2924 +
2925 +       return 0;
2926 +
2927 +err_debugfs:
2928 +       raeth_debugfs_exit(re);
2929 +err_phy_disconnect:
2930 +       ramips_phy_disconnect(re);
2931 +err_mdio_cleanup:
2932 +       ramips_mdio_cleanup(re);
2933 +       return err;
2934 +}
2935 +
2936 +static void
2937 +ramips_eth_uninit(struct net_device *dev)
2938 +{
2939 +       struct raeth_priv *re = netdev_priv(dev);
2940 +
2941 +       raeth_debugfs_exit(re);
2942 +       ramips_phy_disconnect(re);
2943 +       ramips_mdio_cleanup(re);
2944 +       ramips_fe_twr(0, RAETH_REG_FE_INT_ENABLE);
2945 +       free_irq(dev->irq, dev);
2946 +       tasklet_kill(&re->tx_housekeeping_tasklet);
2947 +       tasklet_kill(&re->rx_tasklet);
2948 +       ramips_ring_cleanup(re);
2949 +       ramips_ring_free(re);
2950 +}
2951 +
2952 +static const struct net_device_ops ramips_eth_netdev_ops = {
2953 +       .ndo_init               = ramips_eth_probe,
2954 +       .ndo_uninit             = ramips_eth_uninit,
2955 +       .ndo_open               = ramips_eth_open,
2956 +       .ndo_stop               = ramips_eth_stop,
2957 +       .ndo_start_xmit         = ramips_eth_hard_start_xmit,
2958 +       .ndo_tx_timeout         = ramips_eth_timeout,
2959 +       .ndo_change_mtu         = eth_change_mtu,
2960 +       .ndo_set_mac_address    = eth_mac_addr,
2961 +       .ndo_validate_addr      = eth_validate_addr,
2962 +};
2963 +
2964 +#ifdef CONFIG_SOC_RT305X
2965 +static void rt305x_fe_reset(void)
2966 +{
2967 +#define RT305X_RESET_FE                BIT(21)
2968 +#define RT305X_RESET_ESW       BIT(23)
2969 +#define SYSC_REG_RESET_CTRL    0x034
2970 +       u32 reset_bits = RT305X_RESET_FE;
2971 +
2972 +       if (soc_is_rt5350())
2973 +               reset_bits |= RT305X_RESET_ESW;
2974 +       rt_sysc_w32(reset_bits, SYSC_REG_RESET_CTRL);
2975 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
2976 +}
2977 +
2978 +struct ramips_soc_data rt3050_data = {
2979 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
2980 +       .reset_fe = rt305x_fe_reset,
2981 +       .min_pkt_len = 64,
2982 +};
2983 +
2984 +static const struct of_device_id ralink_eth_match[] = {
2985 +       { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
2986 +       {},
2987 +};
2988 +#else
2989 +static void rt3883_fe_reset(void)
2990 +{
2991 +#define RT3883_SYSC_REG_RSTCTRL        0x34
2992 +#define RT3883_RSTCTRL_FE      BIT(21)
2993 +       u32 t;
2994 +
2995 +       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
2996 +       t |= RT3883_RSTCTRL_FE;
2997 +       rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
2998 +
2999 +       t &= ~RT3883_RSTCTRL_FE;
3000 +       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
3001 +}
3002 +
3003 +struct ramips_soc_data rt3883_data = {
3004 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
3005 +       .reset_fe = rt3883_fe_reset,
3006 +       .min_pkt_len = 64,
3007 +};
3008 +
3009 +static const struct of_device_id ralink_eth_match[] = {
3010 +       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
3011 +       {},
3012 +};
3013 +#endif
3014 +MODULE_DEVICE_TABLE(of, ralink_eth_match);
3015 +
3016 +static int
3017 +ramips_eth_plat_probe(struct platform_device *plat)
3018 +{
3019 +       struct raeth_priv *re;
3020 +       struct resource *res;
3021 +       struct clk *clk;
3022 +       int err;
3023 +       const struct of_device_id *match;
3024 +       const struct ramips_soc_data *soc = NULL;
3025 +
3026 +       match = of_match_device(ralink_eth_match, &plat->dev);
3027 +       if (match)
3028 +               soc = (const struct ramips_soc_data *) match->data;
3029 +
3030 +       if (!soc) {
3031 +               dev_err(&plat->dev, "no platform data specified\n");
3032 +               return -EINVAL;
3033 +       }
3034 +
3035 +       res = platform_get_resource(plat, IORESOURCE_MEM, 0);
3036 +       if (!res) {
3037 +               dev_err(&plat->dev, "no memory resource found\n");
3038 +               return -ENXIO;
3039 +       }
3040 +
3041 +       ramips_fe_base = ioremap_nocache(res->start, res->end - res->start + 1);
3042 +       if (!ramips_fe_base)
3043 +               return -ENOMEM;
3044 +
3045 +       ramips_dev = alloc_etherdev(sizeof(struct raeth_priv));
3046 +       if (!ramips_dev) {
3047 +               dev_err(&plat->dev, "alloc_etherdev failed\n");
3048 +               err = -ENOMEM;
3049 +               goto err_unmap;
3050 +       }
3051 +
3052 +       strcpy(ramips_dev->name, "eth%d");
3053 +       ramips_dev->irq = platform_get_irq(plat, 0);
3054 +       if (ramips_dev->irq < 0) {
3055 +               dev_err(&plat->dev, "no IRQ resource found\n");
3056 +               err = -ENXIO;
3057 +               goto err_free_dev;
3058 +       }
3059 +       ramips_dev->addr_len = ETH_ALEN;
3060 +       ramips_dev->base_addr = (unsigned long)ramips_fe_base;
3061 +       ramips_dev->netdev_ops = &ramips_eth_netdev_ops;
3062 +
3063 +       re = netdev_priv(ramips_dev);
3064 +
3065 +       clk = clk_get(&plat->dev, NULL);
3066 +       if (IS_ERR(clk))
3067 +               panic("unable to get SYS clock, err=%ld", PTR_ERR(clk));
3068 +       re->sys_freq = clk_get_rate(clk);
3069 +
3070 +       re->netdev = ramips_dev;
3071 +       re->of_node = plat->dev.of_node;
3072 +       re->parent = &plat->dev;
3073 +       memcpy(re->mac, soc->mac, 6);
3074 +       re->reset_fe = soc->reset_fe;
3075 +       re->min_pkt_len = soc->min_pkt_len;
3076 +
3077 +       err = register_netdev(ramips_dev);
3078 +       if (err) {
3079 +               dev_err(&plat->dev, "error bringing up device\n");
3080 +               goto err_free_dev;
3081 +       }
3082 +
3083 +       netdev_info(ramips_dev, "done loading\n");
3084 +       return 0;
3085 +
3086 + err_free_dev:
3087 +       kfree(ramips_dev);
3088 + err_unmap:
3089 +       iounmap(ramips_fe_base);
3090 +       return err;
3091 +}
3092 +
3093 +static int
3094 +ramips_eth_plat_remove(struct platform_device *plat)
3095 +{
3096 +       unregister_netdev(ramips_dev);
3097 +       free_netdev(ramips_dev);
3098 +       RADEBUG("ramips_eth: unloaded\n");
3099 +       return 0;
3100 +}
3101 +
3102 +
3103 +
3104 +static struct platform_driver ramips_eth_driver = {
3105 +       .probe = ramips_eth_plat_probe,
3106 +       .remove = ramips_eth_plat_remove,
3107 +       .driver = {
3108 +               .name = "ramips_eth",
3109 +               .owner = THIS_MODULE,
3110 +               .of_match_table = ralink_eth_match
3111 +       },
3112 +};
3113 +
3114 +static int __init
3115 +ramips_eth_init(void)
3116 +{
3117 +       int ret;
3118 +
3119 +       ret = raeth_debugfs_root_init();
3120 +       if (ret)
3121 +               goto err_out;
3122 +
3123 +       ret = rt305x_esw_init();
3124 +       if (ret)
3125 +               goto err_debugfs_exit;
3126 +
3127 +       ret = platform_driver_register(&ramips_eth_driver);
3128 +       if (ret) {
3129 +               printk(KERN_ERR
3130 +                      "ramips_eth: Error registering platfom driver!\n");
3131 +               goto esw_cleanup;
3132 +       }
3133 +
3134 +       return 0;
3135 +
3136 +esw_cleanup:
3137 +       rt305x_esw_exit();
3138 +err_debugfs_exit:
3139 +       raeth_debugfs_root_exit();
3140 +err_out:
3141 +       return ret;
3142 +}
3143 +
3144 +static void __exit
3145 +ramips_eth_cleanup(void)
3146 +{
3147 +       platform_driver_unregister(&ramips_eth_driver);
3148 +       rt305x_esw_exit();
3149 +       raeth_debugfs_root_exit();
3150 +}
3151 +
3152 +module_init(ramips_eth_init);
3153 +module_exit(ramips_eth_cleanup);
3154 +
3155 +MODULE_LICENSE("GPL");
3156 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3157 +MODULE_DESCRIPTION("ethernet driver for ramips boards");