target/linux/ramips/patches-3.14/0035-NET-MIPS-add-ralink-SoC-ethernet-driver.patch

   1 From c55d6cf3e2c593bf7d228c6532ec9bd8da82e09d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 22 Apr 2013 23:20:03 +0200
   4 Subject: [PATCH 35/57] NET: MIPS: add ralink SoC ethernet driver
   5
   6 Add support for Ralink FE and ESW.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
  11  arch/mips/ralink/rt305x.c                          |    1 +
  12  drivers/net/ethernet/Kconfig                       |    1 +
  13  drivers/net/ethernet/Makefile                      |    1 +
  14  drivers/net/ethernet/ralink/Kconfig                |   32 +
  15  drivers/net/ethernet/ralink/Makefile               |   18 +
  16  drivers/net/ethernet/ralink/esw_rt3052.c           | 1463 ++++++++++++++++++++
  17  drivers/net/ethernet/ralink/esw_rt3052.h           |   32 +
  18  drivers/net/ethernet/ralink/gsw_mt7620a.c          |  566 ++++++++
  19  drivers/net/ethernet/ralink/gsw_mt7620a.h          |   30 +
  20  drivers/net/ethernet/ralink/mdio.c                 |  244 ++++
  21  drivers/net/ethernet/ralink/mdio.h                 |   29 +
  22  drivers/net/ethernet/ralink/mdio_rt2880.c          |  232 ++++
  23  drivers/net/ethernet/ralink/mdio_rt2880.h          |   26 +
  24  drivers/net/ethernet/ralink/mt7530.c               |  579 ++++++++
  25  drivers/net/ethernet/ralink/mt7530.h               |   20 +
  26  drivers/net/ethernet/ralink/ralink_soc_eth.c       |  844 +++++++++++
  27  drivers/net/ethernet/ralink/ralink_soc_eth.h       |  384 +++++
  28  drivers/net/ethernet/ralink/soc_mt7620.c           |  172 +++
  29  drivers/net/ethernet/ralink/soc_rt2880.c           |   52 +
  30  drivers/net/ethernet/ralink/soc_rt305x.c           |  113 ++
  31  drivers/net/ethernet/ralink/soc_rt3883.c           |   60 +
  32  22 files changed, 4926 insertions(+)
  33  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  34  create mode 100644 drivers/net/ethernet/ralink/Kconfig
  35  create mode 100644 drivers/net/ethernet/ralink/Makefile
  36  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
  37  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
  38  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
  39  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
  40  create mode 100644 drivers/net/ethernet/ralink/mdio.c
  41  create mode 100644 drivers/net/ethernet/ralink/mdio.h
  42  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
  43  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
  44  create mode 100644 drivers/net/ethernet/ralink/mt7530.c
  45  create mode 100644 drivers/net/ethernet/ralink/mt7530.h
  46  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
  47  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
  48  create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
  49  create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
  50  create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
  51  create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
  52
  53 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  54 ===================================================================
  55 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  56 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h       2014-10-28 10:43:11.882131200 +0100
  57 @@ -0,0 +1,27 @@
  58 +/*
  59 + *  Ralink RT305x SoC platform device registration
  60 + *
  61 + *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  62 + *
  63 + *  This program is free software; you can redistribute it and/or modify it
  64 + *  under the terms of the GNU General Public License version 2 as published
  65 + *  by the Free Software Foundation.
  66 + */
  67 +
  68 +#ifndef _RT305X_ESW_PLATFORM_H
  69 +#define _RT305X_ESW_PLATFORM_H
  70 +
  71 +enum {
  72 +       RT305X_ESW_VLAN_CONFIG_NONE = 0,
  73 +       RT305X_ESW_VLAN_CONFIG_LLLLW,
  74 +       RT305X_ESW_VLAN_CONFIG_WLLLL,
  75 +};
  76 +
  77 +struct rt305x_esw_platform_data
  78 +{
  79 +       u8 vlan_config;
  80 +       u32 reg_initval_fct2;
  81 +       u32 reg_initval_fpa2;
  82 +};
  83 +
  84 +#endif /* _RT305X_ESW_PLATFORM_H */
  85 Index: linux-3.14.18/arch/mips/ralink/rt305x.c
  86 ===================================================================
  87 --- linux-3.14.18.orig/arch/mips/ralink/rt305x.c        2014-10-28 10:43:11.766130990 +0100
  88 +++ linux-3.14.18/arch/mips/ralink/rt305x.c     2014-10-28 10:43:11.882131200 +0100
  89 @@ -199,6 +199,7 @@
  90         }
  91
  92         ralink_clk_add("cpu", cpu_rate);
  93 +       ralink_clk_add("sys", sys_rate);
  94         ralink_clk_add("10000b00.spi", sys_rate);
  95         ralink_clk_add("10000100.timer", wdt_rate);
  96         ralink_clk_add("10000120.watchdog", wdt_rate);
  97 Index: linux-3.14.18/drivers/net/ethernet/Kconfig
  98 ===================================================================
  99 --- linux-3.14.18.orig/drivers/net/ethernet/Kconfig     2014-09-06 01:34:59.000000000 +0200
 100 +++ linux-3.14.18/drivers/net/ethernet/Kconfig  2014-10-29 14:59:06.927617708 +0100
 101 @@ -134,6 +134,7 @@
 102  source "drivers/net/ethernet/packetengines/Kconfig"
 103  source "drivers/net/ethernet/pasemi/Kconfig"
 104  source "drivers/net/ethernet/qlogic/Kconfig"
 105 +source "drivers/net/ethernet/ralink/Kconfig"
 106  source "drivers/net/ethernet/realtek/Kconfig"
 107  source "drivers/net/ethernet/renesas/Kconfig"
 108  source "drivers/net/ethernet/rdc/Kconfig"
 109 Index: linux-3.14.18/drivers/net/ethernet/Makefile
 110 ===================================================================
 111 --- linux-3.14.18.orig/drivers/net/ethernet/Makefile    2014-09-06 01:34:59.000000000 +0200
 112 +++ linux-3.14.18/drivers/net/ethernet/Makefile 2014-10-29 14:59:06.927617708 +0100
 113 @@ -56,6 +56,7 @@
 114  obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
 115  obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
 116  obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
 117 +obj-$(CONFIG_NET_RALINK) += ralink/
 118  obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
 119  obj-$(CONFIG_SH_ETH) += renesas/
 120  obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
 121 Index: linux-3.14.18/drivers/net/ethernet/ralink/Kconfig
 122 ===================================================================
 123 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 124 +++ linux-3.14.18/drivers/net/ethernet/ralink/Kconfig   2014-10-28 10:43:11.886131208 +0100
 125 @@ -0,0 +1,32 @@
 126 +config NET_RALINK
 127 +       tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
 128 +       depends on RALINK
 129 +       help
 130 +         This driver supports the ethernet mac inside the ralink wisocs
 131 +
 132 +if NET_RALINK
 133 +
 134 +config NET_RALINK_MDIO
 135 +       def_bool NET_RALINK
 136 +       depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
 137 +       select PHYLIB
 138 +
 139 +config NET_RALINK_MDIO_RT2880
 140 +       def_bool NET_RALINK
 141 +       depends on (SOC_RT288X || SOC_RT3883)
 142 +       select NET_RALINK_MDIO
 143 +
 144 +config NET_RALINK_ESW_RT3052
 145 +       def_bool NET_RALINK
 146 +       depends on SOC_RT305X
 147 +       select PHYLIB
 148 +       select SWCONFIG
 149 +
 150 +config NET_RALINK_GSW_MT7620
 151 +       def_bool NET_RALINK
 152 +       depends on SOC_MT7620
 153 +       select INET_LRO
 154 +       select NET_RALINK_MDIO
 155 +       select PHYLIB
 156 +       select SWCONFIG
 157 +endif
 158 Index: linux-3.14.18/drivers/net/ethernet/ralink/Makefile
 159 ===================================================================
 160 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 161 +++ linux-3.14.18/drivers/net/ethernet/ralink/Makefile  2014-10-28 10:43:11.886131208 +0100
 162 @@ -0,0 +1,18 @@
 163 +#
 164 +# Makefile for the Ralink SoCs built-in ethernet macs
 165 +#
 166 +
 167 +ralink-eth-y                                   += ralink_soc_eth.o
 168 +
 169 +ralink-eth-$(CONFIG_NET_RALINK_MDIO)           += mdio.o
 170 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880)    += mdio_rt2880.o
 171 +
 172 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052)     += esw_rt3052.o
 173 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620)     += gsw_mt7620a.o mt7530.o
 174 +
 175 +ralink-eth-$(CONFIG_SOC_RT288X)                        += soc_rt2880.o
 176 +ralink-eth-$(CONFIG_SOC_RT305X)                        += soc_rt305x.o
 177 +ralink-eth-$(CONFIG_SOC_RT3883)                        += soc_rt3883.o
 178 +ralink-eth-$(CONFIG_SOC_MT7620)                        += soc_mt7620.o
 179 +
 180 +obj-$(CONFIG_NET_RALINK)                       += ralink-eth.o
 181 Index: linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.c
 182 ===================================================================
 183 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 184 +++ linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.c      2014-10-28 10:43:11.886131208 +0100
 185 @@ -0,0 +1,1463 @@
 186 +/*
 187 + *   This program is free software; you can redistribute it and/or modify
 188 + *   it under the terms of the GNU General Public License as published by
 189 + *   the Free Software Foundation; version 2 of the License
 190 + *
 191 + *   This program is distributed in the hope that it will be useful,
 192 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 193 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 194 + *   GNU General Public License for more details.
 195 + *
 196 + *   You should have received a copy of the GNU General Public License
 197 + *   along with this program; if not, write to the Free Software
 198 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 199 + *
 200 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
 201 + */
 202 +
 203 +#include <linux/module.h>
 204 +#include <linux/kernel.h>
 205 +#include <linux/types.h>
 206 +#include <linux/dma-mapping.h>
 207 +#include <linux/init.h>
 208 +#include <linux/skbuff.h>
 209 +#include <linux/etherdevice.h>
 210 +#include <linux/ethtool.h>
 211 +#include <linux/platform_device.h>
 212 +#include <linux/of_device.h>
 213 +#include <linux/clk.h>
 214 +#include <linux/of_net.h>
 215 +#include <linux/of_mdio.h>
 216 +
 217 +#include <asm/mach-ralink/ralink_regs.h>
 218 +
 219 +#include "ralink_soc_eth.h"
 220 +
 221 +#include <linux/ioport.h>
 222 +#include <linux/switch.h>
 223 +#include <linux/mii.h>
 224 +
 225 +#include <ralink_regs.h>
 226 +#include <asm/mach-ralink/rt305x.h>
 227 +#include <asm/mach-ralink/rt305x_esw_platform.h>
 228 +
 229 +/*
 230 + * HW limitations for this switch:
 231 + * - No large frame support (PKT_MAX_LEN at most 1536)
 232 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
 233 + *   though this might be possible using the undocumented PPE.
 234 + */
 235 +
 236 +#define RT305X_ESW_REG_ISR             0x00
 237 +#define RT305X_ESW_REG_IMR             0x04
 238 +#define RT305X_ESW_REG_FCT0            0x08
 239 +#define RT305X_ESW_REG_PFC1            0x14
 240 +#define RT305X_ESW_REG_ATS             0x24
 241 +#define RT305X_ESW_REG_ATS0            0x28
 242 +#define RT305X_ESW_REG_ATS1            0x2c
 243 +#define RT305X_ESW_REG_ATS2            0x30
 244 +#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
 245 +#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 246 +#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 247 +#define RT305X_ESW_REG_POA             0x80
 248 +#define RT305X_ESW_REG_FPA             0x84
 249 +#define RT305X_ESW_REG_SOCPC           0x8c
 250 +#define RT305X_ESW_REG_POC0            0x90
 251 +#define RT305X_ESW_REG_POC1            0x94
 252 +#define RT305X_ESW_REG_POC2            0x98
 253 +#define RT305X_ESW_REG_SGC             0x9c
 254 +#define RT305X_ESW_REG_STRT            0xa0
 255 +#define RT305X_ESW_REG_PCR0            0xc0
 256 +#define RT305X_ESW_REG_PCR1            0xc4
 257 +#define RT305X_ESW_REG_FPA2            0xc8
 258 +#define RT305X_ESW_REG_FCT2            0xcc
 259 +#define RT305X_ESW_REG_SGC2            0xe4
 260 +#define RT305X_ESW_REG_P0LED           0xa4
 261 +#define RT305X_ESW_REG_P1LED           0xa8
 262 +#define RT305X_ESW_REG_P2LED           0xac
 263 +#define RT305X_ESW_REG_P3LED           0xb0
 264 +#define RT305X_ESW_REG_P4LED           0xb4
 265 +#define RT305X_ESW_REG_PXPC(_x)                (0xe8 + (4 * _x))
 266 +#define RT305X_ESW_REG_P1PC            0xec
 267 +#define RT305X_ESW_REG_P2PC            0xf0
 268 +#define RT305X_ESW_REG_P3PC            0xf4
 269 +#define RT305X_ESW_REG_P4PC            0xf8
 270 +#define RT305X_ESW_REG_P5PC            0xfc
 271 +
 272 +#define RT305X_ESW_LED_LINK            0
 273 +#define RT305X_ESW_LED_100M            1
 274 +#define RT305X_ESW_LED_DUPLEX          2
 275 +#define RT305X_ESW_LED_ACTIVITY                3
 276 +#define RT305X_ESW_LED_COLLISION       4
 277 +#define RT305X_ESW_LED_LINKACT         5
 278 +#define RT305X_ESW_LED_DUPLCOLL                6
 279 +#define RT305X_ESW_LED_10MACT          7
 280 +#define RT305X_ESW_LED_100MACT         8
 281 +/* Additional led states not in datasheet: */
 282 +#define RT305X_ESW_LED_BLINK           10
 283 +#define RT305X_ESW_LED_ON              12
 284 +
 285 +#define RT305X_ESW_LINK_S              25
 286 +#define RT305X_ESW_DUPLEX_S            9
 287 +#define RT305X_ESW_SPD_S               0
 288 +
 289 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
 290 +#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
 291 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
 292 +
 293 +#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
 294 +
 295 +#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
 296 +#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 297 +
 298 +#define RT305X_ESW_PVIDC_PVID_M                0xfff
 299 +#define RT305X_ESW_PVIDC_PVID_S                12
 300 +
 301 +#define RT305X_ESW_VLANI_VID_M         0xfff
 302 +#define RT305X_ESW_VLANI_VID_S         12
 303 +
 304 +#define RT305X_ESW_VMSC_MSC_M          0xff
 305 +#define RT305X_ESW_VMSC_MSC_S          8
 306 +
 307 +#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
 308 +#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
 309 +#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
 310 +#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
 311 +
 312 +#define RT305X_ESW_POC0_EN_BP_S                0
 313 +#define RT305X_ESW_POC0_EN_FC_S                8
 314 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
 315 +#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
 316 +#define RT305X_ESW_POC0_DIS_PORT_S     23
 317 +
 318 +#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
 319 +#define RT305X_ESW_POC2_UNTAG_EN_S     0
 320 +#define RT305X_ESW_POC2_ENAGING_S      8
 321 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
 322 +
 323 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
 324 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
 325 +#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
 326 +#define RT305X_ESW_SGC2_LAN_PMAP_S     24
 327 +
 328 +#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
 329 +#define RT305X_ESW_PFC1_EN_VLAN_S      16
 330 +#define RT305X_ESW_PFC1_EN_TOS_S       24
 331 +
 332 +#define RT305X_ESW_VLAN_NONE           0xfff
 333 +
 334 +#define RT305X_ESW_GSC_BC_STROM_MASK   0x3
 335 +#define RT305X_ESW_GSC_BC_STROM_SHIFT  4
 336 +
 337 +#define RT305X_ESW_GSC_LED_FREQ_MASK   0x3
 338 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT  23
 339 +
 340 +#define RT305X_ESW_POA_LINK_MASK       0x1f
 341 +#define RT305X_ESW_POA_LINK_SHIFT      25
 342 +
 343 +#define RT305X_ESW_PORT_ST_CHG         BIT(26)
 344 +#define RT305X_ESW_PORT0               0
 345 +#define RT305X_ESW_PORT1               1
 346 +#define RT305X_ESW_PORT2               2
 347 +#define RT305X_ESW_PORT3               3
 348 +#define RT305X_ESW_PORT4               4
 349 +#define RT305X_ESW_PORT5               5
 350 +#define RT305X_ESW_PORT6               6
 351 +
 352 +#define RT305X_ESW_PORTS_NONE          0
 353 +
 354 +#define RT305X_ESW_PMAP_LLLLLL         0x3f
 355 +#define RT305X_ESW_PMAP_LLLLWL         0x2f
 356 +#define RT305X_ESW_PMAP_WLLLLL         0x3e
 357 +
 358 +#define RT305X_ESW_PORTS_INTERNAL                                      \
 359 +               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
 360 +                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
 361 +                BIT(RT305X_ESW_PORT4))
 362 +
 363 +#define RT305X_ESW_PORTS_NOCPU                                         \
 364 +               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
 365 +
 366 +#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
 367 +
 368 +#define RT305X_ESW_PORTS_ALL                                           \
 369 +               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
 370 +
 371 +#define RT305X_ESW_NUM_VLANS           16
 372 +#define RT305X_ESW_NUM_VIDS            4096
 373 +#define RT305X_ESW_NUM_PORTS           7
 374 +#define RT305X_ESW_NUM_LANWAN          6
 375 +#define RT305X_ESW_NUM_LEDS            5
 376 +
 377 +#define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
 378 +#define RT5350_EWS_REG_LED_POLARITY    0x168
 379 +#define RT5350_RESET_EPHY              BIT(24)
 380 +#define SYSC_REG_RESET_CTRL            0x34
 381 +
 382 +enum {
 383 +       /* Global attributes. */
 384 +       RT305X_ESW_ATTR_ENABLE_VLAN,
 385 +       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 386 +       RT305X_ESW_ATTR_BC_STATUS,
 387 +       RT305X_ESW_ATTR_LED_FREQ,
 388 +       /* Port attributes. */
 389 +       RT305X_ESW_ATTR_PORT_DISABLE,
 390 +       RT305X_ESW_ATTR_PORT_DOUBLETAG,
 391 +       RT305X_ESW_ATTR_PORT_UNTAG,
 392 +       RT305X_ESW_ATTR_PORT_LED,
 393 +       RT305X_ESW_ATTR_PORT_LAN,
 394 +       RT305X_ESW_ATTR_PORT_RECV_BAD,
 395 +       RT305X_ESW_ATTR_PORT_RECV_GOOD,
 396 +       RT5350_ESW_ATTR_PORT_TR_BAD,
 397 +       RT5350_ESW_ATTR_PORT_TR_GOOD,
 398 +};
 399 +
 400 +struct esw_port {
 401 +       bool    disable;
 402 +       bool    doubletag;
 403 +       bool    untag;
 404 +       u8      led;
 405 +       u16     pvid;
 406 +};
 407 +
 408 +struct esw_vlan {
 409 +       u8      ports;
 410 +       u16     vid;
 411 +};
 412 +
 413 +struct rt305x_esw {
 414 +       struct device           *dev;
 415 +       void __iomem            *base;
 416 +       int                     irq;
 417 +       const struct rt305x_esw_platform_data *pdata;
 418 +       /* Protects against concurrent register rmw operations. */
 419 +       spinlock_t              reg_rw_lock;
 420 +
 421 +       unsigned char           port_map;
 422 +       unsigned int            reg_initval_fct2;
 423 +       unsigned int            reg_initval_fpa2;
 424 +       unsigned int            reg_led_polarity;
 425 +
 426 +
 427 +       struct switch_dev       swdev;
 428 +       bool                    global_vlan_enable;
 429 +       bool                    alt_vlan_disable;
 430 +       int                     bc_storm_protect;
 431 +       int                     led_frequency;
 432 +       struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
 433 +       struct esw_port ports[RT305X_ESW_NUM_PORTS];
 434 +
 435 +};
 436 +
 437 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
 438 +{
 439 +       __raw_writel(val, esw->base + reg);
 440 +}
 441 +
 442 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
 443 +{
 444 +       return __raw_readl(esw->base + reg);
 445 +}
 446 +
 447 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 448 +                  unsigned long val)
 449 +{
 450 +       unsigned long t;
 451 +
 452 +       t = __raw_readl(esw->base + reg) & ~mask;
 453 +       __raw_writel(t | val, esw->base + reg);
 454 +}
 455 +
 456 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 457 +              unsigned long val)
 458 +{
 459 +       unsigned long flags;
 460 +
 461 +       spin_lock_irqsave(&esw->reg_rw_lock, flags);
 462 +       esw_rmw_raw(esw, reg, mask, val);
 463 +       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 464 +}
 465 +
 466 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 467 +                u32 write_data)
 468 +{
 469 +       unsigned long t_start = jiffies;
 470 +       int ret = 0;
 471 +
 472 +       while (1) {
 473 +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
 474 +                     RT305X_ESW_PCR1_WT_DONE))
 475 +                       break;
 476 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 477 +                       ret = 1;
 478 +                       goto out;
 479 +               }
 480 +       }
 481 +
 482 +       write_data &= 0xffff;
 483 +       esw_w32(esw,
 484 +                     (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 485 +                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 486 +                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 487 +                     RT305X_ESW_REG_PCR0);
 488 +
 489 +       t_start = jiffies;
 490 +       while (1) {
 491 +               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
 492 +                   RT305X_ESW_PCR1_WT_DONE)
 493 +                       break;
 494 +
 495 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 496 +                       ret = 1;
 497 +                       break;
 498 +               }
 499 +       }
 500 +out:
 501 +       if (ret)
 502 +               printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 503 +       return ret;
 504 +}
 505 +
 506 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
 507 +{
 508 +       unsigned s;
 509 +       unsigned val;
 510 +
 511 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 512 +       val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
 513 +       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
 514 +
 515 +       return val;
 516 +}
 517 +
 518 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 519 +{
 520 +       unsigned s;
 521 +
 522 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 523 +       esw_rmw(esw,
 524 +                      RT305X_ESW_REG_VLANI(vlan / 2),
 525 +                      RT305X_ESW_VLANI_VID_M << s,
 526 +                      (vid & RT305X_ESW_VLANI_VID_M) << s);
 527 +}
 528 +
 529 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
 530 +{
 531 +       unsigned s, val;
 532 +
 533 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 534 +       val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
 535 +       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
 536 +}
 537 +
 538 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 539 +{
 540 +       unsigned s;
 541 +
 542 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 543 +       esw_rmw(esw,
 544 +                      RT305X_ESW_REG_PVIDC(port / 2),
 545 +                      RT305X_ESW_PVIDC_PVID_M << s,
 546 +                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 547 +}
 548 +
 549 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
 550 +{
 551 +       unsigned s, val;
 552 +
 553 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 554 +       val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
 555 +       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
 556 +
 557 +       return val;
 558 +}
 559 +
 560 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 561 +{
 562 +       unsigned s;
 563 +
 564 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 565 +       esw_rmw(esw,
 566 +                      RT305X_ESW_REG_VMSC(vlan / 4),
 567 +                      RT305X_ESW_VMSC_MSC_M << s,
 568 +                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
 569 +}
 570 +
 571 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
 572 +{
 573 +       unsigned reg;
 574 +       reg = esw_r32(esw, RT305X_ESW_REG_POC0);
 575 +       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
 576 +              RT305X_ESW_POC0_DIS_PORT_M;
 577 +}
 578 +
 579 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
 580 +{
 581 +       unsigned old_mask;
 582 +       unsigned enable_mask;
 583 +       unsigned changed;
 584 +       int i;
 585 +
 586 +       old_mask = esw_get_port_disable(esw);
 587 +       changed = old_mask ^ disable_mask;
 588 +       enable_mask = old_mask & disable_mask;
 589 +
 590 +       /* enable before writing to MII */
 591 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 592 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 593 +                       RT305X_ESW_POC0_DIS_PORT_S),
 594 +                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 595 +
 596 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
 597 +               if (!(changed & (1 << i)))
 598 +                       continue;
 599 +               if (disable_mask & (1 << i)) {
 600 +                       /* disable */
 601 +                       rt305x_mii_write(esw, i, MII_BMCR,
 602 +                                        BMCR_PDOWN);
 603 +               } else {
 604 +                       /* enable */
 605 +                       rt305x_mii_write(esw, i, MII_BMCR,
 606 +                                        BMCR_FULLDPLX |
 607 +                                        BMCR_ANENABLE |
 608 +                                        BMCR_ANRESTART |
 609 +                                        BMCR_SPEED100);
 610 +               }
 611 +       }
 612 +
 613 +       /* disable after writing to MII */
 614 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 615 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 616 +                       RT305X_ESW_POC0_DIS_PORT_S),
 617 +                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 618 +}
 619 +
 620 +static void esw_set_gsc(struct rt305x_esw *esw)
 621 +{
 622 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 623 +               RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
 624 +               esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
 625 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 626 +               RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
 627 +               esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
 628 +}
 629 +
 630 +static int esw_apply_config(struct switch_dev *dev);
 631 +
 632 +static void esw_hw_init(struct rt305x_esw *esw)
 633 +{
 634 +       int i;
 635 +       u8 port_disable = 0;
 636 +       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
 637 +
 638 +       /* vodoo from original driver */
 639 +       esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 640 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 641 +       /* Port priority 1 for all ports, vlan enabled. */
 642 +       esw_w32(esw, 0x00005555 |
 643 +                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
 644 +                     RT305X_ESW_REG_PFC1);
 645 +
 646 +       /* Enable Back Pressure, and Flow Control */
 647 +       esw_w32(esw,
 648 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
 649 +                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
 650 +                     RT305X_ESW_REG_POC0);
 651 +
 652 +       /* Enable Aging, and VLAN TAG removal */
 653 +       esw_w32(esw,
 654 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
 655 +                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
 656 +                     RT305X_ESW_REG_POC2);
 657 +
 658 +       if (esw->reg_initval_fct2)
 659 +               esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 660 +       else
 661 +               esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 662 +
 663 +       /*
 664 +        * 300s aging timer, max packet len 1536, broadcast storm prevention
 665 +        * disabled, disable collision abort, mac xor48 hash, 10 packet back
 666 +        * pressure jam, GMII disable was_transmit, back pressure disabled,
 667 +        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
 668 +        * ports.
 669 +        */
 670 +       esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 671 +
 672 +       /* Setup SoC Port control register */
 673 +       esw_w32(esw,
 674 +                     (RT305X_ESW_SOCPC_CRC_PADDING |
 675 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 676 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 677 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 678 +                     RT305X_ESW_REG_SOCPC);
 679 +
 680 +       if (esw->reg_initval_fpa2)
 681 +               esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 682 +       else
 683 +               esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 684 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
 685 +
 686 +       /* Force Link/Activity on ports */
 687 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
 688 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
 689 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
 690 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
 691 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
 692 +
 693 +       /* Copy disabled port configuration from bootloader setup */
 694 +       port_disable = esw_get_port_disable(esw);
 695 +       for (i = 0; i < 6; i++)
 696 +               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
 697 +
 698 +       if (soc_is_rt3352()) {
 699 +               /* reset EPHY */
 700 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 701 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 702 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 703 +
 704 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 705 +               for (i = 0; i < 5; i++) {
 706 +                       if (esw->ports[i].disable) {
 707 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 708 +                       } else {
 709 +                               rt305x_mii_write(esw, i, MII_BMCR,
 710 +                                        BMCR_FULLDPLX |
 711 +                                        BMCR_ANENABLE |
 712 +                                        BMCR_SPEED100);
 713 +                       }
 714 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 715 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 716 +                       /* TX100/TX10 AD/DA current bias */
 717 +                       rt305x_mii_write(esw, i, 29, 0x7016);
 718 +                       /* TX100 slew rate control */
 719 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 720 +               }
 721 +
 722 +               /* select global register */
 723 +               rt305x_mii_write(esw, 0, 31, 0x0);
 724 +               /* enlarge agcsel threshold 3 and threshold 2 */
 725 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 726 +               /* enlarge agcsel threshold 5 and threshold 4 */
 727 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 728 +               /* enlarge agcsel threshold  */
 729 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 730 +               rt305x_mii_write(esw, 0,12, 0x7eaa);
 731 +               /* longer TP_IDL tail length */
 732 +               rt305x_mii_write(esw, 0, 14, 0x65);
 733 +               /* increased squelch pulse count threshold. */
 734 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 735 +               /* set TX10 signal amplitude threshold to minimum */
 736 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 737 +               /* set squelch amplitude to higher threshold */
 738 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 739 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 740 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 741 +               /* set PLL/Receive bias current are calibrated */
 742 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 743 +               /* change PLL/Receive bias current to internal(RT3350) */
 744 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 745 +               /* change PLL bias current to internal(RT3052_MP3) */
 746 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 747 +               /* select local register */
 748 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 749 +       } else if (soc_is_rt5350()) {
 750 +               /* reset EPHY */
 751 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 752 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 753 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 754 +
 755 +               /* set the led polarity */
 756 +               esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
 757 +
 758 +               /* local registers */
 759 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 760 +               for (i = 0; i < 5; i++) {
 761 +                       if (esw->ports[i].disable) {
 762 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 763 +                       } else {
 764 +                               rt305x_mii_write(esw, i, MII_BMCR,
 765 +                                        BMCR_FULLDPLX |
 766 +                                        BMCR_ANENABLE |
 767 +                                        BMCR_SPEED100);
 768 +                       }
 769 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 770 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 771 +                       /* TX100/TX10 AD/DA current bias */
 772 +                       rt305x_mii_write(esw, i, 29, 0x7015);
 773 +                       /* TX100 slew rate control */
 774 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 775 +               }
 776 +
 777 +               /* global registers */
 778 +               rt305x_mii_write(esw, 0, 31, 0x0);
 779 +               /* enlarge agcsel threshold 3 and threshold 2 */
 780 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 781 +               /* enlarge agcsel threshold 5 and threshold 4 */
 782 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 783 +               /* enlarge agcsel threshold 6 */
 784 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 785 +               rt305x_mii_write(esw, 0, 12, 0x7eaa);
 786 +               /* longer TP_IDL tail length */
 787 +               rt305x_mii_write(esw, 0, 14, 0x65);
 788 +               /* increased squelch pulse count threshold. */
 789 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 790 +               /* set TX10 signal amplitude threshold to minimum */
 791 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 792 +               /* set squelch amplitude to higher threshold */
 793 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 794 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 795 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 796 +               /* set PLL/Receive bias current are calibrated */
 797 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 798 +               /* change PLL/Receive bias current to internal(RT3350) */
 799 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 800 +               /* change PLL bias current to internal(RT3052_MP3) */
 801 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 802 +               /* select local register */
 803 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 804 +       } else {
 805 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 806 +               for (i = 0; i < 5; i++) {
 807 +                       if (esw->ports[i].disable) {
 808 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 809 +                       } else {
 810 +                               rt305x_mii_write(esw, i, MII_BMCR,
 811 +                                        BMCR_FULLDPLX |
 812 +                                        BMCR_ANENABLE |
 813 +                                        BMCR_SPEED100);
 814 +                       }
 815 +                       /* TX10 waveform coefficient */
 816 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 817 +                       /* TX100/TX10 AD/DA current bias */
 818 +                       rt305x_mii_write(esw, i, 29, 0x7058);
 819 +                       /* TX100 slew rate control */
 820 +                       rt305x_mii_write(esw, i, 30, 0x0018);
 821 +               }
 822 +
 823 +               /* PHY IOT */
 824 +               /* select global register */
 825 +               rt305x_mii_write(esw, 0, 31, 0x0);
 826 +               /* tune TP_IDL tail and head waveform */
 827 +               rt305x_mii_write(esw, 0, 22, 0x052f);
 828 +               /* set TX10 signal amplitude threshold to minimum */
 829 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 830 +               /* set squelch amplitude to higher threshold */
 831 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 832 +               /* longer TP_IDL tail length */
 833 +               rt305x_mii_write(esw, 0, 14, 0x65);
 834 +               /* select local register */
 835 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 836 +       }
 837 +
 838 +       if (esw->port_map)
 839 +               port_map = esw->port_map;
 840 +       else
 841 +               port_map = RT305X_ESW_PMAP_LLLLLL;
 842 +
 843 +       /*
 844 +        * Unused HW feature, but still nice to be consistent here...
 845 +        * This is also exported to userspace ('lan' attribute) so it's
 846 +        * conveniently usable to decide which ports go into the wan vlan by
 847 +        * default.
 848 +        */
 849 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 850 +                      RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
 851 +                      port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
 852 +
 853 +       /* make the switch leds blink */
 854 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
 855 +               esw->ports[i].led = 0x05;
 856 +
 857 +       /* Apply the empty config. */
 858 +       esw_apply_config(&esw->swdev);
 859 +
 860 +       /* Only unmask the port change interrupt */
 861 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
 862 +}
 863 +
 864 +static irqreturn_t esw_interrupt(int irq, void *_esw)
 865 +{
 866 +       struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
 867 +       u32 status;
 868 +
 869 +       status = esw_r32(esw, RT305X_ESW_REG_ISR);
 870 +       if (status & RT305X_ESW_PORT_ST_CHG) {
 871 +               u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
 872 +               link >>= RT305X_ESW_POA_LINK_SHIFT;
 873 +               link &= RT305X_ESW_POA_LINK_MASK;
 874 +               dev_info(esw->dev, "link changed 0x%02X\n", link);
 875 +       }
 876 +       esw_w32(esw, status, RT305X_ESW_REG_ISR);
 877 +
 878 +       return IRQ_HANDLED;
 879 +}
 880 +
 881 +static int esw_apply_config(struct switch_dev *dev)
 882 +{
 883 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 884 +       int i;
 885 +       u8 disable = 0;
 886 +       u8 doubletag = 0;
 887 +       u8 en_vlan = 0;
 888 +       u8 untag = 0;
 889 +
 890 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 891 +               u32 vid, vmsc;
 892 +               if (esw->global_vlan_enable) {
 893 +                       vid = esw->vlans[i].vid;
 894 +                       vmsc = esw->vlans[i].ports;
 895 +               } else {
 896 +                       vid = RT305X_ESW_VLAN_NONE;
 897 +                       vmsc = RT305X_ESW_PORTS_NONE;
 898 +               }
 899 +               esw_set_vlan_id(esw, i, vid);
 900 +               esw_set_vmsc(esw, i, vmsc);
 901 +       }
 902 +
 903 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 904 +               u32 pvid;
 905 +               disable |= esw->ports[i].disable << i;
 906 +               if (esw->global_vlan_enable) {
 907 +                       doubletag |= esw->ports[i].doubletag << i;
 908 +                       en_vlan   |= 1                       << i;
 909 +                       untag     |= esw->ports[i].untag     << i;
 910 +                       pvid       = esw->ports[i].pvid;
 911 +               } else {
 912 +                       int x = esw->alt_vlan_disable ? 0 : 1;
 913 +                       doubletag |= x << i;
 914 +                       en_vlan   |= x << i;
 915 +                       untag     |= x << i;
 916 +                       pvid       = 0;
 917 +               }
 918 +               esw_set_pvid(esw, i, pvid);
 919 +               if (i < RT305X_ESW_NUM_LEDS)
 920 +                       esw_w32(esw, esw->ports[i].led,
 921 +                                     RT305X_ESW_REG_P0LED + 4*i);
 922 +       }
 923 +
 924 +       esw_set_gsc(esw);
 925 +       esw_set_port_disable(esw, disable);
 926 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 927 +                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
 928 +                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
 929 +                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
 930 +       esw_rmw(esw, RT305X_ESW_REG_PFC1,
 931 +                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
 932 +                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
 933 +       esw_rmw(esw, RT305X_ESW_REG_POC2,
 934 +                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
 935 +                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
 936 +
 937 +       if (!esw->global_vlan_enable) {
 938 +               /*
 939 +                * Still need to put all ports into vlan 0 or they'll be
 940 +                * isolated.
 941 +                * NOTE: vlan 0 is special, no vlan tag is prepended
 942 +                */
 943 +               esw_set_vlan_id(esw, 0, 0);
 944 +               esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
 945 +       }
 946 +
 947 +       return 0;
 948 +}
 949 +
 950 +static int esw_reset_switch(struct switch_dev *dev)
 951 +{
 952 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 953 +
 954 +       esw->global_vlan_enable = 0;
 955 +       memset(esw->ports, 0, sizeof(esw->ports));
 956 +       memset(esw->vlans, 0, sizeof(esw->vlans));
 957 +       esw_hw_init(esw);
 958 +
 959 +       return 0;
 960 +}
 961 +
 962 +static int esw_get_vlan_enable(struct switch_dev *dev,
 963 +                          const struct switch_attr *attr,
 964 +                          struct switch_val *val)
 965 +{
 966 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 967 +
 968 +       val->value.i = esw->global_vlan_enable;
 969 +
 970 +       return 0;
 971 +}
 972 +
 973 +static int esw_set_vlan_enable(struct switch_dev *dev,
 974 +                          const struct switch_attr *attr,
 975 +                          struct switch_val *val)
 976 +{
 977 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 978 +
 979 +       esw->global_vlan_enable = val->value.i != 0;
 980 +
 981 +       return 0;
 982 +}
 983 +
 984 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
 985 +                               const struct switch_attr *attr,
 986 +                               struct switch_val *val)
 987 +{
 988 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 989 +
 990 +       val->value.i = esw->alt_vlan_disable;
 991 +
 992 +       return 0;
 993 +}
 994 +
 995 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
 996 +                               const struct switch_attr *attr,
 997 +                               struct switch_val *val)
 998 +{
 999 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1000 +
1001 +       esw->alt_vlan_disable = val->value.i != 0;
1002 +
1003 +       return 0;
1004 +}
1005 +
1006 +static int
1007 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1008 +                       const struct switch_attr *attr,
1009 +                       struct switch_val *val)
1010 +{
1011 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1012 +
1013 +       esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1014 +
1015 +       return 0;
1016 +}
1017 +
1018 +static int
1019 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1020 +                       const struct switch_attr *attr,
1021 +                       struct switch_val *val)
1022 +{
1023 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1024 +
1025 +       val->value.i = esw->bc_storm_protect;
1026 +
1027 +       return 0;
1028 +}
1029 +
1030 +static int
1031 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1032 +                       const struct switch_attr *attr,
1033 +                       struct switch_val *val)
1034 +{
1035 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1036 +
1037 +       esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1038 +
1039 +       return 0;
1040 +}
1041 +
1042 +static int
1043 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1044 +                       const struct switch_attr *attr,
1045 +                       struct switch_val *val)
1046 +{
1047 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1048 +
1049 +       val->value.i = esw->led_frequency;
1050 +
1051 +       return 0;
1052 +}
1053 +
1054 +static int esw_get_port_link(struct switch_dev *dev,
1055 +                        int port,
1056 +                        struct switch_port_link *link)
1057 +{
1058 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1059 +       u32 speed, poa;
1060 +
1061 +       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1062 +               return -EINVAL;
1063 +
1064 +       poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1065 +
1066 +       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1067 +       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1068 +       if (port < RT305X_ESW_NUM_LEDS) {
1069 +               speed = (poa >> RT305X_ESW_SPD_S) & 1;
1070 +       } else {
1071 +               if (port == RT305X_ESW_NUM_PORTS - 1)
1072 +                       poa >>= 1;
1073 +               speed = (poa >> RT305X_ESW_SPD_S) & 3;
1074 +       }
1075 +       switch (speed) {
1076 +       case 0:
1077 +               link->speed = SWITCH_PORT_SPEED_10;
1078 +               break;
1079 +       case 1:
1080 +               link->speed = SWITCH_PORT_SPEED_100;
1081 +               break;
1082 +       case 2:
1083 +       case 3: /* forced gige speed can be 2 or 3 */
1084 +               link->speed = SWITCH_PORT_SPEED_1000;
1085 +               break;
1086 +       default:
1087 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1088 +               break;
1089 +       }
1090 +
1091 +       return 0;
1092 +}
1093 +
1094 +static int esw_get_port_bool(struct switch_dev *dev,
1095 +                        const struct switch_attr *attr,
1096 +                        struct switch_val *val)
1097 +{
1098 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1099 +       int idx = val->port_vlan;
1100 +       u32 x, reg, shift;
1101 +
1102 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1103 +               return -EINVAL;
1104 +
1105 +       switch (attr->id) {
1106 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1107 +               reg = RT305X_ESW_REG_POC0;
1108 +               shift = RT305X_ESW_POC0_DIS_PORT_S;
1109 +               break;
1110 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1111 +               reg = RT305X_ESW_REG_SGC2;
1112 +               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1113 +               break;
1114 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1115 +               reg = RT305X_ESW_REG_POC2;
1116 +               shift = RT305X_ESW_POC2_UNTAG_EN_S;
1117 +               break;
1118 +       case RT305X_ESW_ATTR_PORT_LAN:
1119 +               reg = RT305X_ESW_REG_SGC2;
1120 +               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1121 +               if (idx >= RT305X_ESW_NUM_LANWAN)
1122 +                       return -EINVAL;
1123 +               break;
1124 +       default:
1125 +               return -EINVAL;
1126 +       }
1127 +
1128 +       x = esw_r32(esw, reg);
1129 +       val->value.i = (x >> (idx + shift)) & 1;
1130 +
1131 +       return 0;
1132 +}
1133 +
1134 +static int esw_set_port_bool(struct switch_dev *dev,
1135 +                        const struct switch_attr *attr,
1136 +                        struct switch_val *val)
1137 +{
1138 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1139 +       int idx = val->port_vlan;
1140 +
1141 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1142 +           val->value.i < 0 || val->value.i > 1)
1143 +               return -EINVAL;
1144 +
1145 +       switch (attr->id) {
1146 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1147 +               esw->ports[idx].disable = val->value.i;
1148 +               break;
1149 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1150 +               esw->ports[idx].doubletag = val->value.i;
1151 +               break;
1152 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1153 +               esw->ports[idx].untag = val->value.i;
1154 +               break;
1155 +       default:
1156 +               return -EINVAL;
1157 +       }
1158 +
1159 +       return 0;
1160 +}
1161 +
1162 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1163 +                                const struct switch_attr *attr,
1164 +                                struct switch_val *val)
1165 +{
1166 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1167 +       int idx = val->port_vlan;
1168 +       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1169 +       u32 reg;
1170 +
1171 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1172 +               return -EINVAL;
1173 +       reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1174 +       val->value.i = (reg >> shift) & 0xffff;
1175 +
1176 +       return 0;
1177 +}
1178 +
1179 +static int
1180 +esw_get_port_tr_badgood(struct switch_dev *dev,
1181 +                                const struct switch_attr *attr,
1182 +                                struct switch_val *val)
1183 +{
1184 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1185 +
1186 +       int idx = val->port_vlan;
1187 +       int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1188 +       u32 reg;
1189 +
1190 +       if (!soc_is_rt5350())
1191 +               return -EINVAL;
1192 +
1193 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1194 +               return -EINVAL;
1195 +
1196 +       reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1197 +       val->value.i = (reg >> shift) & 0xffff;
1198 +
1199 +       return 0;
1200 +}
1201 +
1202 +static int esw_get_port_led(struct switch_dev *dev,
1203 +                       const struct switch_attr *attr,
1204 +                       struct switch_val *val)
1205 +{
1206 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1207 +       int idx = val->port_vlan;
1208 +
1209 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1210 +           idx >= RT305X_ESW_NUM_LEDS)
1211 +               return -EINVAL;
1212 +
1213 +       val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1214 +
1215 +       return 0;
1216 +}
1217 +
1218 +static int esw_set_port_led(struct switch_dev *dev,
1219 +                       const struct switch_attr *attr,
1220 +                       struct switch_val *val)
1221 +{
1222 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1223 +       int idx = val->port_vlan;
1224 +
1225 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1226 +               return -EINVAL;
1227 +
1228 +       esw->ports[idx].led = val->value.i;
1229 +
1230 +       return 0;
1231 +}
1232 +
1233 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1234 +{
1235 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1236 +
1237 +       if (port >= RT305X_ESW_NUM_PORTS)
1238 +               return -EINVAL;
1239 +
1240 +       *val = esw_get_pvid(esw, port);
1241 +
1242 +       return 0;
1243 +}
1244 +
1245 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1246 +{
1247 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1248 +
1249 +       if (port >= RT305X_ESW_NUM_PORTS)
1250 +               return -EINVAL;
1251 +
1252 +       esw->ports[port].pvid = val;
1253 +
1254 +       return 0;
1255 +}
1256 +
1257 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1258 +{
1259 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1260 +       u32 vmsc, poc2;
1261 +       int vlan_idx = -1;
1262 +       int i;
1263 +
1264 +       val->len = 0;
1265 +
1266 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1267 +               return -EINVAL;
1268 +
1269 +       /* valid vlan? */
1270 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1271 +               if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1272 +                   esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1273 +                       vlan_idx = i;
1274 +                       break;
1275 +               }
1276 +       }
1277 +
1278 +       if (vlan_idx == -1)
1279 +               return -EINVAL;
1280 +
1281 +       vmsc = esw_get_vmsc(esw, vlan_idx);
1282 +       poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1283 +
1284 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1285 +               struct switch_port *p;
1286 +               int port_mask = 1 << i;
1287 +
1288 +               if (!(vmsc & port_mask))
1289 +                       continue;
1290 +
1291 +               p = &val->value.ports[val->len++];
1292 +               p->id = i;
1293 +               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1294 +                       p->flags = 0;
1295 +               else
1296 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1297 +       }
1298 +
1299 +       return 0;
1300 +}
1301 +
1302 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1303 +{
1304 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1305 +       int ports;
1306 +       int vlan_idx = -1;
1307 +       int i;
1308 +
1309 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1310 +           val->len > RT305X_ESW_NUM_PORTS)
1311 +               return -EINVAL;
1312 +
1313 +       /* one of the already defined vlans? */
1314 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1315 +               if (esw->vlans[i].vid == val->port_vlan &&
1316 +                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1317 +                       vlan_idx = i;
1318 +                       break;
1319 +               }
1320 +       }
1321 +
1322 +       /* select a free slot */
1323 +       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1324 +               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1325 +                       vlan_idx = i;
1326 +       }
1327 +
1328 +       /* bail if all slots are in use */
1329 +       if (vlan_idx == -1)
1330 +               return -EINVAL;
1331 +
1332 +       ports = RT305X_ESW_PORTS_NONE;
1333 +       for (i = 0; i < val->len; i++) {
1334 +               struct switch_port *p = &val->value.ports[i];
1335 +               int port_mask = 1 << p->id;
1336 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1337 +
1338 +               if (p->id >= RT305X_ESW_NUM_PORTS)
1339 +                       return -EINVAL;
1340 +
1341 +               ports |= port_mask;
1342 +               esw->ports[p->id].untag = untagged;
1343 +       }
1344 +       esw->vlans[vlan_idx].ports = ports;
1345 +       if (ports == RT305X_ESW_PORTS_NONE)
1346 +               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1347 +       else
1348 +               esw->vlans[vlan_idx].vid = val->port_vlan;
1349 +
1350 +       return 0;
1351 +}
1352 +
1353 +static const struct switch_attr esw_global[] = {
1354 +       {
1355 +               .type = SWITCH_TYPE_INT,
1356 +               .name = "enable_vlan",
1357 +               .description = "VLAN mode (1:enabled)",
1358 +               .max = 1,
1359 +               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1360 +               .get = esw_get_vlan_enable,
1361 +               .set = esw_set_vlan_enable,
1362 +       },
1363 +       {
1364 +               .type = SWITCH_TYPE_INT,
1365 +               .name = "alternate_vlan_disable",
1366 +               .description = "Use en_vlan instead of doubletag to disable"
1367 +                               " VLAN mode",
1368 +               .max = 1,
1369 +               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1370 +               .get = esw_get_alt_vlan_disable,
1371 +               .set = esw_set_alt_vlan_disable,
1372 +       },
1373 +       {
1374 +               .type = SWITCH_TYPE_INT,
1375 +               .name = "bc_storm_protect",
1376 +               .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1377 +               .max = 3,
1378 +               .id = RT305X_ESW_ATTR_BC_STATUS,
1379 +               .get = rt305x_esw_get_bc_status,
1380 +               .set = rt305x_esw_set_bc_status,
1381 +       },
1382 +       {
1383 +               .type = SWITCH_TYPE_INT,
1384 +               .name = "led_frequency",
1385 +               .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1386 +               .max = 3,
1387 +               .id = RT305X_ESW_ATTR_LED_FREQ,
1388 +               .get = rt305x_esw_get_led_freq,
1389 +               .set = rt305x_esw_set_led_freq,
1390 +       }
1391 +};
1392 +
1393 +static const struct switch_attr esw_port[] = {
1394 +       {
1395 +               .type = SWITCH_TYPE_INT,
1396 +               .name = "disable",
1397 +               .description = "Port state (1:disabled)",
1398 +               .max = 1,
1399 +               .id = RT305X_ESW_ATTR_PORT_DISABLE,
1400 +               .get = esw_get_port_bool,
1401 +               .set = esw_set_port_bool,
1402 +       },
1403 +       {
1404 +               .type = SWITCH_TYPE_INT,
1405 +               .name = "doubletag",
1406 +               .description = "Double tagging for incoming vlan packets "
1407 +                               "(1:enabled)",
1408 +               .max = 1,
1409 +               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1410 +               .get = esw_get_port_bool,
1411 +               .set = esw_set_port_bool,
1412 +       },
1413 +       {
1414 +               .type = SWITCH_TYPE_INT,
1415 +               .name = "untag",
1416 +               .description = "Untag (1:strip outgoing vlan tag)",
1417 +               .max = 1,
1418 +               .id = RT305X_ESW_ATTR_PORT_UNTAG,
1419 +               .get = esw_get_port_bool,
1420 +               .set = esw_set_port_bool,
1421 +       },
1422 +       {
1423 +               .type = SWITCH_TYPE_INT,
1424 +               .name = "led",
1425 +               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1426 +                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1427 +                               " 8:100mact, 10:blink, 11:off, 12:on)",
1428 +               .max = 15,
1429 +               .id = RT305X_ESW_ATTR_PORT_LED,
1430 +               .get = esw_get_port_led,
1431 +               .set = esw_set_port_led,
1432 +       },
1433 +       {
1434 +               .type = SWITCH_TYPE_INT,
1435 +               .name = "lan",
1436 +               .description = "HW port group (0:wan, 1:lan)",
1437 +               .max = 1,
1438 +               .id = RT305X_ESW_ATTR_PORT_LAN,
1439 +               .get = esw_get_port_bool,
1440 +       },
1441 +       {
1442 +               .type = SWITCH_TYPE_INT,
1443 +               .name = "recv_bad",
1444 +               .description = "Receive bad packet counter",
1445 +               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1446 +               .get = esw_get_port_recv_badgood,
1447 +       },
1448 +       {
1449 +               .type = SWITCH_TYPE_INT,
1450 +               .name = "recv_good",
1451 +               .description = "Receive good packet counter",
1452 +               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1453 +               .get = esw_get_port_recv_badgood,
1454 +       },
1455 +       {
1456 +               .type = SWITCH_TYPE_INT,
1457 +               .name = "tr_bad",
1458 +
1459 +               .description = "Transmit bad packet counter. rt5350 only",
1460 +               .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1461 +               .get = esw_get_port_tr_badgood,
1462 +       },
1463 +       {
1464 +               .type = SWITCH_TYPE_INT,
1465 +               .name = "tr_good",
1466 +
1467 +               .description = "Transmit good packet counter. rt5350 only",
1468 +               .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1469 +               .get = esw_get_port_tr_badgood,
1470 +       },
1471 +};
1472 +
1473 +static const struct switch_attr esw_vlan[] = {
1474 +};
1475 +
1476 +static const struct switch_dev_ops esw_ops = {
1477 +       .attr_global = {
1478 +               .attr = esw_global,
1479 +               .n_attr = ARRAY_SIZE(esw_global),
1480 +       },
1481 +       .attr_port = {
1482 +               .attr = esw_port,
1483 +               .n_attr = ARRAY_SIZE(esw_port),
1484 +       },
1485 +       .attr_vlan = {
1486 +               .attr = esw_vlan,
1487 +               .n_attr = ARRAY_SIZE(esw_vlan),
1488 +       },
1489 +       .get_vlan_ports = esw_get_vlan_ports,
1490 +       .set_vlan_ports = esw_set_vlan_ports,
1491 +       .get_port_pvid = esw_get_port_pvid,
1492 +       .set_port_pvid = esw_set_port_pvid,
1493 +       .get_port_link = esw_get_port_link,
1494 +       .apply_config = esw_apply_config,
1495 +       .reset_switch = esw_reset_switch,
1496 +};
1497 +
1498 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1499 +       /* All ports are LAN ports. */
1500 +       .vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
1501 +       .reg_initval_fct2       = 0x00d6500c,
1502 +       /*
1503 +        * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1504 +        * turbo mii off, rgmi 3.3v off
1505 +        * port5: disabled
1506 +        * port6: enabled, gige, full-duplex, rx/tx-flow-control
1507 +        */
1508 +       .reg_initval_fpa2       = 0x3f502b28,
1509 +};
1510 +
1511 +static const struct of_device_id ralink_esw_match[] = {
1512 +       { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1513 +       {},
1514 +};
1515 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1516 +
1517 +static int esw_probe(struct platform_device *pdev)
1518 +{
1519 +       struct device_node *np = pdev->dev.of_node;
1520 +       const struct rt305x_esw_platform_data *pdata;
1521 +       const __be32 *port_map, *reg_init;
1522 +       struct rt305x_esw *esw;
1523 +       struct switch_dev *swdev;
1524 +       struct resource *res, *irq;
1525 +       int err;
1526 +
1527 +       pdata = pdev->dev.platform_data;
1528 +       if (!pdata) {
1529 +               const struct of_device_id *match;
1530 +               match = of_match_device(ralink_esw_match, &pdev->dev);
1531 +               if (match)
1532 +                       pdata = (struct rt305x_esw_platform_data *) match->data;
1533 +       }
1534 +       if (!pdata)
1535 +               return -EINVAL;
1536 +
1537 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1538 +       if (!res) {
1539 +               dev_err(&pdev->dev, "no memory resource found\n");
1540 +               return -ENOMEM;
1541 +       }
1542 +
1543 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1544 +       if (!irq) {
1545 +               dev_err(&pdev->dev, "no irq resource found\n");
1546 +               return -ENOMEM;
1547 +       }
1548 +
1549 +       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1550 +       if (!esw) {
1551 +               dev_err(&pdev->dev, "no memory for private data\n");
1552 +               return -ENOMEM;
1553 +       }
1554 +
1555 +       esw->dev = &pdev->dev;
1556 +       esw->irq = irq->start;
1557 +       esw->base = ioremap(res->start, resource_size(res));
1558 +       if (!esw->base) {
1559 +               dev_err(&pdev->dev, "ioremap failed\n");
1560 +               err = -ENOMEM;
1561 +               goto free_esw;
1562 +       }
1563 +
1564 +       port_map = of_get_property(np, "ralink,portmap", NULL);
1565 +        if (port_map)
1566 +               esw->port_map = be32_to_cpu(*port_map);
1567 +
1568 +       reg_init = of_get_property(np, "ralink,fct2", NULL);
1569 +        if (reg_init)
1570 +               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1571 +
1572 +       reg_init = of_get_property(np, "ralink,fpa2", NULL);
1573 +        if (reg_init)
1574 +               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1575 +
1576 +       reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1577 +        if (reg_init)
1578 +               esw->reg_led_polarity = be32_to_cpu(*reg_init);
1579 +
1580 +       swdev = &esw->swdev;
1581 +       swdev->of_node = pdev->dev.of_node;
1582 +       swdev->name = "rt305x-esw";
1583 +       swdev->alias = "rt305x";
1584 +       swdev->cpu_port = RT305X_ESW_PORT6;
1585 +       swdev->ports = RT305X_ESW_NUM_PORTS;
1586 +       swdev->vlans = RT305X_ESW_NUM_VIDS;
1587 +       swdev->ops = &esw_ops;
1588 +
1589 +       err = register_switch(swdev, NULL);
1590 +       if (err < 0) {
1591 +               dev_err(&pdev->dev, "register_switch failed\n");
1592 +               goto unmap_base;
1593 +       }
1594 +
1595 +       platform_set_drvdata(pdev, esw);
1596 +
1597 +       esw->pdata = pdata;
1598 +       spin_lock_init(&esw->reg_rw_lock);
1599 +
1600 +       esw_hw_init(esw);
1601 +
1602 +       esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1603 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1604 +       request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1605 +
1606 +       return 0;
1607 +
1608 +unmap_base:
1609 +       iounmap(esw->base);
1610 +free_esw:
1611 +       kfree(esw);
1612 +       return err;
1613 +}
1614 +
1615 +static int esw_remove(struct platform_device *pdev)
1616 +{
1617 +       struct rt305x_esw *esw;
1618 +
1619 +       esw = platform_get_drvdata(pdev);
1620 +       if (esw) {
1621 +               unregister_switch(&esw->swdev);
1622 +               platform_set_drvdata(pdev, NULL);
1623 +               iounmap(esw->base);
1624 +               kfree(esw);
1625 +       }
1626 +
1627 +       return 0;
1628 +}
1629 +
1630 +static struct platform_driver esw_driver = {
1631 +       .probe = esw_probe,
1632 +       .remove = esw_remove,
1633 +       .driver = {
1634 +               .name = "rt305x-esw",
1635 +               .owner = THIS_MODULE,
1636 +               .of_match_table = ralink_esw_match,
1637 +       },
1638 +};
1639 +
1640 +int __init rtesw_init(void)
1641 +{
1642 +       return platform_driver_register(&esw_driver);
1643 +}
1644 +
1645 +void rtesw_exit(void)
1646 +{
1647 +       platform_driver_unregister(&esw_driver);
1648 +}
1649 Index: linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.h
1650 ===================================================================
1651 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1652 +++ linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.h      2014-10-28 10:43:11.886131208 +0100
1653 @@ -0,0 +1,32 @@
1654 +/*
1655 + *   This program is free software; you can redistribute it and/or modify
1656 + *   it under the terms of the GNU General Public License as published by
1657 + *   the Free Software Foundation; version 2 of the License
1658 + *
1659 + *   This program is distributed in the hope that it will be useful,
1660 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1661 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1662 + *   GNU General Public License for more details.
1663 + *
1664 + *   You should have received a copy of the GNU General Public License
1665 + *   along with this program; if not, write to the Free Software
1666 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1667 + *
1668 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1669 + */
1670 +
1671 +#ifndef _RALINK_ESW_RT3052_H__
1672 +#define _RALINK_ESW_RT3052_H__
1673 +
1674 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1675 +
1676 +int __init rtesw_init(void);
1677 +void rtesw_exit(void);
1678 +
1679 +#else
1680 +
1681 +static inline int __init rtesw_init(void) { return 0; }
1682 +static inline void rtesw_exit(void) { }
1683 +
1684 +#endif
1685 +#endif
1686 Index: linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.c
1687 ===================================================================
1688 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1689 +++ linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.c     2014-10-29 14:58:32.303564882 +0100
1690 @@ -0,0 +1,568 @@
1691 +/*
1692 + *   This program is free software; you can redistribute it and/or modify
1693 + *   it under the terms of the GNU General Public License as published by
1694 + *   the Free Software Foundation; version 2 of the License
1695 + *
1696 + *   This program is distributed in the hope that it will be useful,
1697 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1698 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1699 + *   GNU General Public License for more details.
1700 + *
1701 + *   You should have received a copy of the GNU General Public License
1702 + *   along with this program; if not, write to the Free Software
1703 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1704 + *
1705 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1706 + */
1707 +
1708 +#include <linux/module.h>
1709 +#include <linux/kernel.h>
1710 +#include <linux/types.h>
1711 +#include <linux/dma-mapping.h>
1712 +#include <linux/init.h>
1713 +#include <linux/skbuff.h>
1714 +#include <linux/etherdevice.h>
1715 +#include <linux/ethtool.h>
1716 +#include <linux/platform_device.h>
1717 +#include <linux/of_device.h>
1718 +#include <linux/clk.h>
1719 +#include <linux/of_net.h>
1720 +#include <linux/of_mdio.h>
1721 +#include <linux/of_irq.h>
1722 +#include <linux/of_address.h>
1723 +#include <linux/switch.h>
1724 +
1725 +#include <asm/mach-ralink/ralink_regs.h>
1726 +
1727 +#include "ralink_soc_eth.h"
1728 +
1729 +#include <linux/ioport.h>
1730 +#include <linux/switch.h>
1731 +#include <linux/mii.h>
1732 +
1733 +#include <ralink_regs.h>
1734 +#include <asm/mach-ralink/mt7620.h>
1735 +
1736 +#include "ralink_soc_eth.h"
1737 +#include "gsw_mt7620a.h"
1738 +#include "mt7530.h"
1739 +#include "mdio.h"
1740 +
1741 +#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
1742 +
1743 +#define MT7620A_GSW_REG_PIAC   0x7004
1744 +
1745 +#define GSW_NUM_VLANS          16
1746 +#define GSW_NUM_VIDS           4096
1747 +#define GSW_NUM_PORTS          7
1748 +#define GSW_PORT6              6
1749 +
1750 +#define GSW_MDIO_ACCESS                BIT(31)
1751 +#define GSW_MDIO_READ          BIT(19)
1752 +#define GSW_MDIO_WRITE         BIT(18)
1753 +#define GSW_MDIO_START         BIT(16)
1754 +#define GSW_MDIO_ADDR_SHIFT    20
1755 +#define GSW_MDIO_REG_SHIFT     25
1756 +
1757 +#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
1758 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1759 +#define GSW_REG_SMACCR0                0x3fE4
1760 +#define GSW_REG_SMACCR1                0x3fE8
1761 +#define GSW_REG_CKGCR          0x3ff0
1762 +
1763 +#define GSW_REG_IMR            0x7008
1764 +#define GSW_REG_ISR            0x700c
1765 +
1766 +#define SYSC_REG_CFG1          0x14
1767 +
1768 +#define PORT_IRQ_ST_CHG                0x7f
1769 +
1770 +#define SYSCFG1                        0x14
1771 +
1772 +#define ESW_PHY_POLLING                0x7000
1773 +
1774 +#define        PMCR_IPG                BIT(18)
1775 +#define        PMCR_MAC_MODE           BIT(16)
1776 +#define        PMCR_FORCE              BIT(15)
1777 +#define        PMCR_TX_EN              BIT(14)
1778 +#define        PMCR_RX_EN              BIT(13)
1779 +#define        PMCR_BACKOFF            BIT(9)
1780 +#define        PMCR_BACKPRES           BIT(8)
1781 +#define        PMCR_RX_FC              BIT(5)
1782 +#define        PMCR_TX_FC              BIT(4)
1783 +#define        PMCR_SPEED(_x)          (_x << 2)
1784 +#define        PMCR_DUPLEX             BIT(1)
1785 +#define        PMCR_LINK               BIT(0)
1786 +
1787 +#define PHY_AN_EN              BIT(31)
1788 +#define PHY_PRE_EN             BIT(30)
1789 +#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
1790 +
1791 +enum {
1792 +       /* Global attributes. */
1793 +       GSW_ATTR_ENABLE_VLAN,
1794 +       /* Port attributes. */
1795 +       GSW_ATTR_PORT_UNTAG,
1796 +};
1797 +
1798 +enum {
1799 +       PORT4_EPHY = 0,
1800 +       PORT4_EXT,
1801 +};
1802 +
1803 +struct mt7620_gsw {
1804 +       struct device           *dev;
1805 +       void __iomem            *base;
1806 +       int                     irq;
1807 +       int                     port4;
1808 +       long unsigned int       autopoll;
1809 +};
1810 +
1811 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1812 +{
1813 +       iowrite32(val, gsw->base + reg);
1814 +}
1815 +
1816 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1817 +{
1818 +       return ioread32(gsw->base + reg);
1819 +}
1820 +
1821 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1822 +{
1823 +       unsigned long t_start = jiffies;
1824 +
1825 +       while (1) {
1826 +               if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1827 +                       return 0;
1828 +               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1829 +                       break;
1830 +               }
1831 +       }
1832 +
1833 +       printk(KERN_ERR "mdio: MDIO timeout\n");
1834 +       return -1;
1835 +}
1836 +
1837 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1838 +                               u32 write_data)
1839 +{
1840 +       if (mt7620_mii_busy_wait(gsw))
1841 +               return -1;
1842 +
1843 +       write_data &= 0xffff;
1844 +
1845 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1846 +               (phy_register << GSW_MDIO_REG_SHIFT) |
1847 +               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1848 +               MT7620A_GSW_REG_PIAC);
1849 +
1850 +       if (mt7620_mii_busy_wait(gsw))
1851 +               return -1;
1852 +
1853 +       return 0;
1854 +}
1855 +
1856 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1857 +{
1858 +       u32 d;
1859 +
1860 +       if (mt7620_mii_busy_wait(gsw))
1861 +               return 0xffff;
1862 +
1863 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1864 +               (phy_reg << GSW_MDIO_REG_SHIFT) |
1865 +               (phy_addr << GSW_MDIO_ADDR_SHIFT),
1866 +               MT7620A_GSW_REG_PIAC);
1867 +
1868 +       if (mt7620_mii_busy_wait(gsw))
1869 +               return 0xffff;
1870 +
1871 +       d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1872 +
1873 +       return d;
1874 +}
1875 +
1876 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1877 +{
1878 +       struct fe_priv *priv = bus->priv;
1879 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1880 +
1881 +       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1882 +}
1883 +
1884 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1885 +{
1886 +       struct fe_priv *priv = bus->priv;
1887 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1888 +
1889 +       return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1890 +}
1891 +
1892 +static unsigned char *fe_speed_str(int speed)
1893 +{
1894 +       switch (speed) {
1895 +       case 2:
1896 +       case SPEED_1000:
1897 +               return "1000";
1898 +       case 1:
1899 +       case SPEED_100:
1900 +               return "100";
1901 +       case 0:
1902 +       case SPEED_10:
1903 +               return "10";
1904 +       }
1905 +
1906 +       return "? ";
1907 +}
1908 +
1909 +int mt7620a_has_carrier(struct fe_priv *priv)
1910 +{
1911 +        struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1912 +       int i;
1913 +
1914 +       for (i = 0; i < GSW_PORT6; i++)
1915 +               if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1916 +                       return 1;
1917 +       return 0;
1918 +}
1919 +
1920 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1921 +{
1922 +       if (!priv->phy)
1923 +               return;
1924 +
1925 +       if (mt7620a_has_carrier(priv))
1926 +               netif_carrier_on(priv->netdev);
1927 +       else
1928 +               netif_carrier_off(priv->netdev);
1929 +}
1930 +
1931 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1932 +{
1933 +       if (priv->link[port])
1934 +               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1935 +                       port, fe_speed_str(priv->phy->speed[port]),
1936 +                       (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1937 +       else
1938 +               netdev_info(priv->netdev, "port %d link down\n", port);
1939 +       mt7620a_handle_carrier(priv);
1940 +}
1941 +
1942 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1943 +{
1944 +       struct fe_priv *priv = (struct fe_priv *) _priv;
1945 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1946 +       u32 status;
1947 +       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1948 +
1949 +       status = gsw_r32(gsw, GSW_REG_ISR);
1950 +       if (status & PORT_IRQ_ST_CHG)
1951 +               for (i = 0; i <= max; i++) {
1952 +                       u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1953 +                       int link = status & 0x1;
1954 +
1955 +                       if (link != priv->link[i]) {
1956 +                               if (link)
1957 +                                       netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1958 +                                                       i, fe_speed_str((status >> 2) & 3),
1959 +                                                       (status & 0x2) ? "Full" : "Half");
1960 +                               else
1961 +                                       netdev_info(priv->netdev, "port %d link down\n", i);
1962 +                       }
1963 +
1964 +                       priv->link[i] = link;
1965 +               }
1966 +       mt7620a_handle_carrier(priv);
1967 +
1968 +       gsw_w32(gsw, status, GSW_REG_ISR);
1969 +
1970 +       return IRQ_HANDLED;
1971 +}
1972 +
1973 +static int mt7620_is_bga(void)
1974 +{
1975 +       u32 bga = rt_sysc_r32(0x0c);
1976 +
1977 +       return (bga >> 16) & 1;
1978 +}
1979 +
1980 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1981 +{
1982 +       int phy;
1983 +       int lsb = -1, msb = 0;
1984 +
1985 +       for_each_set_bit(phy, &gsw->autopoll, 32) {
1986 +               if (lsb < 0)
1987 +                       lsb = phy;
1988 +               msb = phy;
1989 +       }
1990 +
1991 +       gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1992 +}
1993 +
1994 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1995 +{
1996 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1997 +       const __be32 *_id = of_get_property(np, "reg", NULL);
1998 +       int phy_mode, size, id;
1999 +       int shift = 12;
2000 +       u32 val, mask = 0;
2001 +       int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2002 +
2003 +       if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2004 +               if (_id)
2005 +                       pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2006 +               else
2007 +                       pr_err("%s: invalid port id\n", np->name);
2008 +               return;
2009 +       }
2010 +
2011 +       id = be32_to_cpu(*_id);
2012 +
2013 +       if (id == 4)
2014 +               shift = 14;
2015 +
2016 +       priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2017 +       if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2018 +               pr_err("%s: invalid fixed link property\n", np->name);
2019 +               priv->phy->phy_fixed[id] = NULL;
2020 +               return;
2021 +       }
2022 +
2023 +       phy_mode = of_get_phy_mode(np);
2024 +       switch (phy_mode) {
2025 +       case PHY_INTERFACE_MODE_RGMII:
2026 +               mask = 0;
2027 +               break;
2028 +       case PHY_INTERFACE_MODE_MII:
2029 +               mask = 1;
2030 +               break;
2031 +       case PHY_INTERFACE_MODE_RMII:
2032 +               mask = 2;
2033 +               break;
2034 +       default:
2035 +               dev_err(priv->device, "port %d - invalid phy mode\n", id);
2036 +               return;
2037 +       }
2038 +
2039 +       priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2040 +       if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2041 +               return;
2042 +
2043 +       val = rt_sysc_r32(SYSCFG1);
2044 +       val &= ~(3 << shift);
2045 +       val |= mask << shift;
2046 +       rt_sysc_w32(val, SYSCFG1);
2047 +
2048 +       if (priv->phy->phy_fixed[id]) {
2049 +               const __be32 *link = priv->phy->phy_fixed[id];
2050 +               int tx_fc, rx_fc;
2051 +               u32 val = 0;
2052 +
2053 +               priv->phy->speed[id] = be32_to_cpup(link++);
2054 +               tx_fc = be32_to_cpup(link++);
2055 +               rx_fc = be32_to_cpup(link++);
2056 +               priv->phy->duplex[id] = be32_to_cpup(link++);
2057 +               priv->link[id] = 1;
2058 +
2059 +               switch (priv->phy->speed[id]) {
2060 +               case SPEED_10:
2061 +                       val = 0;
2062 +                       break;
2063 +               case SPEED_100:
2064 +                       val = 1;
2065 +                       break;
2066 +               case SPEED_1000:
2067 +                       val = 2;
2068 +                       break;
2069 +               default:
2070 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2071 +                       priv->phy->phy_fixed[id] = 0;
2072 +                       return;
2073 +               }
2074 +               val = PMCR_SPEED(val);
2075 +               val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2076 +                       PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2077 +               if (tx_fc)
2078 +                       val |= PMCR_TX_FC;
2079 +               if (rx_fc)
2080 +                       val |= PMCR_RX_FC;
2081 +               if (priv->phy->duplex[id])
2082 +                       val |= PMCR_DUPLEX;
2083 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2084 +               dev_info(priv->device, "using fixed link parameters\n");
2085 +               return;
2086 +       }
2087 +
2088 +       if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2089 +               u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2090 +                       PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
2091 +
2092 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2093 +               fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2094 +               gsw->autopoll |= BIT(id);
2095 +               gsw_auto_poll(gsw);
2096 +               return;
2097 +       }
2098 +}
2099 +
2100 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2101 +{
2102 +       u32 is_BGA = mt7620_is_bga();
2103 +
2104 +       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2105 +       gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2106 +
2107 +       /*correct  PHY  setting L3.0 BGA*/
2108 +       _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2109 +
2110 +       _mt7620_mii_write(gsw, 1, 17, 0x7444);
2111 +       if (is_BGA)
2112 +               _mt7620_mii_write(gsw, 1, 19, 0x0114);
2113 +       else
2114 +               _mt7620_mii_write(gsw, 1, 19, 0x0117);
2115 +
2116 +       _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2117 +       _mt7620_mii_write(gsw, 1, 25, 0x6212);
2118 +       _mt7620_mii_write(gsw, 1, 26, 0x0777);
2119 +       _mt7620_mii_write(gsw, 1, 29, 0x4000);
2120 +       _mt7620_mii_write(gsw, 1, 28, 0xc077);
2121 +       _mt7620_mii_write(gsw, 1, 24, 0x0000);
2122 +
2123 +       _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2124 +       _mt7620_mii_write(gsw, 1, 17, 0x4838);
2125 +
2126 +       _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2127 +       if (is_BGA) {
2128 +               _mt7620_mii_write(gsw, 1, 21, 0x0515);
2129 +               _mt7620_mii_write(gsw, 1, 22, 0x0053);
2130 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2131 +               _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2132 +               _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2133 +               _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2134 +       } else {
2135 +               _mt7620_mii_write(gsw, 1, 21, 0x0517);
2136 +               _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2137 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2138 +               _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2139 +               _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2140 +               _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2141 +       }
2142 +       _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2143 +       _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2144 +
2145 +       _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2146 +       _mt7620_mii_write(gsw, 0, 30, 0xa000);
2147 +       _mt7620_mii_write(gsw, 1, 30, 0xa000);
2148 +       _mt7620_mii_write(gsw, 2, 30, 0xa000);
2149 +       _mt7620_mii_write(gsw, 3, 30, 0xa000);
2150 +
2151 +       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2152 +       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2153 +       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2154 +       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2155 +       _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2156 +       _mt7620_mii_write(gsw, 0, 16, 0x1111);
2157 +       _mt7620_mii_write(gsw, 1, 16, 0x1010);
2158 +       _mt7620_mii_write(gsw, 2, 16, 0x1515);
2159 +       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2160 +
2161 +       /* CPU Port6 Force Link 1G, FC ON */
2162 +       gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2163 +       /* Set Port6 CPU Port */
2164 +       gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2165 +
2166 +       /* setup port 4 */
2167 +       if (gsw->port4 == PORT4_EPHY) {
2168 +               u32 val = rt_sysc_r32(SYSCFG1);
2169 +               val |= 3 << 14;
2170 +               rt_sysc_w32(val, SYSCFG1);
2171 +               _mt7620_mii_write(gsw, 4, 30, 0xa000);
2172 +               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2173 +               _mt7620_mii_write(gsw, 4, 16, 0x1313);
2174 +               pr_info("gsw: setting port4 to ephy mode\n");
2175 +       }
2176 +}
2177 +
2178 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2179 +{
2180 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2181 +       unsigned long flags;
2182 +
2183 +       spin_lock_irqsave(&priv->page_lock, flags);
2184 +       gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2185 +       gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2186 +               GSW_REG_SMACCR0);
2187 +       spin_unlock_irqrestore(&priv->page_lock, flags);
2188 +}
2189 +
2190 +static struct of_device_id gsw_match[] = {
2191 +       { .compatible = "ralink,mt7620a-gsw" },
2192 +       {}
2193 +};
2194 +
2195 +int mt7620_gsw_config(struct fe_priv *priv)
2196 +{
2197 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2198 +
2199 +       /* is the mt7530 internal or external */
2200 +       if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef)) {
2201 +               mt7530_probe(priv->device, gsw->base, NULL, 0);
2202 +               mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
2203 +       } else {
2204 +               mt7530_probe(priv->device, gsw->base, NULL, 1);
2205 +       }
2206 +
2207 +       return 0;
2208 +}
2209 +
2210 +int mt7620_gsw_probe(struct fe_priv *priv)
2211 +{
2212 +       struct mt7620_gsw *gsw;
2213 +       struct device_node *np;
2214 +       const char *port4 = NULL;
2215 +
2216 +       np = of_find_matching_node(NULL, gsw_match);
2217 +       if (!np) {
2218 +               dev_err(priv->device, "no gsw node found\n");
2219 +               return -EINVAL;
2220 +       }
2221 +       np = of_node_get(np);
2222 +
2223 +       gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2224 +       if (!gsw) {
2225 +               dev_err(priv->device, "no gsw memory for private data\n");
2226 +               return -ENOMEM;
2227 +       }
2228 +
2229 +       gsw->irq = irq_of_parse_and_map(np, 0);
2230 +       if (!gsw->irq) {
2231 +               dev_err(priv->device, "no gsw irq resource found\n");
2232 +               return -ENOMEM;
2233 +       }
2234 +
2235 +       gsw->base = of_iomap(np, 0);
2236 +       if (!gsw->base) {
2237 +               dev_err(priv->device, "gsw ioremap failed\n");
2238 +               return -ENOMEM;
2239 +       }
2240 +
2241 +       gsw->dev = priv->device;
2242 +       priv->soc->swpriv = gsw;
2243 +
2244 +       of_property_read_string(np, "ralink,port4", &port4);
2245 +       if (port4 && !strcmp(port4, "ephy"))
2246 +               gsw->port4 = PORT4_EPHY;
2247 +       else if (port4 && !strcmp(port4, "gmac"))
2248 +               gsw->port4 = PORT4_EXT;
2249 +       else
2250 +               WARN_ON(port4);
2251 +
2252 +       gsw_hw_init(gsw);
2253 +
2254 +       gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2255 +       request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2256 +
2257 +       return 0;
2258 +}
2259 Index: linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.h
2260 ===================================================================
2261 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2262 +++ linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.h     2014-10-28 10:43:11.890131215 +0100
2263 @@ -0,0 +1,30 @@
2264 +/*
2265 + *   This program is free software; you can redistribute it and/or modify
2266 + *   it under the terms of the GNU General Public License as published by
2267 + *   the Free Software Foundation; version 2 of the License
2268 + *
2269 + *   This program is distributed in the hope that it will be useful,
2270 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2271 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2272 + *   GNU General Public License for more details.
2273 + *
2274 + *   You should have received a copy of the GNU General Public License
2275 + *   along with this program; if not, write to the Free Software
2276 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2277 + *
2278 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2279 + */
2280 +
2281 +#ifndef _RALINK_GSW_MT7620_H__
2282 +#define _RALINK_GSW_MT7620_H__
2283 +
2284 +extern int mt7620_gsw_config(struct fe_priv *priv);
2285 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2286 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2287 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2288 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2289 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2290 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2291 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2292 +
2293 +#endif
2294 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio.c
2295 ===================================================================
2296 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2297 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio.c    2014-10-28 10:43:11.890131215 +0100
2298 @@ -0,0 +1,244 @@
2299 +/*
2300 + *   This program is free software; you can redistribute it and/or modify
2301 + *   it under the terms of the GNU General Public License as published by
2302 + *   the Free Software Foundation; version 2 of the License
2303 + *
2304 + *   This program is distributed in the hope that it will be useful,
2305 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2306 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2307 + *   GNU General Public License for more details.
2308 + *
2309 + *   You should have received a copy of the GNU General Public License
2310 + *   along with this program; if not, write to the Free Software
2311 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2312 + *
2313 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2314 + */
2315 +
2316 +#include <linux/module.h>
2317 +#include <linux/kernel.h>
2318 +#include <linux/types.h>
2319 +#include <linux/dma-mapping.h>
2320 +#include <linux/init.h>
2321 +#include <linux/skbuff.h>
2322 +#include <linux/etherdevice.h>
2323 +#include <linux/ethtool.h>
2324 +#include <linux/platform_device.h>
2325 +#include <linux/phy.h>
2326 +#include <linux/of_device.h>
2327 +#include <linux/clk.h>
2328 +#include <linux/of_net.h>
2329 +#include <linux/of_mdio.h>
2330 +
2331 +#include "ralink_soc_eth.h"
2332 +#include "mdio.h"
2333 +
2334 +static int fe_mdio_reset(struct mii_bus *bus)
2335 +{
2336 +       /* TODO */
2337 +       return 0;
2338 +}
2339 +
2340 +static void fe_phy_link_adjust(struct net_device *dev)
2341 +{
2342 +       struct fe_priv *priv = netdev_priv(dev);
2343 +       unsigned long flags;
2344 +       int i;
2345 +
2346 +       spin_lock_irqsave(&priv->phy->lock, flags);
2347 +       for (i = 0; i < 8; i++) {
2348 +               if (priv->phy->phy_node[i]) {
2349 +                       struct phy_device *phydev = priv->phy->phy[i];
2350 +                       int status_change = 0;
2351 +
2352 +                       if (phydev->link)
2353 +                               if (priv->phy->duplex[i] != phydev->duplex ||
2354 +                                               priv->phy->speed[i] != phydev->speed)
2355 +                                       status_change = 1;
2356 +
2357 +                       if (phydev->link != priv->link[i])
2358 +                               status_change = 1;
2359 +
2360 +                       switch (phydev->speed) {
2361 +                       case SPEED_1000:
2362 +                       case SPEED_100:
2363 +                       case SPEED_10:
2364 +                               priv->link[i] = phydev->link;
2365 +                               priv->phy->duplex[i] = phydev->duplex;
2366 +                               priv->phy->speed[i] = phydev->speed;
2367 +
2368 +                               if (status_change && priv->soc->mdio_adjust_link)
2369 +                                       priv->soc->mdio_adjust_link(priv, i);
2370 +                               break;
2371 +                       }
2372 +               }
2373 +       }
2374 +}
2375 +
2376 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2377 +{
2378 +       const __be32 *_port = NULL;
2379 +       struct phy_device *phydev;
2380 +       int phy_mode, port;
2381 +
2382 +       _port = of_get_property(phy_node, "reg", NULL);
2383 +
2384 +       if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2385 +               pr_err("%s: invalid port id\n", phy_node->name);
2386 +               return -EINVAL;
2387 +       }
2388 +       port = be32_to_cpu(*_port);
2389 +       phy_mode = of_get_phy_mode(phy_node);
2390 +       if (phy_mode < 0) {
2391 +               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2392 +               priv->phy->phy_node[port] = NULL;
2393 +               return -EINVAL;
2394 +       }
2395 +
2396 +       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2397 +                               0, phy_mode);
2398 +       if (IS_ERR(phydev)) {
2399 +               dev_err(priv->device, "could not connect to PHY\n");
2400 +               priv->phy->phy_node[port] = NULL;
2401 +               return PTR_ERR(phydev);
2402 +       }
2403 +
2404 +       phydev->supported &= PHY_GBIT_FEATURES;
2405 +       phydev->advertising = phydev->supported;
2406 +       phydev->no_auto_carrier_off = 1;
2407 +
2408 +       dev_info(priv->device,
2409 +                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2410 +                port, dev_name(&phydev->dev), phydev->phy_id,
2411 +                phydev->drv->name);
2412 +
2413 +       priv->phy->phy[port] = phydev;
2414 +       priv->link[port] = 0;
2415 +
2416 +       return 0;
2417 +}
2418 +
2419 +static int fe_phy_connect(struct fe_priv *priv)
2420 +{
2421 +       return 0;
2422 +}
2423 +
2424 +static void fe_phy_disconnect(struct fe_priv *priv)
2425 +{
2426 +       unsigned long flags;
2427 +       int i;
2428 +
2429 +       for (i = 0; i < 8; i++)
2430 +               if (priv->phy->phy_fixed[i]) {
2431 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2432 +                       priv->link[i] = 0;
2433 +                       if (priv->soc->mdio_adjust_link)
2434 +                               priv->soc->mdio_adjust_link(priv, i);
2435 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2436 +               } else if (priv->phy->phy[i]) {
2437 +                       phy_disconnect(priv->phy->phy[i]);
2438 +               }
2439 +}
2440 +
2441 +static void fe_phy_start(struct fe_priv *priv)
2442 +{
2443 +       unsigned long flags;
2444 +       int i;
2445 +
2446 +       for (i = 0; i < 8; i++) {
2447 +               if (priv->phy->phy_fixed[i]) {
2448 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2449 +                       priv->link[i] = 1;
2450 +                       if (priv->soc->mdio_adjust_link)
2451 +                               priv->soc->mdio_adjust_link(priv, i);
2452 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2453 +               } else if (priv->phy->phy[i]) {
2454 +                       phy_start(priv->phy->phy[i]);
2455 +               }
2456 +       }
2457 +}
2458 +
2459 +static void fe_phy_stop(struct fe_priv *priv)
2460 +{
2461 +       unsigned long flags;
2462 +       int i;
2463 +
2464 +       for (i = 0; i < 8; i++)
2465 +               if (priv->phy->phy_fixed[i]) {
2466 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2467 +                       priv->link[i] = 0;
2468 +                       if (priv->soc->mdio_adjust_link)
2469 +                               priv->soc->mdio_adjust_link(priv, i);
2470 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2471 +               } else if (priv->phy->phy[i]) {
2472 +                       phy_stop(priv->phy->phy[i]);
2473 +               }
2474 +}
2475 +
2476 +static struct fe_phy phy_ralink = {
2477 +       .connect = fe_phy_connect,
2478 +       .disconnect = fe_phy_disconnect,
2479 +       .start = fe_phy_start,
2480 +       .stop = fe_phy_stop,
2481 +};
2482 +
2483 +int fe_mdio_init(struct fe_priv *priv)
2484 +{
2485 +       struct device_node *mii_np;
2486 +       int err;
2487 +
2488 +       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2489 +               return 0;
2490 +
2491 +       spin_lock_init(&phy_ralink.lock);
2492 +       priv->phy = &phy_ralink;
2493 +
2494 +       mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2495 +       if (!mii_np) {
2496 +               dev_err(priv->device, "no %s child node found", "mdio-bus");
2497 +               return -ENODEV;
2498 +       }
2499 +
2500 +       if (!of_device_is_available(mii_np)) {
2501 +               err = 0;
2502 +               goto err_put_node;
2503 +       }
2504 +
2505 +       priv->mii_bus = mdiobus_alloc();
2506 +       if (priv->mii_bus == NULL) {
2507 +               err = -ENOMEM;
2508 +               goto err_put_node;
2509 +       }
2510 +
2511 +       priv->mii_bus->name = "mdio";
2512 +       priv->mii_bus->read = priv->soc->mdio_read;
2513 +       priv->mii_bus->write = priv->soc->mdio_write;
2514 +       priv->mii_bus->reset = fe_mdio_reset;
2515 +       priv->mii_bus->irq = priv->mii_irq;
2516 +       priv->mii_bus->priv = priv;
2517 +       priv->mii_bus->parent = priv->device;
2518 +
2519 +       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2520 +       err = of_mdiobus_register(priv->mii_bus, mii_np);
2521 +       if (err)
2522 +               goto err_free_bus;
2523 +
2524 +       return 0;
2525 +
2526 +err_free_bus:
2527 +       kfree(priv->mii_bus);
2528 +err_put_node:
2529 +       of_node_put(mii_np);
2530 +       priv->mii_bus = NULL;
2531 +       return err;
2532 +}
2533 +
2534 +void fe_mdio_cleanup(struct fe_priv *priv)
2535 +{
2536 +       if (!priv->mii_bus)
2537 +               return;
2538 +
2539 +       mdiobus_unregister(priv->mii_bus);
2540 +       of_node_put(priv->mii_bus->dev.of_node);
2541 +       kfree(priv->mii_bus);
2542 +}
2543 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio.h
2544 ===================================================================
2545 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2546 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio.h    2014-10-28 10:43:11.890131215 +0100
2547 @@ -0,0 +1,29 @@
2548 +/*
2549 + *   This program is free software; you can redistribute it and/or modify
2550 + *   it under the terms of the GNU General Public License as published by
2551 + *   the Free Software Foundation; version 2 of the License
2552 + *
2553 + *   This program is distributed in the hope that it will be useful,
2554 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2555 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2556 + *   GNU General Public License for more details.
2557 + *
2558 + *   You should have received a copy of the GNU General Public License
2559 + *   along with this program; if not, write to the Free Software
2560 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2561 + *
2562 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2563 + */
2564 +
2565 +#ifndef _RALINK_MDIO_H__
2566 +#define _RALINK_MDIO_H__
2567 +
2568 +#ifdef CONFIG_NET_RALINK_MDIO
2569 +extern int fe_mdio_init(struct fe_priv *priv);
2570 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2571 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2572 +#else
2573 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2574 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2575 +#endif
2576 +#endif
2577 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.c
2578 ===================================================================
2579 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2580 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.c     2014-10-28 10:43:11.890131215 +0100
2581 @@ -0,0 +1,232 @@
2582 +/*
2583 + *   This program is free software; you can redistribute it and/or modify
2584 + *   it under the terms of the GNU General Public License as published by
2585 + *   the Free Software Foundation; version 2 of the License
2586 + *
2587 + *   This program is distributed in the hope that it will be useful,
2588 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2589 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2590 + *   GNU General Public License for more details.
2591 + *
2592 + *   You should have received a copy of the GNU General Public License
2593 + *   along with this program; if not, write to the Free Software
2594 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2595 + *
2596 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2597 + */
2598 +
2599 +#include <linux/module.h>
2600 +#include <linux/kernel.h>
2601 +#include <linux/types.h>
2602 +#include <linux/dma-mapping.h>
2603 +#include <linux/init.h>
2604 +#include <linux/skbuff.h>
2605 +#include <linux/etherdevice.h>
2606 +#include <linux/ethtool.h>
2607 +#include <linux/platform_device.h>
2608 +#include <linux/phy.h>
2609 +#include <linux/of_device.h>
2610 +#include <linux/clk.h>
2611 +#include <linux/of_net.h>
2612 +#include <linux/of_mdio.h>
2613 +
2614 +#include "ralink_soc_eth.h"
2615 +#include "mdio_rt2880.h"
2616 +#include "mdio.h"
2617 +
2618 +#define FE_MDIO_RETRY  1000
2619 +
2620 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2621 +{
2622 +       switch (priv->phy->speed[0]) {
2623 +       case SPEED_1000:
2624 +               return "1000";
2625 +       case SPEED_100:
2626 +               return "100";
2627 +       case SPEED_10:
2628 +               return "10";
2629 +       }
2630 +
2631 +       return "?";
2632 +}
2633 +
2634 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2635 +{
2636 +       u32 mdio_cfg;
2637 +
2638 +       if (!priv->link[0]) {
2639 +               netif_carrier_off(priv->netdev);
2640 +               netdev_info(priv->netdev, "link down\n");
2641 +               return;
2642 +       }
2643 +
2644 +       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2645 +                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
2646 +                  FE_MDIO_CFG_GP1_FRC_EN;
2647 +
2648 +       if (priv->phy->duplex[0] == DUPLEX_FULL)
2649 +               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2650 +
2651 +       if (priv->phy->tx_fc[0])
2652 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2653 +
2654 +       if (priv->phy->rx_fc[0])
2655 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2656 +
2657 +       switch (priv->phy->speed[0]) {
2658 +       case SPEED_10:
2659 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2660 +               break;
2661 +       case SPEED_100:
2662 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2663 +               break;
2664 +       case SPEED_1000:
2665 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2666 +               break;
2667 +       default:
2668 +               BUG();
2669 +       }
2670 +
2671 +       fe_w32(mdio_cfg, FE_MDIO_CFG);
2672 +
2673 +       netif_carrier_on(priv->netdev);
2674 +       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2675 +                   rt2880_speed_str(priv),
2676 +                   (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2677 +}
2678 +
2679 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2680 +{
2681 +       int retries;
2682 +
2683 +       retries = FE_MDIO_RETRY;
2684 +       while (1) {
2685 +               u32 t;
2686 +
2687 +               t = fe_r32(FE_MDIO_ACCESS);
2688 +               if ((t & (0x1 << 31)) == 0)
2689 +                       return 0;
2690 +
2691 +               if (retries-- == 0)
2692 +                       break;
2693 +
2694 +               udelay(1);
2695 +       }
2696 +
2697 +       dev_err(priv->device, "MDIO operation timed out\n");
2698 +       return -ETIMEDOUT;
2699 +}
2700 +
2701 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2702 +{
2703 +       struct fe_priv *priv = bus->priv;
2704 +       int err;
2705 +       u32 t;
2706 +
2707 +       err = rt2880_mdio_wait_ready(priv);
2708 +       if (err)
2709 +               return 0xffff;
2710 +
2711 +       t = (phy_addr << 24) | (phy_reg << 16);
2712 +       fe_w32(t, FE_MDIO_ACCESS);
2713 +       t |= (1 << 31);
2714 +       fe_w32(t, FE_MDIO_ACCESS);
2715 +
2716 +       err = rt2880_mdio_wait_ready(priv);
2717 +       if (err)
2718 +               return 0xffff;
2719 +
2720 +       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2721 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2722 +
2723 +       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2724 +}
2725 +
2726 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2727 +{
2728 +       struct fe_priv *priv = bus->priv;
2729 +       int err;
2730 +       u32 t;
2731 +
2732 +       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2733 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2734 +
2735 +       err = rt2880_mdio_wait_ready(priv);
2736 +       if (err)
2737 +               return err;
2738 +
2739 +       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2740 +       fe_w32(t, FE_MDIO_ACCESS);
2741 +       t |= (1 << 31);
2742 +       fe_w32(t, FE_MDIO_ACCESS);
2743 +
2744 +       return rt2880_mdio_wait_ready(priv);
2745 +}
2746 +
2747 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2748 +{
2749 +       const __be32 *id = of_get_property(np, "reg", NULL);
2750 +       const __be32 *link;
2751 +       int size;
2752 +       int phy_mode;
2753 +
2754 +       if (!id || (be32_to_cpu(*id) != 0)) {
2755 +               pr_err("%s: invalid port id\n", np->name);
2756 +               return;
2757 +       }
2758 +
2759 +       priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2760 +       if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2761 +               pr_err("%s: invalid fixed link property\n", np->name);
2762 +               priv->phy->phy_fixed[0] = NULL;
2763 +               return;
2764 +       }
2765 +
2766 +       phy_mode = of_get_phy_mode(np);
2767 +       switch (phy_mode) {
2768 +       case PHY_INTERFACE_MODE_RGMII:
2769 +               break;
2770 +       case PHY_INTERFACE_MODE_MII:
2771 +               break;
2772 +       case PHY_INTERFACE_MODE_RMII:
2773 +               break;
2774 +       default:
2775 +               if (!priv->phy->phy_fixed[0])
2776 +                       dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2777 +               break;
2778 +       }
2779 +
2780 +       priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2781 +       if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2782 +               return;
2783 +
2784 +       if (priv->phy->phy_fixed[0]) {
2785 +               link = priv->phy->phy_fixed[0];
2786 +               priv->phy->speed[0] = be32_to_cpup(link++);
2787 +               priv->phy->duplex[0] = be32_to_cpup(link++);
2788 +               priv->phy->tx_fc[0] = be32_to_cpup(link++);
2789 +               priv->phy->rx_fc[0] = be32_to_cpup(link++);
2790 +
2791 +               priv->link[0] = 1;
2792 +               switch (priv->phy->speed[0]) {
2793 +               case SPEED_10:
2794 +                       break;
2795 +               case SPEED_100:
2796 +                       break;
2797 +               case SPEED_1000:
2798 +                       break;
2799 +               default:
2800 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2801 +                       priv->phy->phy_fixed[0] = 0;
2802 +                       return;
2803 +               }
2804 +               dev_info(priv->device, "using fixed link parameters\n");
2805 +               rt2880_mdio_link_adjust(priv, 0);
2806 +               return;
2807 +       }
2808 +       if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2809 +               fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2810 +       }
2811 +
2812 +       return;
2813 +}
2814 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.h
2815 ===================================================================
2816 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2817 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.h     2014-10-28 10:43:11.890131215 +0100
2818 @@ -0,0 +1,26 @@
2819 +/*
2820 + *   This program is free software; you can redistribute it and/or modify
2821 + *   it under the terms of the GNU General Public License as published by
2822 + *   the Free Software Foundation; version 2 of the License
2823 + *
2824 + *   This program is distributed in the hope that it will be useful,
2825 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2826 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2827 + *   GNU General Public License for more details.
2828 + *
2829 + *   You should have received a copy of the GNU General Public License
2830 + *   along with this program; if not, write to the Free Software
2831 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2832 + *
2833 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2834 + */
2835 +
2836 +#ifndef _RALINK_MDIO_RT2880_H__
2837 +#define _RALINK_MDIO_RT2880_H__
2838 +
2839 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2840 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2841 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2842 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2843 +
2844 +#endif
2845 Index: linux-3.14.18/drivers/net/ethernet/ralink/mt7530.c
2846 ===================================================================
2847 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2848 +++ linux-3.14.18/drivers/net/ethernet/ralink/mt7530.c  2014-10-29 14:58:52.303587070 +0100
2849 @@ -0,0 +1,582 @@
2850 +/*
2851 + * This program is free software; you can redistribute it and/or
2852 + * modify it under the terms of the GNU General Public License
2853 + * as published by the Free Software Foundation; either version 2
2854 + * of the License, or (at your option) any later version.
2855 + *
2856 + * This program is distributed in the hope that it will be useful,
2857 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2858 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2859 + * GNU General Public License for more details.
2860 + *
2861 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
2862 + */
2863 +
2864 +#include <linux/if.h>
2865 +#include <linux/module.h>
2866 +#include <linux/init.h>
2867 +#include <linux/list.h>
2868 +#include <linux/if_ether.h>
2869 +#include <linux/skbuff.h>
2870 +#include <linux/netdevice.h>
2871 +#include <linux/netlink.h>
2872 +#include <linux/bitops.h>
2873 +#include <net/genetlink.h>
2874 +#include <linux/switch.h>
2875 +#include <linux/delay.h>
2876 +#include <linux/phy.h>
2877 +#include <linux/netdevice.h>
2878 +#include <linux/etherdevice.h>
2879 +#include <linux/lockdep.h>
2880 +#include <linux/workqueue.h>
2881 +#include <linux/of_device.h>
2882 +
2883 +#include "mt7530.h"
2884 +
2885 +#define MT7530_CPU_PORT                6
2886 +#define MT7530_NUM_PORTS       8
2887 +#define MT7530_NUM_VLANS       16
2888 +#define MT7530_MAX_VID         4095
2889 +#define MT7530_MIN_VID         0
2890 +
2891 +/* registers */
2892 +#define REG_ESW_VLAN_VTCR              0x90
2893 +#define REG_ESW_VLAN_VAWD1             0x94
2894 +#define REG_ESW_VLAN_VAWD2             0x98
2895 +#define REG_ESW_VLAN_VTIM(x)   (0x100 + 4 * ((x) / 2))
2896 +
2897 +#define REG_ESW_VLAN_VAWD1_IVL_MAC     BIT(30)
2898 +#define REG_ESW_VLAN_VAWD1_VTAG_EN     BIT(28)
2899 +#define REG_ESW_VLAN_VAWD1_VALID       BIT(0)
2900 +
2901 +/* vlan egress mode */
2902 +enum {
2903 +       ETAG_CTRL_UNTAG = 0,
2904 +       ETAG_CTRL_TAG   = 2,
2905 +       ETAG_CTRL_SWAP  = 1,
2906 +       ETAG_CTRL_STACK = 3,
2907 +};
2908 +
2909 +#define REG_ESW_PORT_PCR(x)    (0x2004 | ((x) << 8))
2910 +#define REG_ESW_PORT_PVC(x)    (0x2010 | ((x) << 8))
2911 +#define REG_ESW_PORT_PPBV1(x)  (0x2014 | ((x) << 8))
2912 +enum {
2913 +       /* Global attributes. */
2914 +       MT7530_ATTR_ENABLE_VLAN,
2915 +};
2916 +
2917 +struct mt7530_port_entry {
2918 +       u16     pvid;
2919 +};
2920 +
2921 +struct mt7530_vlan_entry {
2922 +       u16     vid;
2923 +       u8      member;
2924 +       u8      etags;
2925 +};
2926 +
2927 +struct mt7530_priv {
2928 +       void __iomem            *base;
2929 +       struct mii_bus          *bus;
2930 +       struct switch_dev       swdev;
2931 +
2932 +       bool                    global_vlan_enable;
2933 +       struct mt7530_vlan_entry        vlan_entries[MT7530_NUM_VLANS];
2934 +       struct mt7530_port_entry        port_entries[MT7530_NUM_PORTS];
2935 +};
2936 +
2937 +struct mt7530_mapping {
2938 +       char    *name;
2939 +       u16     pvids[MT7530_NUM_PORTS];
2940 +       u8      members[MT7530_NUM_VLANS];
2941 +       u8      etags[MT7530_NUM_VLANS];
2942 +       u16     vids[MT7530_NUM_VLANS];
2943 +} mt7530_defaults[] = {
2944 +       {
2945 +               .name = "llllw",
2946 +               .pvids = { 1, 1, 1, 1, 2, 1, 1 },
2947 +               .members = { 0, 0x6f, 0x50 },
2948 +               .etags = { 0, 0x40, 0x40 },
2949 +               .vids = { 0, 1, 2 },
2950 +       }, {
2951 +               .name = "wllll",
2952 +               .pvids = { 2, 1, 1, 1, 1, 1, 1 },
2953 +               .members = { 0, 0x7e, 0x41 },
2954 +               .etags = { 0, 0x40, 0x40 },
2955 +               .vids = { 0, 1, 2 },
2956 +       },
2957 +};
2958 +
2959 +struct mt7530_mapping*
2960 +mt7530_find_mapping(struct device_node *np)
2961 +{
2962 +       const char *map;
2963 +       int i;
2964 +
2965 +       if (of_property_read_string(np, "ralink,port-map", &map))
2966 +               return NULL;
2967 +
2968 +       for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
2969 +               if (!strcmp(map, mt7530_defaults[i].name))
2970 +                       return &mt7530_defaults[i];
2971 +
2972 +       return NULL;
2973 +}
2974 +
2975 +static void
2976 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
2977 +{
2978 +       int i = 0;
2979 +
2980 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
2981 +               mt7530->port_entries[i].pvid = map->pvids[i];
2982 +
2983 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
2984 +               mt7530->vlan_entries[i].member = map->members[i];
2985 +               mt7530->vlan_entries[i].etags = map->etags[i];
2986 +               mt7530->vlan_entries[i].vid = map->vids[i];
2987 +       }
2988 +}
2989 +
2990 +static int
2991 +mt7530_reset_switch(struct switch_dev *dev)
2992 +{
2993 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
2994 +       int i;
2995 +
2996 +       memset(priv->port_entries, 0, sizeof(priv->port_entries));
2997 +       memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
2998 +
2999 +       /* set default vid of each vlan to the same number of vlan, so the vid
3000 +        * won't need be set explicitly.
3001 +        */
3002 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
3003 +               priv->vlan_entries[i].vid = i;
3004 +       }
3005 +
3006 +       return 0;
3007 +}
3008 +
3009 +static int
3010 +mt7530_get_vlan_enable(struct switch_dev *dev,
3011 +                          const struct switch_attr *attr,
3012 +                          struct switch_val *val)
3013 +{
3014 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3015 +
3016 +       val->value.i = priv->global_vlan_enable;
3017 +
3018 +       return 0;
3019 +}
3020 +
3021 +static int
3022 +mt7530_set_vlan_enable(struct switch_dev *dev,
3023 +                          const struct switch_attr *attr,
3024 +                          struct switch_val *val)
3025 +{
3026 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3027 +
3028 +       priv->global_vlan_enable = val->value.i != 0;
3029 +
3030 +       return 0;
3031 +}
3032 +
3033 +static u32
3034 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
3035 +{
3036 +       u32 val;
3037 +       if (priv->bus) {
3038 +               u16 high, low;
3039 +
3040 +               mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3041 +               low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
3042 +               high = mdiobus_read(priv->bus, 0x1f, 0x10);
3043 +
3044 +               return (high << 16) | (low & 0xffff);
3045 +       }
3046 +
3047 +       val = ioread32(priv->base + reg);
3048 +       pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
3049 +
3050 +       return val;
3051 +}
3052 +
3053 +static void
3054 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
3055 +{
3056 +       if (priv->bus) {
3057 +               mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3058 +               mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
3059 +               mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
3060 +               return;
3061 +       }
3062 +
3063 +       pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
3064 +       iowrite32(val, priv->base + reg);
3065 +}
3066 +
3067 +static void
3068 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
3069 +{
3070 +       int i;
3071 +
3072 +       mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
3073 +
3074 +       for (i = 0; i < 20; i++) {
3075 +               u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
3076 +
3077 +               if ((val & BIT(31)) == 0)
3078 +                       break;
3079 +
3080 +               udelay(1000);
3081 +       }
3082 +       if (i == 20)
3083 +               printk("mt7530: vtcr timeout\n");
3084 +}
3085 +
3086 +static int
3087 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
3088 +{
3089 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3090 +
3091 +       if (port >= MT7530_NUM_PORTS)
3092 +               return -EINVAL;
3093 +
3094 +       *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
3095 +       *val &= 0xfff;
3096 +
3097 +       return 0;
3098 +}
3099 +
3100 +static int
3101 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
3102 +{
3103 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3104 +
3105 +       if (port >= MT7530_NUM_PORTS)
3106 +               return -EINVAL;
3107 +
3108 +       if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
3109 +               return -EINVAL;
3110 +
3111 +       priv->port_entries[port].pvid = pvid;
3112 +
3113 +       return 0;
3114 +}
3115 +
3116 +static int
3117 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3118 +{
3119 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3120 +       u32 member;
3121 +       u32 etags;
3122 +       int i;
3123 +
3124 +       val->len = 0;
3125 +
3126 +       if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
3127 +               return -EINVAL;
3128 +
3129 +       mt7530_vtcr(priv, 0, val->port_vlan);
3130 +
3131 +       member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
3132 +       member >>= 16;
3133 +       member &= 0xff;
3134 +
3135 +       etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
3136 +
3137 +       for (i = 0; i < MT7530_NUM_PORTS; i++) {
3138 +               struct switch_port *p;
3139 +               int etag;
3140 +
3141 +               if (!(member & BIT(i)))
3142 +                       continue;
3143 +
3144 +               p = &val->value.ports[val->len++];
3145 +               p->id = i;
3146 +
3147 +               etag = (etags >> (i * 2)) & 0x3;
3148 +
3149 +               if (etag == ETAG_CTRL_TAG)
3150 +                       p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
3151 +               else if (etag != ETAG_CTRL_UNTAG)
3152 +                       printk("vlan egress tag control neither untag nor tag.\n");
3153 +       }
3154 +
3155 +       return 0;
3156 +}
3157 +
3158 +static int
3159 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3160 +{
3161 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3162 +       u8 member = 0;
3163 +       u8 etags = 0;
3164 +       int i;
3165 +
3166 +       if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
3167 +                       val->len > MT7530_NUM_PORTS)
3168 +               return -EINVAL;
3169 +
3170 +       for (i = 0; i < val->len; i++) {
3171 +               struct switch_port *p = &val->value.ports[i];
3172 +
3173 +               if (p->id >= MT7530_NUM_PORTS)
3174 +                       return -EINVAL;
3175 +
3176 +               member |= BIT(p->id);
3177 +
3178 +               if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
3179 +                       etags |= BIT(p->id);
3180 +       }
3181 +       priv->vlan_entries[val->port_vlan].member = member;
3182 +       priv->vlan_entries[val->port_vlan].etags = etags;
3183 +
3184 +       return 0;
3185 +}
3186 +
3187 +static int
3188 +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
3189 +               struct switch_val *val)
3190 +{
3191 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3192 +       int vlan;
3193 +       u16 vid;
3194 +
3195 +       vlan = val->port_vlan;
3196 +       vid = (u16)val->value.i;
3197 +
3198 +       if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
3199 +               return -EINVAL;
3200 +
3201 +       if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
3202 +               return -EINVAL;
3203 +
3204 +       priv->vlan_entries[vlan].vid = vid;
3205 +       return 0;
3206 +}
3207 +
3208 +static int
3209 +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
3210 +               struct switch_val *val)
3211 +{
3212 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3213 +       u32 vid;
3214 +       int vlan;
3215 +
3216 +       vlan = val->port_vlan;
3217 +
3218 +       vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
3219 +       if (vlan & 1)
3220 +               vid = vid >> 12;
3221 +       vid &= 0xfff;
3222 +
3223 +       val->value.i = vid;
3224 +       return 0;
3225 +}
3226 +
3227 +static int
3228 +mt7530_apply_config(struct switch_dev *dev)
3229 +{
3230 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3231 +       int i, j;
3232 +
3233 +       if (!priv->global_vlan_enable) {
3234 +               for (i = 0; i < MT7530_NUM_PORTS; i++)
3235 +                       mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0000);
3236 +
3237 +               for (i = 0; i < MT7530_NUM_PORTS; i++)
3238 +                       mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
3239 +
3240 +               return 0;
3241 +       }
3242 +
3243 +       /* set all ports as security mode */
3244 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
3245 +               mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
3246 +
3247 +       /* set all ports as user port */
3248 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
3249 +               mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x81000000);
3250 +
3251 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
3252 +               u16 vid = priv->vlan_entries[i].vid;
3253 +               u8 member = priv->vlan_entries[i].member;
3254 +               u8 etags = priv->vlan_entries[i].etags;
3255 +               u32 val;
3256 +
3257 +               /* vid of vlan */
3258 +               val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
3259 +               if (i % 2 == 0) {
3260 +                       val &= 0xfff000;
3261 +                       val |= vid;
3262 +               } else {
3263 +                       val &= 0xfff;
3264 +                       val |= (vid << 12);
3265 +               }
3266 +               mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
3267 +
3268 +               /* vlan port membership */
3269 +               if (member)
3270 +                       mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
3271 +                               REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
3272 +                               REG_ESW_VLAN_VAWD1_VALID);
3273 +               else
3274 +                       mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
3275 +
3276 +               /* egress mode */
3277 +               val = 0;
3278 +               for (j = 0; j < MT7530_NUM_PORTS; j++) {
3279 +                       if (etags & BIT(j))
3280 +                               val |= ETAG_CTRL_TAG << (j * 2);
3281 +                       else
3282 +                               val |= ETAG_CTRL_UNTAG << (j * 2);
3283 +               }
3284 +               mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
3285 +
3286 +               /* write to vlan table */
3287 +               mt7530_vtcr(priv, 1, i);
3288 +       }
3289 +
3290 +       /* Port Default PVID */
3291 +       for (i = 0; i < MT7530_NUM_PORTS; i++) {
3292 +               u32 val;
3293 +               val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
3294 +               val &= ~0xfff;
3295 +               val |= priv->port_entries[i].pvid;
3296 +               mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
3297 +       }
3298 +
3299 +       return 0;
3300 +}
3301 +
3302 +static int
3303 +mt7530_get_port_link(struct switch_dev *dev,  int port,
3304 +                       struct switch_port_link *link)
3305 +{
3306 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3307 +       u32 speed, pmsr;
3308 +
3309 +       if (port < 0 || port >= MT7530_NUM_PORTS)
3310 +               return -EINVAL;
3311 +
3312 +       pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
3313 +
3314 +       link->link = pmsr & 1;
3315 +       link->duplex = (pmsr >> 1) & 1;
3316 +       speed = (pmsr >> 2) & 3;
3317 +
3318 +       switch (speed) {
3319 +       case 0:
3320 +               link->speed = SWITCH_PORT_SPEED_10;
3321 +               break;
3322 +       case 1:
3323 +               link->speed = SWITCH_PORT_SPEED_100;
3324 +               break;
3325 +       case 2:
3326 +       case 3: /* forced gige speed can be 2 or 3 */
3327 +               link->speed = SWITCH_PORT_SPEED_1000;
3328 +               break;
3329 +       default:
3330 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
3331 +               break;
3332 +       }
3333 +
3334 +       return 0;
3335 +}
3336 +
3337 +static const struct switch_attr mt7530_global[] = {
3338 +       {
3339 +               .type = SWITCH_TYPE_INT,
3340 +               .name = "enable_vlan",
3341 +               .description = "VLAN mode (1:enabled)",
3342 +               .max = 1,
3343 +               .id = MT7530_ATTR_ENABLE_VLAN,
3344 +               .get = mt7530_get_vlan_enable,
3345 +               .set = mt7530_set_vlan_enable,
3346 +       },
3347 +};
3348 +
3349 +static const struct switch_attr mt7530_port[] = {
3350 +};
3351 +
3352 +static const struct switch_attr mt7530_vlan[] = {
3353 +       {
3354 +               .type = SWITCH_TYPE_INT,
3355 +               .name = "vid",
3356 +               .description = "VLAN ID (0-4094)",
3357 +               .set = mt7530_set_vid,
3358 +               .get = mt7530_get_vid,
3359 +               .max = 4094,
3360 +       },
3361 +};
3362 +
3363 +static const struct switch_dev_ops mt7530_ops = {
3364 +       .attr_global = {
3365 +               .attr = mt7530_global,
3366 +               .n_attr = ARRAY_SIZE(mt7530_global),
3367 +       },
3368 +       .attr_port = {
3369 +               .attr = mt7530_port,
3370 +               .n_attr = ARRAY_SIZE(mt7530_port),
3371 +       },
3372 +       .attr_vlan = {
3373 +               .attr = mt7530_vlan,
3374 +               .n_attr = ARRAY_SIZE(mt7530_vlan),
3375 +       },
3376 +       .get_vlan_ports = mt7530_get_vlan_ports,
3377 +       .set_vlan_ports = mt7530_set_vlan_ports,
3378 +       .get_port_pvid = mt7530_get_port_pvid,
3379 +       .set_port_pvid = mt7530_set_port_pvid,
3380 +       .get_port_link = mt7530_get_port_link,
3381 +       .apply_config = mt7530_apply_config,
3382 +       .reset_switch = mt7530_reset_switch,
3383 +};
3384 +
3385 +int
3386 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
3387 +{
3388 +       struct switch_dev *swdev;
3389 +       struct mt7530_priv *mt7530;
3390 +       struct mt7530_mapping *map;
3391 +       int ret;
3392 +
3393 +       if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
3394 +               return 0;
3395 +
3396 +       mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
3397 +       if (!mt7530)
3398 +               return -ENOMEM;
3399 +
3400 +       mt7530->base = base;
3401 +       mt7530->bus = bus;
3402 +       mt7530->global_vlan_enable = vlan;
3403 +
3404 +       swdev = &mt7530->swdev;
3405 +       if (bus) {
3406 +               swdev->alias = "mt7530";
3407 +               swdev->name = "mt7530";
3408 +       } else {
3409 +               swdev->alias = "mt7620";
3410 +               swdev->name = "mt7620";
3411 +       }
3412 +       swdev->cpu_port = MT7530_CPU_PORT;
3413 +       swdev->ports = MT7530_NUM_PORTS;
3414 +       swdev->vlans = MT7530_NUM_VLANS;
3415 +       swdev->ops = &mt7530_ops;
3416 +
3417 +       ret = register_switch(swdev, NULL);
3418 +       if (ret) {
3419 +               dev_err(dev, "failed to register mt7530\n");
3420 +               return ret;
3421 +       }
3422 +
3423 +       dev_info(dev, "loaded %s driver\n", swdev->name);
3424 +
3425 +       map = mt7530_find_mapping(dev->of_node);
3426 +       if (map)
3427 +               mt7530_apply_mapping(mt7530, map);
3428 +       mt7530_apply_config(swdev);
3429 +
3430 +       return 0;
3431 +}
3432 Index: linux-3.14.18/drivers/net/ethernet/ralink/mt7530.h
3433 ===================================================================
3434 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
3435 +++ linux-3.14.18/drivers/net/ethernet/ralink/mt7530.h  2014-10-28 12:34:25.187728544 +0100
3436 @@ -0,0 +1,20 @@
3437 +/*
3438 + * This program is free software; you can redistribute it and/or
3439 + * modify it under the terms of the GNU General Public License
3440 + * as published by the Free Software Foundation; either version 2
3441 + * of the License, or (at your option) any later version.
3442 + *
3443 + * This program is distributed in the hope that it will be useful,
3444 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3445 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3446 + * GNU General Public License for more details.
3447 + *
3448 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
3449 + */
3450 +
3451 +#ifndef _MT7530_H__
3452 +#define _MT7530_H__
3453 +
3454 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
3455 +
3456 +#endif
3457 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.c
3458 ===================================================================
3459 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
3460 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.c  2014-10-28 10:43:11.890131215 +0100
3461 @@ -0,0 +1,844 @@
3462 +/*
3463 + *   This program is free software; you can redistribute it and/or modify
3464 + *   it under the terms of the GNU General Public License as published by
3465 + *   the Free Software Foundation; version 2 of the License
3466 + *
3467 + *   This program is distributed in the hope that it will be useful,
3468 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3469 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3470 + *   GNU General Public License for more details.
3471 + *
3472 + *   You should have received a copy of the GNU General Public License
3473 + *   along with this program; if not, write to the Free Software
3474 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3475 + *
3476 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3477 + */
3478 +
3479 +#include <linux/module.h>
3480 +#include <linux/kernel.h>
3481 +#include <linux/types.h>
3482 +#include <linux/dma-mapping.h>
3483 +#include <linux/init.h>
3484 +#include <linux/skbuff.h>
3485 +#include <linux/etherdevice.h>
3486 +#include <linux/ethtool.h>
3487 +#include <linux/platform_device.h>
3488 +#include <linux/of_device.h>
3489 +#include <linux/clk.h>
3490 +#include <linux/of_net.h>
3491 +#include <linux/of_mdio.h>
3492 +#include <linux/if_vlan.h>
3493 +#include <linux/reset.h>
3494 +
3495 +#include <asm/mach-ralink/ralink_regs.h>
3496 +
3497 +#include "ralink_soc_eth.h"
3498 +#include "esw_rt3052.h"
3499 +#include "mdio.h"
3500 +
3501 +#define TX_TIMEOUT             (2 * HZ)
3502 +#define        MAX_RX_LENGTH           1536
3503 +#define DMA_DUMMY_DESC         0xffffffff
3504 +
3505 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3506 +       [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3507 +       [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3508 +       [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3509 +       [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3510 +       [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3511 +       [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3512 +       [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3513 +       [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3514 +       [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3515 +       [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3516 +       [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3517 +};
3518 +
3519 +static const u32 *fe_reg_table = fe_reg_table_default;
3520 +
3521 +static void __iomem *fe_base = 0;
3522 +
3523 +void fe_w32(u32 val, unsigned reg)
3524 +{
3525 +       __raw_writel(val, fe_base + reg);
3526 +}
3527 +
3528 +u32 fe_r32(unsigned reg)
3529 +{
3530 +       return __raw_readl(fe_base + reg);
3531 +}
3532 +
3533 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
3534 +{
3535 +       fe_w32(val, fe_reg_table[reg]);
3536 +}
3537 +
3538 +static inline u32 fe_reg_r32(enum fe_reg reg)
3539 +{
3540 +       return fe_r32(fe_reg_table[reg]);
3541 +}
3542 +
3543 +static inline void fe_int_disable(u32 mask)
3544 +{
3545 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3546 +                    FE_REG_FE_INT_ENABLE);
3547 +       /* flush write */
3548 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3549 +}
3550 +
3551 +static inline void fe_int_enable(u32 mask)
3552 +{
3553 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3554 +                    FE_REG_FE_INT_ENABLE);
3555 +       /* flush write */
3556 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3557 +}
3558 +
3559 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3560 +{
3561 +       unsigned long flags;
3562 +
3563 +       spin_lock_irqsave(&priv->page_lock, flags);
3564 +       fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3565 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3566 +                    FE_GDMA1_MAC_ADRL);
3567 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3568 +}
3569 +
3570 +static int fe_set_mac_address(struct net_device *dev, void *p)
3571 +{
3572 +       int ret = eth_mac_addr(dev, p);
3573 +
3574 +       if (!ret) {
3575 +               struct fe_priv *priv = netdev_priv(dev);
3576 +
3577 +               if (priv->soc->set_mac)
3578 +                       priv->soc->set_mac(priv, dev->dev_addr);
3579 +               else
3580 +                       fe_hw_set_macaddr(priv, p);
3581 +       }
3582 +
3583 +       return ret;
3584 +}
3585 +
3586 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
3587 +{
3588 +       struct sk_buff *skb;
3589 +
3590 +       skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
3591 +       if (!skb)
3592 +               return NULL;
3593 +
3594 +       skb_reserve(skb, NET_IP_ALIGN);
3595 +
3596 +       return skb;
3597 +}
3598 +
3599 +static int fe_alloc_rx(struct fe_priv *priv)
3600 +{
3601 +       int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3602 +       int i;
3603 +
3604 +       priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3605 +                                       &priv->rx_phys, GFP_ATOMIC);
3606 +       if (!priv->rx_dma)
3607 +               return -ENOMEM;
3608 +
3609 +       memset(priv->rx_dma, 0, size);
3610 +
3611 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3612 +               priv->rx_skb[i] = fe_alloc_skb(priv);
3613 +               if (!priv->rx_skb[i])
3614 +                       return -ENOMEM;
3615 +       }
3616 +
3617 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3618 +               dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3619 +                                               priv->rx_skb[i]->data,
3620 +                                               MAX_RX_LENGTH,
3621 +                                               DMA_FROM_DEVICE);
3622 +               priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3623 +
3624 +               if (priv->soc->rx_dma)
3625 +                       priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3626 +               else
3627 +                       priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3628 +       }
3629 +       wmb();
3630 +
3631 +       fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3632 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3633 +       fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3634 +       fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3635 +
3636 +       return 0;
3637 +}
3638 +
3639 +static int fe_alloc_tx(struct fe_priv *priv)
3640 +{
3641 +       int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3642 +       int i;
3643 +
3644 +       priv->tx_free_idx = 0;
3645 +
3646 +       priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3647 +                                       &priv->tx_phys, GFP_ATOMIC);
3648 +       if (!priv->tx_dma)
3649 +               return -ENOMEM;
3650 +
3651 +       memset(priv->tx_dma, 0, size);
3652 +
3653 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3654 +               if (priv->soc->tx_dma) {
3655 +                       priv->soc->tx_dma(priv, i, NULL);
3656 +                       continue;
3657 +               }
3658 +
3659 +               priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3660 +               priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3661 +       }
3662 +
3663 +       fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3664 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3665 +       fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3666 +       fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3667 +
3668 +       return 0;
3669 +}
3670 +
3671 +static void fe_free_dma(struct fe_priv *priv)
3672 +{
3673 +       int i;
3674 +
3675 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3676 +               if (priv->rx_skb[i]) {
3677 +                       dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3678 +                                               MAX_RX_LENGTH, DMA_FROM_DEVICE);
3679 +                       dev_kfree_skb_any(priv->rx_skb[i]);
3680 +                       priv->rx_skb[i] = NULL;
3681 +               }
3682 +
3683 +               if (priv->tx_skb[i]) {
3684 +                       dev_kfree_skb_any(priv->tx_skb[i]);
3685 +                       priv->tx_skb[i] = NULL;
3686 +               }
3687 +       }
3688 +
3689 +       if (priv->rx_dma) {
3690 +               int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3691 +               dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3692 +                                       priv->rx_phys);
3693 +       }
3694 +
3695 +       if (priv->tx_dma) {
3696 +               int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3697 +               dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3698 +                                       priv->tx_phys);
3699 +       }
3700 +
3701 +       netdev_reset_queue(priv->netdev);
3702 +}
3703 +
3704 +static void fe_start_tso(struct sk_buff *skb, struct net_device *dev, unsigned int nr_frags, int idx)
3705 +{
3706 +        struct fe_priv *priv = netdev_priv(dev);
3707 +       struct skb_frag_struct *frag;
3708 +       int i;
3709 +
3710 +       for (i = 0; i < nr_frags; i++) {
3711 +               dma_addr_t mapped_addr;
3712 +
3713 +               frag = &skb_shinfo(skb)->frags[i];
3714 +               mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE);
3715 +               if (i % 2) {
3716 +                       idx = (idx + 1) % NUM_DMA_DESC;
3717 +                       priv->tx_dma[idx].txd1 = mapped_addr;
3718 +                       if (i == nr_frags - 1)
3719 +                               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(frag->size);
3720 +                       else
3721 +                               priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(frag->size);
3722 +               } else {
3723 +                       priv->tx_dma[idx].txd3 = mapped_addr;
3724 +                       if (i == nr_frags - 1)
3725 +                               priv->tx_dma[idx].txd2 |= TX_DMA_LS1 | TX_DMA_PLEN1(frag->size);
3726 +                       else
3727 +                               priv->tx_dma[idx].txd2 |= TX_DMA_PLEN1(frag->size);
3728 +               }
3729 +       }
3730 +}
3731 +
3732 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3733 +{
3734 +       unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3735 +       struct fe_priv *priv = netdev_priv(dev);
3736 +       dma_addr_t mapped_addr;
3737 +       u32 tx_next, tx, tx_num = 1;
3738 +       int i;
3739 +
3740 +       if (priv->soc->min_pkt_len) {
3741 +               if (skb->len < priv->soc->min_pkt_len) {
3742 +                       if (skb_padto(skb, priv->soc->min_pkt_len)) {
3743 +                               printk(KERN_ERR
3744 +                                      "fe_eth: skb_padto failed\n");
3745 +                               kfree_skb(skb);
3746 +                               return 0;
3747 +                       }
3748 +                       skb_put(skb, priv->soc->min_pkt_len - skb->len);
3749 +               }
3750 +       }
3751 +
3752 +       dev->trans_start = jiffies;
3753 +       mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3754 +                               skb->len, DMA_TO_DEVICE);
3755 +
3756 +       spin_lock(&priv->page_lock);
3757 +
3758 +       tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3759 +       if (priv->soc->tso && nr_frags)
3760 +               tx_num += nr_frags >> 1;
3761 +       tx_next = (tx + tx_num) % NUM_DMA_DESC;
3762 +       if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3763 +                       !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3764 +                       !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3765 +       {
3766 +               spin_unlock(&priv->page_lock);
3767 +               dev->stats.tx_dropped++;
3768 +               kfree_skb(skb);
3769 +
3770 +               return NETDEV_TX_OK;
3771 +       }
3772 +
3773 +       if (priv->soc->tso) {
3774 +               int t = tx_num;
3775 +
3776 +               priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = skb;
3777 +               while (--t)
3778 +                       priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = (struct sk_buff *) DMA_DUMMY_DESC;
3779 +       } else {
3780 +               priv->tx_skb[tx] = skb;
3781 +       }
3782 +       priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3783 +       wmb();
3784 +
3785 +       priv->tx_dma[tx].txd4 &= ~0x80;
3786 +       if (priv->soc->tx_dma)
3787 +               priv->soc->tx_dma(priv, tx, skb);
3788 +       else
3789 +               priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3790 +
3791 +       if (skb->ip_summed == CHECKSUM_PARTIAL)
3792 +               priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3793 +       else
3794 +               priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3795 +
3796 +       if (priv->soc->tso)
3797 +               fe_start_tso(skb, dev, nr_frags, tx);
3798 +
3799 +       if (priv->soc->tso && (skb_shinfo(skb)->gso_segs > 1)) {
3800 +               struct iphdr *iph = NULL;
3801 +               struct tcphdr *th = NULL;
3802 +               struct ipv6hdr *ip6h = NULL;
3803 +
3804 +               ip6h = (struct ipv6hdr *) skb_network_header(skb);
3805 +               iph = (struct iphdr *) skb_network_header(skb);
3806 +               if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
3807 +                       th = (struct tcphdr *)skb_transport_header(skb);
3808 +                       priv->tx_dma[tx].txd4 |= BIT(28);
3809 +                       th->check = htons(skb_shinfo(skb)->gso_size);
3810 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3811 +               } else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
3812 +                       th = (struct tcphdr *)skb_transport_header(skb);
3813 +                       priv->tx_dma[tx].txd4 |= BIT(28);
3814 +                       th->check = htons(skb_shinfo(skb)->gso_size);
3815 +                       dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3816 +               }
3817 +       }
3818 +
3819 +       for (i = 0; i < tx_num; i++)
3820 +               dma_cache_sync(NULL,  &priv->tx_dma[tx + i], sizeof(struct fe_tx_dma), DMA_TO_DEVICE);
3821 +
3822 +       dev->stats.tx_packets++;
3823 +       dev->stats.tx_bytes += skb->len;
3824 +
3825 +       wmb();
3826 +       fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3827 +       netdev_sent_queue(dev, skb->len);
3828 +
3829 +       spin_unlock(&priv->page_lock);
3830 +
3831 +       return NETDEV_TX_OK;
3832 +}
3833 +
3834 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3835 +{
3836 +       struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3837 +       int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3838 +       int complete = 0;
3839 +       int rx = 0;
3840 +
3841 +       while ((rx < budget) && !complete) {
3842 +               idx = (idx + 1) % NUM_DMA_DESC;
3843 +
3844 +               if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3845 +                       struct sk_buff *new_skb = fe_alloc_skb(priv);
3846 +
3847 +                       if (new_skb) {
3848 +                               int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3849 +                               dma_addr_t dma_addr;
3850 +
3851 +                               dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3852 +                                               MAX_RX_LENGTH, DMA_FROM_DEVICE);
3853 +
3854 +                               skb_put(priv->rx_skb[idx], pktlen);
3855 +                               priv->rx_skb[idx]->dev = priv->netdev;
3856 +                               priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3857 +                               if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3858 +                                       priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3859 +                               else
3860 +                                       priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3861 +                               priv->netdev->stats.rx_packets++;
3862 +                               priv->netdev->stats.rx_bytes += pktlen;
3863 +
3864 +#ifdef CONFIG_INET_LRO
3865 +                               if (priv->soc->get_skb_header && priv->rx_skb[idx]->ip_summed == CHECKSUM_UNNECESSARY)
3866 +                                       lro_receive_skb(&priv->lro_mgr, priv->rx_skb[idx], NULL);
3867 +                               else
3868 +#endif
3869 +                                       netif_receive_skb(priv->rx_skb[idx]);
3870 +
3871 +                               priv->rx_skb[idx] = new_skb;
3872 +
3873 +                               dma_addr = dma_map_single(&priv->netdev->dev,
3874 +                                                 new_skb->data,
3875 +                                                 MAX_RX_LENGTH,
3876 +                                                 DMA_FROM_DEVICE);
3877 +                               priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3878 +                               wmb();
3879 +                       } else {
3880 +                               priv->netdev->stats.rx_dropped++;
3881 +                       }
3882 +
3883 +                       if (priv->soc->rx_dma)
3884 +                               priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3885 +                       else
3886 +                               priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3887 +                       fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3888 +
3889 +                       rx++;
3890 +               } else {
3891 +                       complete = 1;
3892 +               }
3893 +       }
3894 +
3895 +#ifdef CONFIG_INET_LRO
3896 +       if (priv->soc->get_skb_header)
3897 +               lro_flush_all(&priv->lro_mgr);
3898 +#endif
3899 +       if (complete) {
3900 +               napi_complete(&priv->rx_napi);
3901 +               fe_int_enable(priv->soc->rx_dly_int);
3902 +       }
3903 +
3904 +       return rx;
3905 +}
3906 +
3907 +static void fe_tx_housekeeping(unsigned long ptr)
3908 +{
3909 +       struct net_device *dev = (struct net_device*)ptr;
3910 +       struct fe_priv *priv = netdev_priv(dev);
3911 +       unsigned int bytes_compl = 0;
3912 +       unsigned int pkts_compl = 0;
3913 +
3914 +       spin_lock(&priv->page_lock);
3915 +       while (1) {
3916 +               struct fe_tx_dma *txd;
3917 +
3918 +               txd = &priv->tx_dma[priv->tx_free_idx];
3919 +
3920 +               if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3921 +                       break;
3922 +
3923 +               if (priv->tx_skb[priv->tx_free_idx] != (struct sk_buff *) DMA_DUMMY_DESC) {
3924 +                       bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3925 +                       dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3926 +               }
3927 +               pkts_compl++;
3928 +               priv->tx_skb[priv->tx_free_idx] = NULL;
3929 +               priv->tx_free_idx++;
3930 +               if (priv->tx_free_idx >= NUM_DMA_DESC)
3931 +                       priv->tx_free_idx = 0;
3932 +       }
3933 +
3934 +       netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3935 +        spin_unlock(&priv->page_lock);
3936 +
3937 +       fe_int_enable(priv->soc->tx_dly_int);
3938 +}
3939 +
3940 +static void fe_tx_timeout(struct net_device *dev)
3941 +{
3942 +       struct fe_priv *priv = netdev_priv(dev);
3943 +
3944 +        tasklet_schedule(&priv->tx_tasklet);
3945 +       priv->netdev->stats.tx_errors++;
3946 +       netdev_err(dev, "transmit timed out, waking up the queue\n");
3947 +       netif_wake_queue(dev);
3948 +}
3949 +
3950 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3951 +{
3952 +       struct fe_priv *priv = netdev_priv(dev);
3953 +       unsigned int status;
3954 +       unsigned int mask;
3955 +
3956 +       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3957 +       mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3958 +
3959 +       if (!(status & mask))
3960 +               return IRQ_NONE;
3961 +
3962 +       if (status & priv->soc->rx_dly_int) {
3963 +               fe_int_disable(priv->soc->rx_dly_int);
3964 +               napi_schedule(&priv->rx_napi);
3965 +       }
3966 +
3967 +       if (status & priv->soc->tx_dly_int) {
3968 +               fe_int_disable(priv->soc->tx_dly_int);
3969 +               tasklet_schedule(&priv->tx_tasklet);
3970 +       }
3971 +
3972 +       fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3973 +
3974 +       return IRQ_HANDLED;
3975 +}
3976 +
3977 +static int fe_hw_init(struct net_device *dev)
3978 +{
3979 +       struct fe_priv *priv = netdev_priv(dev);
3980 +       int err;
3981 +
3982 +       err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3983 +                               dev_name(priv->device), dev);
3984 +       if (err)
3985 +               return err;
3986 +
3987 +       err = fe_alloc_rx(priv);
3988 +       if (!err)
3989 +               err = fe_alloc_tx(priv);
3990 +       if (err)
3991 +               return err;
3992 +
3993 +       if (priv->soc->set_mac)
3994 +               priv->soc->set_mac(priv, dev->dev_addr);
3995 +       else
3996 +               fe_hw_set_macaddr(priv, dev->dev_addr);
3997 +
3998 +       fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3999 +
4000 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4001 +
4002 +       tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
4003 +
4004 +       if (priv->soc->fwd_config) {
4005 +               priv->soc->fwd_config(priv);
4006 +       } else {
4007 +               unsigned long sysclk = priv->sysclk;
4008 +
4009 +               if (!sysclk) {
4010 +                       netdev_err(dev, "unable to get clock\n");
4011 +                       return -EINVAL;
4012 +               }
4013 +
4014 +               sysclk /= FE_US_CYC_CNT_DIVISOR;
4015 +               sysclk <<= FE_US_CYC_CNT_SHIFT;
4016 +
4017 +               fe_w32((fe_r32(FE_FE_GLO_CFG) &
4018 +                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4019 +                       FE_FE_GLO_CFG);
4020 +
4021 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
4022 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
4023 +                       FE_GDMA1_FWD_CFG);
4024 +               fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
4025 +                       FE_CDMA_CSG_CFG);
4026 +               fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
4027 +       }
4028 +
4029 +       fe_w32(1, FE_FE_RST_GL);
4030 +       fe_w32(0, FE_FE_RST_GL);
4031 +
4032 +       return 0;
4033 +}
4034 +
4035 +static int fe_open(struct net_device *dev)
4036 +{
4037 +       struct fe_priv *priv = netdev_priv(dev);
4038 +       unsigned long flags;
4039 +       u32 val;
4040 +
4041 +       spin_lock_irqsave(&priv->page_lock, flags);
4042 +       napi_enable(&priv->rx_napi);
4043 +
4044 +       val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
4045 +       val |= priv->soc->pdma_glo_cfg;
4046 +       fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
4047 +
4048 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4049 +
4050 +       if (priv->phy)
4051 +               priv->phy->start(priv);
4052 +
4053 +       if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
4054 +               netif_carrier_on(dev);
4055 +
4056 +       netif_start_queue(dev);
4057 +       fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4058 +
4059 +       return 0;
4060 +}
4061 +
4062 +static int fe_stop(struct net_device *dev)
4063 +{
4064 +       struct fe_priv *priv = netdev_priv(dev);
4065 +       unsigned long flags;
4066 +
4067 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4068 +
4069 +       netif_stop_queue(dev);
4070 +
4071 +       if (priv->phy)
4072 +               priv->phy->stop(priv);
4073 +
4074 +       spin_lock_irqsave(&priv->page_lock, flags);
4075 +       napi_disable(&priv->rx_napi);
4076 +
4077 +       fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
4078 +                    ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
4079 +                    FE_REG_PDMA_GLO_CFG);
4080 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4081 +
4082 +       return 0;
4083 +}
4084 +
4085 +static int __init fe_init(struct net_device *dev)
4086 +{
4087 +       struct fe_priv *priv = netdev_priv(dev);
4088 +       struct device_node *port;
4089 +       int err;
4090 +
4091 +       BUG_ON(!priv->soc->reset_fe);
4092 +       priv->soc->reset_fe();
4093 +
4094 +       if (priv->soc->switch_init)
4095 +               priv->soc->switch_init(priv);
4096 +
4097 +       memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
4098 +       of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
4099 +
4100 +       err = fe_mdio_init(priv);
4101 +       if (err)
4102 +               return err;
4103 +
4104 +       if (priv->phy) {
4105 +               err = priv->phy->connect(priv);
4106 +               if (err)
4107 +                       goto err_mdio_cleanup;
4108 +       }
4109 +
4110 +       if (priv->soc->port_init)
4111 +               for_each_child_of_node(priv->device->of_node, port)
4112 +                       if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
4113 +                               priv->soc->port_init(priv, port);
4114 +
4115 +       err = fe_hw_init(dev);
4116 +       if (err)
4117 +               goto err_phy_disconnect;
4118 +
4119 +       if (priv->soc->switch_config)
4120 +               priv->soc->switch_config(priv);
4121 +
4122 +       return 0;
4123 +
4124 +err_phy_disconnect:
4125 +       if (priv->phy)
4126 +               priv->phy->disconnect(priv);
4127 +err_mdio_cleanup:
4128 +       fe_mdio_cleanup(priv);
4129 +
4130 +       return err;
4131 +}
4132 +
4133 +static void fe_uninit(struct net_device *dev)
4134 +{
4135 +       struct fe_priv *priv = netdev_priv(dev);
4136 +
4137 +       tasklet_kill(&priv->tx_tasklet);
4138 +
4139 +       if (priv->phy)
4140 +               priv->phy->disconnect(priv);
4141 +       fe_mdio_cleanup(priv);
4142 +
4143 +       fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
4144 +       free_irq(dev->irq, dev);
4145 +
4146 +       fe_free_dma(priv);
4147 +}
4148 +
4149 +static const struct net_device_ops fe_netdev_ops = {
4150 +       .ndo_init               = fe_init,
4151 +       .ndo_uninit             = fe_uninit,
4152 +       .ndo_open               = fe_open,
4153 +       .ndo_stop               = fe_stop,
4154 +       .ndo_start_xmit         = fe_start_xmit,
4155 +       .ndo_tx_timeout         = fe_tx_timeout,
4156 +       .ndo_set_mac_address    = fe_set_mac_address,
4157 +       .ndo_change_mtu         = eth_change_mtu,
4158 +       .ndo_validate_addr      = eth_validate_addr,
4159 +};
4160 +
4161 +static int fe_probe(struct platform_device *pdev)
4162 +{
4163 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4164 +       const struct of_device_id *match;
4165 +       struct fe_soc_data *soc = NULL;
4166 +       struct net_device *netdev;
4167 +       struct fe_priv *priv;
4168 +       struct clk *sysclk;
4169 +       int err;
4170 +
4171 +       device_reset(&pdev->dev);
4172 +
4173 +       match = of_match_device(of_fe_match, &pdev->dev);
4174 +       soc = (struct fe_soc_data *) match->data;
4175 +
4176 +       if (soc->init_data)
4177 +               soc->init_data(soc);
4178 +       if (soc->reg_table)
4179 +               fe_reg_table = soc->reg_table;
4180 +
4181 +       fe_base = devm_request_and_ioremap(&pdev->dev, res);
4182 +       if (!fe_base)
4183 +               return -ENOMEM;
4184 +
4185 +       netdev = alloc_etherdev(sizeof(struct fe_priv));
4186 +       if (!netdev) {
4187 +               dev_err(&pdev->dev, "alloc_etherdev failed\n");
4188 +               return -ENOMEM;
4189 +       }
4190 +
4191 +       strcpy(netdev->name, "eth%d");
4192 +       netdev->netdev_ops = &fe_netdev_ops;
4193 +       netdev->base_addr = (unsigned long) fe_base;
4194 +       netdev->watchdog_timeo = TX_TIMEOUT;
4195 +       netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
4196 +
4197 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
4198 +               netdev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4199 +
4200 +       if (soc->tso) {
4201 +               dev_info(&pdev->dev, "Enabling TSO\n");
4202 +               netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
4203 +       }
4204 +       netdev->hw_features = netdev->features;
4205 +
4206 +       netdev->irq = platform_get_irq(pdev, 0);
4207 +       if (netdev->irq < 0) {
4208 +               dev_err(&pdev->dev, "no IRQ resource found\n");
4209 +               kfree(netdev);
4210 +               return -ENXIO;
4211 +       }
4212 +
4213 +       priv = netdev_priv(netdev);
4214 +       memset(priv, 0, sizeof(struct fe_priv));
4215 +       spin_lock_init(&priv->page_lock);
4216 +
4217 +       sysclk = devm_clk_get(&pdev->dev, NULL);
4218 +       if (!IS_ERR(sysclk))
4219 +               priv->sysclk = clk_get_rate(sysclk);
4220 +
4221 +       priv->netdev = netdev;
4222 +       priv->device = &pdev->dev;
4223 +       priv->soc = soc;
4224 +
4225 +       err = register_netdev(netdev);
4226 +       if (err) {
4227 +               dev_err(&pdev->dev, "error bringing up device\n");
4228 +               kfree(netdev);
4229 +               return err;
4230 +       }
4231 +       netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
4232 +
4233 +#ifdef CONFIG_INET_LRO
4234 +       if (priv->soc->get_skb_header) {
4235 +               priv->lro_mgr.dev = netdev;
4236 +               memset(&priv->lro_mgr.stats, 0, sizeof(priv->lro_mgr.stats));
4237 +               priv->lro_mgr.features = LRO_F_NAPI;
4238 +               priv->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
4239 +               priv->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
4240 +               priv->lro_mgr.max_desc = ARRAY_SIZE(priv->lro_arr);
4241 +               priv->lro_mgr.max_aggr = 64;
4242 +               priv->lro_mgr.frag_align_pad = 0;
4243 +               priv->lro_mgr.lro_arr = priv->lro_arr;
4244 +               priv->lro_mgr.get_skb_header = priv->soc->get_skb_header;
4245 +       }
4246 +#endif
4247 +
4248 +       platform_set_drvdata(pdev, netdev);
4249 +
4250 +       netdev_info(netdev, "done loading\n");
4251 +
4252 +       return 0;
4253 +}
4254 +
4255 +static int fe_remove(struct platform_device *pdev)
4256 +{
4257 +        struct net_device *dev = platform_get_drvdata(pdev);
4258 +       struct fe_priv *priv = netdev_priv(dev);
4259 +
4260 +       netif_stop_queue(dev);
4261 +       netif_napi_del(&priv->rx_napi);
4262 +
4263 +       unregister_netdev(dev);
4264 +       free_netdev(dev);
4265 +
4266 +       return 0;
4267 +}
4268 +
4269 +static struct platform_driver fe_driver = {
4270 +       .probe = fe_probe,
4271 +       .remove = fe_remove,
4272 +       .driver = {
4273 +               .name = "ralink_soc_eth",
4274 +               .owner = THIS_MODULE,
4275 +               .of_match_table = of_fe_match,
4276 +       },
4277 +};
4278 +
4279 +static int __init init_rtfe(void)
4280 +{
4281 +       int ret;
4282 +
4283 +       ret = rtesw_init();
4284 +       if (ret)
4285 +               return ret;
4286 +
4287 +       ret = platform_driver_register(&fe_driver);
4288 +       if (ret)
4289 +               rtesw_exit();
4290 +
4291 +       return ret;
4292 +}
4293 +
4294 +static void __exit exit_rtfe(void)
4295 +{
4296 +       platform_driver_unregister(&fe_driver);
4297 +       rtesw_exit();
4298 +}
4299 +
4300 +module_init(init_rtfe);
4301 +module_exit(exit_rtfe);
4302 +
4303 +MODULE_LICENSE("GPL");
4304 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4305 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4306 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.h
4307 ===================================================================
4308 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4309 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.h  2014-10-28 10:43:11.894131220 +0100
4310 @@ -0,0 +1,384 @@
4311 +/*
4312 + *   This program is free software; you can redistribute it and/or modify
4313 + *   it under the terms of the GNU General Public License as published by
4314 + *   the Free Software Foundation; version 2 of the License
4315 + *
4316 + *   This program is distributed in the hope that it will be useful,
4317 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4318 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4319 + *   GNU General Public License for more details.
4320 + *
4321 + *   You should have received a copy of the GNU General Public License
4322 + *   along with this program; if not, write to the Free Software
4323 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4324 + *
4325 + *   based on Ralink SDK3.3
4326 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4327 + */
4328 +
4329 +#ifndef FE_ETH_H
4330 +#define FE_ETH_H
4331 +
4332 +#include <linux/mii.h>
4333 +#include <linux/interrupt.h>
4334 +#include <linux/netdevice.h>
4335 +#include <linux/dma-mapping.h>
4336 +#include <linux/phy.h>
4337 +#include <linux/inet_lro.h>
4338 +
4339 +
4340 +enum fe_reg {
4341 +       FE_REG_PDMA_GLO_CFG = 0,
4342 +       FE_REG_PDMA_RST_CFG,
4343 +       FE_REG_DLY_INT_CFG,
4344 +       FE_REG_TX_BASE_PTR0,
4345 +       FE_REG_TX_MAX_CNT0,
4346 +       FE_REG_TX_CTX_IDX0,
4347 +       FE_REG_RX_BASE_PTR0,
4348 +       FE_REG_RX_MAX_CNT0,
4349 +       FE_REG_RX_CALC_IDX0,
4350 +       FE_REG_FE_INT_ENABLE,
4351 +       FE_REG_FE_INT_STATUS,
4352 +       FE_REG_FE_DMA_VID_BASE,
4353 +       FE_REG_COUNT
4354 +};
4355 +
4356 +#define NUM_DMA_DESC           0x100
4357 +
4358 +#define FE_DELAY_EN_INT                0x80
4359 +#define FE_DELAY_MAX_INT       0x04
4360 +#define FE_DELAY_MAX_TOUT      0x04
4361 +#define FE_DELAY_CHAN          (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4362 +#define FE_DELAY_INIT          ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4363 +#define FE_PSE_FQFC_CFG_INIT   0x80504000
4364 +
4365 +/* interrupt bits */
4366 +#define FE_CNT_PPE_AF          BIT(31)
4367 +#define FE_CNT_GDM_AF          BIT(29)
4368 +#define FE_PSE_P2_FC           BIT(26)
4369 +#define FE_PSE_BUF_DROP                BIT(24)
4370 +#define FE_GDM_OTHER_DROP      BIT(23)
4371 +#define FE_PSE_P1_FC           BIT(22)
4372 +#define FE_PSE_P0_FC           BIT(21)
4373 +#define FE_PSE_FQ_EMPTY                BIT(20)
4374 +#define FE_GE1_STA_CHG         BIT(18)
4375 +#define FE_TX_COHERENT         BIT(17)
4376 +#define FE_RX_COHERENT         BIT(16)
4377 +#define FE_TX_DONE_INT3                BIT(11)
4378 +#define FE_TX_DONE_INT2                BIT(10)
4379 +#define FE_TX_DONE_INT1                BIT(9)
4380 +#define FE_TX_DONE_INT0                BIT(8)
4381 +#define FE_RX_DONE_INT0                BIT(2)
4382 +#define FE_TX_DLY_INT          BIT(1)
4383 +#define FE_RX_DLY_INT          BIT(0)
4384 +
4385 +#define RT5350_RX_DLY_INT      BIT(30)
4386 +#define RT5350_TX_DLY_INT      BIT(28)
4387 +
4388 +/* registers */
4389 +#define FE_FE_OFFSET           0x0000
4390 +#define FE_GDMA_OFFSET         0x0020
4391 +#define FE_PSE_OFFSET          0x0040
4392 +#define FE_GDMA2_OFFSET                0x0060
4393 +#define FE_CDMA_OFFSET         0x0080
4394 +#define FE_DMA_VID0            0x00a8
4395 +#define FE_PDMA_OFFSET         0x0100
4396 +#define FE_PPE_OFFSET          0x0200
4397 +#define FE_CMTABLE_OFFSET      0x0400
4398 +#define FE_POLICYTABLE_OFFSET  0x1000
4399 +
4400 +#define RT5350_PDMA_OFFSET     0x0800
4401 +#define RT5350_SDM_OFFSET      0x0c00
4402 +
4403 +#define FE_MDIO_ACCESS         (FE_FE_OFFSET + 0x00)
4404 +#define FE_MDIO_CFG            (FE_FE_OFFSET + 0x04)
4405 +#define FE_FE_GLO_CFG          (FE_FE_OFFSET + 0x08)
4406 +#define FE_FE_RST_GL           (FE_FE_OFFSET + 0x0C)
4407 +#define FE_FE_INT_STATUS       (FE_FE_OFFSET + 0x10)
4408 +#define FE_FE_INT_ENABLE       (FE_FE_OFFSET + 0x14)
4409 +#define FE_MDIO_CFG2           (FE_FE_OFFSET + 0x18)
4410 +#define FE_FOC_TS_T            (FE_FE_OFFSET + 0x1C)
4411 +
4412 +#define        FE_GDMA1_FWD_CFG        (FE_GDMA_OFFSET + 0x00)
4413 +#define FE_GDMA1_SCH_CFG       (FE_GDMA_OFFSET + 0x04)
4414 +#define FE_GDMA1_SHPR_CFG      (FE_GDMA_OFFSET + 0x08)
4415 +#define FE_GDMA1_MAC_ADRL      (FE_GDMA_OFFSET + 0x0C)
4416 +#define FE_GDMA1_MAC_ADRH      (FE_GDMA_OFFSET + 0x10)
4417 +
4418 +#define        FE_GDMA2_FWD_CFG        (FE_GDMA2_OFFSET + 0x00)
4419 +#define FE_GDMA2_SCH_CFG       (FE_GDMA2_OFFSET + 0x04)
4420 +#define FE_GDMA2_SHPR_CFG      (FE_GDMA2_OFFSET + 0x08)
4421 +#define FE_GDMA2_MAC_ADRL      (FE_GDMA2_OFFSET + 0x0C)
4422 +#define FE_GDMA2_MAC_ADRH      (FE_GDMA2_OFFSET + 0x10)
4423 +
4424 +#define FE_PSE_FQ_CFG          (FE_PSE_OFFSET + 0x00)
4425 +#define FE_CDMA_FC_CFG         (FE_PSE_OFFSET + 0x04)
4426 +#define FE_GDMA1_FC_CFG                (FE_PSE_OFFSET + 0x08)
4427 +#define FE_GDMA2_FC_CFG                (FE_PSE_OFFSET + 0x0C)
4428 +
4429 +#define FE_CDMA_CSG_CFG                (FE_CDMA_OFFSET + 0x00)
4430 +#define FE_CDMA_SCH_CFG                (FE_CDMA_OFFSET + 0x04)
4431 +
4432 +#define MT7620A_GDMA_OFFSET            0x0600
4433 +#define        MT7620A_GDMA1_FWD_CFG           (MT7620A_GDMA_OFFSET + 0x00)
4434 +#define MT7620A_FE_GDMA1_SCH_CFG       (MT7620A_GDMA_OFFSET + 0x04)
4435 +#define MT7620A_FE_GDMA1_SHPR_CFG      (MT7620A_GDMA_OFFSET + 0x08)
4436 +#define MT7620A_FE_GDMA1_MAC_ADRL      (MT7620A_GDMA_OFFSET + 0x0C)
4437 +#define MT7620A_FE_GDMA1_MAC_ADRH      (MT7620A_GDMA_OFFSET + 0x10)
4438 +
4439 +#define RT5350_TX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x00)
4440 +#define RT5350_TX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x04)
4441 +#define RT5350_TX_CTX_IDX0     (RT5350_PDMA_OFFSET + 0x08)
4442 +#define RT5350_TX_DTX_IDX0     (RT5350_PDMA_OFFSET + 0x0C)
4443 +#define RT5350_TX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x10)
4444 +#define RT5350_TX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x14)
4445 +#define RT5350_TX_CTX_IDX1     (RT5350_PDMA_OFFSET + 0x18)
4446 +#define RT5350_TX_DTX_IDX1     (RT5350_PDMA_OFFSET + 0x1C)
4447 +#define RT5350_TX_BASE_PTR2    (RT5350_PDMA_OFFSET + 0x20)
4448 +#define RT5350_TX_MAX_CNT2     (RT5350_PDMA_OFFSET + 0x24)
4449 +#define RT5350_TX_CTX_IDX2     (RT5350_PDMA_OFFSET + 0x28)
4450 +#define RT5350_TX_DTX_IDX2     (RT5350_PDMA_OFFSET + 0x2C)
4451 +#define RT5350_TX_BASE_PTR3    (RT5350_PDMA_OFFSET + 0x30)
4452 +#define RT5350_TX_MAX_CNT3     (RT5350_PDMA_OFFSET + 0x34)
4453 +#define RT5350_TX_CTX_IDX3     (RT5350_PDMA_OFFSET + 0x38)
4454 +#define RT5350_TX_DTX_IDX3     (RT5350_PDMA_OFFSET + 0x3C)
4455 +#define RT5350_RX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x100)
4456 +#define RT5350_RX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x104)
4457 +#define RT5350_RX_CALC_IDX0    (RT5350_PDMA_OFFSET + 0x108)
4458 +#define RT5350_RX_DRX_IDX0     (RT5350_PDMA_OFFSET + 0x10C)
4459 +#define RT5350_RX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x110)
4460 +#define RT5350_RX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x114)
4461 +#define RT5350_RX_CALC_IDX1    (RT5350_PDMA_OFFSET + 0x118)
4462 +#define RT5350_RX_DRX_IDX1     (RT5350_PDMA_OFFSET + 0x11C)
4463 +#define RT5350_PDMA_GLO_CFG    (RT5350_PDMA_OFFSET + 0x204)
4464 +#define RT5350_PDMA_RST_CFG    (RT5350_PDMA_OFFSET + 0x208)
4465 +#define RT5350_DLY_INT_CFG     (RT5350_PDMA_OFFSET + 0x20c)
4466 +#define RT5350_FE_INT_STATUS   (RT5350_PDMA_OFFSET + 0x220)
4467 +#define RT5350_FE_INT_ENABLE   (RT5350_PDMA_OFFSET + 0x228)
4468 +#define RT5350_PDMA_SCH_CFG    (RT5350_PDMA_OFFSET + 0x280)
4469 +
4470 +#define FE_PDMA_GLO_CFG                (FE_PDMA_OFFSET + 0x00)
4471 +#define FE_PDMA_RST_CFG                (FE_PDMA_OFFSET + 0x04)
4472 +#define FE_PDMA_SCH_CFG                (FE_PDMA_OFFSET + 0x08)
4473 +#define FE_DLY_INT_CFG         (FE_PDMA_OFFSET + 0x0C)
4474 +#define FE_TX_BASE_PTR0                (FE_PDMA_OFFSET + 0x10)
4475 +#define FE_TX_MAX_CNT0         (FE_PDMA_OFFSET + 0x14)
4476 +#define FE_TX_CTX_IDX0         (FE_PDMA_OFFSET + 0x18)
4477 +#define FE_TX_DTX_IDX0         (FE_PDMA_OFFSET + 0x1C)
4478 +#define FE_TX_BASE_PTR1                (FE_PDMA_OFFSET + 0x20)
4479 +#define FE_TX_MAX_CNT1         (FE_PDMA_OFFSET + 0x24)
4480 +#define FE_TX_CTX_IDX1         (FE_PDMA_OFFSET + 0x28)
4481 +#define FE_TX_DTX_IDX1         (FE_PDMA_OFFSET + 0x2C)
4482 +#define FE_RX_BASE_PTR0                (FE_PDMA_OFFSET + 0x30)
4483 +#define FE_RX_MAX_CNT0         (FE_PDMA_OFFSET + 0x34)
4484 +#define FE_RX_CALC_IDX0                (FE_PDMA_OFFSET + 0x38)
4485 +#define FE_RX_DRX_IDX0         (FE_PDMA_OFFSET + 0x3C)
4486 +#define FE_TX_BASE_PTR2                (FE_PDMA_OFFSET + 0x40)
4487 +#define FE_TX_MAX_CNT2         (FE_PDMA_OFFSET + 0x44)
4488 +#define FE_TX_CTX_IDX2         (FE_PDMA_OFFSET + 0x48)
4489 +#define FE_TX_DTX_IDX2         (FE_PDMA_OFFSET + 0x4C)
4490 +#define FE_TX_BASE_PTR3                (FE_PDMA_OFFSET + 0x50)
4491 +#define FE_TX_MAX_CNT3         (FE_PDMA_OFFSET + 0x54)
4492 +#define FE_TX_CTX_IDX3         (FE_PDMA_OFFSET + 0x58)
4493 +#define FE_TX_DTX_IDX3         (FE_PDMA_OFFSET + 0x5C)
4494 +#define FE_RX_BASE_PTR1                (FE_PDMA_OFFSET + 0x60)
4495 +#define FE_RX_MAX_CNT1         (FE_PDMA_OFFSET + 0x64)
4496 +#define FE_RX_CALC_IDX1                (FE_PDMA_OFFSET + 0x68)
4497 +#define FE_RX_DRX_IDX1         (FE_PDMA_OFFSET + 0x6C)
4498 +
4499 +#define RT5350_SDM_CFG         (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
4500 +#define RT5350_SDM_RRING       (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
4501 +#define RT5350_SDM_TRING       (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
4502 +#define RT5350_SDM_MAC_ADRL    (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
4503 +#define RT5350_SDM_MAC_ADRH    (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
4504 +#define RT5350_SDM_TPCNT       (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
4505 +#define RT5350_SDM_TBCNT       (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
4506 +#define RT5350_SDM_RPCNT       (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
4507 +#define RT5350_SDM_RBCNT       (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
4508 +#define RT5350_SDM_CS_ERR      (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
4509 +
4510 +#define RT5350_SDM_ICS_EN      BIT(16)
4511 +#define RT5350_SDM_TCS_EN      BIT(17)
4512 +#define RT5350_SDM_UCS_EN      BIT(18)
4513 +
4514 +
4515 +/* MDIO_CFG register bits */
4516 +#define FE_MDIO_CFG_AUTO_POLL_EN       BIT(29)
4517 +#define FE_MDIO_CFG_GP1_BP_EN          BIT(16)
4518 +#define FE_MDIO_CFG_GP1_FRC_EN         BIT(15)
4519 +#define FE_MDIO_CFG_GP1_SPEED_10       (0 << 13)
4520 +#define FE_MDIO_CFG_GP1_SPEED_100      (1 << 13)
4521 +#define FE_MDIO_CFG_GP1_SPEED_1000     (2 << 13)
4522 +#define FE_MDIO_CFG_GP1_DUPLEX         BIT(12)
4523 +#define FE_MDIO_CFG_GP1_FC_TX          BIT(11)
4524 +#define FE_MDIO_CFG_GP1_FC_RX          BIT(10)
4525 +#define FE_MDIO_CFG_GP1_LNK_DWN                BIT(9)
4526 +#define FE_MDIO_CFG_GP1_AN_FAIL                BIT(8)
4527 +#define FE_MDIO_CFG_MDC_CLK_DIV_1      (0 << 6)
4528 +#define FE_MDIO_CFG_MDC_CLK_DIV_2      (1 << 6)
4529 +#define FE_MDIO_CFG_MDC_CLK_DIV_4      (2 << 6)
4530 +#define FE_MDIO_CFG_MDC_CLK_DIV_8      (3 << 6)
4531 +#define FE_MDIO_CFG_TURBO_MII_FREQ     BIT(5)
4532 +#define FE_MDIO_CFG_TURBO_MII_MODE     BIT(4)
4533 +#define FE_MDIO_CFG_RX_CLK_SKEW_0      (0 << 2)
4534 +#define FE_MDIO_CFG_RX_CLK_SKEW_200    (1 << 2)
4535 +#define FE_MDIO_CFG_RX_CLK_SKEW_400    (2 << 2)
4536 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV    (3 << 2)
4537 +#define FE_MDIO_CFG_TX_CLK_SKEW_0      0
4538 +#define FE_MDIO_CFG_TX_CLK_SKEW_200    1
4539 +#define FE_MDIO_CFG_TX_CLK_SKEW_400    2
4540 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV    3
4541 +
4542 +/* uni-cast port */
4543 +#define FE_GDM1_ICS_EN         BIT(22)
4544 +#define FE_GDM1_TCS_EN         BIT(21)
4545 +#define FE_GDM1_UCS_EN         BIT(20)
4546 +#define FE_GDM1_JMB_EN         BIT(19)
4547 +#define FE_GDM1_STRPCRC                BIT(16)
4548 +#define FE_GDM1_UFRC_P_CPU     (0 << 12)
4549 +#define FE_GDM1_UFRC_P_GDMA1   (1 << 12)
4550 +#define FE_GDM1_UFRC_P_PPE     (6 << 12)
4551 +
4552 +/* checksums */
4553 +#define FE_ICS_GEN_EN          BIT(2)
4554 +#define FE_UCS_GEN_EN          BIT(1)
4555 +#define FE_TCS_GEN_EN          BIT(0)
4556 +
4557 +/* dma ring */
4558 +#define FE_PST_DRX_IDX0                BIT(16)
4559 +#define FE_PST_DTX_IDX3                BIT(3)
4560 +#define FE_PST_DTX_IDX2                BIT(2)
4561 +#define FE_PST_DTX_IDX1                BIT(1)
4562 +#define FE_PST_DTX_IDX0                BIT(0)
4563 +
4564 +#define FE_TX_WB_DDONE         BIT(6)
4565 +#define FE_RX_DMA_BUSY         BIT(3)
4566 +#define FE_TX_DMA_BUSY         BIT(1)
4567 +#define FE_RX_DMA_EN           BIT(2)
4568 +#define FE_TX_DMA_EN           BIT(0)
4569 +
4570 +#define FE_PDMA_SIZE_4DWORDS   (0 << 4)
4571 +#define FE_PDMA_SIZE_8DWORDS   (1 << 4)
4572 +#define FE_PDMA_SIZE_16DWORDS  (2 << 4)
4573 +
4574 +#define FE_US_CYC_CNT_MASK     0xff
4575 +#define FE_US_CYC_CNT_SHIFT    0x8
4576 +#define FE_US_CYC_CNT_DIVISOR  1000000
4577 +
4578 +#define RX_DMA_PLEN0(_x)       (((_x) >> 16) & 0x3fff)
4579 +#define RX_DMA_LSO             BIT(30)
4580 +#define RX_DMA_DONE            BIT(31)
4581 +#define RX_DMA_L4VALID         BIT(30)
4582 +
4583 +struct fe_rx_dma {
4584 +       unsigned int rxd1;
4585 +       unsigned int rxd2;
4586 +       unsigned int rxd3;
4587 +       unsigned int rxd4;
4588 +} __packed __aligned(4);
4589 +
4590 +#define TX_DMA_PLEN0_MASK      ((0x3fff) << 16)
4591 +#define TX_DMA_PLEN0(_x)       (((_x) & 0x3fff) << 16)
4592 +#define TX_DMA_PLEN1(_x)       ((_x) & 0x3fff)
4593 +#define TX_DMA_LS1             BIT(14)
4594 +#define TX_DMA_LSO             BIT(30)
4595 +#define TX_DMA_DONE            BIT(31)
4596 +#define TX_DMA_QN(_x)          ((_x) << 16)
4597 +#define TX_DMA_PN(_x)          ((_x) << 24)
4598 +#define TX_DMA_QN_MASK         TX_DMA_QN(0x7)
4599 +#define TX_DMA_PN_MASK         TX_DMA_PN(0x7)
4600 +#define TX_DMA_CHKSUM          (0x7 << 29)
4601 +
4602 +struct fe_tx_dma {
4603 +       unsigned int txd1;
4604 +       unsigned int txd2;
4605 +       unsigned int txd3;
4606 +       unsigned int txd4;
4607 +} __packed __aligned(4);
4608 +
4609 +struct fe_priv;
4610 +
4611 +struct fe_phy {
4612 +       struct phy_device       *phy[8];
4613 +       struct device_node      *phy_node[8];
4614 +       const __be32            *phy_fixed[8];
4615 +       int                     duplex[8];
4616 +       int                     speed[8];
4617 +       int                     tx_fc[8];
4618 +       int                     rx_fc[8];
4619 +       spinlock_t              lock;
4620 +
4621 +       int (*connect)(struct fe_priv *priv);
4622 +       void (*disconnect)(struct fe_priv *priv);
4623 +       void (*start)(struct fe_priv *priv);
4624 +       void (*stop)(struct fe_priv *priv);
4625 +};
4626 +
4627 +struct fe_soc_data
4628 +{
4629 +       unsigned char mac[6];
4630 +       const u32 *reg_table;
4631 +
4632 +       void (*init_data)(struct fe_soc_data *data);
4633 +       void (*reset_fe)(void);
4634 +       void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
4635 +       void (*fwd_config)(struct fe_priv *priv);
4636 +       void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
4637 +       void (*rx_dma)(struct fe_priv *priv, int idx, int len);
4638 +       int (*switch_init)(struct fe_priv *priv);
4639 +       int (*switch_config)(struct fe_priv *priv);
4640 +       void (*port_init)(struct fe_priv *priv, struct device_node *port);
4641 +       int (*has_carrier)(struct fe_priv *priv);
4642 +       int (*mdio_init)(struct fe_priv *priv);
4643 +       void (*mdio_cleanup)(struct fe_priv *priv);
4644 +       int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
4645 +       int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
4646 +       void (*mdio_adjust_link)(struct fe_priv *priv, int port);
4647 +       int (*get_skb_header)(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv);
4648 +
4649 +       void *swpriv;
4650 +       u32 pdma_glo_cfg;
4651 +       u32 rx_dly_int;
4652 +       u32 tx_dly_int;
4653 +       u32 checksum_bit;
4654 +       u32 tso;
4655 +
4656 +       int min_pkt_len;
4657 +};
4658 +
4659 +struct fe_priv
4660 +{
4661 +       spinlock_t                      page_lock;
4662 +
4663 +       struct fe_soc_data              *soc;
4664 +       struct net_device               *netdev;
4665 +       struct device                   *device;
4666 +       unsigned long                   sysclk;
4667 +
4668 +       struct fe_rx_dma                *rx_dma;
4669 +        struct napi_struct             rx_napi;
4670 +       struct sk_buff                  *rx_skb[NUM_DMA_DESC];
4671 +       dma_addr_t                      rx_phys;
4672 +
4673 +       struct fe_tx_dma                *tx_dma;
4674 +       struct tasklet_struct           tx_tasklet;
4675 +       struct sk_buff                  *tx_skb[NUM_DMA_DESC];
4676 +       dma_addr_t                      tx_phys;
4677 +       unsigned int                    tx_free_idx;
4678 +
4679 +       struct fe_phy                   *phy;
4680 +       struct mii_bus                  *mii_bus;
4681 +       int                             mii_irq[PHY_MAX_ADDR];
4682 +
4683 +       int                             link[8];
4684 +
4685 +       struct net_lro_mgr              lro_mgr;
4686 +       struct net_lro_desc             lro_arr[8];
4687 +};
4688 +
4689 +extern const struct of_device_id of_fe_match[];
4690 +
4691 +void fe_w32(u32 val, unsigned reg);
4692 +u32 fe_r32(unsigned reg);
4693 +
4694 +#endif /* FE_ETH_H */
4695 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_mt7620.c
4696 ===================================================================
4697 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4698 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_mt7620.c      2014-10-28 10:43:11.894131220 +0100
4699 @@ -0,0 +1,172 @@
4700 +/*
4701 + *   This program is free software; you can redistribute it and/or modify
4702 + *   it under the terms of the GNU General Public License as published by
4703 + *   the Free Software Foundation; version 2 of the License
4704 + *
4705 + *   This program is distributed in the hope that it will be useful,
4706 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4707 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4708 + *   GNU General Public License for more details.
4709 + *
4710 + *   You should have received a copy of the GNU General Public License
4711 + *   along with this program; if not, write to the Free Software
4712 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4713 + *
4714 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4715 + */
4716 +
4717 +#include <linux/module.h>
4718 +#include <linux/platform_device.h>
4719 +#include <linux/if_vlan.h>
4720 +
4721 +#include <asm/mach-ralink/ralink_regs.h>
4722 +
4723 +#include <mt7620.h>
4724 +#include "ralink_soc_eth.h"
4725 +#include "gsw_mt7620a.h"
4726 +
4727 +#define MT7620A_CDMA_CSG_CFG   0x400
4728 +#define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
4729 +#define MT7620A_DMA_2B_OFFSET  BIT(31)
4730 +#define MT7620A_RESET_FE       BIT(21)
4731 +#define MT7620A_RESET_ESW      BIT(23)
4732 +#define MT7620_L4_VALID                BIT(23)
4733 +
4734 +#define SYSC_REG_RESET_CTRL     0x34
4735 +#define MAX_RX_LENGTH           1536
4736 +
4737 +#define CDMA_ICS_EN            BIT(2)
4738 +#define CDMA_UCS_EN            BIT(1)
4739 +#define CDMA_TCS_EN            BIT(0)
4740 +
4741 +#define GDMA_ICS_EN            BIT(22)
4742 +#define GDMA_TCS_EN            BIT(21)
4743 +#define GDMA_UCS_EN            BIT(20)
4744 +
4745 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4746 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4747 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4748 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4749 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4750 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4751 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4752 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4753 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4754 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4755 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4756 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4757 +       [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4758 +};
4759 +
4760 +static void mt7620_fe_reset(void)
4761 +{
4762 +       rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4763 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4764 +}
4765 +
4766 +static void mt7620_fwd_config(struct fe_priv *priv)
4767 +{
4768 +       int i;
4769 +
4770 +       /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
4771 +       for (i = 0; i < 16; i += 2)
4772 +               fe_w32(((i + 1) << 16) + i, MT7620_DMA_VID + (i * 2));
4773 +
4774 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4775 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4776 +       fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4777 +}
4778 +
4779 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
4780 +{
4781 +       unsigned int nr_frags = 0;
4782 +       unsigned int len = 0;
4783 +
4784 +       if (skb) {
4785 +               nr_frags = skb_shinfo(skb)->nr_frags;
4786 +               len = skb->len - skb->data_len;
4787 +       }
4788 +
4789 +       if (!skb)
4790 +               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4791 +       else if (!nr_frags)
4792 +               priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4793 +       else
4794 +               priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(len);
4795 +
4796 +       if(skb && vlan_tx_tag_present(skb))
4797 +               priv->tx_dma[idx].txd4 = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
4798 +       else
4799 +               priv->tx_dma[idx].txd4 = 0;
4800 +}
4801 +
4802 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4803 +{
4804 +       priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4805 +}
4806 +
4807 +#ifdef CONFIG_INET_LRO
4808 +static int
4809 +mt7620_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
4810 +                       u64 *hdr_flags, void *_priv)
4811 +{
4812 +       struct iphdr *iph = NULL;
4813 +       int vhdr_len = 0;
4814 +
4815 +       /*
4816 +        * Make sure that this packet is Ethernet II, is not VLAN
4817 +        * tagged, is IPv4, has a valid IP header, and is TCP.
4818 +        */
4819 +       if (skb->protocol == 0x0081)
4820 +               vhdr_len = VLAN_HLEN;
4821 +
4822 +       iph = (struct iphdr *)(skb->data + vhdr_len);
4823 +       if(iph->protocol != IPPROTO_TCP)
4824 +               return -1;
4825 +
4826 +       *iphdr = iph;
4827 +       *tcph = skb->data + (iph->ihl << 2) + vhdr_len;
4828 +       *hdr_flags = LRO_IPV4 | LRO_TCP;
4829 +
4830 +       return 0;
4831 +}
4832 +#endif
4833 +
4834 +static void mt7620_init_data(struct fe_soc_data *data)
4835 +{
4836 +       if (mt7620_get_eco() >= 5)
4837 +               data->tso = 1;
4838 +}
4839 +
4840 +static struct fe_soc_data mt7620_data = {
4841 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4842 +       .init_data = mt7620_init_data,
4843 +       .reset_fe = mt7620_fe_reset,
4844 +       .set_mac = mt7620_set_mac,
4845 +       .fwd_config = mt7620_fwd_config,
4846 +       .tx_dma = mt7620_tx_dma,
4847 +       .rx_dma = mt7620_rx_dma,
4848 +       .switch_init = mt7620_gsw_probe,
4849 +       .switch_config = mt7620_gsw_config,
4850 +       .port_init = mt7620_port_init,
4851 +       .min_pkt_len = 0,
4852 +       .reg_table = rt5350_reg_table,
4853 +       .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4854 +       .rx_dly_int = RT5350_RX_DLY_INT,
4855 +       .tx_dly_int = RT5350_TX_DLY_INT,
4856 +       .checksum_bit = MT7620_L4_VALID,
4857 +       .has_carrier = mt7620a_has_carrier,
4858 +       .mdio_read = mt7620_mdio_read,
4859 +       .mdio_write = mt7620_mdio_write,
4860 +       .mdio_adjust_link = mt7620_mdio_link_adjust,
4861 +#ifdef CONFIG_INET_LRO
4862 +       .get_skb_header = mt7620_get_skb_header,
4863 +#endif
4864 +};
4865 +
4866 +const struct of_device_id of_fe_match[] = {
4867 +       { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4868 +       {},
4869 +};
4870 +
4871 +MODULE_DEVICE_TABLE(of, of_fe_match);
4872 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt2880.c
4873 ===================================================================
4874 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4875 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt2880.c      2014-10-28 10:43:11.894131220 +0100
4876 @@ -0,0 +1,52 @@
4877 +/*
4878 + *   This program is free software; you can redistribute it and/or modify
4879 + *   it under the terms of the GNU General Public License as published by
4880 + *   the Free Software Foundation; version 2 of the License
4881 + *
4882 + *   This program is distributed in the hope that it will be useful,
4883 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4884 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4885 + *   GNU General Public License for more details.
4886 + *
4887 + *   You should have received a copy of the GNU General Public License
4888 + *   along with this program; if not, write to the Free Software
4889 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4890 + *
4891 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4892 + */
4893 +
4894 +#include <linux/module.h>
4895 +
4896 +#include <asm/mach-ralink/ralink_regs.h>
4897 +
4898 +#include "ralink_soc_eth.h"
4899 +#include "mdio_rt2880.h"
4900 +
4901 +#define SYSC_REG_RESET_CTRL            0x034
4902 +#define RT2880_RESET_FE                        BIT(18)
4903 +
4904 +void rt2880_fe_reset(void)
4905 +{
4906 +       rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4907 +}
4908 +
4909 +struct fe_soc_data rt2880_data = {
4910 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4911 +       .reset_fe = rt2880_fe_reset,
4912 +       .min_pkt_len = 64,
4913 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4914 +       .checksum_bit = RX_DMA_L4VALID,
4915 +       .rx_dly_int = FE_RX_DLY_INT,
4916 +       .tx_dly_int = FE_TX_DLY_INT,
4917 +       .mdio_read = rt2880_mdio_read,
4918 +       .mdio_write = rt2880_mdio_write,
4919 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
4920 +       .port_init = rt2880_port_init,
4921 +};
4922 +
4923 +const struct of_device_id of_fe_match[] = {
4924 +       { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4925 +       {},
4926 +};
4927 +
4928 +MODULE_DEVICE_TABLE(of, of_fe_match);
4929 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt305x.c
4930 ===================================================================
4931 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4932 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt305x.c      2014-10-28 10:43:11.894131220 +0100
4933 @@ -0,0 +1,113 @@
4934 +/*
4935 + *   This program is free software; you can redistribute it and/or modify
4936 + *   it under the terms of the GNU General Public License as published by
4937 + *   the Free Software Foundation; version 2 of the License
4938 + *
4939 + *   This program is distributed in the hope that it will be useful,
4940 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4941 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4942 + *   GNU General Public License for more details.
4943 + *
4944 + *   You should have received a copy of the GNU General Public License
4945 + *   along with this program; if not, write to the Free Software
4946 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4947 + *
4948 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4949 + */
4950 +
4951 +#include <linux/module.h>
4952 +
4953 +#include <asm/mach-ralink/ralink_regs.h>
4954 +
4955 +#include "ralink_soc_eth.h"
4956 +
4957 +#define RT305X_RESET_FE         BIT(21)
4958 +#define RT305X_RESET_ESW        BIT(23)
4959 +#define SYSC_REG_RESET_CTRL     0x034
4960 +
4961 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4962 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4963 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4964 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4965 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4966 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4967 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4968 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4969 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4970 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4971 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4972 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4973 +       [FE_REG_FE_DMA_VID_BASE] = 0,
4974 +};
4975 +
4976 +static void rt305x_fe_reset(void)
4977 +{
4978 +       rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4979 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4980 +}
4981 +
4982 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4983 +{
4984 +       unsigned long flags;
4985 +
4986 +       spin_lock_irqsave(&priv->page_lock, flags);
4987 +       fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4988 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4989 +               RT5350_SDM_MAC_ADRL);
4990 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4991 +}
4992 +
4993 +static void rt5350_fwd_config(struct fe_priv *priv)
4994 +{
4995 +       unsigned long sysclk = priv->sysclk;
4996 +
4997 +       if (sysclk) {
4998 +               sysclk /= FE_US_CYC_CNT_DIVISOR;
4999 +               sysclk <<= FE_US_CYC_CNT_SHIFT;
5000 +
5001 +               fe_w32((fe_r32(FE_FE_GLO_CFG) &
5002 +                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
5003 +                       FE_FE_GLO_CFG);
5004 +       }
5005 +
5006 +       fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
5007 +       fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
5008 +               RT5350_SDM_CFG);
5009 +}
5010 +
5011 +static void rt5350_fe_reset(void)
5012 +{
5013 +       rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
5014 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
5015 +}
5016 +
5017 +static struct fe_soc_data rt3050_data = {
5018 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5019 +       .reset_fe = rt305x_fe_reset,
5020 +       .min_pkt_len = 64,
5021 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
5022 +       .checksum_bit = RX_DMA_L4VALID,
5023 +       .rx_dly_int = FE_RX_DLY_INT,
5024 +       .tx_dly_int = FE_TX_DLY_INT,
5025 +};
5026 +
5027 +static struct fe_soc_data rt5350_data = {
5028 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5029 +       .reg_table = rt5350_reg_table,
5030 +       .reset_fe = rt5350_fe_reset,
5031 +       .set_mac = rt5350_set_mac,
5032 +       .fwd_config = rt5350_fwd_config,
5033 +       .min_pkt_len = 64,
5034 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
5035 +       .checksum_bit = RX_DMA_L4VALID,
5036 +       .rx_dly_int = RT5350_RX_DLY_INT,
5037 +       .tx_dly_int = RT5350_TX_DLY_INT,
5038 +};
5039 +
5040 +const struct of_device_id of_fe_match[] = {
5041 +       { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
5042 +       { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
5043 +       {},
5044 +};
5045 +
5046 +MODULE_DEVICE_TABLE(of, of_fe_match);
5047 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt3883.c
5048 ===================================================================
5049 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5050 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt3883.c      2014-10-28 10:43:11.894131220 +0100
5051 @@ -0,0 +1,60 @@
5052 +/*
5053 + *   This program is free software; you can redistribute it and/or modify
5054 + *   it under the terms of the GNU General Public License as published by
5055 + *   the Free Software Foundation; version 2 of the License
5056 + *
5057 + *   This program is distributed in the hope that it will be useful,
5058 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
5059 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5060 + *   GNU General Public License for more details.
5061 + *
5062 + *   You should have received a copy of the GNU General Public License
5063 + *   along with this program; if not, write to the Free Software
5064 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5065 + *
5066 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5067 + */
5068 +
5069 +#include <linux/module.h>
5070 +
5071 +#include <asm/mach-ralink/ralink_regs.h>
5072 +
5073 +#include "ralink_soc_eth.h"
5074 +#include "mdio_rt2880.h"
5075 +
5076 +#define RT3883_SYSC_REG_RSTCTRL                0x34
5077 +#define RT3883_RSTCTRL_FE              BIT(21)
5078 +
5079 +static void rt3883_fe_reset(void)
5080 +{
5081 +       u32 t;
5082 +
5083 +       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
5084 +       t |= RT3883_RSTCTRL_FE;
5085 +       rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
5086 +
5087 +       t &= ~RT3883_RSTCTRL_FE;
5088 +       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
5089 +}
5090 +
5091 +static struct fe_soc_data rt3883_data = {
5092 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5093 +       .reset_fe = rt3883_fe_reset,
5094 +       .min_pkt_len = 64,
5095 +        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
5096 +       .rx_dly_int = FE_RX_DLY_INT,
5097 +       .tx_dly_int = FE_TX_DLY_INT,
5098 +       .checksum_bit = RX_DMA_L4VALID,
5099 +       .mdio_read = rt2880_mdio_read,
5100 +       .mdio_write = rt2880_mdio_write,
5101 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
5102 +       .port_init = rt2880_port_init,
5103 +};
5104 +
5105 +const struct of_device_id of_fe_match[] = {
5106 +       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
5107 +       {},
5108 +};
5109 +
5110 +MODULE_DEVICE_TABLE(of, of_fe_match);
5111 +