target/linux/ramips/patches-3.10/0012-PCI-MIPS-adds-rt3883-pci-support.patch

   1 From b43e77699154356a39796d95ef316699dafe409d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 17:34:08 +0100
   4 Subject: [PATCH 12/33] PCI: MIPS: adds rt3883 pci support
   5
   6 Add support for the pcie found on the rt3883 SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/pci/Makefile     |    1 +
  11  arch/mips/pci/pci-rt3883.c |  640 ++++++++++++++++++++++++++++++++++++++++++++
  12  arch/mips/ralink/Kconfig   |    1 +
  13  3 files changed, 642 insertions(+)
  14  create mode 100644 arch/mips/pci/pci-rt3883.c
  15
  16 --- a/arch/mips/pci/Makefile
  17 +++ b/arch/mips/pci/Makefile
  18 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops
  19  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  20  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  21  obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
  22 +obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  23  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  24  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
  25  obj-$(CONFIG_TANBAC_TB0287)    += fixup-tb0287.o
  26 --- /dev/null
  27 +++ b/arch/mips/pci/pci-rt3883.c
  28 @@ -0,0 +1,640 @@
  29 +/*
  30 + *  Ralink RT3662/RT3883 SoC PCI support
  31 + *
  32 + *  Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  33 + *
  34 + *  Parts of this file are based on Ralink's 2.6.21 BSP
  35 + *
  36 + *  This program is free software; you can redistribute it and/or modify it
  37 + *  under the terms of the GNU General Public License version 2 as published
  38 + *  by the Free Software Foundation.
  39 + */
  40 +
  41 +#include <linux/types.h>
  42 +#include <linux/pci.h>
  43 +#include <linux/io.h>
  44 +#include <linux/init.h>
  45 +#include <linux/delay.h>
  46 +#include <linux/interrupt.h>
  47 +#include <linux/module.h>
  48 +#include <linux/of.h>
  49 +#include <linux/of_irq.h>
  50 +#include <linux/of_pci.h>
  51 +#include <linux/platform_device.h>
  52 +
  53 +#include <asm/mach-ralink/rt3883.h>
  54 +#include <asm/mach-ralink/ralink_regs.h>
  55 +
  56 +#define RT3883_MEMORY_BASE             0x00000000
  57 +#define RT3883_MEMORY_SIZE             0x02000000
  58 +
  59 +#define RT3883_PCI_REG_PCICFG          0x00
  60 +#define   RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
  61 +#define   RT3883_PCICFG_P2P_BR_DEVNUM_S 16
  62 +#define   RT3883_PCICFG_PCIRST         BIT(1)
  63 +#define RT3883_PCI_REG_PCIRAW          0x04
  64 +#define RT3883_PCI_REG_PCIINT          0x08
  65 +#define RT3883_PCI_REG_PCIENA          0x0c
  66 +
  67 +#define RT3883_PCI_REG_CFGADDR         0x20
  68 +#define RT3883_PCI_REG_CFGDATA         0x24
  69 +#define RT3883_PCI_REG_MEMBASE         0x28
  70 +#define RT3883_PCI_REG_IOBASE          0x2c
  71 +#define RT3883_PCI_REG_ARBCTL          0x80
  72 +
  73 +#define RT3883_PCI_REG_BASE(_x)                (0x1000 + (_x) * 0x1000)
  74 +#define RT3883_PCI_REG_BAR0SETUP(_x)   (RT3883_PCI_REG_BASE((_x)) + 0x10)
  75 +#define RT3883_PCI_REG_IMBASEBAR0(_x)  (RT3883_PCI_REG_BASE((_x)) + 0x18)
  76 +#define RT3883_PCI_REG_ID(_x)          (RT3883_PCI_REG_BASE((_x)) + 0x30)
  77 +#define RT3883_PCI_REG_CLASS(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x34)
  78 +#define RT3883_PCI_REG_SUBID(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x38)
  79 +#define RT3883_PCI_REG_STATUS(_x)      (RT3883_PCI_REG_BASE((_x)) + 0x50)
  80 +
  81 +#define RT3883_PCI_MODE_NONE   0
  82 +#define RT3883_PCI_MODE_PCI    BIT(0)
  83 +#define RT3883_PCI_MODE_PCIE   BIT(1)
  84 +#define RT3883_PCI_MODE_BOTH   (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
  85 +
  86 +#define RT3883_PCI_IRQ_COUNT   32
  87 +
  88 +#define RT3883_P2P_BR_DEVNUM   1
  89 +
  90 +struct rt3883_pci_controller {
  91 +       void __iomem *base;
  92 +       spinlock_t lock;
  93 +
  94 +       struct irq_domain *irq_domain;
  95 +
  96 +       struct pci_controller pci_controller;
  97 +       struct resource io_res;
  98 +       struct resource mem_res;
  99 +
 100 +       bool pcie_ready;
 101 +       unsigned char p2p_devnum;
 102 +};
 103 +
 104 +static inline struct rt3883_pci_controller *
 105 +pci_bus_to_rt3883_controller(struct pci_bus *bus)
 106 +{
 107 +       struct pci_controller *hose;
 108 +
 109 +       hose = (struct pci_controller *) bus->sysdata;
 110 +       return container_of(hose, struct rt3883_pci_controller, pci_controller);
 111 +}
 112 +
 113 +static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
 114 +                                unsigned reg)
 115 +{
 116 +       return ioread32(rpc->base + reg);
 117 +}
 118 +
 119 +static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
 120 +                                 u32 val, unsigned reg)
 121 +{
 122 +       iowrite32(val, rpc->base + reg);
 123 +}
 124 +
 125 +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 126 +                                        unsigned int func, unsigned int where)
 127 +{
 128 +       return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
 129 +               0x80000000);
 130 +}
 131 +
 132 +static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
 133 +                              unsigned bus, unsigned slot,
 134 +                              unsigned func, unsigned reg)
 135 +{
 136 +       unsigned long flags;
 137 +       u32 address;
 138 +       u32 ret;
 139 +
 140 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 141 +
 142 +       spin_lock_irqsave(&rpc->lock, flags);
 143 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 144 +       ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 145 +       spin_unlock_irqrestore(&rpc->lock, flags);
 146 +
 147 +       return ret;
 148 +}
 149 +
 150 +static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
 151 +                                unsigned bus, unsigned slot,
 152 +                                unsigned func, unsigned reg, u32 val)
 153 +{
 154 +       unsigned long flags;
 155 +       u32 address;
 156 +
 157 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 158 +
 159 +       spin_lock_irqsave(&rpc->lock, flags);
 160 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 161 +       rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
 162 +       spin_unlock_irqrestore(&rpc->lock, flags);
 163 +}
 164 +
 165 +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 166 +{
 167 +       struct rt3883_pci_controller *rpc;
 168 +       u32 pending;
 169 +
 170 +       rpc = irq_get_handler_data(irq);
 171 +
 172 +       pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
 173 +                 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 174 +
 175 +       if (!pending) {
 176 +               spurious_interrupt();
 177 +               return;
 178 +       }
 179 +
 180 +       while (pending) {
 181 +               unsigned bit = __ffs(pending);
 182 +
 183 +               irq = irq_find_mapping(rpc->irq_domain, bit);
 184 +               generic_handle_irq(irq);
 185 +
 186 +               pending &= ~BIT(bit);
 187 +       }
 188 +}
 189 +
 190 +static void rt3883_pci_irq_unmask(struct irq_data *d)
 191 +{
 192 +       struct rt3883_pci_controller *rpc;
 193 +       u32 t;
 194 +
 195 +       rpc = irq_data_get_irq_chip_data(d);
 196 +
 197 +       t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 198 +       rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 199 +       /* flush write */
 200 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 201 +}
 202 +
 203 +static void rt3883_pci_irq_mask(struct irq_data *d)
 204 +{
 205 +       struct rt3883_pci_controller *rpc;
 206 +       u32 t;
 207 +
 208 +       rpc = irq_data_get_irq_chip_data(d);
 209 +
 210 +       t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 211 +       rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 212 +       /* flush write */
 213 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 214 +}
 215 +
 216 +static struct irq_chip rt3883_pci_irq_chip = {
 217 +       .name           = "RT3883 PCI",
 218 +       .irq_mask       = rt3883_pci_irq_mask,
 219 +       .irq_unmask     = rt3883_pci_irq_unmask,
 220 +       .irq_mask_ack   = rt3883_pci_irq_mask,
 221 +};
 222 +
 223 +static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
 224 +                             irq_hw_number_t hw)
 225 +{
 226 +       irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
 227 +       irq_set_chip_data(irq, d->host_data);
 228 +
 229 +       return 0;
 230 +}
 231 +
 232 +static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
 233 +       .map = rt3883_pci_irq_map,
 234 +       .xlate = irq_domain_xlate_onecell,
 235 +};
 236 +
 237 +static int rt3883_pci_irq_init(struct device *dev,
 238 +                              struct rt3883_pci_controller *rpc)
 239 +{
 240 +       struct device_node *np = dev->of_node;
 241 +       struct device_node *intc_np;
 242 +       int irq;
 243 +       int err;
 244 +
 245 +       intc_np = of_get_child_by_name(np, "interrupt-controller");
 246 +       if (!intc_np) {
 247 +               dev_err(dev, "no %s child node found", "interrupt-controller");
 248 +               return -ENODEV;
 249 +       }
 250 +
 251 +       irq = irq_of_parse_and_map(intc_np, 0);
 252 +       if (irq == 0) {
 253 +               dev_err(dev, "%s has no IRQ", of_node_full_name(intc_np));
 254 +               err = -EINVAL;
 255 +               goto err_put_intc;
 256 +       }
 257 +
 258 +       /* disable all interrupts */
 259 +       rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
 260 +
 261 +       rpc->irq_domain =
 262 +               irq_domain_add_linear(intc_np, RT3883_PCI_IRQ_COUNT,
 263 +                                     &rt3883_pci_irq_domain_ops,
 264 +                                     rpc);
 265 +       if (!rpc->irq_domain) {
 266 +               dev_err(dev, "unable to add IRQ domain\n");
 267 +               err = -ENODEV;
 268 +               goto err_put_intc;
 269 +       }
 270 +
 271 +       irq_set_handler_data(irq, rpc);
 272 +       irq_set_chained_handler(irq, rt3883_pci_irq_handler);
 273 +
 274 +       return 0;
 275 +
 276 +err_put_intc:
 277 +       of_node_put(intc_np);
 278 +       return err;
 279 +}
 280 +
 281 +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 282 +                                 int where, int size, u32 *val)
 283 +{
 284 +       struct rt3883_pci_controller *rpc;
 285 +       unsigned long flags;
 286 +       u32 address;
 287 +       u32 data;
 288 +
 289 +       rpc = pci_bus_to_rt3883_controller(bus);
 290 +
 291 +       if (!rpc->pcie_ready && bus->number == 1)
 292 +               return PCIBIOS_DEVICE_NOT_FOUND;
 293 +
 294 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 295 +                                        PCI_FUNC(devfn), where);
 296 +
 297 +       spin_lock_irqsave(&rpc->lock, flags);
 298 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 299 +       data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 300 +       spin_unlock_irqrestore(&rpc->lock, flags);
 301 +
 302 +       switch (size) {
 303 +       case 1:
 304 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 305 +               break;
 306 +       case 2:
 307 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 308 +               break;
 309 +       case 4:
 310 +               *val = data;
 311 +               break;
 312 +       }
 313 +
 314 +       return PCIBIOS_SUCCESSFUL;
 315 +}
 316 +
 317 +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 318 +                                  int where, int size, u32 val)
 319 +{
 320 +       struct rt3883_pci_controller *rpc;
 321 +       unsigned long flags;
 322 +       u32 address;
 323 +       u32 data;
 324 +
 325 +       rpc = pci_bus_to_rt3883_controller(bus);
 326 +
 327 +       if (!rpc->pcie_ready && bus->number == 1)
 328 +               return PCIBIOS_DEVICE_NOT_FOUND;
 329 +
 330 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 331 +                                        PCI_FUNC(devfn), where);
 332 +
 333 +       spin_lock_irqsave(&rpc->lock, flags);
 334 +       rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 335 +       data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 336 +
 337 +       switch (size) {
 338 +       case 1:
 339 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 340 +                      (val << ((where & 3) << 3));
 341 +               break;
 342 +       case 2:
 343 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 344 +                      (val << ((where & 3) << 3));
 345 +               break;
 346 +       case 4:
 347 +               data = val;
 348 +               break;
 349 +       }
 350 +
 351 +       rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
 352 +       spin_unlock_irqrestore(&rpc->lock, flags);
 353 +
 354 +       return PCIBIOS_SUCCESSFUL;
 355 +}
 356 +
 357 +static struct pci_ops rt3883_pci_ops = {
 358 +       .read   = rt3883_pci_config_read,
 359 +       .write  = rt3883_pci_config_write,
 360 +};
 361 +
 362 +static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
 363 +{
 364 +       u32 syscfg1;
 365 +       u32 rstctrl;
 366 +       u32 clkcfg1;
 367 +       u32 t;
 368 +
 369 +       rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 370 +       syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
 371 +       clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 372 +
 373 +       if (mode & RT3883_PCI_MODE_PCIE) {
 374 +               rstctrl |= RT3883_RSTCTRL_PCIE;
 375 +               rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 376 +
 377 +               /* setup PCI PAD drive mode */
 378 +               syscfg1 &= ~(0x30);
 379 +               syscfg1 |= (2 << 4);
 380 +               rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 381 +
 382 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 383 +               t &= ~BIT(31);
 384 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 385 +
 386 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 387 +               t &= 0x80ffffff;
 388 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 389 +
 390 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 391 +               t |= 0xa << 24;
 392 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 393 +
 394 +               t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 395 +               t |= BIT(31);
 396 +               rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 397 +
 398 +               msleep(50);
 399 +
 400 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 401 +               rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 402 +       }
 403 +
 404 +       syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
 405 +
 406 +       clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
 407 +
 408 +       if (mode & RT3883_PCI_MODE_PCI) {
 409 +               clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
 410 +               rstctrl &= ~RT3883_RSTCTRL_PCI;
 411 +       }
 412 +
 413 +       if (mode & RT3883_PCI_MODE_PCIE) {
 414 +               clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
 415 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 416 +       }
 417 +
 418 +       rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 419 +       rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 420 +       rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 421 +
 422 +       msleep(500);
 423 +
 424 +       /*
 425 +        * setup the device number of the P2P bridge
 426 +        * and de-assert the reset line
 427 +        */
 428 +       t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
 429 +       rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
 430 +
 431 +       /* flush write */
 432 +       rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
 433 +       msleep(500);
 434 +
 435 +       if (mode & RT3883_PCI_MODE_PCIE) {
 436 +               msleep(500);
 437 +
 438 +               t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
 439 +
 440 +               rpc->pcie_ready = t & BIT(0);
 441 +
 442 +               if (!rpc->pcie_ready) {
 443 +                       /* reset the PCIe block */
 444 +                       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 445 +                       t |= RT3883_RSTCTRL_PCIE;
 446 +                       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 447 +                       t &= ~RT3883_RSTCTRL_PCIE;
 448 +                       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 449 +
 450 +                       /* turn off PCIe clock */
 451 +                       t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 452 +                       t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
 453 +                       rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
 454 +
 455 +                       t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 456 +                       t &= ~0xf000c080;
 457 +                       rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 458 +               }
 459 +       }
 460 +
 461 +       /* enable PCI arbiter */
 462 +       rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
 463 +}
 464 +
 465 +static inline void
 466 +rt3883_dump_pci_config(struct rt3883_pci_controller *rpc,
 467 +                      int bus, int slot)
 468 +{
 469 +       int i;
 470 +
 471 +       for (i = 0; i < 16; i++) {
 472 +               u32 val;
 473 +
 474 +               val = rt3883_pci_read_cfg32(rpc, bus, slot, 0, i << 2);
 475 +               pr_info("pci %02x:%02x.0 0x%02x = %08x\n",
 476 +                       bus, slot, i << 2, val);
 477 +       }
 478 +}
 479 +
 480 +static int rt3883_pci_probe(struct platform_device *pdev)
 481 +{
 482 +       struct rt3883_pci_controller *rpc;
 483 +       struct device *dev = &pdev->dev;
 484 +       struct device_node *np = dev->of_node;
 485 +       struct resource *res;
 486 +       struct device_node *child;
 487 +       u32 val;
 488 +       int err;
 489 +       int mode;
 490 +
 491 +       rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
 492 +       if (!rpc)
 493 +               return -ENOMEM;
 494 +
 495 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 496 +       if (!res)
 497 +               return -EINVAL;
 498 +
 499 +       rpc->base = devm_ioremap_resource(dev, res);
 500 +       if (IS_ERR(rpc->base))
 501 +               return PTR_ERR(rpc->base);
 502 +
 503 +       rpc->pci_controller.of_node = of_get_child_by_name(np, "host-bridge");
 504 +       if (!rpc->pci_controller.of_node) {
 505 +               dev_err(dev, "no %s child node found", "host-bridge");
 506 +               return -ENODEV;
 507 +       }
 508 +
 509 +       mode = RT3883_PCI_MODE_NONE;
 510 +       for_each_child_of_node(rpc->pci_controller.of_node, child) {
 511 +               u32 slot;
 512 +
 513 +               if (!of_device_is_available(child))
 514 +                       continue;
 515 +
 516 +               if (of_property_read_u32(child, "ralink,pci-slot",
 517 +                                        &slot)) {
 518 +                       dev_err(dev, "no '%s' property found for %s\n",
 519 +                               "ralink,pci-slot",
 520 +                               of_node_full_name(child));
 521 +                       continue;
 522 +               }
 523 +
 524 +               switch (slot) {
 525 +               case 1:
 526 +                       mode |= RT3883_PCI_MODE_PCIE;
 527 +                       break;
 528 +
 529 +               case 17:
 530 +               case 18:
 531 +                       mode |= RT3883_PCI_MODE_PCI;
 532 +                       break;
 533 +               }
 534 +       }
 535 +
 536 +       if (mode == RT3883_PCI_MODE_NONE) {
 537 +               dev_err(dev, "unable to determine PCI mode\n");
 538 +               err = -EINVAL;
 539 +               goto err_put_hb_node;
 540 +       }
 541 +
 542 +       dev_info(dev, "mode:%s%s\n",
 543 +                (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
 544 +                (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
 545 +
 546 +       rt3883_pci_preinit(rpc, mode);
 547 +
 548 +       rpc->pci_controller.pci_ops = &rt3883_pci_ops;
 549 +       rpc->pci_controller.io_resource = &rpc->io_res;
 550 +       rpc->pci_controller.mem_resource = &rpc->mem_res;
 551 +
 552 +       /* Load PCI I/O and memory resources from DT */
 553 +       pci_load_of_ranges(&rpc->pci_controller,
 554 +                          rpc->pci_controller.of_node);
 555 +
 556 +       rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
 557 +       rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
 558 +
 559 +       ioport_resource.start = rpc->io_res.start;
 560 +       ioport_resource.end = rpc->io_res.end;
 561 +
 562 +       /* PCI */
 563 +       rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
 564 +       rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
 565 +       rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
 566 +       rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
 567 +       rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
 568 +
 569 +       /* PCIe */
 570 +       rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
 571 +       rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
 572 +       rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
 573 +       rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
 574 +       rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
 575 +
 576 +       err = rt3883_pci_irq_init(dev, rpc);
 577 +       if (err)
 578 +               goto err_put_hb_node;
 579 +
 580 +       /* PCIe */
 581 +       val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
 582 +       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 583 +       rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
 584 +
 585 +       /* PCI */
 586 +       val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
 587 +       val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 588 +       rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
 589 +
 590 +       if (mode == RT3883_PCI_MODE_PCIE) {
 591 +               rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
 592 +               rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
 593 +
 594 +               rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 595 +                                      PCI_BASE_ADDRESS_0,
 596 +                                      RT3883_MEMORY_BASE);
 597 +               /* flush write */
 598 +               rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 599 +                                     PCI_BASE_ADDRESS_0);
 600 +       } else {
 601 +               rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 602 +                                      PCI_IO_BASE, 0x00000101);
 603 +       }
 604 +
 605 +       register_pci_controller(&rpc->pci_controller);
 606 +
 607 +       return 0;
 608 +
 609 +err_put_hb_node:
 610 +       of_node_put(rpc->pci_controller.of_node);
 611 +       return err;
 612 +}
 613 +
 614 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 615 +{
 616 +       struct rt3883_pci_controller *rpc;
 617 +       struct of_irq dev_irq;
 618 +       int err;
 619 +       int irq;
 620 +
 621 +       rpc = pci_bus_to_rt3883_controller(dev->bus);
 622 +       err = of_irq_map_pci(dev, &dev_irq);
 623 +       if (err) {
 624 +               pr_err("pci %s: unable to get irq map, err=%d\n",
 625 +                      pci_name((struct pci_dev *) dev), err);
 626 +               return 0;
 627 +       }
 628 +
 629 +       irq = irq_create_of_mapping(dev_irq.controller,
 630 +                                   dev_irq.specifier,
 631 +                                   dev_irq.size);
 632 +
 633 +       if (irq == 0)
 634 +               pr_crit("pci %s: no irq found for pin %u\n",
 635 +                       pci_name((struct pci_dev *) dev), pin);
 636 +       else
 637 +               pr_info("pci %s: using irq %d for pin %u\n",
 638 +                       pci_name((struct pci_dev *) dev), irq, pin);
 639 +
 640 +       return irq;
 641 +}
 642 +
 643 +int pcibios_plat_dev_init(struct pci_dev *dev)
 644 +{
 645 +       return 0;
 646 +}
 647 +
 648 +static const struct of_device_id rt3883_pci_ids[] = {
 649 +       { .compatible = "ralink,rt3883-pci" },
 650 +       {},
 651 +};
 652 +MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
 653 +
 654 +static struct platform_driver rt3883_pci_driver = {
 655 +       .probe = rt3883_pci_probe,
 656 +       .driver = {
 657 +               .name = "rt3883-pci",
 658 +               .owner = THIS_MODULE,
 659 +               .of_match_table = of_match_ptr(rt3883_pci_ids),
 660 +       },
 661 +};
 662 +
 663 +static int __init rt3883_pci_init(void)
 664 +{
 665 +       return platform_driver_register(&rt3883_pci_driver);
 666 +}
 667 +
 668 +postcore_initcall(rt3883_pci_init);
 669 --- a/arch/mips/ralink/Kconfig
 670 +++ b/arch/mips/ralink/Kconfig
 671 @@ -20,6 +20,7 @@ choice
 672                 bool "RT3883"
 673                 select USB_ARCH_HAS_OHCI
 674                 select USB_ARCH_HAS_EHCI
 675 +               select HW_HAS_PCI
 676
 677         config SOC_MT7620
 678                 bool "MT7620"