target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c

   1 /*
   2  *  Ralink RT305X clock API
   3  *
   4  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16
  17 #include <asm/mach-ralink/common.h>
  18 #include <asm/mach-ralink/rt305x.h>
  19 #include <asm/mach-ralink/rt305x_regs.h>
  20 #include "common.h"
  21
  22 struct clk {
  23         unsigned long rate;
  24 };
  25
  26 static struct clk rt305x_cpu_clk;
  27 static struct clk rt305x_sys_clk;
  28 static struct clk rt305x_wdt_clk;
  29 static struct clk rt305x_uart_clk;
  30
  31 void __init rt305x_clocks_init(void)
  32 {
  33         u32     t;
  34
  35         t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
  36
  37         if (soc_is_rt305x() || soc_is_rt3350()) {
  38                 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
  39                      RT305X_SYSCFG_CPUCLK_MASK;
  40                 switch (t) {
  41                 case RT305X_SYSCFG_CPUCLK_LOW:
  42                         rt305x_cpu_clk.rate = 320000000;
  43                         break;
  44                 case RT305X_SYSCFG_CPUCLK_HIGH:
  45                         rt305x_cpu_clk.rate = 384000000;
  46                         break;
  47                 }
  48                 rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
  49                 rt305x_uart_clk.rate = rt305x_sys_clk.rate;
  50                 rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
  51         } else if (soc_is_rt3352()) {
  52                 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
  53                      RT3352_SYSCFG0_CPUCLK_MASK;
  54                 switch (t) {
  55                 case RT3352_SYSCFG0_CPUCLK_LOW:
  56                         rt305x_cpu_clk.rate = 384000000;
  57                         break;
  58                 case RT3352_SYSCFG0_CPUCLK_HIGH:
  59                         rt305x_cpu_clk.rate = 400000000;
  60                         break;
  61                 }
  62                 rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
  63                 rt305x_uart_clk.rate = 40000000;
  64                 rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
  65         } else {
  66                 BUG();
  67         }
  68
  69 }
  70
  71 /*
  72  * Linux clock API
  73  */
  74 struct clk *clk_get(struct device *dev, const char *id)
  75 {
  76         if (!strcmp(id, "sys"))
  77                 return &rt305x_sys_clk;
  78
  79         if (!strcmp(id, "cpu"))
  80                 return &rt305x_cpu_clk;
  81
  82         if (!strcmp(id, "wdt"))
  83                 return &rt305x_wdt_clk;
  84
  85         if (!strcmp(id, "uart"))
  86                 return &rt305x_uart_clk;
  87
  88         return ERR_PTR(-ENOENT);
  89 }
  90 EXPORT_SYMBOL(clk_get);
  91
  92 int clk_enable(struct clk *clk)
  93 {
  94         return 0;
  95 }
  96 EXPORT_SYMBOL(clk_enable);
  97
  98 void clk_disable(struct clk *clk)
  99 {
 100 }
 101 EXPORT_SYMBOL(clk_disable);
 102
 103 unsigned long clk_get_rate(struct clk *clk)
 104 {
 105         return clk->rate;
 106 }
 107 EXPORT_SYMBOL(clk_get_rate);
 108
 109 void clk_put(struct clk *clk)
 110 {
 111 }
 112 EXPORT_SYMBOL(clk_put);