2 * Ralink SoC specific GPIO support
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/init.h>
14 #include <linux/gpio.h>
16 #include <ralink_soc.h>
18 #define GPIO0_REG_INT 0x00
19 #define GPIO0_REG_EDGE 0x04
20 #define GPIO0_REG_RENA 0x08
21 #define GPIO0_REG_FENA 0x0c
22 #define GPIO0_REG_DATA 0x20
23 #define GPIO0_REG_DIR 0x24
24 #define GPIO0_REG_POL 0x28
25 #define GPIO0_REG_SET 0x2c
26 #define GPIO0_REG_RESET 0x30
27 #define GPIO0_REG_TOGGLE 0x34
29 #define GPIO1_REG_INT 0x38
30 #define GPIO1_REG_EDGE 0x3c
31 #define GPIO1_REG_RENA 0x40
32 #define GPIO1_REG_FENA 0x44
33 #define GPIO1_REG_DATA 0x48
34 #define GPIO1_REG_DIR 0x4c
35 #define GPIO1_REG_POL 0x50
36 #define GPIO1_REG_SET 0x54
37 #define GPIO1_REG_RESET 0x58
38 #define GPIO1_REG_TOGGLE 0x5c
40 #define GPIO2_REG_INT 0x60
41 #define GPIO2_REG_EDGE 0x64
42 #define GPIO2_REG_RENA 0x68
43 #define GPIO2_REG_FENA 0x6c
44 #define GPIO2_REG_DATA 0x70
45 #define GPIO2_REG_DIR 0x74
46 #define GPIO2_REG_POL 0x78
47 #define GPIO2_REG_SET 0x7c
48 #define GPIO2_REG_RESET 0x80
49 #define GPIO2_REG_TOGGLE 0x84
52 RAMIPS_GPIO_REG_INT, /* Interrupt status */
57 RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */
58 RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */
60 RAMIPS_GPIO_REG_RESET,
61 RAMIPS_GPIO_REG_TOGGLE,
65 struct ramips_gpio_chip {
66 struct gpio_chip chip;
67 u8 regs[RAMIPS_GPIO_REG_MAX];
70 static void __iomem *ramips_gpio_base;
72 static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip)
74 struct ramips_gpio_chip *rg;
76 rg = container_of(chip, struct ramips_gpio_chip, chip);
80 static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val)
82 __raw_writel(val, ramips_gpio_base + rg->regs[reg]);
85 static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg)
87 return __raw_readl(ramips_gpio_base + rg->regs[reg]);
90 static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
92 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
95 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
97 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
102 static int ramips_gpio_direction_output(struct gpio_chip *chip,
103 unsigned offset, int value)
105 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
109 reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
110 ramips_gpio_wr(rg, reg, 1 << offset);
112 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
114 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
119 static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
121 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
124 reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
125 ramips_gpio_wr(rg, reg, 1 << offset);
128 static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
130 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
133 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA);
134 return !!(t & (1 << offset));
137 static struct ramips_gpio_chip ramips_gpio_chip0 = {
139 .label = "ramips-gpio0",
140 .direction_input = ramips_gpio_direction_input,
141 .direction_output = ramips_gpio_direction_output,
142 .get = ramips_gpio_get,
143 .set = ramips_gpio_set,
145 .ngpio = RALINK_SOC_GPIO0_COUNT,
148 [RAMIPS_GPIO_REG_INT] = GPIO0_REG_INT,
149 [RAMIPS_GPIO_REG_EDGE] = GPIO0_REG_EDGE,
150 [RAMIPS_GPIO_REG_RENA] = GPIO0_REG_RENA,
151 [RAMIPS_GPIO_REG_FENA] = GPIO0_REG_FENA,
152 [RAMIPS_GPIO_REG_DATA] = GPIO0_REG_DATA,
153 [RAMIPS_GPIO_REG_DIR] = GPIO0_REG_DIR,
154 [RAMIPS_GPIO_REG_POL] = GPIO0_REG_POL,
155 [RAMIPS_GPIO_REG_SET] = GPIO0_REG_SET,
156 [RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,
157 [RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,
161 static struct ramips_gpio_chip ramips_gpio_chip1 = {
163 .label = "ramips-gpio1",
164 .direction_input = ramips_gpio_direction_input,
165 .direction_output = ramips_gpio_direction_output,
166 .get = ramips_gpio_get,
167 .set = ramips_gpio_set,
169 .ngpio = RALINK_SOC_GPIO1_COUNT,
172 [RAMIPS_GPIO_REG_INT] = GPIO1_REG_INT,
173 [RAMIPS_GPIO_REG_EDGE] = GPIO1_REG_EDGE,
174 [RAMIPS_GPIO_REG_RENA] = GPIO1_REG_RENA,
175 [RAMIPS_GPIO_REG_FENA] = GPIO1_REG_FENA,
176 [RAMIPS_GPIO_REG_DATA] = GPIO1_REG_DATA,
177 [RAMIPS_GPIO_REG_DIR] = GPIO1_REG_DIR,
178 [RAMIPS_GPIO_REG_POL] = GPIO1_REG_POL,
179 [RAMIPS_GPIO_REG_SET] = GPIO1_REG_SET,
180 [RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,
181 [RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,
185 static struct ramips_gpio_chip ramips_gpio_chip2 = {
187 .label = "ramips-gpio2",
188 .direction_input = ramips_gpio_direction_input,
189 .direction_output = ramips_gpio_direction_output,
190 .get = ramips_gpio_get,
191 .set = ramips_gpio_set,
193 .ngpio = RALINK_SOC_GPIO2_COUNT,
196 [RAMIPS_GPIO_REG_INT] = GPIO2_REG_INT,
197 [RAMIPS_GPIO_REG_EDGE] = GPIO2_REG_EDGE,
198 [RAMIPS_GPIO_REG_RENA] = GPIO2_REG_RENA,
199 [RAMIPS_GPIO_REG_FENA] = GPIO2_REG_FENA,
200 [RAMIPS_GPIO_REG_DATA] = GPIO2_REG_DATA,
201 [RAMIPS_GPIO_REG_DIR] = GPIO2_REG_DIR,
202 [RAMIPS_GPIO_REG_POL] = GPIO2_REG_POL,
203 [RAMIPS_GPIO_REG_SET] = GPIO2_REG_SET,
204 [RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,
205 [RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,
209 static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
211 /* set polarity to low for all lines */
212 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0);
214 gpiochip_add(&rg->chip);
217 __init int ramips_gpio_init(void)
219 ramips_gpio_base = ioremap_nocache(RALINK_SOC_GPIO_BASE, PAGE_SIZE);
221 ramips_gpio_chip_add(&ramips_gpio_chip0);
222 ramips_gpio_chip_add(&ramips_gpio_chip1);
223 ramips_gpio_chip_add(&ramips_gpio_chip2);