target/linux/ramips/dts/mt7621.dtsi

   1 / {
   2         #address-cells = <1>;
   3         #size-cells = <1>;
   4         compatible = "mediatek,mtk7621-soc";
   5
   6         cpus {
   7                 cpu@0 {
   8                         compatible = "mips,mips1004Kc";
   9                 };
  10
  11                 cpu@1 {
  12                         compatible = "mips,mips1004Kc";
  13                 };
  14         };
  15
  16         cpuintc: cpuintc@0 {
  17                 #address-cells = <0>;
  18                 #interrupt-cells = <1>;
  19                 interrupt-controller;
  20                 compatible = "mti,cpu-interrupt-controller";
  21         };
  22
  23         palmbus@1E000000 {
  24                 compatible = "palmbus";
  25                 reg = <0x1E000000 0x100000>;
  26                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  27
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30
  31                 sysc@0 {
  32                         compatible = "mtk,mt7621-sysc";
  33                         reg = <0x0 0x100>;
  34                 };
  35
  36                 wdt@100 {
  37                         compatible = "mtk,mt7621-wdt";
  38                         reg = <0x100 0x100>;
  39                 };
  40
  41                 gpio@600 {
  42                         #address-cells = <1>;
  43                         #size-cells = <0>;
  44
  45                         compatible = "mtk,mt7621-gpio";
  46                         reg = <0x600 0x100>;
  47
  48                         gpio0: bank@0 {
  49                                 reg = <0>;
  50                                 compatible = "mtk,mt7621-gpio-bank";
  51                                 gpio-controller;
  52                                 #gpio-cells = <2>;
  53                         };
  54
  55                         gpio1: bank@1 {
  56                                 reg = <1>;
  57                                 compatible = "mtk,mt7621-gpio-bank";
  58                                 gpio-controller;
  59                                 #gpio-cells = <2>;
  60                         };
  61
  62                         gpio2: bank@2 {
  63                                 reg = <2>;
  64                                 compatible = "mtk,mt7621-gpio-bank";
  65                                 gpio-controller;
  66                                 #gpio-cells = <2>;
  67                         };
  68                 };
  69
  70                 memc@5000 {
  71                         compatible = "mtk,mt7621-memc";
  72                         reg = <0x300 0x100>;
  73                 };
  74
  75                 uartlite@c00 {
  76                         compatible = "ns16550a";
  77                         reg = <0xc00 0x100>;
  78
  79                         interrupt-parent = <&gic>;
  80                         interrupts = <26>;
  81
  82                         reg-shift = <2>;
  83                         reg-io-width = <4>;
  84                         no-loopback-test;
  85                 };
  86
  87                 spi@b00 {
  88                         status = "okay";
  89
  90                         compatible = "ralink,mt7621-spi";
  91                         reg = <0xb00 0x100>;
  92
  93                         resets = <&rstctrl 18>;
  94                         reset-names = "spi";
  95
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98
  99                         pinctrl-names = "default";
 100                         pinctrl-0 = <&spi_pins>;
 101
 102                         m25p80@0 {
 103                                 #address-cells = <1>;
 104                                 #size-cells = <1>;
 105                                 reg = <0 0>;
 106                                 spi-max-frequency = <10000000>;
 107                                 m25p,chunked-io = <32>;
 108                         };
 109                 };
 110         };
 111
 112         pinctrl {
 113                 compatible = "ralink,rt2880-pinmux";
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&state_default>;
 116
 117                 state_default: pinctrl0 {
 118                 };
 119
 120                 spi_pins: spi {
 121                         spi {
 122                                 ralink,group = "spi";
 123                                 ralink,function = "spi";
 124                         };
 125                 };
 126
 127                 i2c_pins: i2c {
 128                         i2c {
 129                                 ralink,group = "i2c";
 130                                 ralink,function = "i2c";
 131                         };
 132                 };
 133
 134                 uart1_pins: uart1 {
 135                         uart1 {
 136                                 ralink,group = "uart1";
 137                                 ralink,function = "uart1";
 138                         };
 139                 };
 140
 141                 uart2_pins: uart2 {
 142                         uart2 {
 143                                 ralink,group = "uart2";
 144                                 ralink,function = "uart2";
 145                         };
 146                 };
 147
 148                 uart3_pins: uart3 {
 149                         uart3 {
 150                                 ralink,group = "uart3";
 151                                 ralink,function = "uart3";
 152                         };
 153                 };
 154
 155                 rgmii1_pins: rgmii1 {
 156                         rgmii1 {
 157                                 ralink,group = "rgmii1";
 158                                 ralink,function = "rgmii1";
 159                         };
 160                 };
 161
 162                 rgmii2_pins: rgmii2 {
 163                         rgmii2 {
 164                                 ralink,group = "rgmii2";
 165                                 ralink,function = "rgmii2";
 166                         };
 167                 };
 168
 169                 mdio_pins: mdio {
 170                         mdio {
 171                                 ralink,group = "mdio";
 172                                 ralink,function = "mdio";
 173                         };
 174                 };
 175
 176                 pcie_pins: pcie {
 177                         pcie {
 178                                 ralink,group = "pcie";
 179                                 ralink,function = "pcie rst";
 180                         };
 181                 };
 182
 183                 nand_pins: nand {
 184                         spi-nand {
 185                                 ralink,group = "spi";
 186                                 ralink,function = "nand1";
 187                         };
 188
 189                         sdhci-nand {
 190                                 ralink,group = "sdhci";
 191                                 ralink,function = "nand2";
 192                         };
 193                 };
 194
 195                 sdhci_pins: sdhci {
 196                         sdhci {
 197                                 ralink,group = "sdhci";
 198                                 ralink,function = "sdhci";
 199                         };
 200                 };
 201         };
 202
 203         rstctrl: rstctrl {
 204                 compatible = "ralink,rt2880-reset";
 205                 #reset-cells = <1>;
 206         };
 207
 208         sdhci@1E130000 {
 209                 compatible = "ralink,mt7620-sdhci";
 210                 reg = <0x1E130000 4000>;
 211
 212                 interrupt-parent = <&gic>;
 213                 interrupts = <20>;
 214         };
 215
 216         xhci@1E1C0000 {
 217                 status = "disabled";
 218
 219                 compatible = "xhci-platform";
 220                 reg = <0x1E1C0000 4000>;
 221
 222                 interrupt-parent = <&gic>;
 223                 interrupts = <22>;
 224         };
 225
 226         gic: gic@1fbc0000 {
 227                 #address-cells = <0>;
 228                 #interrupt-cells = <1>;
 229                 interrupt-controller;
 230                 compatible = "ralink,mt7621-gic";
 231                 reg = < 0x1fbc0000 0x80 /* gic */
 232                         0x1fbf0000 0x8000 /* cpc */
 233                         0x1fbf8000 0x8000 /* gpmc */
 234                 >;
 235         };
 236
 237         nand@1e003000 {
 238                 compatible = "mtk,mt7621-nand";
 239                 bank-width = <2>;
 240                 reg = <0x1e003000 0x800
 241                         0x1e003800 0x800>;
 242                 #address-cells = <1>;
 243                 #size-cells = <1>;
 244
 245                 partition@0 {
 246                         label = "uboot";
 247                         reg = <0x00000 0x80000>; /* 64 KB */
 248                 };
 249
 250                 partition@80000 {
 251                         label = "uboot_env";
 252                         reg = <0x80000 0x80000>; /* 64 KB */
 253                 };
 254
 255                 partition@100000 {
 256                         label = "factory";
 257                         reg = <0x100000 0x40000>;
 258                 };
 259
 260                 partition@140000 {
 261                         label = "rootfs";
 262                         reg = <0x140000 0xec0000>;
 263                 };
 264         };
 265
 266         ethernet@1e100000 {
 267                 compatible = "ralink,mt7621-eth";
 268                 reg = <0x1e100000 10000>;
 269
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272
 273                 resets = <&rstctrl 6 &rstctrl 23>;
 274                 reset-names = "fe", "eth";
 275
 276                 interrupt-parent = <&gic>;
 277                 interrupts = <3>;
 278
 279                 mdio-bus {
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282
 283                         phy1f: ethernet-phy@1f {
 284                                 reg = <0x1f>;
 285                                 phy-mode = "rgmii";
 286                         };
 287                 };
 288         };
 289
 290         gsw@1e110000 {
 291                 compatible = "ralink,mt7620a-gsw";
 292                 reg = <0x1e110000 8000>;
 293                 interrupt-parent = <&gic>;
 294                 interrupts = <23>;
 295         };
 296
 297         pcie@1e140000 {
 298                 compatible = "mediatek,mt7621-pci";
 299                 reg = <0x1e140000 0x100
 300                         0x1e142000 0x100>;
 301
 302                 #address-cells = <3>;
 303                 #size-cells = <2>;
 304
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&pcie_pins>;
 307
 308                 device_type = "pci";
 309
 310                 bus-range = <0 255>;
 311                 ranges = <
 312                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 313                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 314                 >;
 315
 316                 status = "okay";
 317
 318                 pcie0 {
 319                         reg = <0x0000 0 0 0 0>;
 320
 321                         #address-cells = <3>;
 322                         #size-cells = <2>;
 323
 324                         device_type = "pci";
 325                 };
 326
 327                 pcie1 {
 328                         reg = <0x0800 0 0 0 0>;
 329
 330                         #address-cells = <3>;
 331                         #size-cells = <2>;
 332
 333                         device_type = "pci";
 334                 };
 335
 336                 pcie2 {
 337                         reg = <0x1000 0 0 0 0>;
 338
 339                         #address-cells = <3>;
 340                         #size-cells = <2>;
 341
 342                         device_type = "pci";
 343                 };
 344         };
 345 };