target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mtk7621-soc";
   7
   8         cpus {
   9                 cpu@0 {
  10                         compatible = "mips,mips1004Kc";
  11                 };
  12
  13                 cpu@1 {
  14                         compatible = "mips,mips1004Kc";
  15                 };
  16         };
  17
  18         cpuintc: cpuintc@0 {
  19                 #address-cells = <0>;
  20                 #interrupt-cells = <1>;
  21                 interrupt-controller;
  22                 compatible = "mti,cpu-interrupt-controller";
  23         };
  24
  25         palmbus@1E000000 {
  26                 compatible = "palmbus";
  27                 reg = <0x1E000000 0x100000>;
  28                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  29
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32
  33                 sysc@0 {
  34                         compatible = "mtk,mt7621-sysc";
  35                         reg = <0x0 0x100>;
  36                 };
  37
  38                 wdt@100 {
  39                         compatible = "mtk,mt7621-wdt";
  40                         reg = <0x100 0x100>;
  41                 };
  42
  43                 gpio@600 {
  44                         #address-cells = <1>;
  45                         #size-cells = <0>;
  46
  47                         compatible = "mtk,mt7621-gpio";
  48                         reg = <0x600 0x100>;
  49
  50                         gpio0: bank@0 {
  51                                 reg = <0>;
  52                                 compatible = "mtk,mt7621-gpio-bank";
  53                                 gpio-controller;
  54                                 #gpio-cells = <2>;
  55                         };
  56
  57                         gpio1: bank@1 {
  58                                 reg = <1>;
  59                                 compatible = "mtk,mt7621-gpio-bank";
  60                                 gpio-controller;
  61                                 #gpio-cells = <2>;
  62                         };
  63
  64                         gpio2: bank@2 {
  65                                 reg = <2>;
  66                                 compatible = "mtk,mt7621-gpio-bank";
  67                                 gpio-controller;
  68                                 #gpio-cells = <2>;
  69                         };
  70                 };
  71
  72                 memc@5000 {
  73                         compatible = "mtk,mt7621-memc";
  74                         reg = <0x300 0x100>;
  75                 };
  76
  77                 cpc@1fbf0000 {
  78                              compatible = "mtk,mt7621-cpc";
  79                              reg = <0x1fbf0000 0x8000>;
  80                 };
  81
  82                 mc@1fbf8000 {
  83                             compatible = "mtk,mt7621-mc";
  84                             reg = <0x1fbf8000 0x8000>;
  85                 };
  86
  87                 uartlite@c00 {
  88                         compatible = "ns16550a";
  89                         reg = <0xc00 0x100>;
  90
  91                         /* FIXME: there should be way to detect this */
  92                         clock-frequency = <50000000>;
  93
  94                         interrupt-parent = <&gic>;
  95                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
  96
  97                         reg-shift = <2>;
  98                         reg-io-width = <4>;
  99                         no-loopback-test;
 100                 };
 101
 102                 spi@b00 {
 103                         status = "okay";
 104
 105                         compatible = "ralink,mt7621-spi";
 106                         reg = <0xb00 0x100>;
 107
 108                         /* FIXME: there should be way to detect this */
 109                         clock-frequency = <50000000>;
 110
 111                         resets = <&rstctrl 18>;
 112                         reset-names = "spi";
 113
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116
 117                         pinctrl-names = "default";
 118                         pinctrl-0 = <&spi_pins>;
 119
 120                         m25p80@0 {
 121                                 #address-cells = <1>;
 122                                 #size-cells = <1>;
 123                                 reg = <0 0>;
 124                                 spi-max-frequency = <10000000>;
 125                                 m25p,chunked-io = <32>;
 126                         };
 127                 };
 128         };
 129
 130         pinctrl {
 131                 compatible = "ralink,rt2880-pinmux";
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&state_default>;
 134
 135                 state_default: pinctrl0 {
 136                 };
 137
 138                 spi_pins: spi {
 139                         spi {
 140                                 ralink,group = "spi";
 141                                 ralink,function = "spi";
 142                         };
 143                 };
 144
 145                 i2c_pins: i2c {
 146                         i2c {
 147                                 ralink,group = "i2c";
 148                                 ralink,function = "i2c";
 149                         };
 150                 };
 151
 152                 uart1_pins: uart1 {
 153                         uart1 {
 154                                 ralink,group = "uart1";
 155                                 ralink,function = "uart1";
 156                         };
 157                 };
 158
 159                 uart2_pins: uart2 {
 160                         uart2 {
 161                                 ralink,group = "uart2";
 162                                 ralink,function = "uart2";
 163                         };
 164                 };
 165
 166                 uart3_pins: uart3 {
 167                         uart3 {
 168                                 ralink,group = "uart3";
 169                                 ralink,function = "uart3";
 170                         };
 171                 };
 172
 173                 rgmii1_pins: rgmii1 {
 174                         rgmii1 {
 175                                 ralink,group = "rgmii1";
 176                                 ralink,function = "rgmii1";
 177                         };
 178                 };
 179
 180                 rgmii2_pins: rgmii2 {
 181                         rgmii2 {
 182                                 ralink,group = "rgmii2";
 183                                 ralink,function = "rgmii2";
 184                         };
 185                 };
 186
 187                 mdio_pins: mdio {
 188                         mdio {
 189                                 ralink,group = "mdio";
 190                                 ralink,function = "mdio";
 191                         };
 192                 };
 193
 194                 pcie_pins: pcie {
 195                         pcie {
 196                                 ralink,group = "pcie";
 197                                 ralink,function = "pcie rst";
 198                         };
 199                 };
 200
 201                 nand_pins: nand {
 202                         spi-nand {
 203                                 ralink,group = "spi";
 204                                 ralink,function = "nand1";
 205                         };
 206
 207                         sdhci-nand {
 208                                 ralink,group = "sdhci";
 209                                 ralink,function = "nand2";
 210                         };
 211                 };
 212
 213                 sdhci_pins: sdhci {
 214                         sdhci {
 215                                 ralink,group = "sdhci";
 216                                 ralink,function = "sdhci";
 217                         };
 218                 };
 219         };
 220
 221         rstctrl: rstctrl {
 222                 compatible = "ralink,rt2880-reset";
 223                 #reset-cells = <1>;
 224         };
 225
 226         sdhci@1E130000 {
 227                 compatible = "ralink,mt7620-sdhci";
 228                 reg = <0x1E130000 4000>;
 229
 230                 interrupt-parent = <&gic>;
 231                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 232         };
 233
 234         xhci@1E1C0000 {
 235                 status = "okay";
 236
 237                 compatible = "xhci-platform";
 238                 reg = <0x1E1C0000 4000>;
 239
 240                 interrupt-parent = <&gic>;
 241                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 242         };
 243
 244         gic: interrupt-controller@1fbc0000 {
 245                 compatible = "mti,gic";
 246                 reg = <0x1fbc0000 0x2000>;
 247
 248                 interrupt-controller;
 249                 #interrupt-cells = <3>;
 250
 251                 mti,reserved-cpu-vectors = <7>;
 252
 253                 timer {
 254                         compatible = "mti,gic-timer";
 255                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 256
 257                         /* FIXME: there should be way to detect this */
 258                         clock-frequency = <880000000>;
 259                 };
 260         };
 261
 262         nand@1e003000 {
 263                 compatible = "mtk,mt7621-nand";
 264                 bank-width = <2>;
 265                 reg = <0x1e003000 0x800
 266                         0x1e003800 0x800>;
 267                 #address-cells = <1>;
 268                 #size-cells = <1>;
 269
 270                 partition@0 {
 271                         label = "uboot";
 272                         reg = <0x00000 0x80000>; /* 64 KB */
 273                 };
 274
 275                 partition@80000 {
 276                         label = "uboot_env";
 277                         reg = <0x80000 0x80000>; /* 64 KB */
 278                 };
 279
 280                 partition@100000 {
 281                         label = "factory";
 282                         reg = <0x100000 0x40000>;
 283                 };
 284
 285                 partition@140000 {
 286                         label = "rootfs";
 287                         reg = <0x140000 0xec0000>;
 288                 };
 289         };
 290
 291         ethernet@1e100000 {
 292                 compatible = "ralink,mt7621-eth";
 293                 reg = <0x1e100000 10000>;
 294
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297
 298                 resets = <&rstctrl 6 &rstctrl 23>;
 299                 reset-names = "fe", "eth";
 300
 301                 interrupt-parent = <&gic>;
 302                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 303
 304                 mdio-bus {
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307
 308                         phy1f: ethernet-phy@1f {
 309                                 reg = <0x1f>;
 310                                 phy-mode = "rgmii";
 311                         };
 312                 };
 313         };
 314
 315         gsw@1e110000 {
 316                 compatible = "ralink,mt7620a-gsw";
 317                 reg = <0x1e110000 8000>;
 318                 interrupt-parent = <&gic>;
 319                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 320         };
 321
 322         pcie@1e140000 {
 323                 compatible = "mediatek,mt7621-pci";
 324                 reg = <0x1e140000 0x100
 325                         0x1e142000 0x100>;
 326
 327                 #address-cells = <3>;
 328                 #size-cells = <2>;
 329
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&pcie_pins>;
 332
 333                 device_type = "pci";
 334
 335                 bus-range = <0 255>;
 336                 ranges = <
 337                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 338                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 339                 >;
 340
 341                 interrupt-parent = <&gic>;
 342                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 343                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 344                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 345
 346                 status = "okay";
 347
 348                 pcie0 {
 349                         reg = <0x0000 0 0 0 0>;
 350
 351                         #address-cells = <3>;
 352                         #size-cells = <2>;
 353
 354                         device_type = "pci";
 355                 };
 356
 357                 pcie1 {
 358                         reg = <0x0800 0 0 0 0>;
 359
 360                         #address-cells = <3>;
 361                         #size-cells = <2>;
 362
 363                         device_type = "pci";
 364                 };
 365
 366                 pcie2 {
 367                         reg = <0x1000 0 0 0 0>;
 368
 369                         #address-cells = <3>;
 370                         #size-cells = <2>;
 371
 372                         device_type = "pci";
 373                 };
 374         };
 375 };