target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mtk7621-soc";
   7
   8         cpus {
   9                 cpu@0 {
  10                         compatible = "mips,mips1004Kc";
  11                 };
  12
  13                 cpu@1 {
  14                         compatible = "mips,mips1004Kc";
  15                 };
  16         };
  17
  18         cpuintc: cpuintc@0 {
  19                 #address-cells = <0>;
  20                 #interrupt-cells = <1>;
  21                 interrupt-controller;
  22                 compatible = "mti,cpu-interrupt-controller";
  23         };
  24
  25         cpuclock: cpuclock@0 {
  26                 #clock-cells = <0>;
  27                 compatible = "fixed-clock";
  28
  29                 /* FIXME: there should be way to detect this */
  30                 clock-frequency = <880000000>;
  31         };
  32
  33         sysclock: sysclock@0 {
  34                 #clock-cells = <0>;
  35                 compatible = "fixed-clock";
  36
  37                 /* FIXME: there should be way to detect this */
  38                 clock-frequency = <50000000>;
  39         };
  40
  41         palmbus@1E000000 {
  42                 compatible = "palmbus";
  43                 reg = <0x1E000000 0x100000>;
  44                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  45
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48
  49                 sysc@0 {
  50                         compatible = "mtk,mt7621-sysc";
  51                         reg = <0x0 0x100>;
  52                 };
  53
  54                 wdt@100 {
  55                         compatible = "mtk,mt7621-wdt";
  56                         reg = <0x100 0x100>;
  57                 };
  58
  59                 gpio@600 {
  60                         #address-cells = <1>;
  61                         #size-cells = <0>;
  62
  63                         compatible = "mtk,mt7621-gpio";
  64                         reg = <0x600 0x100>;
  65
  66                         gpio0: bank@0 {
  67                                 reg = <0>;
  68                                 compatible = "mtk,mt7621-gpio-bank";
  69                                 gpio-controller;
  70                                 #gpio-cells = <2>;
  71                         };
  72
  73                         gpio1: bank@1 {
  74                                 reg = <1>;
  75                                 compatible = "mtk,mt7621-gpio-bank";
  76                                 gpio-controller;
  77                                 #gpio-cells = <2>;
  78                         };
  79
  80                         gpio2: bank@2 {
  81                                 reg = <2>;
  82                                 compatible = "mtk,mt7621-gpio-bank";
  83                                 gpio-controller;
  84                                 #gpio-cells = <2>;
  85                         };
  86                 };
  87
  88                 memc@5000 {
  89                         compatible = "mtk,mt7621-memc";
  90                         reg = <0x300 0x100>;
  91                 };
  92
  93                 cpc@1fbf0000 {
  94                              compatible = "mtk,mt7621-cpc";
  95                              reg = <0x1fbf0000 0x8000>;
  96                 };
  97
  98                 mc@1fbf8000 {
  99                             compatible = "mtk,mt7621-mc";
 100                             reg = <0x1fbf8000 0x8000>;
 101                 };
 102
 103                 uartlite@c00 {
 104                         compatible = "ns16550a";
 105                         reg = <0xc00 0x100>;
 106
 107                         clocks = <&sysclock>;
 108
 109                         interrupt-parent = <&gic>;
 110                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 111
 112                         reg-shift = <2>;
 113                         reg-io-width = <4>;
 114                         no-loopback-test;
 115                 };
 116
 117                 spi@b00 {
 118                         status = "okay";
 119
 120                         compatible = "ralink,mt7621-spi";
 121                         reg = <0xb00 0x100>;
 122
 123                         clocks = <&sysclock>;
 124
 125                         resets = <&rstctrl 18>;
 126                         reset-names = "spi";
 127
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130
 131                         pinctrl-names = "default";
 132                         pinctrl-0 = <&spi_pins>;
 133
 134                         m25p80@0 {
 135                                 #address-cells = <1>;
 136                                 #size-cells = <1>;
 137                                 reg = <0 0>;
 138                                 spi-max-frequency = <10000000>;
 139                                 m25p,chunked-io = <32>;
 140                         };
 141                 };
 142         };
 143
 144         pinctrl {
 145                 compatible = "ralink,rt2880-pinmux";
 146                 pinctrl-names = "default";
 147                 pinctrl-0 = <&state_default>;
 148
 149                 state_default: pinctrl0 {
 150                 };
 151
 152                 spi_pins: spi {
 153                         spi {
 154                                 ralink,group = "spi";
 155                                 ralink,function = "spi";
 156                         };
 157                 };
 158
 159                 i2c_pins: i2c {
 160                         i2c {
 161                                 ralink,group = "i2c";
 162                                 ralink,function = "i2c";
 163                         };
 164                 };
 165
 166                 uart1_pins: uart1 {
 167                         uart1 {
 168                                 ralink,group = "uart1";
 169                                 ralink,function = "uart1";
 170                         };
 171                 };
 172
 173                 uart2_pins: uart2 {
 174                         uart2 {
 175                                 ralink,group = "uart2";
 176                                 ralink,function = "uart2";
 177                         };
 178                 };
 179
 180                 uart3_pins: uart3 {
 181                         uart3 {
 182                                 ralink,group = "uart3";
 183                                 ralink,function = "uart3";
 184                         };
 185                 };
 186
 187                 rgmii1_pins: rgmii1 {
 188                         rgmii1 {
 189                                 ralink,group = "rgmii1";
 190                                 ralink,function = "rgmii1";
 191                         };
 192                 };
 193
 194                 rgmii2_pins: rgmii2 {
 195                         rgmii2 {
 196                                 ralink,group = "rgmii2";
 197                                 ralink,function = "rgmii2";
 198                         };
 199                 };
 200
 201                 mdio_pins: mdio {
 202                         mdio {
 203                                 ralink,group = "mdio";
 204                                 ralink,function = "mdio";
 205                         };
 206                 };
 207
 208                 pcie_pins: pcie {
 209                         pcie {
 210                                 ralink,group = "pcie";
 211                                 ralink,function = "pcie rst";
 212                         };
 213                 };
 214
 215                 nand_pins: nand {
 216                         spi-nand {
 217                                 ralink,group = "spi";
 218                                 ralink,function = "nand1";
 219                         };
 220
 221                         sdhci-nand {
 222                                 ralink,group = "sdhci";
 223                                 ralink,function = "nand2";
 224                         };
 225                 };
 226
 227                 sdhci_pins: sdhci {
 228                         sdhci {
 229                                 ralink,group = "sdhci";
 230                                 ralink,function = "sdhci";
 231                         };
 232                 };
 233         };
 234
 235         rstctrl: rstctrl {
 236                 compatible = "ralink,rt2880-reset";
 237                 #reset-cells = <1>;
 238         };
 239
 240         sdhci@1E130000 {
 241                 compatible = "ralink,mt7620-sdhci";
 242                 reg = <0x1E130000 4000>;
 243
 244                 interrupt-parent = <&gic>;
 245                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 246         };
 247
 248         xhci@1E1C0000 {
 249                 status = "okay";
 250
 251                 compatible = "mediatek,mt8173-xhci";
 252                 reg = <0x1e1c0000 0x1000
 253                        0x1e1d0700 0x0100>;
 254
 255                 clocks = <&sysclock>;
 256                 clock-names = "sys_ck";
 257
 258                 interrupt-parent = <&gic>;
 259                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 260         };
 261
 262         gic: interrupt-controller@1fbc0000 {
 263                 compatible = "mti,gic";
 264                 reg = <0x1fbc0000 0x2000>;
 265
 266                 interrupt-controller;
 267                 #interrupt-cells = <3>;
 268
 269                 mti,reserved-cpu-vectors = <7>;
 270
 271                 timer {
 272                         compatible = "mti,gic-timer";
 273                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 274                         clocks = <&cpuclock>;
 275                 };
 276         };
 277
 278         nand@1e003000 {
 279                 status = "disabled";
 280
 281                 compatible = "mtk,mt7621-nand";
 282                 bank-width = <2>;
 283                 reg = <0x1e003000 0x800
 284                         0x1e003800 0x800>;
 285                 #address-cells = <1>;
 286                 #size-cells = <1>;
 287         };
 288
 289         ethernet@1e100000 {
 290                 compatible = "mediatek,mt7621-eth";
 291                 reg = <0x1e100000 10000>;
 292
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295
 296                 resets = <&rstctrl 6 &rstctrl 23>;
 297                 reset-names = "fe", "eth";
 298
 299                 interrupt-parent = <&gic>;
 300                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 301
 302                 mediatek,switch = <&gsw>;
 303
 304                 mdio-bus {
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307
 308                         phy1f: ethernet-phy@1f {
 309                                 reg = <0x1f>;
 310                                 phy-mode = "rgmii";
 311                         };
 312                 };
 313         };
 314
 315         gsw: gsw@1e110000 {
 316                 compatible = "mediatek,mt7621-gsw";
 317                 reg = <0x1e110000 8000>;
 318                 interrupt-parent = <&gic>;
 319                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 320         };
 321
 322         pcie@1e140000 {
 323                 compatible = "mediatek,mt7621-pci";
 324                 reg = <0x1e140000 0x100
 325                         0x1e142000 0x100>;
 326
 327                 #address-cells = <3>;
 328                 #size-cells = <2>;
 329
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&pcie_pins>;
 332
 333                 device_type = "pci";
 334
 335                 bus-range = <0 255>;
 336                 ranges = <
 337                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 338                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 339                 >;
 340
 341                 interrupt-parent = <&gic>;
 342                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 343                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 344                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 345
 346                 status = "okay";
 347
 348                 pcie0 {
 349                         reg = <0x0000 0 0 0 0>;
 350
 351                         #address-cells = <3>;
 352                         #size-cells = <2>;
 353
 354                         device_type = "pci";
 355                 };
 356
 357                 pcie1 {
 358                         reg = <0x0800 0 0 0 0>;
 359
 360                         #address-cells = <3>;
 361                         #size-cells = <2>;
 362
 363                         device_type = "pci";
 364                 };
 365
 366                 pcie2 {
 367                         reg = <0x1000 0 0 0 0>;
 368
 369                         #address-cells = <3>;
 370                         #size-cells = <2>;
 371
 372                         device_type = "pci";
 373                 };
 374         };
 375 };