target/linux/octeon/patches/002-register_defs_pci.patch

   1 Here we add the register definitions for the processor blocks used by
   2 the following PCI support patch.
   3
   4 Signed-off-by: David Daney <ddaney@caviumnetworks.com>
   5 ---
   6  arch/mips/include/asm/octeon/cvmx-npei-defs.h    | 2560 ++++++++++++++++++++++
   7  arch/mips/include/asm/octeon/cvmx-npi-defs.h     | 1735 +++++++++++++++
   8  arch/mips/include/asm/octeon/cvmx-pci-defs.h     | 1645 ++++++++++++++
   9  arch/mips/include/asm/octeon/cvmx-pcieep-defs.h  | 1365 ++++++++++++
  10  arch/mips/include/asm/octeon/cvmx-pciercx-defs.h | 1397 ++++++++++++
  11  arch/mips/include/asm/octeon/cvmx-pescx-defs.h   |  410 ++++
  12  arch/mips/include/asm/octeon/cvmx-pexp-defs.h    |  229 ++
  13  7 files changed, 9341 insertions(+), 0 deletions(-)
  14  create mode 100644 arch/mips/include/asm/octeon/cvmx-npei-defs.h
  15  create mode 100644 arch/mips/include/asm/octeon/cvmx-npi-defs.h
  16  create mode 100644 arch/mips/include/asm/octeon/cvmx-pci-defs.h
  17  create mode 100644 arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
  18  create mode 100644 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
  19  create mode 100644 arch/mips/include/asm/octeon/cvmx-pescx-defs.h
  20  create mode 100644 arch/mips/include/asm/octeon/cvmx-pexp-defs.h
  21
  22 --- /dev/null
  23 +++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
  24 @@ -0,0 +1,2560 @@
  25 +/***********************license start***************
  26 + * Author: Cavium Networks
  27 + *
  28 + * Contact: support@caviumnetworks.com
  29 + * This file is part of the OCTEON SDK
  30 + *
  31 + * Copyright (c) 2003-2008 Cavium Networks
  32 + *
  33 + * This file is free software; you can redistribute it and/or modify
  34 + * it under the terms of the GNU General Public License, Version 2, as
  35 + * published by the Free Software Foundation.
  36 + *
  37 + * This file is distributed in the hope that it will be useful, but
  38 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  39 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  40 + * NONINFRINGEMENT.  See the GNU General Public License for more
  41 + * details.
  42 + *
  43 + * You should have received a copy of the GNU General Public License
  44 + * along with this file; if not, write to the Free Software
  45 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  46 + * or visit http://www.gnu.org/licenses/.
  47 + *
  48 + * This file may also be available under a different license from Cavium.
  49 + * Contact Cavium Networks for more information
  50 + ***********************license end**************************************/
  51 +
  52 +#ifndef __CVMX_NPEI_DEFS_H__
  53 +#define __CVMX_NPEI_DEFS_H__
  54 +
  55 +#define CVMX_NPEI_BAR1_INDEXX(offset) \
  56 +        (0x0000000000000000ull + (((offset) & 31) * 16))
  57 +#define CVMX_NPEI_BIST_STATUS \
  58 +        (0x0000000000000580ull)
  59 +#define CVMX_NPEI_BIST_STATUS2 \
  60 +        (0x0000000000000680ull)
  61 +#define CVMX_NPEI_CTL_PORT0 \
  62 +        (0x0000000000000250ull)
  63 +#define CVMX_NPEI_CTL_PORT1 \
  64 +        (0x0000000000000260ull)
  65 +#define CVMX_NPEI_CTL_STATUS \
  66 +        (0x0000000000000570ull)
  67 +#define CVMX_NPEI_CTL_STATUS2 \
  68 +        (0x0000000000003C00ull)
  69 +#define CVMX_NPEI_DATA_OUT_CNT \
  70 +        (0x00000000000005F0ull)
  71 +#define CVMX_NPEI_DBG_DATA \
  72 +        (0x0000000000000510ull)
  73 +#define CVMX_NPEI_DBG_SELECT \
  74 +        (0x0000000000000500ull)
  75 +#define CVMX_NPEI_DMA0_INT_LEVEL \
  76 +        (0x00000000000005C0ull)
  77 +#define CVMX_NPEI_DMA1_INT_LEVEL \
  78 +        (0x00000000000005D0ull)
  79 +#define CVMX_NPEI_DMAX_COUNTS(offset) \
  80 +        (0x0000000000000450ull + (((offset) & 7) * 16))
  81 +#define CVMX_NPEI_DMAX_DBELL(offset) \
  82 +        (0x00000000000003B0ull + (((offset) & 7) * 16))
  83 +#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
  84 +        (0x0000000000000400ull + (((offset) & 7) * 16))
  85 +#define CVMX_NPEI_DMAX_NADDR(offset) \
  86 +        (0x00000000000004A0ull + (((offset) & 7) * 16))
  87 +#define CVMX_NPEI_DMA_CNTS \
  88 +        (0x00000000000005E0ull)
  89 +#define CVMX_NPEI_DMA_CONTROL \
  90 +        (0x00000000000003A0ull)
  91 +#define CVMX_NPEI_INT_A_ENB \
  92 +        (0x0000000000000560ull)
  93 +#define CVMX_NPEI_INT_A_ENB2 \
  94 +        (0x0000000000003CE0ull)
  95 +#define CVMX_NPEI_INT_A_SUM \
  96 +        (0x0000000000000550ull)
  97 +#define CVMX_NPEI_INT_ENB \
  98 +        (0x0000000000000540ull)
  99 +#define CVMX_NPEI_INT_ENB2 \
 100 +        (0x0000000000003CD0ull)
 101 +#define CVMX_NPEI_INT_INFO \
 102 +        (0x0000000000000590ull)
 103 +#define CVMX_NPEI_INT_SUM \
 104 +        (0x0000000000000530ull)
 105 +#define CVMX_NPEI_INT_SUM2 \
 106 +        (0x0000000000003CC0ull)
 107 +#define CVMX_NPEI_LAST_WIN_RDATA0 \
 108 +        (0x0000000000000600ull)
 109 +#define CVMX_NPEI_LAST_WIN_RDATA1 \
 110 +        (0x0000000000000610ull)
 111 +#define CVMX_NPEI_MEM_ACCESS_CTL \
 112 +        (0x00000000000004F0ull)
 113 +#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
 114 +        (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
 115 +#define CVMX_NPEI_MSI_ENB0 \
 116 +        (0x0000000000003C50ull)
 117 +#define CVMX_NPEI_MSI_ENB1 \
 118 +        (0x0000000000003C60ull)
 119 +#define CVMX_NPEI_MSI_ENB2 \
 120 +        (0x0000000000003C70ull)
 121 +#define CVMX_NPEI_MSI_ENB3 \
 122 +        (0x0000000000003C80ull)
 123 +#define CVMX_NPEI_MSI_RCV0 \
 124 +        (0x0000000000003C10ull)
 125 +#define CVMX_NPEI_MSI_RCV1 \
 126 +        (0x0000000000003C20ull)
 127 +#define CVMX_NPEI_MSI_RCV2 \
 128 +        (0x0000000000003C30ull)
 129 +#define CVMX_NPEI_MSI_RCV3 \
 130 +        (0x0000000000003C40ull)
 131 +#define CVMX_NPEI_MSI_RD_MAP \
 132 +        (0x0000000000003CA0ull)
 133 +#define CVMX_NPEI_MSI_W1C_ENB0 \
 134 +        (0x0000000000003CF0ull)
 135 +#define CVMX_NPEI_MSI_W1C_ENB1 \
 136 +        (0x0000000000003D00ull)
 137 +#define CVMX_NPEI_MSI_W1C_ENB2 \
 138 +        (0x0000000000003D10ull)
 139 +#define CVMX_NPEI_MSI_W1C_ENB3 \
 140 +        (0x0000000000003D20ull)
 141 +#define CVMX_NPEI_MSI_W1S_ENB0 \
 142 +        (0x0000000000003D30ull)
 143 +#define CVMX_NPEI_MSI_W1S_ENB1 \
 144 +        (0x0000000000003D40ull)
 145 +#define CVMX_NPEI_MSI_W1S_ENB2 \
 146 +        (0x0000000000003D50ull)
 147 +#define CVMX_NPEI_MSI_W1S_ENB3 \
 148 +        (0x0000000000003D60ull)
 149 +#define CVMX_NPEI_MSI_WR_MAP \
 150 +        (0x0000000000003C90ull)
 151 +#define CVMX_NPEI_PCIE_CREDIT_CNT \
 152 +        (0x0000000000003D70ull)
 153 +#define CVMX_NPEI_PCIE_MSI_RCV \
 154 +        (0x0000000000003CB0ull)
 155 +#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
 156 +        (0x0000000000000650ull)
 157 +#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
 158 +        (0x0000000000000660ull)
 159 +#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
 160 +        (0x0000000000000670ull)
 161 +#define CVMX_NPEI_PKTX_CNTS(offset) \
 162 +        (0x0000000000002400ull + (((offset) & 31) * 16))
 163 +#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
 164 +        (0x0000000000002800ull + (((offset) & 31) * 16))
 165 +#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
 166 +        (0x0000000000002C00ull + (((offset) & 31) * 16))
 167 +#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
 168 +        (0x0000000000003000ull + (((offset) & 31) * 16))
 169 +#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
 170 +        (0x0000000000003400ull + (((offset) & 31) * 16))
 171 +#define CVMX_NPEI_PKTX_IN_BP(offset) \
 172 +        (0x0000000000003800ull + (((offset) & 31) * 16))
 173 +#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
 174 +        (0x0000000000001400ull + (((offset) & 31) * 16))
 175 +#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
 176 +        (0x0000000000001800ull + (((offset) & 31) * 16))
 177 +#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
 178 +        (0x0000000000001C00ull + (((offset) & 31) * 16))
 179 +#define CVMX_NPEI_PKT_CNT_INT \
 180 +        (0x0000000000001110ull)
 181 +#define CVMX_NPEI_PKT_CNT_INT_ENB \
 182 +        (0x0000000000001130ull)
 183 +#define CVMX_NPEI_PKT_DATA_OUT_ES \
 184 +        (0x00000000000010B0ull)
 185 +#define CVMX_NPEI_PKT_DATA_OUT_NS \
 186 +        (0x00000000000010A0ull)
 187 +#define CVMX_NPEI_PKT_DATA_OUT_ROR \
 188 +        (0x0000000000001090ull)
 189 +#define CVMX_NPEI_PKT_DPADDR \
 190 +        (0x0000000000001080ull)
 191 +#define CVMX_NPEI_PKT_INPUT_CONTROL \
 192 +        (0x0000000000001150ull)
 193 +#define CVMX_NPEI_PKT_INSTR_ENB \
 194 +        (0x0000000000001000ull)
 195 +#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
 196 +        (0x0000000000001190ull)
 197 +#define CVMX_NPEI_PKT_INSTR_SIZE \
 198 +        (0x0000000000001020ull)
 199 +#define CVMX_NPEI_PKT_INT_LEVELS \
 200 +        (0x0000000000001100ull)
 201 +#define CVMX_NPEI_PKT_IN_BP \
 202 +        (0x00000000000006B0ull)
 203 +#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
 204 +        (0x0000000000002000ull + (((offset) & 31) * 16))
 205 +#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
 206 +        (0x00000000000006A0ull)
 207 +#define CVMX_NPEI_PKT_IN_PCIE_PORT \
 208 +        (0x00000000000011A0ull)
 209 +#define CVMX_NPEI_PKT_IPTR \
 210 +        (0x0000000000001070ull)
 211 +#define CVMX_NPEI_PKT_OUTPUT_WMARK \
 212 +        (0x0000000000001160ull)
 213 +#define CVMX_NPEI_PKT_OUT_BMODE \
 214 +        (0x00000000000010D0ull)
 215 +#define CVMX_NPEI_PKT_OUT_ENB \
 216 +        (0x0000000000001010ull)
 217 +#define CVMX_NPEI_PKT_PCIE_PORT \
 218 +        (0x00000000000010E0ull)
 219 +#define CVMX_NPEI_PKT_PORT_IN_RST \
 220 +        (0x0000000000000690ull)
 221 +#define CVMX_NPEI_PKT_SLIST_ES \
 222 +        (0x0000000000001050ull)
 223 +#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
 224 +        (0x0000000000001180ull)
 225 +#define CVMX_NPEI_PKT_SLIST_NS \
 226 +        (0x0000000000001040ull)
 227 +#define CVMX_NPEI_PKT_SLIST_ROR \
 228 +        (0x0000000000001030ull)
 229 +#define CVMX_NPEI_PKT_TIME_INT \
 230 +        (0x0000000000001120ull)
 231 +#define CVMX_NPEI_PKT_TIME_INT_ENB \
 232 +        (0x0000000000001140ull)
 233 +#define CVMX_NPEI_RSL_INT_BLOCKS \
 234 +        (0x0000000000000520ull)
 235 +#define CVMX_NPEI_SCRATCH_1 \
 236 +        (0x0000000000000270ull)
 237 +#define CVMX_NPEI_STATE1 \
 238 +        (0x0000000000000620ull)
 239 +#define CVMX_NPEI_STATE2 \
 240 +        (0x0000000000000630ull)
 241 +#define CVMX_NPEI_STATE3 \
 242 +        (0x0000000000000640ull)
 243 +#define CVMX_NPEI_WINDOW_CTL \
 244 +        (0x0000000000000380ull)
 245 +#define CVMX_NPEI_WIN_RD_ADDR \
 246 +        (0x0000000000000210ull)
 247 +#define CVMX_NPEI_WIN_RD_DATA \
 248 +        (0x0000000000000240ull)
 249 +#define CVMX_NPEI_WIN_WR_ADDR \
 250 +        (0x0000000000000200ull)
 251 +#define CVMX_NPEI_WIN_WR_DATA \
 252 +        (0x0000000000000220ull)
 253 +#define CVMX_NPEI_WIN_WR_MASK \
 254 +        (0x0000000000000230ull)
 255 +
 256 +union cvmx_npei_bar1_indexx {
 257 +       uint32_t u32;
 258 +       struct cvmx_npei_bar1_indexx_s {
 259 +               uint32_t reserved_18_31:14;
 260 +               uint32_t addr_idx:14;
 261 +               uint32_t ca:1;
 262 +               uint32_t end_swp:2;
 263 +               uint32_t addr_v:1;
 264 +       } s;
 265 +       struct cvmx_npei_bar1_indexx_s cn52xx;
 266 +       struct cvmx_npei_bar1_indexx_s cn52xxp1;
 267 +       struct cvmx_npei_bar1_indexx_s cn56xx;
 268 +       struct cvmx_npei_bar1_indexx_s cn56xxp1;
 269 +};
 270 +
 271 +union cvmx_npei_bist_status {
 272 +       uint64_t u64;
 273 +       struct cvmx_npei_bist_status_s {
 274 +               uint64_t pkt_rdf:1;
 275 +               uint64_t pkt_pmem:1;
 276 +               uint64_t pkt_p1:1;
 277 +               uint64_t reserved_60_60:1;
 278 +               uint64_t pcr_gim:1;
 279 +               uint64_t pkt_pif:1;
 280 +               uint64_t pcsr_int:1;
 281 +               uint64_t pcsr_im:1;
 282 +               uint64_t pcsr_cnt:1;
 283 +               uint64_t pcsr_id:1;
 284 +               uint64_t pcsr_sl:1;
 285 +               uint64_t reserved_50_52:3;
 286 +               uint64_t pkt_ind:1;
 287 +               uint64_t pkt_slm:1;
 288 +               uint64_t reserved_36_47:12;
 289 +               uint64_t d0_pst:1;
 290 +               uint64_t d1_pst:1;
 291 +               uint64_t d2_pst:1;
 292 +               uint64_t d3_pst:1;
 293 +               uint64_t reserved_31_31:1;
 294 +               uint64_t n2p0_c:1;
 295 +               uint64_t n2p0_o:1;
 296 +               uint64_t n2p1_c:1;
 297 +               uint64_t n2p1_o:1;
 298 +               uint64_t cpl_p0:1;
 299 +               uint64_t cpl_p1:1;
 300 +               uint64_t p2n1_po:1;
 301 +               uint64_t p2n1_no:1;
 302 +               uint64_t p2n1_co:1;
 303 +               uint64_t p2n0_po:1;
 304 +               uint64_t p2n0_no:1;
 305 +               uint64_t p2n0_co:1;
 306 +               uint64_t p2n0_c0:1;
 307 +               uint64_t p2n0_c1:1;
 308 +               uint64_t p2n0_n:1;
 309 +               uint64_t p2n0_p0:1;
 310 +               uint64_t p2n0_p1:1;
 311 +               uint64_t p2n1_c0:1;
 312 +               uint64_t p2n1_c1:1;
 313 +               uint64_t p2n1_n:1;
 314 +               uint64_t p2n1_p0:1;
 315 +               uint64_t p2n1_p1:1;
 316 +               uint64_t csm0:1;
 317 +               uint64_t csm1:1;
 318 +               uint64_t dif0:1;
 319 +               uint64_t dif1:1;
 320 +               uint64_t dif2:1;
 321 +               uint64_t dif3:1;
 322 +               uint64_t reserved_2_2:1;
 323 +               uint64_t msi:1;
 324 +               uint64_t ncb_cmd:1;
 325 +       } s;
 326 +       struct cvmx_npei_bist_status_cn52xx {
 327 +               uint64_t pkt_rdf:1;
 328 +               uint64_t pkt_pmem:1;
 329 +               uint64_t pkt_p1:1;
 330 +               uint64_t reserved_60_60:1;
 331 +               uint64_t pcr_gim:1;
 332 +               uint64_t pkt_pif:1;
 333 +               uint64_t pcsr_int:1;
 334 +               uint64_t pcsr_im:1;
 335 +               uint64_t pcsr_cnt:1;
 336 +               uint64_t pcsr_id:1;
 337 +               uint64_t pcsr_sl:1;
 338 +               uint64_t pkt_imem:1;
 339 +               uint64_t pkt_pfm:1;
 340 +               uint64_t pkt_pof:1;
 341 +               uint64_t reserved_48_49:2;
 342 +               uint64_t pkt_pop0:1;
 343 +               uint64_t pkt_pop1:1;
 344 +               uint64_t d0_mem:1;
 345 +               uint64_t d1_mem:1;
 346 +               uint64_t d2_mem:1;
 347 +               uint64_t d3_mem:1;
 348 +               uint64_t d4_mem:1;
 349 +               uint64_t ds_mem:1;
 350 +               uint64_t reserved_36_39:4;
 351 +               uint64_t d0_pst:1;
 352 +               uint64_t d1_pst:1;
 353 +               uint64_t d2_pst:1;
 354 +               uint64_t d3_pst:1;
 355 +               uint64_t d4_pst:1;
 356 +               uint64_t n2p0_c:1;
 357 +               uint64_t n2p0_o:1;
 358 +               uint64_t n2p1_c:1;
 359 +               uint64_t n2p1_o:1;
 360 +               uint64_t cpl_p0:1;
 361 +               uint64_t cpl_p1:1;
 362 +               uint64_t p2n1_po:1;
 363 +               uint64_t p2n1_no:1;
 364 +               uint64_t p2n1_co:1;
 365 +               uint64_t p2n0_po:1;
 366 +               uint64_t p2n0_no:1;
 367 +               uint64_t p2n0_co:1;
 368 +               uint64_t p2n0_c0:1;
 369 +               uint64_t p2n0_c1:1;
 370 +               uint64_t p2n0_n:1;
 371 +               uint64_t p2n0_p0:1;
 372 +               uint64_t p2n0_p1:1;
 373 +               uint64_t p2n1_c0:1;
 374 +               uint64_t p2n1_c1:1;
 375 +               uint64_t p2n1_n:1;
 376 +               uint64_t p2n1_p0:1;
 377 +               uint64_t p2n1_p1:1;
 378 +               uint64_t csm0:1;
 379 +               uint64_t csm1:1;
 380 +               uint64_t dif0:1;
 381 +               uint64_t dif1:1;
 382 +               uint64_t dif2:1;
 383 +               uint64_t dif3:1;
 384 +               uint64_t dif4:1;
 385 +               uint64_t msi:1;
 386 +               uint64_t ncb_cmd:1;
 387 +       } cn52xx;
 388 +       struct cvmx_npei_bist_status_cn52xxp1 {
 389 +               uint64_t reserved_46_63:18;
 390 +               uint64_t d0_mem0:1;
 391 +               uint64_t d1_mem1:1;
 392 +               uint64_t d2_mem2:1;
 393 +               uint64_t d3_mem3:1;
 394 +               uint64_t dr0_mem:1;
 395 +               uint64_t d0_mem:1;
 396 +               uint64_t d1_mem:1;
 397 +               uint64_t d2_mem:1;
 398 +               uint64_t d3_mem:1;
 399 +               uint64_t dr1_mem:1;
 400 +               uint64_t d0_pst:1;
 401 +               uint64_t d1_pst:1;
 402 +               uint64_t d2_pst:1;
 403 +               uint64_t d3_pst:1;
 404 +               uint64_t dr2_mem:1;
 405 +               uint64_t n2p0_c:1;
 406 +               uint64_t n2p0_o:1;
 407 +               uint64_t n2p1_c:1;
 408 +               uint64_t n2p1_o:1;
 409 +               uint64_t cpl_p0:1;
 410 +               uint64_t cpl_p1:1;
 411 +               uint64_t p2n1_po:1;
 412 +               uint64_t p2n1_no:1;
 413 +               uint64_t p2n1_co:1;
 414 +               uint64_t p2n0_po:1;
 415 +               uint64_t p2n0_no:1;
 416 +               uint64_t p2n0_co:1;
 417 +               uint64_t p2n0_c0:1;
 418 +               uint64_t p2n0_c1:1;
 419 +               uint64_t p2n0_n:1;
 420 +               uint64_t p2n0_p0:1;
 421 +               uint64_t p2n0_p1:1;
 422 +               uint64_t p2n1_c0:1;
 423 +               uint64_t p2n1_c1:1;
 424 +               uint64_t p2n1_n:1;
 425 +               uint64_t p2n1_p0:1;
 426 +               uint64_t p2n1_p1:1;
 427 +               uint64_t csm0:1;
 428 +               uint64_t csm1:1;
 429 +               uint64_t dif0:1;
 430 +               uint64_t dif1:1;
 431 +               uint64_t dif2:1;
 432 +               uint64_t dif3:1;
 433 +               uint64_t dr3_mem:1;
 434 +               uint64_t msi:1;
 435 +               uint64_t ncb_cmd:1;
 436 +       } cn52xxp1;
 437 +       struct cvmx_npei_bist_status_cn56xx {
 438 +               uint64_t pkt_rdf:1;
 439 +               uint64_t reserved_60_62:3;
 440 +               uint64_t pcr_gim:1;
 441 +               uint64_t pkt_pif:1;
 442 +               uint64_t pcsr_int:1;
 443 +               uint64_t pcsr_im:1;
 444 +               uint64_t pcsr_cnt:1;
 445 +               uint64_t pcsr_id:1;
 446 +               uint64_t pcsr_sl:1;
 447 +               uint64_t pkt_imem:1;
 448 +               uint64_t pkt_pfm:1;
 449 +               uint64_t pkt_pof:1;
 450 +               uint64_t reserved_48_49:2;
 451 +               uint64_t pkt_pop0:1;
 452 +               uint64_t pkt_pop1:1;
 453 +               uint64_t d0_mem:1;
 454 +               uint64_t d1_mem:1;
 455 +               uint64_t d2_mem:1;
 456 +               uint64_t d3_mem:1;
 457 +               uint64_t d4_mem:1;
 458 +               uint64_t ds_mem:1;
 459 +               uint64_t reserved_36_39:4;
 460 +               uint64_t d0_pst:1;
 461 +               uint64_t d1_pst:1;
 462 +               uint64_t d2_pst:1;
 463 +               uint64_t d3_pst:1;
 464 +               uint64_t d4_pst:1;
 465 +               uint64_t n2p0_c:1;
 466 +               uint64_t n2p0_o:1;
 467 +               uint64_t n2p1_c:1;
 468 +               uint64_t n2p1_o:1;
 469 +               uint64_t cpl_p0:1;
 470 +               uint64_t cpl_p1:1;
 471 +               uint64_t p2n1_po:1;
 472 +               uint64_t p2n1_no:1;
 473 +               uint64_t p2n1_co:1;
 474 +               uint64_t p2n0_po:1;
 475 +               uint64_t p2n0_no:1;
 476 +               uint64_t p2n0_co:1;
 477 +               uint64_t p2n0_c0:1;
 478 +               uint64_t p2n0_c1:1;
 479 +               uint64_t p2n0_n:1;
 480 +               uint64_t p2n0_p0:1;
 481 +               uint64_t p2n0_p1:1;
 482 +               uint64_t p2n1_c0:1;
 483 +               uint64_t p2n1_c1:1;
 484 +               uint64_t p2n1_n:1;
 485 +               uint64_t p2n1_p0:1;
 486 +               uint64_t p2n1_p1:1;
 487 +               uint64_t csm0:1;
 488 +               uint64_t csm1:1;
 489 +               uint64_t dif0:1;
 490 +               uint64_t dif1:1;
 491 +               uint64_t dif2:1;
 492 +               uint64_t dif3:1;
 493 +               uint64_t dif4:1;
 494 +               uint64_t msi:1;
 495 +               uint64_t ncb_cmd:1;
 496 +       } cn56xx;
 497 +       struct cvmx_npei_bist_status_cn56xxp1 {
 498 +               uint64_t reserved_58_63:6;
 499 +               uint64_t pcsr_int:1;
 500 +               uint64_t pcsr_im:1;
 501 +               uint64_t pcsr_cnt:1;
 502 +               uint64_t pcsr_id:1;
 503 +               uint64_t pcsr_sl:1;
 504 +               uint64_t pkt_pout:1;
 505 +               uint64_t pkt_imem:1;
 506 +               uint64_t pkt_cntm:1;
 507 +               uint64_t pkt_ind:1;
 508 +               uint64_t pkt_slm:1;
 509 +               uint64_t pkt_odf:1;
 510 +               uint64_t pkt_oif:1;
 511 +               uint64_t pkt_out:1;
 512 +               uint64_t pkt_i0:1;
 513 +               uint64_t pkt_i1:1;
 514 +               uint64_t pkt_s0:1;
 515 +               uint64_t pkt_s1:1;
 516 +               uint64_t d0_mem:1;
 517 +               uint64_t d1_mem:1;
 518 +               uint64_t d2_mem:1;
 519 +               uint64_t d3_mem:1;
 520 +               uint64_t d4_mem:1;
 521 +               uint64_t d0_pst:1;
 522 +               uint64_t d1_pst:1;
 523 +               uint64_t d2_pst:1;
 524 +               uint64_t d3_pst:1;
 525 +               uint64_t d4_pst:1;
 526 +               uint64_t n2p0_c:1;
 527 +               uint64_t n2p0_o:1;
 528 +               uint64_t n2p1_c:1;
 529 +               uint64_t n2p1_o:1;
 530 +               uint64_t cpl_p0:1;
 531 +               uint64_t cpl_p1:1;
 532 +               uint64_t p2n1_po:1;
 533 +               uint64_t p2n1_no:1;
 534 +               uint64_t p2n1_co:1;
 535 +               uint64_t p2n0_po:1;
 536 +               uint64_t p2n0_no:1;
 537 +               uint64_t p2n0_co:1;
 538 +               uint64_t p2n0_c0:1;
 539 +               uint64_t p2n0_c1:1;
 540 +               uint64_t p2n0_n:1;
 541 +               uint64_t p2n0_p0:1;
 542 +               uint64_t p2n0_p1:1;
 543 +               uint64_t p2n1_c0:1;
 544 +               uint64_t p2n1_c1:1;
 545 +               uint64_t p2n1_n:1;
 546 +               uint64_t p2n1_p0:1;
 547 +               uint64_t p2n1_p1:1;
 548 +               uint64_t csm0:1;
 549 +               uint64_t csm1:1;
 550 +               uint64_t dif0:1;
 551 +               uint64_t dif1:1;
 552 +               uint64_t dif2:1;
 553 +               uint64_t dif3:1;
 554 +               uint64_t dif4:1;
 555 +               uint64_t msi:1;
 556 +               uint64_t ncb_cmd:1;
 557 +       } cn56xxp1;
 558 +};
 559 +
 560 +union cvmx_npei_bist_status2 {
 561 +       uint64_t u64;
 562 +       struct cvmx_npei_bist_status2_s {
 563 +               uint64_t reserved_5_63:59;
 564 +               uint64_t psc_p0:1;
 565 +               uint64_t psc_p1:1;
 566 +               uint64_t pkt_gd:1;
 567 +               uint64_t pkt_gl:1;
 568 +               uint64_t pkt_blk:1;
 569 +       } s;
 570 +       struct cvmx_npei_bist_status2_s cn52xx;
 571 +       struct cvmx_npei_bist_status2_s cn56xx;
 572 +};
 573 +
 574 +union cvmx_npei_ctl_port0 {
 575 +       uint64_t u64;
 576 +       struct cvmx_npei_ctl_port0_s {
 577 +               uint64_t reserved_21_63:43;
 578 +               uint64_t waitl_com:1;
 579 +               uint64_t intd:1;
 580 +               uint64_t intc:1;
 581 +               uint64_t intb:1;
 582 +               uint64_t inta:1;
 583 +               uint64_t intd_map:2;
 584 +               uint64_t intc_map:2;
 585 +               uint64_t intb_map:2;
 586 +               uint64_t inta_map:2;
 587 +               uint64_t ctlp_ro:1;
 588 +               uint64_t reserved_6_6:1;
 589 +               uint64_t ptlp_ro:1;
 590 +               uint64_t bar2_enb:1;
 591 +               uint64_t bar2_esx:2;
 592 +               uint64_t bar2_cax:1;
 593 +               uint64_t wait_com:1;
 594 +       } s;
 595 +       struct cvmx_npei_ctl_port0_s cn52xx;
 596 +       struct cvmx_npei_ctl_port0_s cn52xxp1;
 597 +       struct cvmx_npei_ctl_port0_s cn56xx;
 598 +       struct cvmx_npei_ctl_port0_s cn56xxp1;
 599 +};
 600 +
 601 +union cvmx_npei_ctl_port1 {
 602 +       uint64_t u64;
 603 +       struct cvmx_npei_ctl_port1_s {
 604 +               uint64_t reserved_21_63:43;
 605 +               uint64_t waitl_com:1;
 606 +               uint64_t intd:1;
 607 +               uint64_t intc:1;
 608 +               uint64_t intb:1;
 609 +               uint64_t inta:1;
 610 +               uint64_t intd_map:2;
 611 +               uint64_t intc_map:2;
 612 +               uint64_t intb_map:2;
 613 +               uint64_t inta_map:2;
 614 +               uint64_t ctlp_ro:1;
 615 +               uint64_t reserved_6_6:1;
 616 +               uint64_t ptlp_ro:1;
 617 +               uint64_t bar2_enb:1;
 618 +               uint64_t bar2_esx:2;
 619 +               uint64_t bar2_cax:1;
 620 +               uint64_t wait_com:1;
 621 +       } s;
 622 +       struct cvmx_npei_ctl_port1_s cn52xx;
 623 +       struct cvmx_npei_ctl_port1_s cn52xxp1;
 624 +       struct cvmx_npei_ctl_port1_s cn56xx;
 625 +       struct cvmx_npei_ctl_port1_s cn56xxp1;
 626 +};
 627 +
 628 +union cvmx_npei_ctl_status {
 629 +       uint64_t u64;
 630 +       struct cvmx_npei_ctl_status_s {
 631 +               uint64_t reserved_44_63:20;
 632 +               uint64_t p1_ntags:6;
 633 +               uint64_t p0_ntags:6;
 634 +               uint64_t cfg_rtry:16;
 635 +               uint64_t ring_en:1;
 636 +               uint64_t lnk_rst:1;
 637 +               uint64_t arb:1;
 638 +               uint64_t pkt_bp:4;
 639 +               uint64_t host_mode:1;
 640 +               uint64_t chip_rev:8;
 641 +       } s;
 642 +       struct cvmx_npei_ctl_status_s cn52xx;
 643 +       struct cvmx_npei_ctl_status_cn52xxp1 {
 644 +               uint64_t reserved_44_63:20;
 645 +               uint64_t p1_ntags:6;
 646 +               uint64_t p0_ntags:6;
 647 +               uint64_t cfg_rtry:16;
 648 +               uint64_t reserved_15_15:1;
 649 +               uint64_t lnk_rst:1;
 650 +               uint64_t arb:1;
 651 +               uint64_t reserved_9_12:4;
 652 +               uint64_t host_mode:1;
 653 +               uint64_t chip_rev:8;
 654 +       } cn52xxp1;
 655 +       struct cvmx_npei_ctl_status_s cn56xx;
 656 +       struct cvmx_npei_ctl_status_cn56xxp1 {
 657 +               uint64_t reserved_16_63:48;
 658 +               uint64_t ring_en:1;
 659 +               uint64_t lnk_rst:1;
 660 +               uint64_t arb:1;
 661 +               uint64_t pkt_bp:4;
 662 +               uint64_t host_mode:1;
 663 +               uint64_t chip_rev:8;
 664 +       } cn56xxp1;
 665 +};
 666 +
 667 +union cvmx_npei_ctl_status2 {
 668 +       uint64_t u64;
 669 +       struct cvmx_npei_ctl_status2_s {
 670 +               uint64_t reserved_16_63:48;
 671 +               uint64_t mps:1;
 672 +               uint64_t mrrs:3;
 673 +               uint64_t c1_w_flt:1;
 674 +               uint64_t c0_w_flt:1;
 675 +               uint64_t c1_b1_s:3;
 676 +               uint64_t c0_b1_s:3;
 677 +               uint64_t c1_wi_d:1;
 678 +               uint64_t c1_b0_d:1;
 679 +               uint64_t c0_wi_d:1;
 680 +               uint64_t c0_b0_d:1;
 681 +       } s;
 682 +       struct cvmx_npei_ctl_status2_s cn52xx;
 683 +       struct cvmx_npei_ctl_status2_s cn52xxp1;
 684 +       struct cvmx_npei_ctl_status2_s cn56xx;
 685 +       struct cvmx_npei_ctl_status2_s cn56xxp1;
 686 +};
 687 +
 688 +union cvmx_npei_data_out_cnt {
 689 +       uint64_t u64;
 690 +       struct cvmx_npei_data_out_cnt_s {
 691 +               uint64_t reserved_44_63:20;
 692 +               uint64_t p1_ucnt:16;
 693 +               uint64_t p1_fcnt:6;
 694 +               uint64_t p0_ucnt:16;
 695 +               uint64_t p0_fcnt:6;
 696 +       } s;
 697 +       struct cvmx_npei_data_out_cnt_s cn52xx;
 698 +       struct cvmx_npei_data_out_cnt_s cn52xxp1;
 699 +       struct cvmx_npei_data_out_cnt_s cn56xx;
 700 +       struct cvmx_npei_data_out_cnt_s cn56xxp1;
 701 +};
 702 +
 703 +union cvmx_npei_dbg_data {
 704 +       uint64_t u64;
 705 +       struct cvmx_npei_dbg_data_s {
 706 +               uint64_t reserved_28_63:36;
 707 +               uint64_t qlm0_rev_lanes:1;
 708 +               uint64_t reserved_25_26:2;
 709 +               uint64_t qlm1_spd:2;
 710 +               uint64_t c_mul:5;
 711 +               uint64_t dsel_ext:1;
 712 +               uint64_t data:17;
 713 +       } s;
 714 +       struct cvmx_npei_dbg_data_cn52xx {
 715 +               uint64_t reserved_29_63:35;
 716 +               uint64_t qlm0_link_width:1;
 717 +               uint64_t qlm0_rev_lanes:1;
 718 +               uint64_t qlm1_mode:2;
 719 +               uint64_t qlm1_spd:2;
 720 +               uint64_t c_mul:5;
 721 +               uint64_t dsel_ext:1;
 722 +               uint64_t data:17;
 723 +       } cn52xx;
 724 +       struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
 725 +       struct cvmx_npei_dbg_data_cn56xx {
 726 +               uint64_t reserved_29_63:35;
 727 +               uint64_t qlm2_rev_lanes:1;
 728 +               uint64_t qlm0_rev_lanes:1;
 729 +               uint64_t qlm3_spd:2;
 730 +               uint64_t qlm1_spd:2;
 731 +               uint64_t c_mul:5;
 732 +               uint64_t dsel_ext:1;
 733 +               uint64_t data:17;
 734 +       } cn56xx;
 735 +       struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
 736 +};
 737 +
 738 +union cvmx_npei_dbg_select {
 739 +       uint64_t u64;
 740 +       struct cvmx_npei_dbg_select_s {
 741 +               uint64_t reserved_16_63:48;
 742 +               uint64_t dbg_sel:16;
 743 +       } s;
 744 +       struct cvmx_npei_dbg_select_s cn52xx;
 745 +       struct cvmx_npei_dbg_select_s cn52xxp1;
 746 +       struct cvmx_npei_dbg_select_s cn56xx;
 747 +       struct cvmx_npei_dbg_select_s cn56xxp1;
 748 +};
 749 +
 750 +union cvmx_npei_dmax_counts {
 751 +       uint64_t u64;
 752 +       struct cvmx_npei_dmax_counts_s {
 753 +               uint64_t reserved_39_63:25;
 754 +               uint64_t fcnt:7;
 755 +               uint64_t dbell:32;
 756 +       } s;
 757 +       struct cvmx_npei_dmax_counts_s cn52xx;
 758 +       struct cvmx_npei_dmax_counts_s cn52xxp1;
 759 +       struct cvmx_npei_dmax_counts_s cn56xx;
 760 +       struct cvmx_npei_dmax_counts_s cn56xxp1;
 761 +};
 762 +
 763 +union cvmx_npei_dmax_dbell {
 764 +       uint32_t u32;
 765 +       struct cvmx_npei_dmax_dbell_s {
 766 +               uint32_t reserved_16_31:16;
 767 +               uint32_t dbell:16;
 768 +       } s;
 769 +       struct cvmx_npei_dmax_dbell_s cn52xx;
 770 +       struct cvmx_npei_dmax_dbell_s cn52xxp1;
 771 +       struct cvmx_npei_dmax_dbell_s cn56xx;
 772 +       struct cvmx_npei_dmax_dbell_s cn56xxp1;
 773 +};
 774 +
 775 +union cvmx_npei_dmax_ibuff_saddr {
 776 +       uint64_t u64;
 777 +       struct cvmx_npei_dmax_ibuff_saddr_s {
 778 +               uint64_t reserved_37_63:27;
 779 +               uint64_t idle:1;
 780 +               uint64_t saddr:29;
 781 +               uint64_t reserved_0_6:7;
 782 +       } s;
 783 +       struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
 784 +               uint64_t reserved_36_63:28;
 785 +               uint64_t saddr:29;
 786 +               uint64_t reserved_0_6:7;
 787 +       } cn52xx;
 788 +       struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
 789 +       struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
 790 +       struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
 791 +};
 792 +
 793 +union cvmx_npei_dmax_naddr {
 794 +       uint64_t u64;
 795 +       struct cvmx_npei_dmax_naddr_s {
 796 +               uint64_t reserved_36_63:28;
 797 +               uint64_t addr:36;
 798 +       } s;
 799 +       struct cvmx_npei_dmax_naddr_s cn52xx;
 800 +       struct cvmx_npei_dmax_naddr_s cn52xxp1;
 801 +       struct cvmx_npei_dmax_naddr_s cn56xx;
 802 +       struct cvmx_npei_dmax_naddr_s cn56xxp1;
 803 +};
 804 +
 805 +union cvmx_npei_dma0_int_level {
 806 +       uint64_t u64;
 807 +       struct cvmx_npei_dma0_int_level_s {
 808 +               uint64_t time:32;
 809 +               uint64_t cnt:32;
 810 +       } s;
 811 +       struct cvmx_npei_dma0_int_level_s cn52xx;
 812 +       struct cvmx_npei_dma0_int_level_s cn52xxp1;
 813 +       struct cvmx_npei_dma0_int_level_s cn56xx;
 814 +       struct cvmx_npei_dma0_int_level_s cn56xxp1;
 815 +};
 816 +
 817 +union cvmx_npei_dma1_int_level {
 818 +       uint64_t u64;
 819 +       struct cvmx_npei_dma1_int_level_s {
 820 +               uint64_t time:32;
 821 +               uint64_t cnt:32;
 822 +       } s;
 823 +       struct cvmx_npei_dma1_int_level_s cn52xx;
 824 +       struct cvmx_npei_dma1_int_level_s cn52xxp1;
 825 +       struct cvmx_npei_dma1_int_level_s cn56xx;
 826 +       struct cvmx_npei_dma1_int_level_s cn56xxp1;
 827 +};
 828 +
 829 +union cvmx_npei_dma_cnts {
 830 +       uint64_t u64;
 831 +       struct cvmx_npei_dma_cnts_s {
 832 +               uint64_t dma1:32;
 833 +               uint64_t dma0:32;
 834 +       } s;
 835 +       struct cvmx_npei_dma_cnts_s cn52xx;
 836 +       struct cvmx_npei_dma_cnts_s cn52xxp1;
 837 +       struct cvmx_npei_dma_cnts_s cn56xx;
 838 +       struct cvmx_npei_dma_cnts_s cn56xxp1;
 839 +};
 840 +
 841 +union cvmx_npei_dma_control {
 842 +       uint64_t u64;
 843 +       struct cvmx_npei_dma_control_s {
 844 +               uint64_t reserved_39_63:25;
 845 +               uint64_t dma4_enb:1;
 846 +               uint64_t dma3_enb:1;
 847 +               uint64_t dma2_enb:1;
 848 +               uint64_t dma1_enb:1;
 849 +               uint64_t dma0_enb:1;
 850 +               uint64_t b0_lend:1;
 851 +               uint64_t dwb_denb:1;
 852 +               uint64_t dwb_ichk:9;
 853 +               uint64_t fpa_que:3;
 854 +               uint64_t o_add1:1;
 855 +               uint64_t o_ro:1;
 856 +               uint64_t o_ns:1;
 857 +               uint64_t o_es:2;
 858 +               uint64_t o_mode:1;
 859 +               uint64_t csize:14;
 860 +       } s;
 861 +       struct cvmx_npei_dma_control_s cn52xx;
 862 +       struct cvmx_npei_dma_control_cn52xxp1 {
 863 +               uint64_t reserved_38_63:26;
 864 +               uint64_t dma3_enb:1;
 865 +               uint64_t dma2_enb:1;
 866 +               uint64_t dma1_enb:1;
 867 +               uint64_t dma0_enb:1;
 868 +               uint64_t b0_lend:1;
 869 +               uint64_t dwb_denb:1;
 870 +               uint64_t dwb_ichk:9;
 871 +               uint64_t fpa_que:3;
 872 +               uint64_t o_add1:1;
 873 +               uint64_t o_ro:1;
 874 +               uint64_t o_ns:1;
 875 +               uint64_t o_es:2;
 876 +               uint64_t o_mode:1;
 877 +               uint64_t csize:14;
 878 +       } cn52xxp1;
 879 +       struct cvmx_npei_dma_control_s cn56xx;
 880 +       struct cvmx_npei_dma_control_s cn56xxp1;
 881 +};
 882 +
 883 +union cvmx_npei_int_a_enb {
 884 +       uint64_t u64;
 885 +       struct cvmx_npei_int_a_enb_s {
 886 +               uint64_t reserved_10_63:54;
 887 +               uint64_t pout_err:1;
 888 +               uint64_t pin_bp:1;
 889 +               uint64_t p1_rdlk:1;
 890 +               uint64_t p0_rdlk:1;
 891 +               uint64_t pgl_err:1;
 892 +               uint64_t pdi_err:1;
 893 +               uint64_t pop_err:1;
 894 +               uint64_t pins_err:1;
 895 +               uint64_t dma1_cpl:1;
 896 +               uint64_t dma0_cpl:1;
 897 +       } s;
 898 +       struct cvmx_npei_int_a_enb_cn52xx {
 899 +               uint64_t reserved_8_63:56;
 900 +               uint64_t p1_rdlk:1;
 901 +               uint64_t p0_rdlk:1;
 902 +               uint64_t pgl_err:1;
 903 +               uint64_t pdi_err:1;
 904 +               uint64_t pop_err:1;
 905 +               uint64_t pins_err:1;
 906 +               uint64_t dma1_cpl:1;
 907 +               uint64_t dma0_cpl:1;
 908 +       } cn52xx;
 909 +       struct cvmx_npei_int_a_enb_cn52xxp1 {
 910 +               uint64_t reserved_2_63:62;
 911 +               uint64_t dma1_cpl:1;
 912 +               uint64_t dma0_cpl:1;
 913 +       } cn52xxp1;
 914 +       struct cvmx_npei_int_a_enb_s cn56xx;
 915 +};
 916 +
 917 +union cvmx_npei_int_a_enb2 {
 918 +       uint64_t u64;
 919 +       struct cvmx_npei_int_a_enb2_s {
 920 +               uint64_t reserved_10_63:54;
 921 +               uint64_t pout_err:1;
 922 +               uint64_t pin_bp:1;
 923 +               uint64_t p1_rdlk:1;
 924 +               uint64_t p0_rdlk:1;
 925 +               uint64_t pgl_err:1;
 926 +               uint64_t pdi_err:1;
 927 +               uint64_t pop_err:1;
 928 +               uint64_t pins_err:1;
 929 +               uint64_t dma1_cpl:1;
 930 +               uint64_t dma0_cpl:1;
 931 +       } s;
 932 +       struct cvmx_npei_int_a_enb2_cn52xx {
 933 +               uint64_t reserved_8_63:56;
 934 +               uint64_t p1_rdlk:1;
 935 +               uint64_t p0_rdlk:1;
 936 +               uint64_t pgl_err:1;
 937 +               uint64_t pdi_err:1;
 938 +               uint64_t pop_err:1;
 939 +               uint64_t pins_err:1;
 940 +               uint64_t reserved_0_1:2;
 941 +       } cn52xx;
 942 +       struct cvmx_npei_int_a_enb2_cn52xxp1 {
 943 +               uint64_t reserved_2_63:62;
 944 +               uint64_t dma1_cpl:1;
 945 +               uint64_t dma0_cpl:1;
 946 +       } cn52xxp1;
 947 +       struct cvmx_npei_int_a_enb2_s cn56xx;
 948 +};
 949 +
 950 +union cvmx_npei_int_a_sum {
 951 +       uint64_t u64;
 952 +       struct cvmx_npei_int_a_sum_s {
 953 +               uint64_t reserved_10_63:54;
 954 +               uint64_t pout_err:1;
 955 +               uint64_t pin_bp:1;
 956 +               uint64_t p1_rdlk:1;
 957 +               uint64_t p0_rdlk:1;
 958 +               uint64_t pgl_err:1;
 959 +               uint64_t pdi_err:1;
 960 +               uint64_t pop_err:1;
 961 +               uint64_t pins_err:1;
 962 +               uint64_t dma1_cpl:1;
 963 +               uint64_t dma0_cpl:1;
 964 +       } s;
 965 +       struct cvmx_npei_int_a_sum_cn52xx {
 966 +               uint64_t reserved_8_63:56;
 967 +               uint64_t p1_rdlk:1;
 968 +               uint64_t p0_rdlk:1;
 969 +               uint64_t pgl_err:1;
 970 +               uint64_t pdi_err:1;
 971 +               uint64_t pop_err:1;
 972 +               uint64_t pins_err:1;
 973 +               uint64_t dma1_cpl:1;
 974 +               uint64_t dma0_cpl:1;
 975 +       } cn52xx;
 976 +       struct cvmx_npei_int_a_sum_cn52xxp1 {
 977 +               uint64_t reserved_2_63:62;
 978 +               uint64_t dma1_cpl:1;
 979 +               uint64_t dma0_cpl:1;
 980 +       } cn52xxp1;
 981 +       struct cvmx_npei_int_a_sum_s cn56xx;
 982 +};
 983 +
 984 +union cvmx_npei_int_enb {
 985 +       uint64_t u64;
 986 +       struct cvmx_npei_int_enb_s {
 987 +               uint64_t mio_inta:1;
 988 +               uint64_t reserved_62_62:1;
 989 +               uint64_t int_a:1;
 990 +               uint64_t c1_ldwn:1;
 991 +               uint64_t c0_ldwn:1;
 992 +               uint64_t c1_exc:1;
 993 +               uint64_t c0_exc:1;
 994 +               uint64_t c1_up_wf:1;
 995 +               uint64_t c0_up_wf:1;
 996 +               uint64_t c1_un_wf:1;
 997 +               uint64_t c0_un_wf:1;
 998 +               uint64_t c1_un_bx:1;
 999 +               uint64_t c1_un_wi:1;
1000 +               uint64_t c1_un_b2:1;
1001 +               uint64_t c1_un_b1:1;
1002 +               uint64_t c1_un_b0:1;
1003 +               uint64_t c1_up_bx:1;
1004 +               uint64_t c1_up_wi:1;
1005 +               uint64_t c1_up_b2:1;
1006 +               uint64_t c1_up_b1:1;
1007 +               uint64_t c1_up_b0:1;
1008 +               uint64_t c0_un_bx:1;
1009 +               uint64_t c0_un_wi:1;
1010 +               uint64_t c0_un_b2:1;
1011 +               uint64_t c0_un_b1:1;
1012 +               uint64_t c0_un_b0:1;
1013 +               uint64_t c0_up_bx:1;
1014 +               uint64_t c0_up_wi:1;
1015 +               uint64_t c0_up_b2:1;
1016 +               uint64_t c0_up_b1:1;
1017 +               uint64_t c0_up_b0:1;
1018 +               uint64_t c1_hpint:1;
1019 +               uint64_t c1_pmei:1;
1020 +               uint64_t c1_wake:1;
1021 +               uint64_t crs1_dr:1;
1022 +               uint64_t c1_se:1;
1023 +               uint64_t crs1_er:1;
1024 +               uint64_t c1_aeri:1;
1025 +               uint64_t c0_hpint:1;
1026 +               uint64_t c0_pmei:1;
1027 +               uint64_t c0_wake:1;
1028 +               uint64_t crs0_dr:1;
1029 +               uint64_t c0_se:1;
1030 +               uint64_t crs0_er:1;
1031 +               uint64_t c0_aeri:1;
1032 +               uint64_t ptime:1;
1033 +               uint64_t pcnt:1;
1034 +               uint64_t pidbof:1;
1035 +               uint64_t psldbof:1;
1036 +               uint64_t dtime1:1;
1037 +               uint64_t dtime0:1;
1038 +               uint64_t dcnt1:1;
1039 +               uint64_t dcnt0:1;
1040 +               uint64_t dma1fi:1;
1041 +               uint64_t dma0fi:1;
1042 +               uint64_t dma4dbo:1;
1043 +               uint64_t dma3dbo:1;
1044 +               uint64_t dma2dbo:1;
1045 +               uint64_t dma1dbo:1;
1046 +               uint64_t dma0dbo:1;
1047 +               uint64_t iob2big:1;
1048 +               uint64_t bar0_to:1;
1049 +               uint64_t rml_wto:1;
1050 +               uint64_t rml_rto:1;
1051 +       } s;
1052 +       struct cvmx_npei_int_enb_s cn52xx;
1053 +       struct cvmx_npei_int_enb_cn52xxp1 {
1054 +               uint64_t mio_inta:1;
1055 +               uint64_t reserved_62_62:1;
1056 +               uint64_t int_a:1;
1057 +               uint64_t c1_ldwn:1;
1058 +               uint64_t c0_ldwn:1;
1059 +               uint64_t c1_exc:1;
1060 +               uint64_t c0_exc:1;
1061 +               uint64_t c1_up_wf:1;
1062 +               uint64_t c0_up_wf:1;
1063 +               uint64_t c1_un_wf:1;
1064 +               uint64_t c0_un_wf:1;
1065 +               uint64_t c1_un_bx:1;
1066 +               uint64_t c1_un_wi:1;
1067 +               uint64_t c1_un_b2:1;
1068 +               uint64_t c1_un_b1:1;
1069 +               uint64_t c1_un_b0:1;
1070 +               uint64_t c1_up_bx:1;
1071 +               uint64_t c1_up_wi:1;
1072 +               uint64_t c1_up_b2:1;
1073 +               uint64_t c1_up_b1:1;
1074 +               uint64_t c1_up_b0:1;
1075 +               uint64_t c0_un_bx:1;
1076 +               uint64_t c0_un_wi:1;
1077 +               uint64_t c0_un_b2:1;
1078 +               uint64_t c0_un_b1:1;
1079 +               uint64_t c0_un_b0:1;
1080 +               uint64_t c0_up_bx:1;
1081 +               uint64_t c0_up_wi:1;
1082 +               uint64_t c0_up_b2:1;
1083 +               uint64_t c0_up_b1:1;
1084 +               uint64_t c0_up_b0:1;
1085 +               uint64_t c1_hpint:1;
1086 +               uint64_t c1_pmei:1;
1087 +               uint64_t c1_wake:1;
1088 +               uint64_t crs1_dr:1;
1089 +               uint64_t c1_se:1;
1090 +               uint64_t crs1_er:1;
1091 +               uint64_t c1_aeri:1;
1092 +               uint64_t c0_hpint:1;
1093 +               uint64_t c0_pmei:1;
1094 +               uint64_t c0_wake:1;
1095 +               uint64_t crs0_dr:1;
1096 +               uint64_t c0_se:1;
1097 +               uint64_t crs0_er:1;
1098 +               uint64_t c0_aeri:1;
1099 +               uint64_t ptime:1;
1100 +               uint64_t pcnt:1;
1101 +               uint64_t pidbof:1;
1102 +               uint64_t psldbof:1;
1103 +               uint64_t dtime1:1;
1104 +               uint64_t dtime0:1;
1105 +               uint64_t dcnt1:1;
1106 +               uint64_t dcnt0:1;
1107 +               uint64_t dma1fi:1;
1108 +               uint64_t dma0fi:1;
1109 +               uint64_t reserved_8_8:1;
1110 +               uint64_t dma3dbo:1;
1111 +               uint64_t dma2dbo:1;
1112 +               uint64_t dma1dbo:1;
1113 +               uint64_t dma0dbo:1;
1114 +               uint64_t iob2big:1;
1115 +               uint64_t bar0_to:1;
1116 +               uint64_t rml_wto:1;
1117 +               uint64_t rml_rto:1;
1118 +       } cn52xxp1;
1119 +       struct cvmx_npei_int_enb_s cn56xx;
1120 +       struct cvmx_npei_int_enb_cn56xxp1 {
1121 +               uint64_t mio_inta:1;
1122 +               uint64_t reserved_61_62:2;
1123 +               uint64_t c1_ldwn:1;
1124 +               uint64_t c0_ldwn:1;
1125 +               uint64_t c1_exc:1;
1126 +               uint64_t c0_exc:1;
1127 +               uint64_t c1_up_wf:1;
1128 +               uint64_t c0_up_wf:1;
1129 +               uint64_t c1_un_wf:1;
1130 +               uint64_t c0_un_wf:1;
1131 +               uint64_t c1_un_bx:1;
1132 +               uint64_t c1_un_wi:1;
1133 +               uint64_t c1_un_b2:1;
1134 +               uint64_t c1_un_b1:1;
1135 +               uint64_t c1_un_b0:1;
1136 +               uint64_t c1_up_bx:1;
1137 +               uint64_t c1_up_wi:1;
1138 +               uint64_t c1_up_b2:1;
1139 +               uint64_t c1_up_b1:1;
1140 +               uint64_t c1_up_b0:1;
1141 +               uint64_t c0_un_bx:1;
1142 +               uint64_t c0_un_wi:1;
1143 +               uint64_t c0_un_b2:1;
1144 +               uint64_t c0_un_b1:1;
1145 +               uint64_t c0_un_b0:1;
1146 +               uint64_t c0_up_bx:1;
1147 +               uint64_t c0_up_wi:1;
1148 +               uint64_t c0_up_b2:1;
1149 +               uint64_t c0_up_b1:1;
1150 +               uint64_t c0_up_b0:1;
1151 +               uint64_t c1_hpint:1;
1152 +               uint64_t c1_pmei:1;
1153 +               uint64_t c1_wake:1;
1154 +               uint64_t reserved_29_29:1;
1155 +               uint64_t c1_se:1;
1156 +               uint64_t reserved_27_27:1;
1157 +               uint64_t c1_aeri:1;
1158 +               uint64_t c0_hpint:1;
1159 +               uint64_t c0_pmei:1;
1160 +               uint64_t c0_wake:1;
1161 +               uint64_t reserved_22_22:1;
1162 +               uint64_t c0_se:1;
1163 +               uint64_t reserved_20_20:1;
1164 +               uint64_t c0_aeri:1;
1165 +               uint64_t ptime:1;
1166 +               uint64_t pcnt:1;
1167 +               uint64_t pidbof:1;
1168 +               uint64_t psldbof:1;
1169 +               uint64_t dtime1:1;
1170 +               uint64_t dtime0:1;
1171 +               uint64_t dcnt1:1;
1172 +               uint64_t dcnt0:1;
1173 +               uint64_t dma1fi:1;
1174 +               uint64_t dma0fi:1;
1175 +               uint64_t dma4dbo:1;
1176 +               uint64_t dma3dbo:1;
1177 +               uint64_t dma2dbo:1;
1178 +               uint64_t dma1dbo:1;
1179 +               uint64_t dma0dbo:1;
1180 +               uint64_t iob2big:1;
1181 +               uint64_t bar0_to:1;
1182 +               uint64_t rml_wto:1;
1183 +               uint64_t rml_rto:1;
1184 +       } cn56xxp1;
1185 +};
1186 +
1187 +union cvmx_npei_int_enb2 {
1188 +       uint64_t u64;
1189 +       struct cvmx_npei_int_enb2_s {
1190 +               uint64_t reserved_62_63:2;
1191 +               uint64_t int_a:1;
1192 +               uint64_t c1_ldwn:1;
1193 +               uint64_t c0_ldwn:1;
1194 +               uint64_t c1_exc:1;
1195 +               uint64_t c0_exc:1;
1196 +               uint64_t c1_up_wf:1;
1197 +               uint64_t c0_up_wf:1;
1198 +               uint64_t c1_un_wf:1;
1199 +               uint64_t c0_un_wf:1;
1200 +               uint64_t c1_un_bx:1;
1201 +               uint64_t c1_un_wi:1;
1202 +               uint64_t c1_un_b2:1;
1203 +               uint64_t c1_un_b1:1;
1204 +               uint64_t c1_un_b0:1;
1205 +               uint64_t c1_up_bx:1;
1206 +               uint64_t c1_up_wi:1;
1207 +               uint64_t c1_up_b2:1;
1208 +               uint64_t c1_up_b1:1;
1209 +               uint64_t c1_up_b0:1;
1210 +               uint64_t c0_un_bx:1;
1211 +               uint64_t c0_un_wi:1;
1212 +               uint64_t c0_un_b2:1;
1213 +               uint64_t c0_un_b1:1;
1214 +               uint64_t c0_un_b0:1;
1215 +               uint64_t c0_up_bx:1;
1216 +               uint64_t c0_up_wi:1;
1217 +               uint64_t c0_up_b2:1;
1218 +               uint64_t c0_up_b1:1;
1219 +               uint64_t c0_up_b0:1;
1220 +               uint64_t c1_hpint:1;
1221 +               uint64_t c1_pmei:1;
1222 +               uint64_t c1_wake:1;
1223 +               uint64_t crs1_dr:1;
1224 +               uint64_t c1_se:1;
1225 +               uint64_t crs1_er:1;
1226 +               uint64_t c1_aeri:1;
1227 +               uint64_t c0_hpint:1;
1228 +               uint64_t c0_pmei:1;
1229 +               uint64_t c0_wake:1;
1230 +               uint64_t crs0_dr:1;
1231 +               uint64_t c0_se:1;
1232 +               uint64_t crs0_er:1;
1233 +               uint64_t c0_aeri:1;
1234 +               uint64_t ptime:1;
1235 +               uint64_t pcnt:1;
1236 +               uint64_t pidbof:1;
1237 +               uint64_t psldbof:1;
1238 +               uint64_t dtime1:1;
1239 +               uint64_t dtime0:1;
1240 +               uint64_t dcnt1:1;
1241 +               uint64_t dcnt0:1;
1242 +               uint64_t dma1fi:1;
1243 +               uint64_t dma0fi:1;
1244 +               uint64_t dma4dbo:1;
1245 +               uint64_t dma3dbo:1;
1246 +               uint64_t dma2dbo:1;
1247 +               uint64_t dma1dbo:1;
1248 +               uint64_t dma0dbo:1;
1249 +               uint64_t iob2big:1;
1250 +               uint64_t bar0_to:1;
1251 +               uint64_t rml_wto:1;
1252 +               uint64_t rml_rto:1;
1253 +       } s;
1254 +       struct cvmx_npei_int_enb2_s cn52xx;
1255 +       struct cvmx_npei_int_enb2_cn52xxp1 {
1256 +               uint64_t reserved_62_63:2;
1257 +               uint64_t int_a:1;
1258 +               uint64_t c1_ldwn:1;
1259 +               uint64_t c0_ldwn:1;
1260 +               uint64_t c1_exc:1;
1261 +               uint64_t c0_exc:1;
1262 +               uint64_t c1_up_wf:1;
1263 +               uint64_t c0_up_wf:1;
1264 +               uint64_t c1_un_wf:1;
1265 +               uint64_t c0_un_wf:1;
1266 +               uint64_t c1_un_bx:1;
1267 +               uint64_t c1_un_wi:1;
1268 +               uint64_t c1_un_b2:1;
1269 +               uint64_t c1_un_b1:1;
1270 +               uint64_t c1_un_b0:1;
1271 +               uint64_t c1_up_bx:1;
1272 +               uint64_t c1_up_wi:1;
1273 +               uint64_t c1_up_b2:1;
1274 +               uint64_t c1_up_b1:1;
1275 +               uint64_t c1_up_b0:1;
1276 +               uint64_t c0_un_bx:1;
1277 +               uint64_t c0_un_wi:1;
1278 +               uint64_t c0_un_b2:1;
1279 +               uint64_t c0_un_b1:1;
1280 +               uint64_t c0_un_b0:1;
1281 +               uint64_t c0_up_bx:1;
1282 +               uint64_t c0_up_wi:1;
1283 +               uint64_t c0_up_b2:1;
1284 +               uint64_t c0_up_b1:1;
1285 +               uint64_t c0_up_b0:1;
1286 +               uint64_t c1_hpint:1;
1287 +               uint64_t c1_pmei:1;
1288 +               uint64_t c1_wake:1;
1289 +               uint64_t crs1_dr:1;
1290 +               uint64_t c1_se:1;
1291 +               uint64_t crs1_er:1;
1292 +               uint64_t c1_aeri:1;
1293 +               uint64_t c0_hpint:1;
1294 +               uint64_t c0_pmei:1;
1295 +               uint64_t c0_wake:1;
1296 +               uint64_t crs0_dr:1;
1297 +               uint64_t c0_se:1;
1298 +               uint64_t crs0_er:1;
1299 +               uint64_t c0_aeri:1;
1300 +               uint64_t ptime:1;
1301 +               uint64_t pcnt:1;
1302 +               uint64_t pidbof:1;
1303 +               uint64_t psldbof:1;
1304 +               uint64_t dtime1:1;
1305 +               uint64_t dtime0:1;
1306 +               uint64_t dcnt1:1;
1307 +               uint64_t dcnt0:1;
1308 +               uint64_t dma1fi:1;
1309 +               uint64_t dma0fi:1;
1310 +               uint64_t reserved_8_8:1;
1311 +               uint64_t dma3dbo:1;
1312 +               uint64_t dma2dbo:1;
1313 +               uint64_t dma1dbo:1;
1314 +               uint64_t dma0dbo:1;
1315 +               uint64_t iob2big:1;
1316 +               uint64_t bar0_to:1;
1317 +               uint64_t rml_wto:1;
1318 +               uint64_t rml_rto:1;
1319 +       } cn52xxp1;
1320 +       struct cvmx_npei_int_enb2_s cn56xx;
1321 +       struct cvmx_npei_int_enb2_cn56xxp1 {
1322 +               uint64_t reserved_61_63:3;
1323 +               uint64_t c1_ldwn:1;
1324 +               uint64_t c0_ldwn:1;
1325 +               uint64_t c1_exc:1;
1326 +               uint64_t c0_exc:1;
1327 +               uint64_t c1_up_wf:1;
1328 +               uint64_t c0_up_wf:1;
1329 +               uint64_t c1_un_wf:1;
1330 +               uint64_t c0_un_wf:1;
1331 +               uint64_t c1_un_bx:1;
1332 +               uint64_t c1_un_wi:1;
1333 +               uint64_t c1_un_b2:1;
1334 +               uint64_t c1_un_b1:1;
1335 +               uint64_t c1_un_b0:1;
1336 +               uint64_t c1_up_bx:1;
1337 +               uint64_t c1_up_wi:1;
1338 +               uint64_t c1_up_b2:1;
1339 +               uint64_t c1_up_b1:1;
1340 +               uint64_t c1_up_b0:1;
1341 +               uint64_t c0_un_bx:1;
1342 +               uint64_t c0_un_wi:1;
1343 +               uint64_t c0_un_b2:1;
1344 +               uint64_t c0_un_b1:1;
1345 +               uint64_t c0_un_b0:1;
1346 +               uint64_t c0_up_bx:1;
1347 +               uint64_t c0_up_wi:1;
1348 +               uint64_t c0_up_b2:1;
1349 +               uint64_t c0_up_b1:1;
1350 +               uint64_t c0_up_b0:1;
1351 +               uint64_t c1_hpint:1;
1352 +               uint64_t c1_pmei:1;
1353 +               uint64_t c1_wake:1;
1354 +               uint64_t reserved_29_29:1;
1355 +               uint64_t c1_se:1;
1356 +               uint64_t reserved_27_27:1;
1357 +               uint64_t c1_aeri:1;
1358 +               uint64_t c0_hpint:1;
1359 +               uint64_t c0_pmei:1;
1360 +               uint64_t c0_wake:1;
1361 +               uint64_t reserved_22_22:1;
1362 +               uint64_t c0_se:1;
1363 +               uint64_t reserved_20_20:1;
1364 +               uint64_t c0_aeri:1;
1365 +               uint64_t ptime:1;
1366 +               uint64_t pcnt:1;
1367 +               uint64_t pidbof:1;
1368 +               uint64_t psldbof:1;
1369 +               uint64_t dtime1:1;
1370 +               uint64_t dtime0:1;
1371 +               uint64_t dcnt1:1;
1372 +               uint64_t dcnt0:1;
1373 +               uint64_t dma1fi:1;
1374 +               uint64_t dma0fi:1;
1375 +               uint64_t dma4dbo:1;
1376 +               uint64_t dma3dbo:1;
1377 +               uint64_t dma2dbo:1;
1378 +               uint64_t dma1dbo:1;
1379 +               uint64_t dma0dbo:1;
1380 +               uint64_t iob2big:1;
1381 +               uint64_t bar0_to:1;
1382 +               uint64_t rml_wto:1;
1383 +               uint64_t rml_rto:1;
1384 +       } cn56xxp1;
1385 +};
1386 +
1387 +union cvmx_npei_int_info {
1388 +       uint64_t u64;
1389 +       struct cvmx_npei_int_info_s {
1390 +               uint64_t reserved_12_63:52;
1391 +               uint64_t pidbof:6;
1392 +               uint64_t psldbof:6;
1393 +       } s;
1394 +       struct cvmx_npei_int_info_s cn52xx;
1395 +       struct cvmx_npei_int_info_s cn56xx;
1396 +       struct cvmx_npei_int_info_s cn56xxp1;
1397 +};
1398 +
1399 +union cvmx_npei_int_sum {
1400 +       uint64_t u64;
1401 +       struct cvmx_npei_int_sum_s {
1402 +               uint64_t mio_inta:1;
1403 +               uint64_t reserved_62_62:1;
1404 +               uint64_t int_a:1;
1405 +               uint64_t c1_ldwn:1;
1406 +               uint64_t c0_ldwn:1;
1407 +               uint64_t c1_exc:1;
1408 +               uint64_t c0_exc:1;
1409 +               uint64_t c1_up_wf:1;
1410 +               uint64_t c0_up_wf:1;
1411 +               uint64_t c1_un_wf:1;
1412 +               uint64_t c0_un_wf:1;
1413 +               uint64_t c1_un_bx:1;
1414 +               uint64_t c1_un_wi:1;
1415 +               uint64_t c1_un_b2:1;
1416 +               uint64_t c1_un_b1:1;
1417 +               uint64_t c1_un_b0:1;
1418 +               uint64_t c1_up_bx:1;
1419 +               uint64_t c1_up_wi:1;
1420 +               uint64_t c1_up_b2:1;
1421 +               uint64_t c1_up_b1:1;
1422 +               uint64_t c1_up_b0:1;
1423 +               uint64_t c0_un_bx:1;
1424 +               uint64_t c0_un_wi:1;
1425 +               uint64_t c0_un_b2:1;
1426 +               uint64_t c0_un_b1:1;
1427 +               uint64_t c0_un_b0:1;
1428 +               uint64_t c0_up_bx:1;
1429 +               uint64_t c0_up_wi:1;
1430 +               uint64_t c0_up_b2:1;
1431 +               uint64_t c0_up_b1:1;
1432 +               uint64_t c0_up_b0:1;
1433 +               uint64_t c1_hpint:1;
1434 +               uint64_t c1_pmei:1;
1435 +               uint64_t c1_wake:1;
1436 +               uint64_t crs1_dr:1;
1437 +               uint64_t c1_se:1;
1438 +               uint64_t crs1_er:1;
1439 +               uint64_t c1_aeri:1;
1440 +               uint64_t c0_hpint:1;
1441 +               uint64_t c0_pmei:1;
1442 +               uint64_t c0_wake:1;
1443 +               uint64_t crs0_dr:1;
1444 +               uint64_t c0_se:1;
1445 +               uint64_t crs0_er:1;
1446 +               uint64_t c0_aeri:1;
1447 +               uint64_t ptime:1;
1448 +               uint64_t pcnt:1;
1449 +               uint64_t pidbof:1;
1450 +               uint64_t psldbof:1;
1451 +               uint64_t dtime1:1;
1452 +               uint64_t dtime0:1;
1453 +               uint64_t dcnt1:1;
1454 +               uint64_t dcnt0:1;
1455 +               uint64_t dma1fi:1;
1456 +               uint64_t dma0fi:1;
1457 +               uint64_t dma4dbo:1;
1458 +               uint64_t dma3dbo:1;
1459 +               uint64_t dma2dbo:1;
1460 +               uint64_t dma1dbo:1;
1461 +               uint64_t dma0dbo:1;
1462 +               uint64_t iob2big:1;
1463 +               uint64_t bar0_to:1;
1464 +               uint64_t rml_wto:1;
1465 +               uint64_t rml_rto:1;
1466 +       } s;
1467 +       struct cvmx_npei_int_sum_s cn52xx;
1468 +       struct cvmx_npei_int_sum_cn52xxp1 {
1469 +               uint64_t mio_inta:1;
1470 +               uint64_t reserved_62_62:1;
1471 +               uint64_t int_a:1;
1472 +               uint64_t c1_ldwn:1;
1473 +               uint64_t c0_ldwn:1;
1474 +               uint64_t c1_exc:1;
1475 +               uint64_t c0_exc:1;
1476 +               uint64_t c1_up_wf:1;
1477 +               uint64_t c0_up_wf:1;
1478 +               uint64_t c1_un_wf:1;
1479 +               uint64_t c0_un_wf:1;
1480 +               uint64_t c1_un_bx:1;
1481 +               uint64_t c1_un_wi:1;
1482 +               uint64_t c1_un_b2:1;
1483 +               uint64_t c1_un_b1:1;
1484 +               uint64_t c1_un_b0:1;
1485 +               uint64_t c1_up_bx:1;
1486 +               uint64_t c1_up_wi:1;
1487 +               uint64_t c1_up_b2:1;
1488 +               uint64_t c1_up_b1:1;
1489 +               uint64_t c1_up_b0:1;
1490 +               uint64_t c0_un_bx:1;
1491 +               uint64_t c0_un_wi:1;
1492 +               uint64_t c0_un_b2:1;
1493 +               uint64_t c0_un_b1:1;
1494 +               uint64_t c0_un_b0:1;
1495 +               uint64_t c0_up_bx:1;
1496 +               uint64_t c0_up_wi:1;
1497 +               uint64_t c0_up_b2:1;
1498 +               uint64_t c0_up_b1:1;
1499 +               uint64_t c0_up_b0:1;
1500 +               uint64_t c1_hpint:1;
1501 +               uint64_t c1_pmei:1;
1502 +               uint64_t c1_wake:1;
1503 +               uint64_t crs1_dr:1;
1504 +               uint64_t c1_se:1;
1505 +               uint64_t crs1_er:1;
1506 +               uint64_t c1_aeri:1;
1507 +               uint64_t c0_hpint:1;
1508 +               uint64_t c0_pmei:1;
1509 +               uint64_t c0_wake:1;
1510 +               uint64_t crs0_dr:1;
1511 +               uint64_t c0_se:1;
1512 +               uint64_t crs0_er:1;
1513 +               uint64_t c0_aeri:1;
1514 +               uint64_t reserved_15_18:4;
1515 +               uint64_t dtime1:1;
1516 +               uint64_t dtime0:1;
1517 +               uint64_t dcnt1:1;
1518 +               uint64_t dcnt0:1;
1519 +               uint64_t dma1fi:1;
1520 +               uint64_t dma0fi:1;
1521 +               uint64_t reserved_8_8:1;
1522 +               uint64_t dma3dbo:1;
1523 +               uint64_t dma2dbo:1;
1524 +               uint64_t dma1dbo:1;
1525 +               uint64_t dma0dbo:1;
1526 +               uint64_t iob2big:1;
1527 +               uint64_t bar0_to:1;
1528 +               uint64_t rml_wto:1;
1529 +               uint64_t rml_rto:1;
1530 +       } cn52xxp1;
1531 +       struct cvmx_npei_int_sum_s cn56xx;
1532 +       struct cvmx_npei_int_sum_cn56xxp1 {
1533 +               uint64_t mio_inta:1;
1534 +               uint64_t reserved_61_62:2;
1535 +               uint64_t c1_ldwn:1;
1536 +               uint64_t c0_ldwn:1;
1537 +               uint64_t c1_exc:1;
1538 +               uint64_t c0_exc:1;
1539 +               uint64_t c1_up_wf:1;
1540 +               uint64_t c0_up_wf:1;
1541 +               uint64_t c1_un_wf:1;
1542 +               uint64_t c0_un_wf:1;
1543 +               uint64_t c1_un_bx:1;
1544 +               uint64_t c1_un_wi:1;
1545 +               uint64_t c1_un_b2:1;
1546 +               uint64_t c1_un_b1:1;
1547 +               uint64_t c1_un_b0:1;
1548 +               uint64_t c1_up_bx:1;
1549 +               uint64_t c1_up_wi:1;
1550 +               uint64_t c1_up_b2:1;
1551 +               uint64_t c1_up_b1:1;
1552 +               uint64_t c1_up_b0:1;
1553 +               uint64_t c0_un_bx:1;
1554 +               uint64_t c0_un_wi:1;
1555 +               uint64_t c0_un_b2:1;
1556 +               uint64_t c0_un_b1:1;
1557 +               uint64_t c0_un_b0:1;
1558 +               uint64_t c0_up_bx:1;
1559 +               uint64_t c0_up_wi:1;
1560 +               uint64_t c0_up_b2:1;
1561 +               uint64_t c0_up_b1:1;
1562 +               uint64_t c0_up_b0:1;
1563 +               uint64_t c1_hpint:1;
1564 +               uint64_t c1_pmei:1;
1565 +               uint64_t c1_wake:1;
1566 +               uint64_t reserved_29_29:1;
1567 +               uint64_t c1_se:1;
1568 +               uint64_t reserved_27_27:1;
1569 +               uint64_t c1_aeri:1;
1570 +               uint64_t c0_hpint:1;
1571 +               uint64_t c0_pmei:1;
1572 +               uint64_t c0_wake:1;
1573 +               uint64_t reserved_22_22:1;
1574 +               uint64_t c0_se:1;
1575 +               uint64_t reserved_20_20:1;
1576 +               uint64_t c0_aeri:1;
1577 +               uint64_t ptime:1;
1578 +               uint64_t pcnt:1;
1579 +               uint64_t pidbof:1;
1580 +               uint64_t psldbof:1;
1581 +               uint64_t dtime1:1;
1582 +               uint64_t dtime0:1;
1583 +               uint64_t dcnt1:1;
1584 +               uint64_t dcnt0:1;
1585 +               uint64_t dma1fi:1;
1586 +               uint64_t dma0fi:1;
1587 +               uint64_t dma4dbo:1;
1588 +               uint64_t dma3dbo:1;
1589 +               uint64_t dma2dbo:1;
1590 +               uint64_t dma1dbo:1;
1591 +               uint64_t dma0dbo:1;
1592 +               uint64_t iob2big:1;
1593 +               uint64_t bar0_to:1;
1594 +               uint64_t rml_wto:1;
1595 +               uint64_t rml_rto:1;
1596 +       } cn56xxp1;
1597 +};
1598 +
1599 +union cvmx_npei_int_sum2 {
1600 +       uint64_t u64;
1601 +       struct cvmx_npei_int_sum2_s {
1602 +               uint64_t mio_inta:1;
1603 +               uint64_t reserved_62_62:1;
1604 +               uint64_t int_a:1;
1605 +               uint64_t c1_ldwn:1;
1606 +               uint64_t c0_ldwn:1;
1607 +               uint64_t c1_exc:1;
1608 +               uint64_t c0_exc:1;
1609 +               uint64_t c1_up_wf:1;
1610 +               uint64_t c0_up_wf:1;
1611 +               uint64_t c1_un_wf:1;
1612 +               uint64_t c0_un_wf:1;
1613 +               uint64_t c1_un_bx:1;
1614 +               uint64_t c1_un_wi:1;
1615 +               uint64_t c1_un_b2:1;
1616 +               uint64_t c1_un_b1:1;
1617 +               uint64_t c1_un_b0:1;
1618 +               uint64_t c1_up_bx:1;
1619 +               uint64_t c1_up_wi:1;
1620 +               uint64_t c1_up_b2:1;
1621 +               uint64_t c1_up_b1:1;
1622 +               uint64_t c1_up_b0:1;
1623 +               uint64_t c0_un_bx:1;
1624 +               uint64_t c0_un_wi:1;
1625 +               uint64_t c0_un_b2:1;
1626 +               uint64_t c0_un_b1:1;
1627 +               uint64_t c0_un_b0:1;
1628 +               uint64_t c0_up_bx:1;
1629 +               uint64_t c0_up_wi:1;
1630 +               uint64_t c0_up_b2:1;
1631 +               uint64_t c0_up_b1:1;
1632 +               uint64_t c0_up_b0:1;
1633 +               uint64_t c1_hpint:1;
1634 +               uint64_t c1_pmei:1;
1635 +               uint64_t c1_wake:1;
1636 +               uint64_t crs1_dr:1;
1637 +               uint64_t c1_se:1;
1638 +               uint64_t crs1_er:1;
1639 +               uint64_t c1_aeri:1;
1640 +               uint64_t c0_hpint:1;
1641 +               uint64_t c0_pmei:1;
1642 +               uint64_t c0_wake:1;
1643 +               uint64_t crs0_dr:1;
1644 +               uint64_t c0_se:1;
1645 +               uint64_t crs0_er:1;
1646 +               uint64_t c0_aeri:1;
1647 +               uint64_t reserved_15_18:4;
1648 +               uint64_t dtime1:1;
1649 +               uint64_t dtime0:1;
1650 +               uint64_t dcnt1:1;
1651 +               uint64_t dcnt0:1;
1652 +               uint64_t dma1fi:1;
1653 +               uint64_t dma0fi:1;
1654 +               uint64_t reserved_8_8:1;
1655 +               uint64_t dma3dbo:1;
1656 +               uint64_t dma2dbo:1;
1657 +               uint64_t dma1dbo:1;
1658 +               uint64_t dma0dbo:1;
1659 +               uint64_t iob2big:1;
1660 +               uint64_t bar0_to:1;
1661 +               uint64_t rml_wto:1;
1662 +               uint64_t rml_rto:1;
1663 +       } s;
1664 +       struct cvmx_npei_int_sum2_s cn52xx;
1665 +       struct cvmx_npei_int_sum2_s cn52xxp1;
1666 +       struct cvmx_npei_int_sum2_s cn56xx;
1667 +};
1668 +
1669 +union cvmx_npei_last_win_rdata0 {
1670 +       uint64_t u64;
1671 +       struct cvmx_npei_last_win_rdata0_s {
1672 +               uint64_t data:64;
1673 +       } s;
1674 +       struct cvmx_npei_last_win_rdata0_s cn52xx;
1675 +       struct cvmx_npei_last_win_rdata0_s cn52xxp1;
1676 +       struct cvmx_npei_last_win_rdata0_s cn56xx;
1677 +       struct cvmx_npei_last_win_rdata0_s cn56xxp1;
1678 +};
1679 +
1680 +union cvmx_npei_last_win_rdata1 {
1681 +       uint64_t u64;
1682 +       struct cvmx_npei_last_win_rdata1_s {
1683 +               uint64_t data:64;
1684 +       } s;
1685 +       struct cvmx_npei_last_win_rdata1_s cn52xx;
1686 +       struct cvmx_npei_last_win_rdata1_s cn52xxp1;
1687 +       struct cvmx_npei_last_win_rdata1_s cn56xx;
1688 +       struct cvmx_npei_last_win_rdata1_s cn56xxp1;
1689 +};
1690 +
1691 +union cvmx_npei_mem_access_ctl {
1692 +       uint64_t u64;
1693 +       struct cvmx_npei_mem_access_ctl_s {
1694 +               uint64_t reserved_14_63:50;
1695 +               uint64_t max_word:4;
1696 +               uint64_t timer:10;
1697 +       } s;
1698 +       struct cvmx_npei_mem_access_ctl_s cn52xx;
1699 +       struct cvmx_npei_mem_access_ctl_s cn52xxp1;
1700 +       struct cvmx_npei_mem_access_ctl_s cn56xx;
1701 +       struct cvmx_npei_mem_access_ctl_s cn56xxp1;
1702 +};
1703 +
1704 +union cvmx_npei_mem_access_subidx {
1705 +       uint64_t u64;
1706 +       struct cvmx_npei_mem_access_subidx_s {
1707 +               uint64_t reserved_42_63:22;
1708 +               uint64_t zero:1;
1709 +               uint64_t port:2;
1710 +               uint64_t nmerge:1;
1711 +               uint64_t esr:2;
1712 +               uint64_t esw:2;
1713 +               uint64_t nsr:1;
1714 +               uint64_t nsw:1;
1715 +               uint64_t ror:1;
1716 +               uint64_t row:1;
1717 +               uint64_t ba:30;
1718 +       } s;
1719 +       struct cvmx_npei_mem_access_subidx_s cn52xx;
1720 +       struct cvmx_npei_mem_access_subidx_s cn52xxp1;
1721 +       struct cvmx_npei_mem_access_subidx_s cn56xx;
1722 +       struct cvmx_npei_mem_access_subidx_s cn56xxp1;
1723 +};
1724 +
1725 +union cvmx_npei_msi_enb0 {
1726 +       uint64_t u64;
1727 +       struct cvmx_npei_msi_enb0_s {
1728 +               uint64_t enb:64;
1729 +       } s;
1730 +       struct cvmx_npei_msi_enb0_s cn52xx;
1731 +       struct cvmx_npei_msi_enb0_s cn52xxp1;
1732 +       struct cvmx_npei_msi_enb0_s cn56xx;
1733 +       struct cvmx_npei_msi_enb0_s cn56xxp1;
1734 +};
1735 +
1736 +union cvmx_npei_msi_enb1 {
1737 +       uint64_t u64;
1738 +       struct cvmx_npei_msi_enb1_s {
1739 +               uint64_t enb:64;
1740 +       } s;
1741 +       struct cvmx_npei_msi_enb1_s cn52xx;
1742 +       struct cvmx_npei_msi_enb1_s cn52xxp1;
1743 +       struct cvmx_npei_msi_enb1_s cn56xx;
1744 +       struct cvmx_npei_msi_enb1_s cn56xxp1;
1745 +};
1746 +
1747 +union cvmx_npei_msi_enb2 {
1748 +       uint64_t u64;
1749 +       struct cvmx_npei_msi_enb2_s {
1750 +               uint64_t enb:64;
1751 +       } s;
1752 +       struct cvmx_npei_msi_enb2_s cn52xx;
1753 +       struct cvmx_npei_msi_enb2_s cn52xxp1;
1754 +       struct cvmx_npei_msi_enb2_s cn56xx;
1755 +       struct cvmx_npei_msi_enb2_s cn56xxp1;
1756 +};
1757 +
1758 +union cvmx_npei_msi_enb3 {
1759 +       uint64_t u64;
1760 +       struct cvmx_npei_msi_enb3_s {
1761 +               uint64_t enb:64;
1762 +       } s;
1763 +       struct cvmx_npei_msi_enb3_s cn52xx;
1764 +       struct cvmx_npei_msi_enb3_s cn52xxp1;
1765 +       struct cvmx_npei_msi_enb3_s cn56xx;
1766 +       struct cvmx_npei_msi_enb3_s cn56xxp1;
1767 +};
1768 +
1769 +union cvmx_npei_msi_rcv0 {
1770 +       uint64_t u64;
1771 +       struct cvmx_npei_msi_rcv0_s {
1772 +               uint64_t intr:64;
1773 +       } s;
1774 +       struct cvmx_npei_msi_rcv0_s cn52xx;
1775 +       struct cvmx_npei_msi_rcv0_s cn52xxp1;
1776 +       struct cvmx_npei_msi_rcv0_s cn56xx;
1777 +       struct cvmx_npei_msi_rcv0_s cn56xxp1;
1778 +};
1779 +
1780 +union cvmx_npei_msi_rcv1 {
1781 +       uint64_t u64;
1782 +       struct cvmx_npei_msi_rcv1_s {
1783 +               uint64_t intr:64;
1784 +       } s;
1785 +       struct cvmx_npei_msi_rcv1_s cn52xx;
1786 +       struct cvmx_npei_msi_rcv1_s cn52xxp1;
1787 +       struct cvmx_npei_msi_rcv1_s cn56xx;
1788 +       struct cvmx_npei_msi_rcv1_s cn56xxp1;
1789 +};
1790 +
1791 +union cvmx_npei_msi_rcv2 {
1792 +       uint64_t u64;
1793 +       struct cvmx_npei_msi_rcv2_s {
1794 +               uint64_t intr:64;
1795 +       } s;
1796 +       struct cvmx_npei_msi_rcv2_s cn52xx;
1797 +       struct cvmx_npei_msi_rcv2_s cn52xxp1;
1798 +       struct cvmx_npei_msi_rcv2_s cn56xx;
1799 +       struct cvmx_npei_msi_rcv2_s cn56xxp1;
1800 +};
1801 +
1802 +union cvmx_npei_msi_rcv3 {
1803 +       uint64_t u64;
1804 +       struct cvmx_npei_msi_rcv3_s {
1805 +               uint64_t intr:64;
1806 +       } s;
1807 +       struct cvmx_npei_msi_rcv3_s cn52xx;
1808 +       struct cvmx_npei_msi_rcv3_s cn52xxp1;
1809 +       struct cvmx_npei_msi_rcv3_s cn56xx;
1810 +       struct cvmx_npei_msi_rcv3_s cn56xxp1;
1811 +};
1812 +
1813 +union cvmx_npei_msi_rd_map {
1814 +       uint64_t u64;
1815 +       struct cvmx_npei_msi_rd_map_s {
1816 +               uint64_t reserved_16_63:48;
1817 +               uint64_t rd_int:8;
1818 +               uint64_t msi_int:8;
1819 +       } s;
1820 +       struct cvmx_npei_msi_rd_map_s cn52xx;
1821 +       struct cvmx_npei_msi_rd_map_s cn52xxp1;
1822 +       struct cvmx_npei_msi_rd_map_s cn56xx;
1823 +       struct cvmx_npei_msi_rd_map_s cn56xxp1;
1824 +};
1825 +
1826 +union cvmx_npei_msi_w1c_enb0 {
1827 +       uint64_t u64;
1828 +       struct cvmx_npei_msi_w1c_enb0_s {
1829 +               uint64_t clr:64;
1830 +       } s;
1831 +       struct cvmx_npei_msi_w1c_enb0_s cn52xx;
1832 +       struct cvmx_npei_msi_w1c_enb0_s cn56xx;
1833 +};
1834 +
1835 +union cvmx_npei_msi_w1c_enb1 {
1836 +       uint64_t u64;
1837 +       struct cvmx_npei_msi_w1c_enb1_s {
1838 +               uint64_t clr:64;
1839 +       } s;
1840 +       struct cvmx_npei_msi_w1c_enb1_s cn52xx;
1841 +       struct cvmx_npei_msi_w1c_enb1_s cn56xx;
1842 +};
1843 +
1844 +union cvmx_npei_msi_w1c_enb2 {
1845 +       uint64_t u64;
1846 +       struct cvmx_npei_msi_w1c_enb2_s {
1847 +               uint64_t clr:64;
1848 +       } s;
1849 +       struct cvmx_npei_msi_w1c_enb2_s cn52xx;
1850 +       struct cvmx_npei_msi_w1c_enb2_s cn56xx;
1851 +};
1852 +
1853 +union cvmx_npei_msi_w1c_enb3 {
1854 +       uint64_t u64;
1855 +       struct cvmx_npei_msi_w1c_enb3_s {
1856 +               uint64_t clr:64;
1857 +       } s;
1858 +       struct cvmx_npei_msi_w1c_enb3_s cn52xx;
1859 +       struct cvmx_npei_msi_w1c_enb3_s cn56xx;
1860 +};
1861 +
1862 +union cvmx_npei_msi_w1s_enb0 {
1863 +       uint64_t u64;
1864 +       struct cvmx_npei_msi_w1s_enb0_s {
1865 +               uint64_t set:64;
1866 +       } s;
1867 +       struct cvmx_npei_msi_w1s_enb0_s cn52xx;
1868 +       struct cvmx_npei_msi_w1s_enb0_s cn56xx;
1869 +};
1870 +
1871 +union cvmx_npei_msi_w1s_enb1 {
1872 +       uint64_t u64;
1873 +       struct cvmx_npei_msi_w1s_enb1_s {
1874 +               uint64_t set:64;
1875 +       } s;
1876 +       struct cvmx_npei_msi_w1s_enb1_s cn52xx;
1877 +       struct cvmx_npei_msi_w1s_enb1_s cn56xx;
1878 +};
1879 +
1880 +union cvmx_npei_msi_w1s_enb2 {
1881 +       uint64_t u64;
1882 +       struct cvmx_npei_msi_w1s_enb2_s {
1883 +               uint64_t set:64;
1884 +       } s;
1885 +       struct cvmx_npei_msi_w1s_enb2_s cn52xx;
1886 +       struct cvmx_npei_msi_w1s_enb2_s cn56xx;
1887 +};
1888 +
1889 +union cvmx_npei_msi_w1s_enb3 {
1890 +       uint64_t u64;
1891 +       struct cvmx_npei_msi_w1s_enb3_s {
1892 +               uint64_t set:64;
1893 +       } s;
1894 +       struct cvmx_npei_msi_w1s_enb3_s cn52xx;
1895 +       struct cvmx_npei_msi_w1s_enb3_s cn56xx;
1896 +};
1897 +
1898 +union cvmx_npei_msi_wr_map {
1899 +       uint64_t u64;
1900 +       struct cvmx_npei_msi_wr_map_s {
1901 +               uint64_t reserved_16_63:48;
1902 +               uint64_t ciu_int:8;
1903 +               uint64_t msi_int:8;
1904 +       } s;
1905 +       struct cvmx_npei_msi_wr_map_s cn52xx;
1906 +       struct cvmx_npei_msi_wr_map_s cn52xxp1;
1907 +       struct cvmx_npei_msi_wr_map_s cn56xx;
1908 +       struct cvmx_npei_msi_wr_map_s cn56xxp1;
1909 +};
1910 +
1911 +union cvmx_npei_pcie_credit_cnt {
1912 +       uint64_t u64;
1913 +       struct cvmx_npei_pcie_credit_cnt_s {
1914 +               uint64_t reserved_48_63:16;
1915 +               uint64_t p1_ccnt:8;
1916 +               uint64_t p1_ncnt:8;
1917 +               uint64_t p1_pcnt:8;
1918 +               uint64_t p0_ccnt:8;
1919 +               uint64_t p0_ncnt:8;
1920 +               uint64_t p0_pcnt:8;
1921 +       } s;
1922 +       struct cvmx_npei_pcie_credit_cnt_s cn52xx;
1923 +       struct cvmx_npei_pcie_credit_cnt_s cn56xx;
1924 +};
1925 +
1926 +union cvmx_npei_pcie_msi_rcv {
1927 +       uint64_t u64;
1928 +       struct cvmx_npei_pcie_msi_rcv_s {
1929 +               uint64_t reserved_8_63:56;
1930 +               uint64_t intr:8;
1931 +       } s;
1932 +       struct cvmx_npei_pcie_msi_rcv_s cn52xx;
1933 +       struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
1934 +       struct cvmx_npei_pcie_msi_rcv_s cn56xx;
1935 +       struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
1936 +};
1937 +
1938 +union cvmx_npei_pcie_msi_rcv_b1 {
1939 +       uint64_t u64;
1940 +       struct cvmx_npei_pcie_msi_rcv_b1_s {
1941 +               uint64_t reserved_16_63:48;
1942 +               uint64_t intr:8;
1943 +               uint64_t reserved_0_7:8;
1944 +       } s;
1945 +       struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
1946 +       struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
1947 +       struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
1948 +       struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
1949 +};
1950 +
1951 +union cvmx_npei_pcie_msi_rcv_b2 {
1952 +       uint64_t u64;
1953 +       struct cvmx_npei_pcie_msi_rcv_b2_s {
1954 +               uint64_t reserved_24_63:40;
1955 +               uint64_t intr:8;
1956 +               uint64_t reserved_0_15:16;
1957 +       } s;
1958 +       struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
1959 +       struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
1960 +       struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
1961 +       struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
1962 +};
1963 +
1964 +union cvmx_npei_pcie_msi_rcv_b3 {
1965 +       uint64_t u64;
1966 +       struct cvmx_npei_pcie_msi_rcv_b3_s {
1967 +               uint64_t reserved_32_63:32;
1968 +               uint64_t intr:8;
1969 +               uint64_t reserved_0_23:24;
1970 +       } s;
1971 +       struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
1972 +       struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
1973 +       struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
1974 +       struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
1975 +};
1976 +
1977 +union cvmx_npei_pktx_cnts {
1978 +       uint64_t u64;
1979 +       struct cvmx_npei_pktx_cnts_s {
1980 +               uint64_t reserved_54_63:10;
1981 +               uint64_t timer:22;
1982 +               uint64_t cnt:32;
1983 +       } s;
1984 +       struct cvmx_npei_pktx_cnts_s cn52xx;
1985 +       struct cvmx_npei_pktx_cnts_s cn56xx;
1986 +       struct cvmx_npei_pktx_cnts_s cn56xxp1;
1987 +};
1988 +
1989 +union cvmx_npei_pktx_in_bp {
1990 +       uint64_t u64;
1991 +       struct cvmx_npei_pktx_in_bp_s {
1992 +               uint64_t wmark:32;
1993 +               uint64_t cnt:32;
1994 +       } s;
1995 +       struct cvmx_npei_pktx_in_bp_s cn52xx;
1996 +       struct cvmx_npei_pktx_in_bp_s cn56xx;
1997 +       struct cvmx_npei_pktx_in_bp_s cn56xxp1;
1998 +};
1999 +
2000 +union cvmx_npei_pktx_instr_baddr {
2001 +       uint64_t u64;
2002 +       struct cvmx_npei_pktx_instr_baddr_s {
2003 +               uint64_t addr:61;
2004 +               uint64_t reserved_0_2:3;
2005 +       } s;
2006 +       struct cvmx_npei_pktx_instr_baddr_s cn52xx;
2007 +       struct cvmx_npei_pktx_instr_baddr_s cn56xx;
2008 +       struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
2009 +};
2010 +
2011 +union cvmx_npei_pktx_instr_baoff_dbell {
2012 +       uint64_t u64;
2013 +       struct cvmx_npei_pktx_instr_baoff_dbell_s {
2014 +               uint64_t aoff:32;
2015 +               uint64_t dbell:32;
2016 +       } s;
2017 +       struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
2018 +       struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
2019 +       struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
2020 +};
2021 +
2022 +union cvmx_npei_pktx_instr_fifo_rsize {
2023 +       uint64_t u64;
2024 +       struct cvmx_npei_pktx_instr_fifo_rsize_s {
2025 +               uint64_t max:9;
2026 +               uint64_t rrp:9;
2027 +               uint64_t wrp:9;
2028 +               uint64_t fcnt:5;
2029 +               uint64_t rsize:32;
2030 +       } s;
2031 +       struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
2032 +       struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
2033 +       struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
2034 +};
2035 +
2036 +union cvmx_npei_pktx_instr_header {
2037 +       uint64_t u64;
2038 +       struct cvmx_npei_pktx_instr_header_s {
2039 +               uint64_t reserved_44_63:20;
2040 +               uint64_t pbp:1;
2041 +               uint64_t rsv_f:5;
2042 +               uint64_t rparmode:2;
2043 +               uint64_t rsv_e:1;
2044 +               uint64_t rskp_len:7;
2045 +               uint64_t rsv_d:6;
2046 +               uint64_t use_ihdr:1;
2047 +               uint64_t rsv_c:5;
2048 +               uint64_t par_mode:2;
2049 +               uint64_t rsv_b:1;
2050 +               uint64_t skp_len:7;
2051 +               uint64_t rsv_a:6;
2052 +       } s;
2053 +       struct cvmx_npei_pktx_instr_header_s cn52xx;
2054 +       struct cvmx_npei_pktx_instr_header_s cn56xx;
2055 +       struct cvmx_npei_pktx_instr_header_s cn56xxp1;
2056 +};
2057 +
2058 +union cvmx_npei_pktx_slist_baddr {
2059 +       uint64_t u64;
2060 +       struct cvmx_npei_pktx_slist_baddr_s {
2061 +               uint64_t addr:60;
2062 +               uint64_t reserved_0_3:4;
2063 +       } s;
2064 +       struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2065 +       struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2066 +       struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
2067 +};
2068 +
2069 +union cvmx_npei_pktx_slist_baoff_dbell {
2070 +       uint64_t u64;
2071 +       struct cvmx_npei_pktx_slist_baoff_dbell_s {
2072 +               uint64_t aoff:32;
2073 +               uint64_t dbell:32;
2074 +       } s;
2075 +       struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2076 +       struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2077 +       struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
2078 +};
2079 +
2080 +union cvmx_npei_pktx_slist_fifo_rsize {
2081 +       uint64_t u64;
2082 +       struct cvmx_npei_pktx_slist_fifo_rsize_s {
2083 +               uint64_t reserved_32_63:32;
2084 +               uint64_t rsize:32;
2085 +       } s;
2086 +       struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2087 +       struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2088 +       struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
2089 +};
2090 +
2091 +union cvmx_npei_pkt_cnt_int {
2092 +       uint64_t u64;
2093 +       struct cvmx_npei_pkt_cnt_int_s {
2094 +               uint64_t reserved_32_63:32;
2095 +               uint64_t port:32;
2096 +       } s;
2097 +       struct cvmx_npei_pkt_cnt_int_s cn52xx;
2098 +       struct cvmx_npei_pkt_cnt_int_s cn56xx;
2099 +       struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
2100 +};
2101 +
2102 +union cvmx_npei_pkt_cnt_int_enb {
2103 +       uint64_t u64;
2104 +       struct cvmx_npei_pkt_cnt_int_enb_s {
2105 +               uint64_t reserved_32_63:32;
2106 +               uint64_t port:32;
2107 +       } s;
2108 +       struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2109 +       struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2110 +       struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
2111 +};
2112 +
2113 +union cvmx_npei_pkt_data_out_es {
2114 +       uint64_t u64;
2115 +       struct cvmx_npei_pkt_data_out_es_s {
2116 +               uint64_t es:64;
2117 +       } s;
2118 +       struct cvmx_npei_pkt_data_out_es_s cn52xx;
2119 +       struct cvmx_npei_pkt_data_out_es_s cn56xx;
2120 +       struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
2121 +};
2122 +
2123 +union cvmx_npei_pkt_data_out_ns {
2124 +       uint64_t u64;
2125 +       struct cvmx_npei_pkt_data_out_ns_s {
2126 +               uint64_t reserved_32_63:32;
2127 +               uint64_t nsr:32;
2128 +       } s;
2129 +       struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2130 +       struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2131 +       struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
2132 +};
2133 +
2134 +union cvmx_npei_pkt_data_out_ror {
2135 +       uint64_t u64;
2136 +       struct cvmx_npei_pkt_data_out_ror_s {
2137 +               uint64_t reserved_32_63:32;
2138 +               uint64_t ror:32;
2139 +       } s;
2140 +       struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2141 +       struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2142 +       struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
2143 +};
2144 +
2145 +union cvmx_npei_pkt_dpaddr {
2146 +       uint64_t u64;
2147 +       struct cvmx_npei_pkt_dpaddr_s {
2148 +               uint64_t reserved_32_63:32;
2149 +               uint64_t dptr:32;
2150 +       } s;
2151 +       struct cvmx_npei_pkt_dpaddr_s cn52xx;
2152 +       struct cvmx_npei_pkt_dpaddr_s cn56xx;
2153 +       struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
2154 +};
2155 +
2156 +union cvmx_npei_pkt_in_bp {
2157 +       uint64_t u64;
2158 +       struct cvmx_npei_pkt_in_bp_s {
2159 +               uint64_t reserved_32_63:32;
2160 +               uint64_t bp:32;
2161 +       } s;
2162 +       struct cvmx_npei_pkt_in_bp_s cn56xx;
2163 +};
2164 +
2165 +union cvmx_npei_pkt_in_donex_cnts {
2166 +       uint64_t u64;
2167 +       struct cvmx_npei_pkt_in_donex_cnts_s {
2168 +               uint64_t reserved_32_63:32;
2169 +               uint64_t cnt:32;
2170 +       } s;
2171 +       struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2172 +       struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2173 +       struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
2174 +};
2175 +
2176 +union cvmx_npei_pkt_in_instr_counts {
2177 +       uint64_t u64;
2178 +       struct cvmx_npei_pkt_in_instr_counts_s {
2179 +               uint64_t wr_cnt:32;
2180 +               uint64_t rd_cnt:32;
2181 +       } s;
2182 +       struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
2183 +       struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
2184 +};
2185 +
2186 +union cvmx_npei_pkt_in_pcie_port {
2187 +       uint64_t u64;
2188 +       struct cvmx_npei_pkt_in_pcie_port_s {
2189 +               uint64_t pp:64;
2190 +       } s;
2191 +       struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
2192 +       struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
2193 +};
2194 +
2195 +union cvmx_npei_pkt_input_control {
2196 +       uint64_t u64;
2197 +       struct cvmx_npei_pkt_input_control_s {
2198 +               uint64_t reserved_23_63:41;
2199 +               uint64_t pkt_rr:1;
2200 +               uint64_t pbp_dhi:13;
2201 +               uint64_t d_nsr:1;
2202 +               uint64_t d_esr:2;
2203 +               uint64_t d_ror:1;
2204 +               uint64_t use_csr:1;
2205 +               uint64_t nsr:1;
2206 +               uint64_t esr:2;
2207 +               uint64_t ror:1;
2208 +       } s;
2209 +       struct cvmx_npei_pkt_input_control_s cn52xx;
2210 +       struct cvmx_npei_pkt_input_control_s cn56xx;
2211 +       struct cvmx_npei_pkt_input_control_s cn56xxp1;
2212 +};
2213 +
2214 +union cvmx_npei_pkt_instr_enb {
2215 +       uint64_t u64;
2216 +       struct cvmx_npei_pkt_instr_enb_s {
2217 +               uint64_t reserved_32_63:32;
2218 +               uint64_t enb:32;
2219 +       } s;
2220 +       struct cvmx_npei_pkt_instr_enb_s cn52xx;
2221 +       struct cvmx_npei_pkt_instr_enb_s cn56xx;
2222 +       struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
2223 +};
2224 +
2225 +union cvmx_npei_pkt_instr_rd_size {
2226 +       uint64_t u64;
2227 +       struct cvmx_npei_pkt_instr_rd_size_s {
2228 +               uint64_t rdsize:64;
2229 +       } s;
2230 +       struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
2231 +       struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
2232 +};
2233 +
2234 +union cvmx_npei_pkt_instr_size {
2235 +       uint64_t u64;
2236 +       struct cvmx_npei_pkt_instr_size_s {
2237 +               uint64_t reserved_32_63:32;
2238 +               uint64_t is_64b:32;
2239 +       } s;
2240 +       struct cvmx_npei_pkt_instr_size_s cn52xx;
2241 +       struct cvmx_npei_pkt_instr_size_s cn56xx;
2242 +       struct cvmx_npei_pkt_instr_size_s cn56xxp1;
2243 +};
2244 +
2245 +union cvmx_npei_pkt_int_levels {
2246 +       uint64_t u64;
2247 +       struct cvmx_npei_pkt_int_levels_s {
2248 +               uint64_t reserved_54_63:10;
2249 +               uint64_t time:22;
2250 +               uint64_t cnt:32;
2251 +       } s;
2252 +       struct cvmx_npei_pkt_int_levels_s cn52xx;
2253 +       struct cvmx_npei_pkt_int_levels_s cn56xx;
2254 +       struct cvmx_npei_pkt_int_levels_s cn56xxp1;
2255 +};
2256 +
2257 +union cvmx_npei_pkt_iptr {
2258 +       uint64_t u64;
2259 +       struct cvmx_npei_pkt_iptr_s {
2260 +               uint64_t reserved_32_63:32;
2261 +               uint64_t iptr:32;
2262 +       } s;
2263 +       struct cvmx_npei_pkt_iptr_s cn52xx;
2264 +       struct cvmx_npei_pkt_iptr_s cn56xx;
2265 +       struct cvmx_npei_pkt_iptr_s cn56xxp1;
2266 +};
2267 +
2268 +union cvmx_npei_pkt_out_bmode {
2269 +       uint64_t u64;
2270 +       struct cvmx_npei_pkt_out_bmode_s {
2271 +               uint64_t reserved_32_63:32;
2272 +               uint64_t bmode:32;
2273 +       } s;
2274 +       struct cvmx_npei_pkt_out_bmode_s cn52xx;
2275 +       struct cvmx_npei_pkt_out_bmode_s cn56xx;
2276 +       struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
2277 +};
2278 +
2279 +union cvmx_npei_pkt_out_enb {
2280 +       uint64_t u64;
2281 +       struct cvmx_npei_pkt_out_enb_s {
2282 +               uint64_t reserved_32_63:32;
2283 +               uint64_t enb:32;
2284 +       } s;
2285 +       struct cvmx_npei_pkt_out_enb_s cn52xx;
2286 +       struct cvmx_npei_pkt_out_enb_s cn56xx;
2287 +       struct cvmx_npei_pkt_out_enb_s cn56xxp1;
2288 +};
2289 +
2290 +union cvmx_npei_pkt_output_wmark {
2291 +       uint64_t u64;
2292 +       struct cvmx_npei_pkt_output_wmark_s {
2293 +               uint64_t reserved_32_63:32;
2294 +               uint64_t wmark:32;
2295 +       } s;
2296 +       struct cvmx_npei_pkt_output_wmark_s cn52xx;
2297 +       struct cvmx_npei_pkt_output_wmark_s cn56xx;
2298 +};
2299 +
2300 +union cvmx_npei_pkt_pcie_port {
2301 +       uint64_t u64;
2302 +       struct cvmx_npei_pkt_pcie_port_s {
2303 +               uint64_t pp:64;
2304 +       } s;
2305 +       struct cvmx_npei_pkt_pcie_port_s cn52xx;
2306 +       struct cvmx_npei_pkt_pcie_port_s cn56xx;
2307 +       struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
2308 +};
2309 +
2310 +union cvmx_npei_pkt_port_in_rst {
2311 +       uint64_t u64;
2312 +       struct cvmx_npei_pkt_port_in_rst_s {
2313 +               uint64_t in_rst:32;
2314 +               uint64_t out_rst:32;
2315 +       } s;
2316 +       struct cvmx_npei_pkt_port_in_rst_s cn52xx;
2317 +       struct cvmx_npei_pkt_port_in_rst_s cn56xx;
2318 +};
2319 +
2320 +union cvmx_npei_pkt_slist_es {
2321 +       uint64_t u64;
2322 +       struct cvmx_npei_pkt_slist_es_s {
2323 +               uint64_t es:64;
2324 +       } s;
2325 +       struct cvmx_npei_pkt_slist_es_s cn52xx;
2326 +       struct cvmx_npei_pkt_slist_es_s cn56xx;
2327 +       struct cvmx_npei_pkt_slist_es_s cn56xxp1;
2328 +};
2329 +
2330 +union cvmx_npei_pkt_slist_id_size {
2331 +       uint64_t u64;
2332 +       struct cvmx_npei_pkt_slist_id_size_s {
2333 +               uint64_t reserved_23_63:41;
2334 +               uint64_t isize:7;
2335 +               uint64_t bsize:16;
2336 +       } s;
2337 +       struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2338 +       struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2339 +       struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
2340 +};
2341 +
2342 +union cvmx_npei_pkt_slist_ns {
2343 +       uint64_t u64;
2344 +       struct cvmx_npei_pkt_slist_ns_s {
2345 +               uint64_t reserved_32_63:32;
2346 +               uint64_t nsr:32;
2347 +       } s;
2348 +       struct cvmx_npei_pkt_slist_ns_s cn52xx;
2349 +       struct cvmx_npei_pkt_slist_ns_s cn56xx;
2350 +       struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
2351 +};
2352 +
2353 +union cvmx_npei_pkt_slist_ror {
2354 +       uint64_t u64;
2355 +       struct cvmx_npei_pkt_slist_ror_s {
2356 +               uint64_t reserved_32_63:32;
2357 +               uint64_t ror:32;
2358 +       } s;
2359 +       struct cvmx_npei_pkt_slist_ror_s cn52xx;
2360 +       struct cvmx_npei_pkt_slist_ror_s cn56xx;
2361 +       struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
2362 +};
2363 +
2364 +union cvmx_npei_pkt_time_int {
2365 +       uint64_t u64;
2366 +       struct cvmx_npei_pkt_time_int_s {
2367 +               uint64_t reserved_32_63:32;
2368 +               uint64_t port:32;
2369 +       } s;
2370 +       struct cvmx_npei_pkt_time_int_s cn52xx;
2371 +       struct cvmx_npei_pkt_time_int_s cn56xx;
2372 +       struct cvmx_npei_pkt_time_int_s cn56xxp1;
2373 +};
2374 +
2375 +union cvmx_npei_pkt_time_int_enb {
2376 +       uint64_t u64;
2377 +       struct cvmx_npei_pkt_time_int_enb_s {
2378 +               uint64_t reserved_32_63:32;
2379 +               uint64_t port:32;
2380 +       } s;
2381 +       struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2382 +       struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2383 +       struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
2384 +};
2385 +
2386 +union cvmx_npei_rsl_int_blocks {
2387 +       uint64_t u64;
2388 +       struct cvmx_npei_rsl_int_blocks_s {
2389 +               uint64_t reserved_31_63:33;
2390 +               uint64_t iob:1;
2391 +               uint64_t lmc1:1;
2392 +               uint64_t agl:1;
2393 +               uint64_t reserved_24_27:4;
2394 +               uint64_t asxpcs1:1;
2395 +               uint64_t asxpcs0:1;
2396 +               uint64_t reserved_21_21:1;
2397 +               uint64_t pip:1;
2398 +               uint64_t reserved_18_19:2;
2399 +               uint64_t lmc0:1;
2400 +               uint64_t l2c:1;
2401 +               uint64_t usb1:1;
2402 +               uint64_t rad:1;
2403 +               uint64_t usb:1;
2404 +               uint64_t pow:1;
2405 +               uint64_t tim:1;
2406 +               uint64_t pko:1;
2407 +               uint64_t ipd:1;
2408 +               uint64_t reserved_8_8:1;
2409 +               uint64_t zip:1;
2410 +               uint64_t reserved_6_6:1;
2411 +               uint64_t fpa:1;
2412 +               uint64_t key:1;
2413 +               uint64_t npei:1;
2414 +               uint64_t gmx1:1;
2415 +               uint64_t gmx0:1;
2416 +               uint64_t mio:1;
2417 +       } s;
2418 +       struct cvmx_npei_rsl_int_blocks_s cn52xx;
2419 +       struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2420 +       struct cvmx_npei_rsl_int_blocks_cn56xx {
2421 +               uint64_t reserved_31_63:33;
2422 +               uint64_t iob:1;
2423 +               uint64_t lmc1:1;
2424 +               uint64_t agl:1;
2425 +               uint64_t reserved_24_27:4;
2426 +               uint64_t asxpcs1:1;
2427 +               uint64_t asxpcs0:1;
2428 +               uint64_t reserved_21_21:1;
2429 +               uint64_t pip:1;
2430 +               uint64_t reserved_18_19:2;
2431 +               uint64_t lmc0:1;
2432 +               uint64_t l2c:1;
2433 +               uint64_t reserved_15_15:1;
2434 +               uint64_t rad:1;
2435 +               uint64_t usb:1;
2436 +               uint64_t pow:1;
2437 +               uint64_t tim:1;
2438 +               uint64_t pko:1;
2439 +               uint64_t ipd:1;
2440 +               uint64_t reserved_8_8:1;
2441 +               uint64_t zip:1;
2442 +               uint64_t reserved_6_6:1;
2443 +               uint64_t fpa:1;
2444 +               uint64_t key:1;
2445 +               uint64_t npei:1;
2446 +               uint64_t gmx1:1;
2447 +               uint64_t gmx0:1;
2448 +               uint64_t mio:1;
2449 +       } cn56xx;
2450 +       struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
2451 +};
2452 +
2453 +union cvmx_npei_scratch_1 {
2454 +       uint64_t u64;
2455 +       struct cvmx_npei_scratch_1_s {
2456 +               uint64_t data:64;
2457 +       } s;
2458 +       struct cvmx_npei_scratch_1_s cn52xx;
2459 +       struct cvmx_npei_scratch_1_s cn52xxp1;
2460 +       struct cvmx_npei_scratch_1_s cn56xx;
2461 +       struct cvmx_npei_scratch_1_s cn56xxp1;
2462 +};
2463 +
2464 +union cvmx_npei_state1 {
2465 +       uint64_t u64;
2466 +       struct cvmx_npei_state1_s {
2467 +               uint64_t cpl1:12;
2468 +               uint64_t cpl0:12;
2469 +               uint64_t arb:1;
2470 +               uint64_t csr:39;
2471 +       } s;
2472 +       struct cvmx_npei_state1_s cn52xx;
2473 +       struct cvmx_npei_state1_s cn52xxp1;
2474 +       struct cvmx_npei_state1_s cn56xx;
2475 +       struct cvmx_npei_state1_s cn56xxp1;
2476 +};
2477 +
2478 +union cvmx_npei_state2 {
2479 +       uint64_t u64;
2480 +       struct cvmx_npei_state2_s {
2481 +               uint64_t reserved_48_63:16;
2482 +               uint64_t npei:1;
2483 +               uint64_t rac:1;
2484 +               uint64_t csm1:15;
2485 +               uint64_t csm0:15;
2486 +               uint64_t nnp0:8;
2487 +               uint64_t nnd:8;
2488 +       } s;
2489 +       struct cvmx_npei_state2_s cn52xx;
2490 +       struct cvmx_npei_state2_s cn52xxp1;
2491 +       struct cvmx_npei_state2_s cn56xx;
2492 +       struct cvmx_npei_state2_s cn56xxp1;
2493 +};
2494 +
2495 +union cvmx_npei_state3 {
2496 +       uint64_t u64;
2497 +       struct cvmx_npei_state3_s {
2498 +               uint64_t reserved_56_63:8;
2499 +               uint64_t psm1:15;
2500 +               uint64_t psm0:15;
2501 +               uint64_t nsm1:13;
2502 +               uint64_t nsm0:13;
2503 +       } s;
2504 +       struct cvmx_npei_state3_s cn52xx;
2505 +       struct cvmx_npei_state3_s cn52xxp1;
2506 +       struct cvmx_npei_state3_s cn56xx;
2507 +       struct cvmx_npei_state3_s cn56xxp1;
2508 +};
2509 +
2510 +union cvmx_npei_win_rd_addr {
2511 +       uint64_t u64;
2512 +       struct cvmx_npei_win_rd_addr_s {
2513 +               uint64_t reserved_51_63:13;
2514 +               uint64_t ld_cmd:2;
2515 +               uint64_t iobit:1;
2516 +               uint64_t rd_addr:48;
2517 +       } s;
2518 +       struct cvmx_npei_win_rd_addr_s cn52xx;
2519 +       struct cvmx_npei_win_rd_addr_s cn52xxp1;
2520 +       struct cvmx_npei_win_rd_addr_s cn56xx;
2521 +       struct cvmx_npei_win_rd_addr_s cn56xxp1;
2522 +};
2523 +
2524 +union cvmx_npei_win_rd_data {
2525 +       uint64_t u64;
2526 +       struct cvmx_npei_win_rd_data_s {
2527 +               uint64_t rd_data:64;
2528 +       } s;
2529 +       struct cvmx_npei_win_rd_data_s cn52xx;
2530 +       struct cvmx_npei_win_rd_data_s cn52xxp1;
2531 +       struct cvmx_npei_win_rd_data_s cn56xx;
2532 +       struct cvmx_npei_win_rd_data_s cn56xxp1;
2533 +};
2534 +
2535 +union cvmx_npei_win_wr_addr {
2536 +       uint64_t u64;
2537 +       struct cvmx_npei_win_wr_addr_s {
2538 +               uint64_t reserved_49_63:15;
2539 +               uint64_t iobit:1;
2540 +               uint64_t wr_addr:46;
2541 +               uint64_t reserved_0_1:2;
2542 +       } s;
2543 +       struct cvmx_npei_win_wr_addr_s cn52xx;
2544 +       struct cvmx_npei_win_wr_addr_s cn52xxp1;
2545 +       struct cvmx_npei_win_wr_addr_s cn56xx;
2546 +       struct cvmx_npei_win_wr_addr_s cn56xxp1;
2547 +};
2548 +
2549 +union cvmx_npei_win_wr_data {
2550 +       uint64_t u64;
2551 +       struct cvmx_npei_win_wr_data_s {
2552 +               uint64_t wr_data:64;
2553 +       } s;
2554 +       struct cvmx_npei_win_wr_data_s cn52xx;
2555 +       struct cvmx_npei_win_wr_data_s cn52xxp1;
2556 +       struct cvmx_npei_win_wr_data_s cn56xx;
2557 +       struct cvmx_npei_win_wr_data_s cn56xxp1;
2558 +};
2559 +
2560 +union cvmx_npei_win_wr_mask {
2561 +       uint64_t u64;
2562 +       struct cvmx_npei_win_wr_mask_s {
2563 +               uint64_t reserved_8_63:56;
2564 +               uint64_t wr_mask:8;
2565 +       } s;
2566 +       struct cvmx_npei_win_wr_mask_s cn52xx;
2567 +       struct cvmx_npei_win_wr_mask_s cn52xxp1;
2568 +       struct cvmx_npei_win_wr_mask_s cn56xx;
2569 +       struct cvmx_npei_win_wr_mask_s cn56xxp1;
2570 +};
2571 +
2572 +union cvmx_npei_window_ctl {
2573 +       uint64_t u64;
2574 +       struct cvmx_npei_window_ctl_s {
2575 +               uint64_t reserved_32_63:32;
2576 +               uint64_t time:32;
2577 +       } s;
2578 +       struct cvmx_npei_window_ctl_s cn52xx;
2579 +       struct cvmx_npei_window_ctl_s cn52xxp1;
2580 +       struct cvmx_npei_window_ctl_s cn56xx;
2581 +       struct cvmx_npei_window_ctl_s cn56xxp1;
2582 +};
2583 +
2584 +#endif
2585 --- /dev/null
2586 +++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
2587 @@ -0,0 +1,1735 @@
2588 +/***********************license start***************
2589 + * Author: Cavium Networks
2590 + *
2591 + * Contact: support@caviumnetworks.com
2592 + * This file is part of the OCTEON SDK
2593 + *
2594 + * Copyright (c) 2003-2008 Cavium Networks
2595 + *
2596 + * This file is free software; you can redistribute it and/or modify
2597 + * it under the terms of the GNU General Public License, Version 2, as
2598 + * published by the Free Software Foundation.
2599 + *
2600 + * This file is distributed in the hope that it will be useful, but
2601 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
2602 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
2603 + * NONINFRINGEMENT.  See the GNU General Public License for more
2604 + * details.
2605 + *
2606 + * You should have received a copy of the GNU General Public License
2607 + * along with this file; if not, write to the Free Software
2608 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
2609 + * or visit http://www.gnu.org/licenses/.
2610 + *
2611 + * This file may also be available under a different license from Cavium.
2612 + * Contact Cavium Networks for more information
2613 + ***********************license end**************************************/
2614 +
2615 +#ifndef __CVMX_NPI_DEFS_H__
2616 +#define __CVMX_NPI_DEFS_H__
2617 +
2618 +#define CVMX_NPI_BASE_ADDR_INPUT0 \
2619 +        CVMX_ADD_IO_SEG(0x00011F0000000070ull)
2620 +#define CVMX_NPI_BASE_ADDR_INPUT1 \
2621 +        CVMX_ADD_IO_SEG(0x00011F0000000080ull)
2622 +#define CVMX_NPI_BASE_ADDR_INPUT2 \
2623 +        CVMX_ADD_IO_SEG(0x00011F0000000090ull)
2624 +#define CVMX_NPI_BASE_ADDR_INPUT3 \
2625 +        CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
2626 +#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
2627 +        CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
2628 +#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
2629 +        CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
2630 +#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
2631 +        CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
2632 +#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
2633 +        CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
2634 +#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
2635 +        CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
2636 +#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
2637 +        CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
2638 +#define CVMX_NPI_BIST_STATUS \
2639 +        CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
2640 +#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
2641 +        CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
2642 +#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
2643 +        CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
2644 +#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
2645 +        CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
2646 +#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
2647 +        CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
2648 +#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
2649 +        CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
2650 +#define CVMX_NPI_COMP_CTL \
2651 +        CVMX_ADD_IO_SEG(0x00011F0000000218ull)
2652 +#define CVMX_NPI_CTL_STATUS \
2653 +        CVMX_ADD_IO_SEG(0x00011F0000000010ull)
2654 +#define CVMX_NPI_DBG_SELECT \
2655 +        CVMX_ADD_IO_SEG(0x00011F0000000008ull)
2656 +#define CVMX_NPI_DMA_CONTROL \
2657 +        CVMX_ADD_IO_SEG(0x00011F0000000128ull)
2658 +#define CVMX_NPI_DMA_HIGHP_COUNTS \
2659 +        CVMX_ADD_IO_SEG(0x00011F0000000148ull)
2660 +#define CVMX_NPI_DMA_HIGHP_NADDR \
2661 +        CVMX_ADD_IO_SEG(0x00011F0000000158ull)
2662 +#define CVMX_NPI_DMA_LOWP_COUNTS \
2663 +        CVMX_ADD_IO_SEG(0x00011F0000000140ull)
2664 +#define CVMX_NPI_DMA_LOWP_NADDR \
2665 +        CVMX_ADD_IO_SEG(0x00011F0000000150ull)
2666 +#define CVMX_NPI_HIGHP_DBELL \
2667 +        CVMX_ADD_IO_SEG(0x00011F0000000120ull)
2668 +#define CVMX_NPI_HIGHP_IBUFF_SADDR \
2669 +        CVMX_ADD_IO_SEG(0x00011F0000000110ull)
2670 +#define CVMX_NPI_INPUT_CONTROL \
2671 +        CVMX_ADD_IO_SEG(0x00011F0000000138ull)
2672 +#define CVMX_NPI_INT_ENB \
2673 +        CVMX_ADD_IO_SEG(0x00011F0000000020ull)
2674 +#define CVMX_NPI_INT_SUM \
2675 +        CVMX_ADD_IO_SEG(0x00011F0000000018ull)
2676 +#define CVMX_NPI_LOWP_DBELL \
2677 +        CVMX_ADD_IO_SEG(0x00011F0000000118ull)
2678 +#define CVMX_NPI_LOWP_IBUFF_SADDR \
2679 +        CVMX_ADD_IO_SEG(0x00011F0000000108ull)
2680 +#define CVMX_NPI_MEM_ACCESS_SUBID3 \
2681 +        CVMX_ADD_IO_SEG(0x00011F0000000028ull)
2682 +#define CVMX_NPI_MEM_ACCESS_SUBID4 \
2683 +        CVMX_ADD_IO_SEG(0x00011F0000000030ull)
2684 +#define CVMX_NPI_MEM_ACCESS_SUBID5 \
2685 +        CVMX_ADD_IO_SEG(0x00011F0000000038ull)
2686 +#define CVMX_NPI_MEM_ACCESS_SUBID6 \
2687 +        CVMX_ADD_IO_SEG(0x00011F0000000040ull)
2688 +#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
2689 +        CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
2690 +#define CVMX_NPI_MSI_RCV \
2691 +        (0x0000000000000190ull)
2692 +#define CVMX_NPI_NPI_MSI_RCV \
2693 +        CVMX_ADD_IO_SEG(0x00011F0000001190ull)
2694 +#define CVMX_NPI_NUM_DESC_OUTPUT0 \
2695 +        CVMX_ADD_IO_SEG(0x00011F0000000050ull)
2696 +#define CVMX_NPI_NUM_DESC_OUTPUT1 \
2697 +        CVMX_ADD_IO_SEG(0x00011F0000000058ull)
2698 +#define CVMX_NPI_NUM_DESC_OUTPUT2 \
2699 +        CVMX_ADD_IO_SEG(0x00011F0000000060ull)
2700 +#define CVMX_NPI_NUM_DESC_OUTPUT3 \
2701 +        CVMX_ADD_IO_SEG(0x00011F0000000068ull)
2702 +#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
2703 +        CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
2704 +#define CVMX_NPI_OUTPUT_CONTROL \
2705 +        CVMX_ADD_IO_SEG(0x00011F0000000100ull)
2706 +#define CVMX_NPI_P0_DBPAIR_ADDR \
2707 +        CVMX_ADD_IO_SEG(0x00011F0000000180ull)
2708 +#define CVMX_NPI_P0_INSTR_ADDR \
2709 +        CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
2710 +#define CVMX_NPI_P0_INSTR_CNTS \
2711 +        CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
2712 +#define CVMX_NPI_P0_PAIR_CNTS \
2713 +        CVMX_ADD_IO_SEG(0x00011F0000000160ull)
2714 +#define CVMX_NPI_P1_DBPAIR_ADDR \
2715 +        CVMX_ADD_IO_SEG(0x00011F0000000188ull)
2716 +#define CVMX_NPI_P1_INSTR_ADDR \
2717 +        CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
2718 +#define CVMX_NPI_P1_INSTR_CNTS \
2719 +        CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
2720 +#define CVMX_NPI_P1_PAIR_CNTS \
2721 +        CVMX_ADD_IO_SEG(0x00011F0000000168ull)
2722 +#define CVMX_NPI_P2_DBPAIR_ADDR \
2723 +        CVMX_ADD_IO_SEG(0x00011F0000000190ull)
2724 +#define CVMX_NPI_P2_INSTR_ADDR \
2725 +        CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
2726 +#define CVMX_NPI_P2_INSTR_CNTS \
2727 +        CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
2728 +#define CVMX_NPI_P2_PAIR_CNTS \
2729 +        CVMX_ADD_IO_SEG(0x00011F0000000170ull)
2730 +#define CVMX_NPI_P3_DBPAIR_ADDR \
2731 +        CVMX_ADD_IO_SEG(0x00011F0000000198ull)
2732 +#define CVMX_NPI_P3_INSTR_ADDR \
2733 +        CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
2734 +#define CVMX_NPI_P3_INSTR_CNTS \
2735 +        CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
2736 +#define CVMX_NPI_P3_PAIR_CNTS \
2737 +        CVMX_ADD_IO_SEG(0x00011F0000000178ull)
2738 +#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
2739 +        CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
2740 +#define CVMX_NPI_PCI_BIST_REG \
2741 +        CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
2742 +#define CVMX_NPI_PCI_BURST_SIZE \
2743 +        CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
2744 +#define CVMX_NPI_PCI_CFG00 \
2745 +        CVMX_ADD_IO_SEG(0x00011F0000001800ull)
2746 +#define CVMX_NPI_PCI_CFG01 \
2747 +        CVMX_ADD_IO_SEG(0x00011F0000001804ull)
2748 +#define CVMX_NPI_PCI_CFG02 \
2749 +        CVMX_ADD_IO_SEG(0x00011F0000001808ull)
2750 +#define CVMX_NPI_PCI_CFG03 \
2751 +        CVMX_ADD_IO_SEG(0x00011F000000180Cull)
2752 +#define CVMX_NPI_PCI_CFG04 \
2753 +        CVMX_ADD_IO_SEG(0x00011F0000001810ull)
2754 +#define CVMX_NPI_PCI_CFG05 \
2755 +        CVMX_ADD_IO_SEG(0x00011F0000001814ull)
2756 +#define CVMX_NPI_PCI_CFG06 \
2757 +        CVMX_ADD_IO_SEG(0x00011F0000001818ull)
2758 +#define CVMX_NPI_PCI_CFG07 \
2759 +        CVMX_ADD_IO_SEG(0x00011F000000181Cull)
2760 +#define CVMX_NPI_PCI_CFG08 \
2761 +        CVMX_ADD_IO_SEG(0x00011F0000001820ull)
2762 +#define CVMX_NPI_PCI_CFG09 \
2763 +        CVMX_ADD_IO_SEG(0x00011F0000001824ull)
2764 +#define CVMX_NPI_PCI_CFG10 \
2765 +        CVMX_ADD_IO_SEG(0x00011F0000001828ull)
2766 +#define CVMX_NPI_PCI_CFG11 \
2767 +        CVMX_ADD_IO_SEG(0x00011F000000182Cull)
2768 +#define CVMX_NPI_PCI_CFG12 \
2769 +        CVMX_ADD_IO_SEG(0x00011F0000001830ull)
2770 +#define CVMX_NPI_PCI_CFG13 \
2771 +        CVMX_ADD_IO_SEG(0x00011F0000001834ull)
2772 +#define CVMX_NPI_PCI_CFG15 \
2773 +        CVMX_ADD_IO_SEG(0x00011F000000183Cull)
2774 +#define CVMX_NPI_PCI_CFG16 \
2775 +        CVMX_ADD_IO_SEG(0x00011F0000001840ull)
2776 +#define CVMX_NPI_PCI_CFG17 \
2777 +        CVMX_ADD_IO_SEG(0x00011F0000001844ull)
2778 +#define CVMX_NPI_PCI_CFG18 \
2779 +        CVMX_ADD_IO_SEG(0x00011F0000001848ull)
2780 +#define CVMX_NPI_PCI_CFG19 \
2781 +        CVMX_ADD_IO_SEG(0x00011F000000184Cull)
2782 +#define CVMX_NPI_PCI_CFG20 \
2783 +        CVMX_ADD_IO_SEG(0x00011F0000001850ull)
2784 +#define CVMX_NPI_PCI_CFG21 \
2785 +        CVMX_ADD_IO_SEG(0x00011F0000001854ull)
2786 +#define CVMX_NPI_PCI_CFG22 \
2787 +        CVMX_ADD_IO_SEG(0x00011F0000001858ull)
2788 +#define CVMX_NPI_PCI_CFG56 \
2789 +        CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
2790 +#define CVMX_NPI_PCI_CFG57 \
2791 +        CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
2792 +#define CVMX_NPI_PCI_CFG58 \
2793 +        CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
2794 +#define CVMX_NPI_PCI_CFG59 \
2795 +        CVMX_ADD_IO_SEG(0x00011F00000018ECull)
2796 +#define CVMX_NPI_PCI_CFG60 \
2797 +        CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
2798 +#define CVMX_NPI_PCI_CFG61 \
2799 +        CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
2800 +#define CVMX_NPI_PCI_CFG62 \
2801 +        CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
2802 +#define CVMX_NPI_PCI_CFG63 \
2803 +        CVMX_ADD_IO_SEG(0x00011F00000018FCull)
2804 +#define CVMX_NPI_PCI_CNT_REG \
2805 +        CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
2806 +#define CVMX_NPI_PCI_CTL_STATUS_2 \
2807 +        CVMX_ADD_IO_SEG(0x00011F000000118Cull)
2808 +#define CVMX_NPI_PCI_INT_ARB_CFG \
2809 +        CVMX_ADD_IO_SEG(0x00011F0000000130ull)
2810 +#define CVMX_NPI_PCI_INT_ENB2 \
2811 +        CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
2812 +#define CVMX_NPI_PCI_INT_SUM2 \
2813 +        CVMX_ADD_IO_SEG(0x00011F0000001198ull)
2814 +#define CVMX_NPI_PCI_READ_CMD \
2815 +        CVMX_ADD_IO_SEG(0x00011F0000000048ull)
2816 +#define CVMX_NPI_PCI_READ_CMD_6 \
2817 +        CVMX_ADD_IO_SEG(0x00011F0000001180ull)
2818 +#define CVMX_NPI_PCI_READ_CMD_C \
2819 +        CVMX_ADD_IO_SEG(0x00011F0000001184ull)
2820 +#define CVMX_NPI_PCI_READ_CMD_E \
2821 +        CVMX_ADD_IO_SEG(0x00011F0000001188ull)
2822 +#define CVMX_NPI_PCI_SCM_REG \
2823 +        CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
2824 +#define CVMX_NPI_PCI_TSR_REG \
2825 +        CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
2826 +#define CVMX_NPI_PORT32_INSTR_HDR \
2827 +        CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
2828 +#define CVMX_NPI_PORT33_INSTR_HDR \
2829 +        CVMX_ADD_IO_SEG(0x00011F0000000200ull)
2830 +#define CVMX_NPI_PORT34_INSTR_HDR \
2831 +        CVMX_ADD_IO_SEG(0x00011F0000000208ull)
2832 +#define CVMX_NPI_PORT35_INSTR_HDR \
2833 +        CVMX_ADD_IO_SEG(0x00011F0000000210ull)
2834 +#define CVMX_NPI_PORT_BP_CONTROL \
2835 +        CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
2836 +#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
2837 +        CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
2838 +#define CVMX_NPI_PX_INSTR_ADDR(offset) \
2839 +        CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
2840 +#define CVMX_NPI_PX_INSTR_CNTS(offset) \
2841 +        CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
2842 +#define CVMX_NPI_PX_PAIR_CNTS(offset) \
2843 +        CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
2844 +#define CVMX_NPI_RSL_INT_BLOCKS \
2845 +        CVMX_ADD_IO_SEG(0x00011F0000000000ull)
2846 +#define CVMX_NPI_SIZE_INPUT0 \
2847 +        CVMX_ADD_IO_SEG(0x00011F0000000078ull)
2848 +#define CVMX_NPI_SIZE_INPUT1 \
2849 +        CVMX_ADD_IO_SEG(0x00011F0000000088ull)
2850 +#define CVMX_NPI_SIZE_INPUT2 \
2851 +        CVMX_ADD_IO_SEG(0x00011F0000000098ull)
2852 +#define CVMX_NPI_SIZE_INPUT3 \
2853 +        CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
2854 +#define CVMX_NPI_SIZE_INPUTX(offset) \
2855 +        CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
2856 +#define CVMX_NPI_WIN_READ_TO \
2857 +        CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
2858 +
2859 +union cvmx_npi_base_addr_inputx {
2860 +       uint64_t u64;
2861 +       struct cvmx_npi_base_addr_inputx_s {
2862 +               uint64_t baddr:61;
2863 +               uint64_t reserved_0_2:3;
2864 +       } s;
2865 +       struct cvmx_npi_base_addr_inputx_s cn30xx;
2866 +       struct cvmx_npi_base_addr_inputx_s cn31xx;
2867 +       struct cvmx_npi_base_addr_inputx_s cn38xx;
2868 +       struct cvmx_npi_base_addr_inputx_s cn38xxp2;
2869 +       struct cvmx_npi_base_addr_inputx_s cn50xx;
2870 +       struct cvmx_npi_base_addr_inputx_s cn58xx;
2871 +       struct cvmx_npi_base_addr_inputx_s cn58xxp1;
2872 +};
2873 +
2874 +union cvmx_npi_base_addr_outputx {
2875 +       uint64_t u64;
2876 +       struct cvmx_npi_base_addr_outputx_s {
2877 +               uint64_t baddr:61;
2878 +               uint64_t reserved_0_2:3;
2879 +       } s;
2880 +       struct cvmx_npi_base_addr_outputx_s cn30xx;
2881 +       struct cvmx_npi_base_addr_outputx_s cn31xx;
2882 +       struct cvmx_npi_base_addr_outputx_s cn38xx;
2883 +       struct cvmx_npi_base_addr_outputx_s cn38xxp2;
2884 +       struct cvmx_npi_base_addr_outputx_s cn50xx;
2885 +       struct cvmx_npi_base_addr_outputx_s cn58xx;
2886 +       struct cvmx_npi_base_addr_outputx_s cn58xxp1;
2887 +};
2888 +
2889 +union cvmx_npi_bist_status {
2890 +       uint64_t u64;
2891 +       struct cvmx_npi_bist_status_s {
2892 +               uint64_t reserved_20_63:44;
2893 +               uint64_t csr_bs:1;
2894 +               uint64_t dif_bs:1;
2895 +               uint64_t rdp_bs:1;
2896 +               uint64_t pcnc_bs:1;
2897 +               uint64_t pcn_bs:1;
2898 +               uint64_t rdn_bs:1;
2899 +               uint64_t pcac_bs:1;
2900 +               uint64_t pcad_bs:1;
2901 +               uint64_t rdnl_bs:1;
2902 +               uint64_t pgf_bs:1;
2903 +               uint64_t pig_bs:1;
2904 +               uint64_t pof0_bs:1;
2905 +               uint64_t pof1_bs:1;
2906 +               uint64_t pof2_bs:1;
2907 +               uint64_t pof3_bs:1;
2908 +               uint64_t pos_bs:1;
2909 +               uint64_t nus_bs:1;
2910 +               uint64_t dob_bs:1;
2911 +               uint64_t pdf_bs:1;
2912 +               uint64_t dpi_bs:1;
2913 +       } s;
2914 +       struct cvmx_npi_bist_status_cn30xx {
2915 +               uint64_t reserved_20_63:44;
2916 +               uint64_t csr_bs:1;
2917 +               uint64_t dif_bs:1;
2918 +               uint64_t rdp_bs:1;
2919 +               uint64_t pcnc_bs:1;
2920 +               uint64_t pcn_bs:1;
2921 +               uint64_t rdn_bs:1;
2922 +               uint64_t pcac_bs:1;
2923 +               uint64_t pcad_bs:1;
2924 +               uint64_t rdnl_bs:1;
2925 +               uint64_t pgf_bs:1;
2926 +               uint64_t pig_bs:1;
2927 +               uint64_t pof0_bs:1;
2928 +               uint64_t reserved_5_7:3;
2929 +               uint64_t pos_bs:1;
2930 +               uint64_t nus_bs:1;
2931 +               uint64_t dob_bs:1;
2932 +               uint64_t pdf_bs:1;
2933 +               uint64_t dpi_bs:1;
2934 +       } cn30xx;
2935 +       struct cvmx_npi_bist_status_s cn31xx;
2936 +       struct cvmx_npi_bist_status_s cn38xx;
2937 +       struct cvmx_npi_bist_status_s cn38xxp2;
2938 +       struct cvmx_npi_bist_status_cn50xx {
2939 +               uint64_t reserved_20_63:44;
2940 +               uint64_t csr_bs:1;
2941 +               uint64_t dif_bs:1;
2942 +               uint64_t rdp_bs:1;
2943 +               uint64_t pcnc_bs:1;
2944 +               uint64_t pcn_bs:1;
2945 +               uint64_t rdn_bs:1;
2946 +               uint64_t pcac_bs:1;
2947 +               uint64_t pcad_bs:1;
2948 +               uint64_t rdnl_bs:1;
2949 +               uint64_t pgf_bs:1;
2950 +               uint64_t pig_bs:1;
2951 +               uint64_t pof0_bs:1;
2952 +               uint64_t pof1_bs:1;
2953 +               uint64_t reserved_5_6:2;
2954 +               uint64_t pos_bs:1;
2955 +               uint64_t nus_bs:1;
2956 +               uint64_t dob_bs:1;
2957 +               uint64_t pdf_bs:1;
2958 +               uint64_t dpi_bs:1;
2959 +       } cn50xx;
2960 +       struct cvmx_npi_bist_status_s cn58xx;
2961 +       struct cvmx_npi_bist_status_s cn58xxp1;
2962 +};
2963 +
2964 +union cvmx_npi_buff_size_outputx {
2965 +       uint64_t u64;
2966 +       struct cvmx_npi_buff_size_outputx_s {
2967 +               uint64_t reserved_23_63:41;
2968 +               uint64_t isize:7;
2969 +               uint64_t bsize:16;
2970 +       } s;
2971 +       struct cvmx_npi_buff_size_outputx_s cn30xx;
2972 +       struct cvmx_npi_buff_size_outputx_s cn31xx;
2973 +       struct cvmx_npi_buff_size_outputx_s cn38xx;
2974 +       struct cvmx_npi_buff_size_outputx_s cn38xxp2;
2975 +       struct cvmx_npi_buff_size_outputx_s cn50xx;
2976 +       struct cvmx_npi_buff_size_outputx_s cn58xx;
2977 +       struct cvmx_npi_buff_size_outputx_s cn58xxp1;
2978 +};
2979 +
2980 +union cvmx_npi_comp_ctl {
2981 +       uint64_t u64;
2982 +       struct cvmx_npi_comp_ctl_s {
2983 +               uint64_t reserved_10_63:54;
2984 +               uint64_t pctl:5;
2985 +               uint64_t nctl:5;
2986 +       } s;
2987 +       struct cvmx_npi_comp_ctl_s cn50xx;
2988 +       struct cvmx_npi_comp_ctl_s cn58xx;
2989 +       struct cvmx_npi_comp_ctl_s cn58xxp1;
2990 +};
2991 +
2992 +union cvmx_npi_ctl_status {
2993 +       uint64_t u64;
2994 +       struct cvmx_npi_ctl_status_s {
2995 +               uint64_t reserved_63_63:1;
2996 +               uint64_t chip_rev:8;
2997 +               uint64_t dis_pniw:1;
2998 +               uint64_t out3_enb:1;
2999 +               uint64_t out2_enb:1;
3000 +               uint64_t out1_enb:1;
3001 +               uint64_t out0_enb:1;
3002 +               uint64_t ins3_enb:1;
3003 +               uint64_t ins2_enb:1;
3004 +               uint64_t ins1_enb:1;
3005 +               uint64_t ins0_enb:1;
3006 +               uint64_t ins3_64b:1;
3007 +               uint64_t ins2_64b:1;
3008 +               uint64_t ins1_64b:1;
3009 +               uint64_t ins0_64b:1;
3010 +               uint64_t pci_wdis:1;
3011 +               uint64_t wait_com:1;
3012 +               uint64_t reserved_37_39:3;
3013 +               uint64_t max_word:5;
3014 +               uint64_t reserved_10_31:22;
3015 +               uint64_t timer:10;
3016 +       } s;
3017 +       struct cvmx_npi_ctl_status_cn30xx {
3018 +               uint64_t reserved_63_63:1;
3019 +               uint64_t chip_rev:8;
3020 +               uint64_t dis_pniw:1;
3021 +               uint64_t reserved_51_53:3;
3022 +               uint64_t out0_enb:1;
3023 +               uint64_t reserved_47_49:3;
3024 +               uint64_t ins0_enb:1;
3025 +               uint64_t reserved_43_45:3;
3026 +               uint64_t ins0_64b:1;
3027 +               uint64_t pci_wdis:1;
3028 +               uint64_t wait_com:1;
3029 +               uint64_t reserved_37_39:3;
3030 +               uint64_t max_word:5;
3031 +               uint64_t reserved_10_31:22;
3032 +               uint64_t timer:10;
3033 +       } cn30xx;
3034 +       struct cvmx_npi_ctl_status_cn31xx {
3035 +               uint64_t reserved_63_63:1;
3036 +               uint64_t chip_rev:8;
3037 +               uint64_t dis_pniw:1;
3038 +               uint64_t reserved_52_53:2;
3039 +               uint64_t out1_enb:1;
3040 +               uint64_t out0_enb:1;
3041 +               uint64_t reserved_48_49:2;
3042 +               uint64_t ins1_enb:1;
3043 +               uint64_t ins0_enb:1;
3044 +               uint64_t reserved_44_45:2;
3045 +               uint64_t ins1_64b:1;
3046 +               uint64_t ins0_64b:1;
3047 +               uint64_t pci_wdis:1;
3048 +               uint64_t wait_com:1;
3049 +               uint64_t reserved_37_39:3;
3050 +               uint64_t max_word:5;
3051 +               uint64_t reserved_10_31:22;
3052 +               uint64_t timer:10;
3053 +       } cn31xx;
3054 +       struct cvmx_npi_ctl_status_s cn38xx;
3055 +       struct cvmx_npi_ctl_status_s cn38xxp2;
3056 +       struct cvmx_npi_ctl_status_cn31xx cn50xx;
3057 +       struct cvmx_npi_ctl_status_s cn58xx;
3058 +       struct cvmx_npi_ctl_status_s cn58xxp1;
3059 +};
3060 +
3061 +union cvmx_npi_dbg_select {
3062 +       uint64_t u64;
3063 +       struct cvmx_npi_dbg_select_s {
3064 +               uint64_t reserved_16_63:48;
3065 +               uint64_t dbg_sel:16;
3066 +       } s;
3067 +       struct cvmx_npi_dbg_select_s cn30xx;
3068 +       struct cvmx_npi_dbg_select_s cn31xx;
3069 +       struct cvmx_npi_dbg_select_s cn38xx;
3070 +       struct cvmx_npi_dbg_select_s cn38xxp2;
3071 +       struct cvmx_npi_dbg_select_s cn50xx;
3072 +       struct cvmx_npi_dbg_select_s cn58xx;
3073 +       struct cvmx_npi_dbg_select_s cn58xxp1;
3074 +};
3075 +
3076 +union cvmx_npi_dma_control {
3077 +       uint64_t u64;
3078 +       struct cvmx_npi_dma_control_s {
3079 +               uint64_t reserved_36_63:28;
3080 +               uint64_t b0_lend:1;
3081 +               uint64_t dwb_denb:1;
3082 +               uint64_t dwb_ichk:9;
3083 +               uint64_t fpa_que:3;
3084 +               uint64_t o_add1:1;
3085 +               uint64_t o_ro:1;
3086 +               uint64_t o_ns:1;
3087 +               uint64_t o_es:2;
3088 +               uint64_t o_mode:1;
3089 +               uint64_t hp_enb:1;
3090 +               uint64_t lp_enb:1;
3091 +               uint64_t csize:14;
3092 +       } s;
3093 +       struct cvmx_npi_dma_control_s cn30xx;
3094 +       struct cvmx_npi_dma_control_s cn31xx;
3095 +       struct cvmx_npi_dma_control_s cn38xx;
3096 +       struct cvmx_npi_dma_control_s cn38xxp2;
3097 +       struct cvmx_npi_dma_control_s cn50xx;
3098 +       struct cvmx_npi_dma_control_s cn58xx;
3099 +       struct cvmx_npi_dma_control_s cn58xxp1;
3100 +};
3101 +
3102 +union cvmx_npi_dma_highp_counts {
3103 +       uint64_t u64;
3104 +       struct cvmx_npi_dma_highp_counts_s {
3105 +               uint64_t reserved_39_63:25;
3106 +               uint64_t fcnt:7;
3107 +               uint64_t dbell:32;
3108 +       } s;
3109 +       struct cvmx_npi_dma_highp_counts_s cn30xx;
3110 +       struct cvmx_npi_dma_highp_counts_s cn31xx;
3111 +       struct cvmx_npi_dma_highp_counts_s cn38xx;
3112 +       struct cvmx_npi_dma_highp_counts_s cn38xxp2;
3113 +       struct cvmx_npi_dma_highp_counts_s cn50xx;
3114 +       struct cvmx_npi_dma_highp_counts_s cn58xx;
3115 +       struct cvmx_npi_dma_highp_counts_s cn58xxp1;
3116 +};
3117 +
3118 +union cvmx_npi_dma_highp_naddr {
3119 +       uint64_t u64;
3120 +       struct cvmx_npi_dma_highp_naddr_s {
3121 +               uint64_t reserved_40_63:24;
3122 +               uint64_t state:4;
3123 +               uint64_t addr:36;
3124 +       } s;
3125 +       struct cvmx_npi_dma_highp_naddr_s cn30xx;
3126 +       struct cvmx_npi_dma_highp_naddr_s cn31xx;
3127 +       struct cvmx_npi_dma_highp_naddr_s cn38xx;
3128 +       struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
3129 +       struct cvmx_npi_dma_highp_naddr_s cn50xx;
3130 +       struct cvmx_npi_dma_highp_naddr_s cn58xx;
3131 +       struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
3132 +};
3133 +
3134 +union cvmx_npi_dma_lowp_counts {
3135 +       uint64_t u64;
3136 +       struct cvmx_npi_dma_lowp_counts_s {
3137 +               uint64_t reserved_39_63:25;
3138 +               uint64_t fcnt:7;
3139 +               uint64_t dbell:32;
3140 +       } s;
3141 +       struct cvmx_npi_dma_lowp_counts_s cn30xx;
3142 +       struct cvmx_npi_dma_lowp_counts_s cn31xx;
3143 +       struct cvmx_npi_dma_lowp_counts_s cn38xx;
3144 +       struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
3145 +       struct cvmx_npi_dma_lowp_counts_s cn50xx;
3146 +       struct cvmx_npi_dma_lowp_counts_s cn58xx;
3147 +       struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
3148 +};
3149 +
3150 +union cvmx_npi_dma_lowp_naddr {
3151 +       uint64_t u64;
3152 +       struct cvmx_npi_dma_lowp_naddr_s {
3153 +               uint64_t reserved_40_63:24;
3154 +               uint64_t state:4;
3155 +               uint64_t addr:36;
3156 +       } s;
3157 +       struct cvmx_npi_dma_lowp_naddr_s cn30xx;
3158 +       struct cvmx_npi_dma_lowp_naddr_s cn31xx;
3159 +       struct cvmx_npi_dma_lowp_naddr_s cn38xx;
3160 +       struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
3161 +       struct cvmx_npi_dma_lowp_naddr_s cn50xx;
3162 +       struct cvmx_npi_dma_lowp_naddr_s cn58xx;
3163 +       struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
3164 +};
3165 +
3166 +union cvmx_npi_highp_dbell {
3167 +       uint64_t u64;
3168 +       struct cvmx_npi_highp_dbell_s {
3169 +               uint64_t reserved_16_63:48;
3170 +               uint64_t dbell:16;
3171 +       } s;
3172 +       struct cvmx_npi_highp_dbell_s cn30xx;
3173 +       struct cvmx_npi_highp_dbell_s cn31xx;
3174 +       struct cvmx_npi_highp_dbell_s cn38xx;
3175 +       struct cvmx_npi_highp_dbell_s cn38xxp2;
3176 +       struct cvmx_npi_highp_dbell_s cn50xx;
3177 +       struct cvmx_npi_highp_dbell_s cn58xx;
3178 +       struct cvmx_npi_highp_dbell_s cn58xxp1;
3179 +};
3180 +
3181 +union cvmx_npi_highp_ibuff_saddr {
3182 +       uint64_t u64;
3183 +       struct cvmx_npi_highp_ibuff_saddr_s {
3184 +               uint64_t reserved_36_63:28;
3185 +               uint64_t saddr:36;
3186 +       } s;
3187 +       struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
3188 +       struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
3189 +       struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
3190 +       struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
3191 +       struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
3192 +       struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
3193 +       struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
3194 +};
3195 +
3196 +union cvmx_npi_input_control {
3197 +       uint64_t u64;
3198 +       struct cvmx_npi_input_control_s {
3199 +               uint64_t reserved_23_63:41;
3200 +               uint64_t pkt_rr:1;
3201 +               uint64_t pbp_dhi:13;
3202 +               uint64_t d_nsr:1;
3203 +               uint64_t d_esr:2;
3204 +               uint64_t d_ror:1;
3205 +               uint64_t use_csr:1;
3206 +               uint64_t nsr:1;
3207 +               uint64_t esr:2;
3208 +               uint64_t ror:1;
3209 +       } s;
3210 +       struct cvmx_npi_input_control_cn30xx {
3211 +               uint64_t reserved_22_63:42;
3212 +               uint64_t pbp_dhi:13;
3213 +               uint64_t d_nsr:1;
3214 +               uint64_t d_esr:2;
3215 +               uint64_t d_ror:1;
3216 +               uint64_t use_csr:1;
3217 +               uint64_t nsr:1;
3218 +               uint64_t esr:2;
3219 +               uint64_t ror:1;
3220 +       } cn30xx;
3221 +       struct cvmx_npi_input_control_cn30xx cn31xx;
3222 +       struct cvmx_npi_input_control_s cn38xx;
3223 +       struct cvmx_npi_input_control_cn30xx cn38xxp2;
3224 +       struct cvmx_npi_input_control_s cn50xx;
3225 +       struct cvmx_npi_input_control_s cn58xx;
3226 +       struct cvmx_npi_input_control_s cn58xxp1;
3227 +};
3228 +
3229 +union cvmx_npi_int_enb {
3230 +       uint64_t u64;
3231 +       struct cvmx_npi_int_enb_s {
3232 +               uint64_t reserved_62_63:2;
3233 +               uint64_t q1_a_f:1;
3234 +               uint64_t q1_s_e:1;
3235 +               uint64_t pdf_p_f:1;
3236 +               uint64_t pdf_p_e:1;
3237 +               uint64_t pcf_p_f:1;
3238 +               uint64_t pcf_p_e:1;
3239 +               uint64_t rdx_s_e:1;
3240 +               uint64_t rwx_s_e:1;
3241 +               uint64_t pnc_a_f:1;
3242 +               uint64_t pnc_s_e:1;
3243 +               uint64_t com_a_f:1;
3244 +               uint64_t com_s_e:1;
3245 +               uint64_t q3_a_f:1;
3246 +               uint64_t q3_s_e:1;
3247 +               uint64_t q2_a_f:1;
3248 +               uint64_t q2_s_e:1;
3249 +               uint64_t pcr_a_f:1;
3250 +               uint64_t pcr_s_e:1;
3251 +               uint64_t fcr_a_f:1;
3252 +               uint64_t fcr_s_e:1;
3253 +               uint64_t iobdma:1;
3254 +               uint64_t p_dperr:1;
3255 +               uint64_t win_rto:1;
3256 +               uint64_t i3_pperr:1;
3257 +               uint64_t i2_pperr:1;
3258 +               uint64_t i1_pperr:1;
3259 +               uint64_t i0_pperr:1;
3260 +               uint64_t p3_ptout:1;
3261 +               uint64_t p2_ptout:1;
3262 +               uint64_t p1_ptout:1;
3263 +               uint64_t p0_ptout:1;
3264 +               uint64_t p3_pperr:1;
3265 +               uint64_t p2_pperr:1;
3266 +               uint64_t p1_pperr:1;
3267 +               uint64_t p0_pperr:1;
3268 +               uint64_t g3_rtout:1;
3269 +               uint64_t g2_rtout:1;
3270 +               uint64_t g1_rtout:1;
3271 +               uint64_t g0_rtout:1;
3272 +               uint64_t p3_perr:1;
3273 +               uint64_t p2_perr:1;
3274 +               uint64_t p1_perr:1;
3275 +               uint64_t p0_perr:1;
3276 +               uint64_t p3_rtout:1;
3277 +               uint64_t p2_rtout:1;
3278 +               uint64_t p1_rtout:1;
3279 +               uint64_t p0_rtout:1;
3280 +               uint64_t i3_overf:1;
3281 +               uint64_t i2_overf:1;
3282 +               uint64_t i1_overf:1;
3283 +               uint64_t i0_overf:1;
3284 +               uint64_t i3_rtout:1;
3285 +               uint64_t i2_rtout:1;
3286 +               uint64_t i1_rtout:1;
3287 +               uint64_t i0_rtout:1;
3288 +               uint64_t po3_2sml:1;
3289 +               uint64_t po2_2sml:1;
3290 +               uint64_t po1_2sml:1;
3291 +               uint64_t po0_2sml:1;
3292 +               uint64_t pci_rsl:1;
3293 +               uint64_t rml_wto:1;
3294 +               uint64_t rml_rto:1;
3295 +       } s;
3296 +       struct cvmx_npi_int_enb_cn30xx {
3297 +               uint64_t reserved_62_63:2;
3298 +               uint64_t q1_a_f:1;
3299 +               uint64_t q1_s_e:1;
3300 +               uint64_t pdf_p_f:1;
3301 +               uint64_t pdf_p_e:1;
3302 +               uint64_t pcf_p_f:1;
3303 +               uint64_t pcf_p_e:1;
3304 +               uint64_t rdx_s_e:1;
3305 +               uint64_t rwx_s_e:1;
3306 +               uint64_t pnc_a_f:1;
3307 +               uint64_t pnc_s_e:1;
3308 +               uint64_t com_a_f:1;
3309 +               uint64_t com_s_e:1;
3310 +               uint64_t q3_a_f:1;
3311 +               uint64_t q3_s_e:1;
3312 +               uint64_t q2_a_f:1;
3313 +               uint64_t q2_s_e:1;
3314 +               uint64_t pcr_a_f:1;
3315 +               uint64_t pcr_s_e:1;
3316 +               uint64_t fcr_a_f:1;
3317 +               uint64_t fcr_s_e:1;
3318 +               uint64_t iobdma:1;
3319 +               uint64_t p_dperr:1;
3320 +               uint64_t win_rto:1;
3321 +               uint64_t reserved_36_38:3;
3322 +               uint64_t i0_pperr:1;
3323 +               uint64_t reserved_32_34:3;
3324 +               uint64_t p0_ptout:1;
3325 +               uint64_t reserved_28_30:3;
3326 +               uint64_t p0_pperr:1;
3327 +               uint64_t reserved_24_26:3;
3328 +               uint64_t g0_rtout:1;
3329 +               uint64_t reserved_20_22:3;
3330 +               uint64_t p0_perr:1;
3331 +               uint64_t reserved_16_18:3;
3332 +               uint64_t p0_rtout:1;
3333 +               uint64_t reserved_12_14:3;
3334 +               uint64_t i0_overf:1;
3335 +               uint64_t reserved_8_10:3;
3336 +               uint64_t i0_rtout:1;
3337 +               uint64_t reserved_4_6:3;
3338 +               uint64_t po0_2sml:1;
3339 +               uint64_t pci_rsl:1;
3340 +               uint64_t rml_wto:1;
3341 +               uint64_t rml_rto:1;
3342 +       } cn30xx;
3343 +       struct cvmx_npi_int_enb_cn31xx {
3344 +               uint64_t reserved_62_63:2;
3345 +               uint64_t q1_a_f:1;
3346 +               uint64_t q1_s_e:1;
3347 +               uint64_t pdf_p_f:1;
3348 +               uint64_t pdf_p_e:1;
3349 +               uint64_t pcf_p_f:1;
3350 +               uint64_t pcf_p_e:1;
3351 +               uint64_t rdx_s_e:1;
3352 +               uint64_t rwx_s_e:1;
3353 +               uint64_t pnc_a_f:1;
3354 +               uint64_t pnc_s_e:1;
3355 +               uint64_t com_a_f:1;
3356 +               uint64_t com_s_e:1;
3357 +               uint64_t q3_a_f:1;
3358 +               uint64_t q3_s_e:1;
3359 +               uint64_t q2_a_f:1;
3360 +               uint64_t q2_s_e:1;
3361 +               uint64_t pcr_a_f:1;
3362 +               uint64_t pcr_s_e:1;
3363 +               uint64_t fcr_a_f:1;
3364 +               uint64_t fcr_s_e:1;
3365 +               uint64_t iobdma:1;
3366 +               uint64_t p_dperr:1;
3367 +               uint64_t win_rto:1;
3368 +               uint64_t reserved_37_38:2;
3369 +               uint64_t i1_pperr:1;
3370 +               uint64_t i0_pperr:1;
3371 +               uint64_t reserved_33_34:2;
3372 +               uint64_t p1_ptout:1;
3373 +               uint64_t p0_ptout:1;
3374 +               uint64_t reserved_29_30:2;
3375 +               uint64_t p1_pperr:1;
3376 +               uint64_t p0_pperr:1;
3377 +               uint64_t reserved_25_26:2;
3378 +               uint64_t g1_rtout:1;
3379 +               uint64_t g0_rtout:1;
3380 +               uint64_t reserved_21_22:2;
3381 +               uint64_t p1_perr:1;
3382 +               uint64_t p0_perr:1;
3383 +               uint64_t reserved_17_18:2;
3384 +               uint64_t p1_rtout:1;
3385 +               uint64_t p0_rtout:1;
3386 +               uint64_t reserved_13_14:2;
3387 +               uint64_t i1_overf:1;
3388 +               uint64_t i0_overf:1;
3389 +               uint64_t reserved_9_10:2;
3390 +               uint64_t i1_rtout:1;
3391 +               uint64_t i0_rtout:1;
3392 +               uint64_t reserved_5_6:2;
3393 +               uint64_t po1_2sml:1;
3394 +               uint64_t po0_2sml:1;
3395 +               uint64_t pci_rsl:1;
3396 +               uint64_t rml_wto:1;
3397 +               uint64_t rml_rto:1;
3398 +       } cn31xx;
3399 +       struct cvmx_npi_int_enb_s cn38xx;
3400 +       struct cvmx_npi_int_enb_cn38xxp2 {
3401 +               uint64_t reserved_42_63:22;
3402 +               uint64_t iobdma:1;
3403 +               uint64_t p_dperr:1;
3404 +               uint64_t win_rto:1;
3405 +               uint64_t i3_pperr:1;
3406 +               uint64_t i2_pperr:1;
3407 +               uint64_t i1_pperr:1;
3408 +               uint64_t i0_pperr:1;
3409 +               uint64_t p3_ptout:1;
3410 +               uint64_t p2_ptout:1;
3411 +               uint64_t p1_ptout:1;
3412 +               uint64_t p0_ptout:1;
3413 +               uint64_t p3_pperr:1;
3414 +               uint64_t p2_pperr:1;
3415 +               uint64_t p1_pperr:1;
3416 +               uint64_t p0_pperr:1;
3417 +               uint64_t g3_rtout:1;
3418 +               uint64_t g2_rtout:1;
3419 +               uint64_t g1_rtout:1;
3420 +               uint64_t g0_rtout:1;
3421 +               uint64_t p3_perr:1;
3422 +               uint64_t p2_perr:1;
3423 +               uint64_t p1_perr:1;
3424 +               uint64_t p0_perr:1;
3425 +               uint64_t p3_rtout:1;
3426 +               uint64_t p2_rtout:1;
3427 +               uint64_t p1_rtout:1;
3428 +               uint64_t p0_rtout:1;
3429 +               uint64_t i3_overf:1;
3430 +               uint64_t i2_overf:1;
3431 +               uint64_t i1_overf:1;
3432 +               uint64_t i0_overf:1;
3433 +               uint64_t i3_rtout:1;
3434 +               uint64_t i2_rtout:1;
3435 +               uint64_t i1_rtout:1;
3436 +               uint64_t i0_rtout:1;
3437 +               uint64_t po3_2sml:1;
3438 +               uint64_t po2_2sml:1;
3439 +               uint64_t po1_2sml:1;
3440 +               uint64_t po0_2sml:1;
3441 +               uint64_t pci_rsl:1;
3442 +               uint64_t rml_wto:1;
3443 +               uint64_t rml_rto:1;
3444 +       } cn38xxp2;
3445 +       struct cvmx_npi_int_enb_cn31xx cn50xx;
3446 +       struct cvmx_npi_int_enb_s cn58xx;
3447 +       struct cvmx_npi_int_enb_s cn58xxp1;
3448 +};
3449 +
3450 +union cvmx_npi_int_sum {
3451 +       uint64_t u64;
3452 +       struct cvmx_npi_int_sum_s {
3453 +               uint64_t reserved_62_63:2;
3454 +               uint64_t q1_a_f:1;
3455 +               uint64_t q1_s_e:1;
3456 +               uint64_t pdf_p_f:1;
3457 +               uint64_t pdf_p_e:1;
3458 +               uint64_t pcf_p_f:1;
3459 +               uint64_t pcf_p_e:1;
3460 +               uint64_t rdx_s_e:1;
3461 +               uint64_t rwx_s_e:1;
3462 +               uint64_t pnc_a_f:1;
3463 +               uint64_t pnc_s_e:1;
3464 +               uint64_t com_a_f:1;
3465 +               uint64_t com_s_e:1;
3466 +               uint64_t q3_a_f:1;
3467 +               uint64_t q3_s_e:1;
3468 +               uint64_t q2_a_f:1;
3469 +               uint64_t q2_s_e:1;
3470 +               uint64_t pcr_a_f:1;
3471 +               uint64_t pcr_s_e:1;
3472 +               uint64_t fcr_a_f:1;
3473 +               uint64_t fcr_s_e:1;
3474 +               uint64_t iobdma:1;
3475 +               uint64_t p_dperr:1;
3476 +               uint64_t win_rto:1;
3477 +               uint64_t i3_pperr:1;
3478 +               uint64_t i2_pperr:1;
3479 +               uint64_t i1_pperr:1;
3480 +               uint64_t i0_pperr:1;
3481 +               uint64_t p3_ptout:1;
3482 +               uint64_t p2_ptout:1;
3483 +               uint64_t p1_ptout:1;
3484 +               uint64_t p0_ptout:1;
3485 +               uint64_t p3_pperr:1;
3486 +               uint64_t p2_pperr:1;
3487 +               uint64_t p1_pperr:1;
3488 +               uint64_t p0_pperr:1;
3489 +               uint64_t g3_rtout:1;
3490 +               uint64_t g2_rtout:1;
3491 +               uint64_t g1_rtout:1;
3492 +               uint64_t g0_rtout:1;
3493 +               uint64_t p3_perr:1;
3494 +               uint64_t p2_perr:1;
3495 +               uint64_t p1_perr:1;
3496 +               uint64_t p0_perr:1;
3497 +               uint64_t p3_rtout:1;
3498 +               uint64_t p2_rtout:1;
3499 +               uint64_t p1_rtout:1;
3500 +               uint64_t p0_rtout:1;
3501 +               uint64_t i3_overf:1;
3502 +               uint64_t i2_overf:1;
3503 +               uint64_t i1_overf:1;
3504 +               uint64_t i0_overf:1;
3505 +               uint64_t i3_rtout:1;
3506 +               uint64_t i2_rtout:1;
3507 +               uint64_t i1_rtout:1;
3508 +               uint64_t i0_rtout:1;
3509 +               uint64_t po3_2sml:1;
3510 +               uint64_t po2_2sml:1;
3511 +               uint64_t po1_2sml:1;
3512 +               uint64_t po0_2sml:1;
3513 +               uint64_t pci_rsl:1;
3514 +               uint64_t rml_wto:1;
3515 +               uint64_t rml_rto:1;
3516 +       } s;
3517 +       struct cvmx_npi_int_sum_cn30xx {
3518 +               uint64_t reserved_62_63:2;
3519 +               uint64_t q1_a_f:1;
3520 +               uint64_t q1_s_e:1;
3521 +               uint64_t pdf_p_f:1;
3522 +               uint64_t pdf_p_e:1;
3523 +               uint64_t pcf_p_f:1;
3524 +               uint64_t pcf_p_e:1;
3525 +               uint64_t rdx_s_e:1;
3526 +               uint64_t rwx_s_e:1;
3527 +               uint64_t pnc_a_f:1;
3528 +               uint64_t pnc_s_e:1;
3529 +               uint64_t com_a_f:1;
3530 +               uint64_t com_s_e:1;
3531 +               uint64_t q3_a_f:1;
3532 +               uint64_t q3_s_e:1;
3533 +               uint64_t q2_a_f:1;
3534 +               uint64_t q2_s_e:1;
3535 +               uint64_t pcr_a_f:1;
3536 +               uint64_t pcr_s_e:1;
3537 +               uint64_t fcr_a_f:1;
3538 +               uint64_t fcr_s_e:1;
3539 +               uint64_t iobdma:1;
3540 +               uint64_t p_dperr:1;
3541 +               uint64_t win_rto:1;
3542 +               uint64_t reserved_36_38:3;
3543 +               uint64_t i0_pperr:1;
3544 +               uint64_t reserved_32_34:3;
3545 +               uint64_t p0_ptout:1;
3546 +               uint64_t reserved_28_30:3;
3547 +               uint64_t p0_pperr:1;
3548 +               uint64_t reserved_24_26:3;
3549 +               uint64_t g0_rtout:1;
3550 +               uint64_t reserved_20_22:3;
3551 +               uint64_t p0_perr:1;
3552 +               uint64_t reserved_16_18:3;
3553 +               uint64_t p0_rtout:1;
3554 +               uint64_t reserved_12_14:3;
3555 +               uint64_t i0_overf:1;
3556 +               uint64_t reserved_8_10:3;
3557 +               uint64_t i0_rtout:1;
3558 +               uint64_t reserved_4_6:3;
3559 +               uint64_t po0_2sml:1;
3560 +               uint64_t pci_rsl:1;
3561 +               uint64_t rml_wto:1;
3562 +               uint64_t rml_rto:1;
3563 +       } cn30xx;
3564 +       struct cvmx_npi_int_sum_cn31xx {
3565 +               uint64_t reserved_62_63:2;
3566 +               uint64_t q1_a_f:1;
3567 +               uint64_t q1_s_e:1;
3568 +               uint64_t pdf_p_f:1;
3569 +               uint64_t pdf_p_e:1;
3570 +               uint64_t pcf_p_f:1;
3571 +               uint64_t pcf_p_e:1;
3572 +               uint64_t rdx_s_e:1;
3573 +               uint64_t rwx_s_e:1;
3574 +               uint64_t pnc_a_f:1;
3575 +               uint64_t pnc_s_e:1;
3576 +               uint64_t com_a_f:1;
3577 +               uint64_t com_s_e:1;
3578 +               uint64_t q3_a_f:1;
3579 +               uint64_t q3_s_e:1;
3580 +               uint64_t q2_a_f:1;
3581 +               uint64_t q2_s_e:1;
3582 +               uint64_t pcr_a_f:1;
3583 +               uint64_t pcr_s_e:1;
3584 +               uint64_t fcr_a_f:1;
3585 +               uint64_t fcr_s_e:1;
3586 +               uint64_t iobdma:1;
3587 +               uint64_t p_dperr:1;
3588 +               uint64_t win_rto:1;
3589 +               uint64_t reserved_37_38:2;
3590 +               uint64_t i1_pperr:1;
3591 +               uint64_t i0_pperr:1;
3592 +               uint64_t reserved_33_34:2;
3593 +               uint64_t p1_ptout:1;
3594 +               uint64_t p0_ptout:1;
3595 +               uint64_t reserved_29_30:2;
3596 +               uint64_t p1_pperr:1;
3597 +               uint64_t p0_pperr:1;
3598 +               uint64_t reserved_25_26:2;
3599 +               uint64_t g1_rtout:1;
3600 +               uint64_t g0_rtout:1;
3601 +               uint64_t reserved_21_22:2;
3602 +               uint64_t p1_perr:1;
3603 +               uint64_t p0_perr:1;
3604 +               uint64_t reserved_17_18:2;
3605 +               uint64_t p1_rtout:1;
3606 +               uint64_t p0_rtout:1;
3607 +               uint64_t reserved_13_14:2;
3608 +               uint64_t i1_overf:1;
3609 +               uint64_t i0_overf:1;
3610 +               uint64_t reserved_9_10:2;
3611 +               uint64_t i1_rtout:1;
3612 +               uint64_t i0_rtout:1;
3613 +               uint64_t reserved_5_6:2;
3614 +               uint64_t po1_2sml:1;
3615 +               uint64_t po0_2sml:1;
3616 +               uint64_t pci_rsl:1;
3617 +               uint64_t rml_wto:1;
3618 +               uint64_t rml_rto:1;
3619 +       } cn31xx;
3620 +       struct cvmx_npi_int_sum_s cn38xx;
3621 +       struct cvmx_npi_int_sum_cn38xxp2 {
3622 +               uint64_t reserved_42_63:22;
3623 +               uint64_t iobdma:1;
3624 +               uint64_t p_dperr:1;
3625 +               uint64_t win_rto:1;
3626 +               uint64_t i3_pperr:1;
3627 +               uint64_t i2_pperr:1;
3628 +               uint64_t i1_pperr:1;
3629 +               uint64_t i0_pperr:1;
3630 +               uint64_t p3_ptout:1;
3631 +               uint64_t p2_ptout:1;
3632 +               uint64_t p1_ptout:1;
3633 +               uint64_t p0_ptout:1;
3634 +               uint64_t p3_pperr:1;
3635 +               uint64_t p2_pperr:1;
3636 +               uint64_t p1_pperr:1;
3637 +               uint64_t p0_pperr:1;
3638 +               uint64_t g3_rtout:1;
3639 +               uint64_t g2_rtout:1;
3640 +               uint64_t g1_rtout:1;
3641 +               uint64_t g0_rtout:1;
3642 +               uint64_t p3_perr:1;
3643 +               uint64_t p2_perr:1;
3644 +               uint64_t p1_perr:1;
3645 +               uint64_t p0_perr:1;
3646 +               uint64_t p3_rtout:1;
3647 +               uint64_t p2_rtout:1;
3648 +               uint64_t p1_rtout:1;
3649 +               uint64_t p0_rtout:1;
3650 +               uint64_t i3_overf:1;
3651 +               uint64_t i2_overf:1;
3652 +               uint64_t i1_overf:1;
3653 +               uint64_t i0_overf:1;
3654 +               uint64_t i3_rtout:1;
3655 +               uint64_t i2_rtout:1;
3656 +               uint64_t i1_rtout:1;
3657 +               uint64_t i0_rtout:1;
3658 +               uint64_t po3_2sml:1;
3659 +               uint64_t po2_2sml:1;
3660 +               uint64_t po1_2sml:1;
3661 +               uint64_t po0_2sml:1;
3662 +               uint64_t pci_rsl:1;
3663 +               uint64_t rml_wto:1;
3664 +               uint64_t rml_rto:1;
3665 +       } cn38xxp2;
3666 +       struct cvmx_npi_int_sum_cn31xx cn50xx;
3667 +       struct cvmx_npi_int_sum_s cn58xx;
3668 +       struct cvmx_npi_int_sum_s cn58xxp1;
3669 +};
3670 +
3671 +union cvmx_npi_lowp_dbell {
3672 +       uint64_t u64;
3673 +       struct cvmx_npi_lowp_dbell_s {
3674 +               uint64_t reserved_16_63:48;
3675 +               uint64_t dbell:16;
3676 +       } s;
3677 +       struct cvmx_npi_lowp_dbell_s cn30xx;
3678 +       struct cvmx_npi_lowp_dbell_s cn31xx;
3679 +       struct cvmx_npi_lowp_dbell_s cn38xx;
3680 +       struct cvmx_npi_lowp_dbell_s cn38xxp2;
3681 +       struct cvmx_npi_lowp_dbell_s cn50xx;
3682 +       struct cvmx_npi_lowp_dbell_s cn58xx;
3683 +       struct cvmx_npi_lowp_dbell_s cn58xxp1;
3684 +};
3685 +
3686 +union cvmx_npi_lowp_ibuff_saddr {
3687 +       uint64_t u64;
3688 +       struct cvmx_npi_lowp_ibuff_saddr_s {
3689 +               uint64_t reserved_36_63:28;
3690 +               uint64_t saddr:36;
3691 +       } s;
3692 +       struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
3693 +       struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
3694 +       struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
3695 +       struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
3696 +       struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
3697 +       struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
3698 +       struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
3699 +};
3700 +
3701 +union cvmx_npi_mem_access_subidx {
3702 +       uint64_t u64;
3703 +       struct cvmx_npi_mem_access_subidx_s {
3704 +               uint64_t reserved_38_63:26;
3705 +               uint64_t shortl:1;
3706 +               uint64_t nmerge:1;
3707 +               uint64_t esr:2;
3708 +               uint64_t esw:2;
3709 +               uint64_t nsr:1;
3710 +               uint64_t nsw:1;
3711 +               uint64_t ror:1;
3712 +               uint64_t row:1;
3713 +               uint64_t ba:28;
3714 +       } s;
3715 +       struct cvmx_npi_mem_access_subidx_s cn30xx;
3716 +       struct cvmx_npi_mem_access_subidx_cn31xx {
3717 +               uint64_t reserved_36_63:28;
3718 +               uint64_t esr:2;
3719 +               uint64_t esw:2;
3720 +               uint64_t nsr:1;
3721 +               uint64_t nsw:1;
3722 +               uint64_t ror:1;
3723 +               uint64_t row:1;
3724 +               uint64_t ba:28;
3725 +       } cn31xx;
3726 +       struct cvmx_npi_mem_access_subidx_s cn38xx;
3727 +       struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
3728 +       struct cvmx_npi_mem_access_subidx_s cn50xx;
3729 +       struct cvmx_npi_mem_access_subidx_s cn58xx;
3730 +       struct cvmx_npi_mem_access_subidx_s cn58xxp1;
3731 +};
3732 +
3733 +union cvmx_npi_msi_rcv {
3734 +       uint64_t u64;
3735 +       struct cvmx_npi_msi_rcv_s {
3736 +               uint64_t int_vec:64;
3737 +       } s;
3738 +       struct cvmx_npi_msi_rcv_s cn30xx;
3739 +       struct cvmx_npi_msi_rcv_s cn31xx;
3740 +       struct cvmx_npi_msi_rcv_s cn38xx;
3741 +       struct cvmx_npi_msi_rcv_s cn38xxp2;
3742 +       struct cvmx_npi_msi_rcv_s cn50xx;
3743 +       struct cvmx_npi_msi_rcv_s cn58xx;
3744 +       struct cvmx_npi_msi_rcv_s cn58xxp1;
3745 +};
3746 +
3747 +union cvmx_npi_num_desc_outputx {
3748 +       uint64_t u64;
3749 +       struct cvmx_npi_num_desc_outputx_s {
3750 +               uint64_t reserved_32_63:32;
3751 +               uint64_t size:32;
3752 +       } s;
3753 +       struct cvmx_npi_num_desc_outputx_s cn30xx;
3754 +       struct cvmx_npi_num_desc_outputx_s cn31xx;
3755 +       struct cvmx_npi_num_desc_outputx_s cn38xx;
3756 +       struct cvmx_npi_num_desc_outputx_s cn38xxp2;
3757 +       struct cvmx_npi_num_desc_outputx_s cn50xx;
3758 +       struct cvmx_npi_num_desc_outputx_s cn58xx;
3759 +       struct cvmx_npi_num_desc_outputx_s cn58xxp1;
3760 +};
3761 +
3762 +union cvmx_npi_output_control {
3763 +       uint64_t u64;
3764 +       struct cvmx_npi_output_control_s {
3765 +               uint64_t reserved_49_63:15;
3766 +               uint64_t pkt_rr:1;
3767 +               uint64_t p3_bmode:1;
3768 +               uint64_t p2_bmode:1;
3769 +               uint64_t p1_bmode:1;
3770 +               uint64_t p0_bmode:1;
3771 +               uint64_t o3_es:2;
3772 +               uint64_t o3_ns:1;
3773 +               uint64_t o3_ro:1;
3774 +               uint64_t o2_es:2;
3775 +               uint64_t o2_ns:1;
3776 +               uint64_t o2_ro:1;
3777 +               uint64_t o1_es:2;
3778 +               uint64_t o1_ns:1;
3779 +               uint64_t o1_ro:1;
3780 +               uint64_t o0_es:2;
3781 +               uint64_t o0_ns:1;
3782 +               uint64_t o0_ro:1;
3783 +               uint64_t o3_csrm:1;
3784 +               uint64_t o2_csrm:1;
3785 +               uint64_t o1_csrm:1;
3786 +               uint64_t o0_csrm:1;
3787 +               uint64_t reserved_20_23:4;
3788 +               uint64_t iptr_o3:1;
3789 +               uint64_t iptr_o2:1;
3790 +               uint64_t iptr_o1:1;
3791 +               uint64_t iptr_o0:1;
3792 +               uint64_t esr_sl3:2;
3793 +               uint64_t nsr_sl3:1;
3794 +               uint64_t ror_sl3:1;
3795 +               uint64_t esr_sl2:2;
3796 +               uint64_t nsr_sl2:1;
3797 +               uint64_t ror_sl2:1;
3798 +               uint64_t esr_sl1:2;
3799 +               uint64_t nsr_sl1:1;
3800 +               uint64_t ror_sl1:1;
3801 +               uint64_t esr_sl0:2;
3802 +               uint64_t nsr_sl0:1;
3803 +               uint64_t ror_sl0:1;
3804 +       } s;
3805 +       struct cvmx_npi_output_control_cn30xx {
3806 +               uint64_t reserved_45_63:19;
3807 +               uint64_t p0_bmode:1;
3808 +               uint64_t reserved_32_43:12;
3809 +               uint64_t o0_es:2;
3810 +               uint64_t o0_ns:1;
3811 +               uint64_t o0_ro:1;
3812 +               uint64_t reserved_25_27:3;
3813 +               uint64_t o0_csrm:1;
3814 +               uint64_t reserved_17_23:7;
3815 +               uint64_t iptr_o0:1;
3816 +               uint64_t reserved_4_15:12;
3817 +               uint64_t esr_sl0:2;
3818 +               uint64_t nsr_sl0:1;
3819 +               uint64_t ror_sl0:1;
3820 +       } cn30xx;
3821 +       struct cvmx_npi_output_control_cn31xx {
3822 +               uint64_t reserved_46_63:18;
3823 +               uint64_t p1_bmode:1;
3824 +               uint64_t p0_bmode:1;
3825 +               uint64_t reserved_36_43:8;
3826 +               uint64_t o1_es:2;
3827 +               uint64_t o1_ns:1;
3828 +               uint64_t o1_ro:1;
3829 +               uint64_t o0_es:2;
3830 +               uint64_t o0_ns:1;
3831 +               uint64_t o0_ro:1;
3832 +               uint64_t reserved_26_27:2;
3833 +               uint64_t o1_csrm:1;
3834 +               uint64_t o0_csrm:1;
3835 +               uint64_t reserved_18_23:6;
3836 +               uint64_t iptr_o1:1;
3837 +               uint64_t iptr_o0:1;
3838 +               uint64_t reserved_8_15:8;
3839 +               uint64_t esr_sl1:2;
3840 +               uint64_t nsr_sl1:1;
3841 +               uint64_t ror_sl1:1;
3842 +               uint64_t esr_sl0:2;
3843 +               uint64_t nsr_sl0:1;
3844 +               uint64_t ror_sl0:1;
3845 +       } cn31xx;
3846 +       struct cvmx_npi_output_control_s cn38xx;
3847 +       struct cvmx_npi_output_control_cn38xxp2 {
3848 +               uint64_t reserved_48_63:16;
3849 +               uint64_t p3_bmode:1;
3850 +               uint64_t p2_bmode:1;
3851 +               uint64_t p1_bmode:1;
3852 +               uint64_t p0_bmode:1;
3853 +               uint64_t o3_es:2;
3854 +               uint64_t o3_ns:1;
3855 +               uint64_t o3_ro:1;
3856 +               uint64_t o2_es:2;
3857 +               uint64_t o2_ns:1;
3858 +               uint64_t o2_ro:1;
3859 +               uint64_t o1_es:2;
3860 +               uint64_t o1_ns:1;
3861 +               uint64_t o1_ro:1;
3862 +               uint64_t o0_es:2;
3863 +               uint64_t o0_ns:1;
3864 +               uint64_t o0_ro:1;
3865 +               uint64_t o3_csrm:1;
3866 +               uint64_t o2_csrm:1;
3867 +               uint64_t o1_csrm:1;
3868 +               uint64_t o0_csrm:1;
3869 +               uint64_t reserved_20_23:4;
3870 +               uint64_t iptr_o3:1;
3871 +               uint64_t iptr_o2:1;
3872 +               uint64_t iptr_o1:1;
3873 +               uint64_t iptr_o0:1;
3874 +               uint64_t esr_sl3:2;
3875 +               uint64_t nsr_sl3:1;
3876 +               uint64_t ror_sl3:1;
3877 +               uint64_t esr_sl2:2;
3878 +               uint64_t nsr_sl2:1;
3879 +               uint64_t ror_sl2:1;
3880 +               uint64_t esr_sl1:2;
3881 +               uint64_t nsr_sl1:1;
3882 +               uint64_t ror_sl1:1;
3883 +               uint64_t esr_sl0:2;
3884 +               uint64_t nsr_sl0:1;
3885 +               uint64_t ror_sl0:1;
3886 +       } cn38xxp2;
3887 +       struct cvmx_npi_output_control_cn50xx {
3888 +               uint64_t reserved_49_63:15;
3889 +               uint64_t pkt_rr:1;
3890 +               uint64_t reserved_46_47:2;
3891 +               uint64_t p1_bmode:1;
3892 +               uint64_t p0_bmode:1;
3893 +               uint64_t reserved_36_43:8;
3894 +               uint64_t o1_es:2;
3895 +               uint64_t o1_ns:1;
3896 +               uint64_t o1_ro:1;
3897 +               uint64_t o0_es:2;
3898 +               uint64_t o0_ns:1;
3899 +               uint64_t o0_ro:1;
3900 +               uint64_t reserved_26_27:2;
3901 +               uint64_t o1_csrm:1;
3902 +               uint64_t o0_csrm:1;
3903 +               uint64_t reserved_18_23:6;
3904 +               uint64_t iptr_o1:1;
3905 +               uint64_t iptr_o0:1;
3906 +               uint64_t reserved_8_15:8;
3907 +               uint64_t esr_sl1:2;
3908 +               uint64_t nsr_sl1:1;
3909 +               uint64_t ror_sl1:1;
3910 +               uint64_t esr_sl0:2;
3911 +               uint64_t nsr_sl0:1;
3912 +               uint64_t ror_sl0:1;
3913 +       } cn50xx;
3914 +       struct cvmx_npi_output_control_s cn58xx;
3915 +       struct cvmx_npi_output_control_s cn58xxp1;
3916 +};
3917 +
3918 +union cvmx_npi_px_dbpair_addr {
3919 +       uint64_t u64;
3920 +       struct cvmx_npi_px_dbpair_addr_s {
3921 +               uint64_t reserved_63_63:1;
3922 +               uint64_t state:2;
3923 +               uint64_t naddr:61;
3924 +       } s;
3925 +       struct cvmx_npi_px_dbpair_addr_s cn30xx;
3926 +       struct cvmx_npi_px_dbpair_addr_s cn31xx;
3927 +       struct cvmx_npi_px_dbpair_addr_s cn38xx;
3928 +       struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
3929 +       struct cvmx_npi_px_dbpair_addr_s cn50xx;
3930 +       struct cvmx_npi_px_dbpair_addr_s cn58xx;
3931 +       struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
3932 +};
3933 +
3934 +union cvmx_npi_px_instr_addr {
3935 +       uint64_t u64;
3936 +       struct cvmx_npi_px_instr_addr_s {
3937 +               uint64_t state:3;
3938 +               uint64_t naddr:61;
3939 +       } s;
3940 +       struct cvmx_npi_px_instr_addr_s cn30xx;
3941 +       struct cvmx_npi_px_instr_addr_s cn31xx;
3942 +       struct cvmx_npi_px_instr_addr_s cn38xx;
3943 +       struct cvmx_npi_px_instr_addr_s cn38xxp2;
3944 +       struct cvmx_npi_px_instr_addr_s cn50xx;
3945 +       struct cvmx_npi_px_instr_addr_s cn58xx;
3946 +       struct cvmx_npi_px_instr_addr_s cn58xxp1;
3947 +};
3948 +
3949 +union cvmx_npi_px_instr_cnts {
3950 +       uint64_t u64;
3951 +       struct cvmx_npi_px_instr_cnts_s {
3952 +               uint64_t reserved_38_63:26;
3953 +               uint64_t fcnt:6;
3954 +               uint64_t avail:32;
3955 +       } s;
3956 +       struct cvmx_npi_px_instr_cnts_s cn30xx;
3957 +       struct cvmx_npi_px_instr_cnts_s cn31xx;
3958 +       struct cvmx_npi_px_instr_cnts_s cn38xx;
3959 +       struct cvmx_npi_px_instr_cnts_s cn38xxp2;
3960 +       struct cvmx_npi_px_instr_cnts_s cn50xx;
3961 +       struct cvmx_npi_px_instr_cnts_s cn58xx;
3962 +       struct cvmx_npi_px_instr_cnts_s cn58xxp1;
3963 +};
3964 +
3965 +union cvmx_npi_px_pair_cnts {
3966 +       uint64_t u64;
3967 +       struct cvmx_npi_px_pair_cnts_s {
3968 +               uint64_t reserved_37_63:27;
3969 +               uint64_t fcnt:5;
3970 +               uint64_t avail:32;
3971 +       } s;
3972 +       struct cvmx_npi_px_pair_cnts_s cn30xx;
3973 +       struct cvmx_npi_px_pair_cnts_s cn31xx;
3974 +       struct cvmx_npi_px_pair_cnts_s cn38xx;
3975 +       struct cvmx_npi_px_pair_cnts_s cn38xxp2;
3976 +       struct cvmx_npi_px_pair_cnts_s cn50xx;
3977 +       struct cvmx_npi_px_pair_cnts_s cn58xx;
3978 +       struct cvmx_npi_px_pair_cnts_s cn58xxp1;
3979 +};
3980 +
3981 +union cvmx_npi_pci_burst_size {
3982 +       uint64_t u64;
3983 +       struct cvmx_npi_pci_burst_size_s {
3984 +               uint64_t reserved_14_63:50;
3985 +               uint64_t wr_brst:7;
3986 +               uint64_t rd_brst:7;
3987 +       } s;
3988 +       struct cvmx_npi_pci_burst_size_s cn30xx;
3989 +       struct cvmx_npi_pci_burst_size_s cn31xx;
3990 +       struct cvmx_npi_pci_burst_size_s cn38xx;
3991 +       struct cvmx_npi_pci_burst_size_s cn38xxp2;
3992 +       struct cvmx_npi_pci_burst_size_s cn50xx;
3993 +       struct cvmx_npi_pci_burst_size_s cn58xx;
3994 +       struct cvmx_npi_pci_burst_size_s cn58xxp1;
3995 +};
3996 +
3997 +union cvmx_npi_pci_int_arb_cfg {
3998 +       uint64_t u64;
3999 +       struct cvmx_npi_pci_int_arb_cfg_s {
4000 +               uint64_t reserved_13_63:51;
4001 +               uint64_t hostmode:1;
4002 +               uint64_t pci_ovr:4;
4003 +               uint64_t reserved_5_7:3;
4004 +               uint64_t en:1;
4005 +               uint64_t park_mod:1;
4006 +               uint64_t park_dev:3;
4007 +       } s;
4008 +       struct cvmx_npi_pci_int_arb_cfg_cn30xx {
4009 +               uint64_t reserved_5_63:59;
4010 +               uint64_t en:1;
4011 +               uint64_t park_mod:1;
4012 +               uint64_t park_dev:3;
4013 +       } cn30xx;
4014 +       struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
4015 +       struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
4016 +       struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
4017 +       struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
4018 +       struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
4019 +       struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
4020 +};
4021 +
4022 +union cvmx_npi_pci_read_cmd {
4023 +       uint64_t u64;
4024 +       struct cvmx_npi_pci_read_cmd_s {
4025 +               uint64_t reserved_11_63:53;
4026 +               uint64_t cmd_size:11;
4027 +       } s;
4028 +       struct cvmx_npi_pci_read_cmd_s cn30xx;
4029 +       struct cvmx_npi_pci_read_cmd_s cn31xx;
4030 +       struct cvmx_npi_pci_read_cmd_s cn38xx;
4031 +       struct cvmx_npi_pci_read_cmd_s cn38xxp2;
4032 +       struct cvmx_npi_pci_read_cmd_s cn50xx;
4033 +       struct cvmx_npi_pci_read_cmd_s cn58xx;
4034 +       struct cvmx_npi_pci_read_cmd_s cn58xxp1;
4035 +};
4036 +
4037 +union cvmx_npi_port32_instr_hdr {
4038 +       uint64_t u64;
4039 +       struct cvmx_npi_port32_instr_hdr_s {
4040 +               uint64_t reserved_44_63:20;
4041 +               uint64_t pbp:1;
4042 +               uint64_t rsv_f:5;
4043 +               uint64_t rparmode:2;
4044 +               uint64_t rsv_e:1;
4045 +               uint64_t rskp_len:7;
4046 +               uint64_t rsv_d:6;
4047 +               uint64_t use_ihdr:1;
4048 +               uint64_t rsv_c:5;
4049 +               uint64_t par_mode:2;
4050 +               uint64_t rsv_b:1;
4051 +               uint64_t skp_len:7;
4052 +               uint64_t rsv_a:6;
4053 +       } s;
4054 +       struct cvmx_npi_port32_instr_hdr_s cn30xx;
4055 +       struct cvmx_npi_port32_instr_hdr_s cn31xx;
4056 +       struct cvmx_npi_port32_instr_hdr_s cn38xx;
4057 +       struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
4058 +       struct cvmx_npi_port32_instr_hdr_s cn50xx;
4059 +       struct cvmx_npi_port32_instr_hdr_s cn58xx;
4060 +       struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
4061 +};
4062 +
4063 +union cvmx_npi_port33_instr_hdr {
4064 +       uint64_t u64;
4065 +       struct cvmx_npi_port33_instr_hdr_s {
4066 +               uint64_t reserved_44_63:20;
4067 +               uint64_t pbp:1;
4068 +               uint64_t rsv_f:5;
4069 +               uint64_t rparmode:2;
4070 +               uint64_t rsv_e:1;
4071 +               uint64_t rskp_len:7;
4072 +               uint64_t rsv_d:6;
4073 +               uint64_t use_ihdr:1;
4074 +               uint64_t rsv_c:5;
4075 +               uint64_t par_mode:2;
4076 +               uint64_t rsv_b:1;
4077 +               uint64_t skp_len:7;
4078 +               uint64_t rsv_a:6;
4079 +       } s;
4080 +       struct cvmx_npi_port33_instr_hdr_s cn31xx;
4081 +       struct cvmx_npi_port33_instr_hdr_s cn38xx;
4082 +       struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
4083 +       struct cvmx_npi_port33_instr_hdr_s cn50xx;
4084 +       struct cvmx_npi_port33_instr_hdr_s cn58xx;
4085 +       struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
4086 +};
4087 +
4088 +union cvmx_npi_port34_instr_hdr {
4089 +       uint64_t u64;
4090 +       struct cvmx_npi_port34_instr_hdr_s {
4091 +               uint64_t reserved_44_63:20;
4092 +               uint64_t pbp:1;
4093 +               uint64_t rsv_f:5;
4094 +               uint64_t rparmode:2;
4095 +               uint64_t rsv_e:1;
4096 +               uint64_t rskp_len:7;
4097 +               uint64_t rsv_d:6;
4098 +               uint64_t use_ihdr:1;
4099 +               uint64_t rsv_c:5;
4100 +               uint64_t par_mode:2;
4101 +               uint64_t rsv_b:1;
4102 +               uint64_t skp_len:7;
4103 +               uint64_t rsv_a:6;
4104 +       } s;
4105 +       struct cvmx_npi_port34_instr_hdr_s cn38xx;
4106 +       struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
4107 +       struct cvmx_npi_port34_instr_hdr_s cn58xx;
4108 +       struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
4109 +};
4110 +
4111 +union cvmx_npi_port35_instr_hdr {
4112 +       uint64_t u64;
4113 +       struct cvmx_npi_port35_instr_hdr_s {
4114 +               uint64_t reserved_44_63:20;
4115 +               uint64_t pbp:1;
4116 +               uint64_t rsv_f:5;
4117 +               uint64_t rparmode:2;
4118 +               uint64_t rsv_e:1;
4119 +               uint64_t rskp_len:7;
4120 +               uint64_t rsv_d:6;
4121 +               uint64_t use_ihdr:1;
4122 +               uint64_t rsv_c:5;
4123 +               uint64_t par_mode:2;
4124 +               uint64_t rsv_b:1;
4125 +               uint64_t skp_len:7;
4126 +               uint64_t rsv_a:6;
4127 +       } s;
4128 +       struct cvmx_npi_port35_instr_hdr_s cn38xx;
4129 +       struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
4130 +       struct cvmx_npi_port35_instr_hdr_s cn58xx;
4131 +       struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
4132 +};
4133 +
4134 +union cvmx_npi_port_bp_control {
4135 +       uint64_t u64;
4136 +       struct cvmx_npi_port_bp_control_s {
4137 +               uint64_t reserved_8_63:56;
4138 +               uint64_t bp_on:4;
4139 +               uint64_t enb:4;
4140 +       } s;
4141 +       struct cvmx_npi_port_bp_control_s cn30xx;
4142 +       struct cvmx_npi_port_bp_control_s cn31xx;
4143 +       struct cvmx_npi_port_bp_control_s cn38xx;
4144 +       struct cvmx_npi_port_bp_control_s cn38xxp2;
4145 +       struct cvmx_npi_port_bp_control_s cn50xx;
4146 +       struct cvmx_npi_port_bp_control_s cn58xx;
4147 +       struct cvmx_npi_port_bp_control_s cn58xxp1;
4148 +};
4149 +
4150 +union cvmx_npi_rsl_int_blocks {
4151 +       uint64_t u64;
4152 +       struct cvmx_npi_rsl_int_blocks_s {
4153 +               uint64_t reserved_32_63:32;
4154 +               uint64_t rint_31:1;
4155 +               uint64_t iob:1;
4156 +               uint64_t reserved_28_29:2;
4157 +               uint64_t rint_27:1;
4158 +               uint64_t rint_26:1;
4159 +               uint64_t rint_25:1;
4160 +               uint64_t rint_24:1;
4161 +               uint64_t asx1:1;
4162 +               uint64_t asx0:1;
4163 +               uint64_t rint_21:1;
4164 +               uint64_t pip:1;
4165 +               uint64_t spx1:1;
4166 +               uint64_t spx0:1;
4167 +               uint64_t lmc:1;
4168 +               uint64_t l2c:1;
4169 +               uint64_t rint_15:1;
4170 +               uint64_t reserved_13_14:2;
4171 +               uint64_t pow:1;
4172 +               uint64_t tim:1;
4173 +               uint64_t pko:1;
4174 +               uint64_t ipd:1;
4175 +               uint64_t rint_8:1;
4176 +               uint64_t zip:1;
4177 +               uint64_t dfa:1;
4178 +               uint64_t fpa:1;
4179 +               uint64_t key:1;
4180 +               uint64_t npi:1;
4181 +               uint64_t gmx1:1;
4182 +               uint64_t gmx0:1;
4183 +               uint64_t mio:1;
4184 +       } s;
4185 +       struct cvmx_npi_rsl_int_blocks_cn30xx {
4186 +               uint64_t reserved_32_63:32;
4187 +               uint64_t rint_31:1;
4188 +               uint64_t iob:1;
4189 +               uint64_t rint_29:1;
4190 +               uint64_t rint_28:1;
4191 +               uint64_t rint_27:1;
4192 +               uint64_t rint_26:1;
4193 +               uint64_t rint_25:1;
4194 +               uint64_t rint_24:1;
4195 +               uint64_t asx1:1;
4196 +               uint64_t asx0:1;
4197 +               uint64_t rint_21:1;
4198 +               uint64_t pip:1;
4199 +               uint64_t spx1:1;
4200 +               uint64_t spx0:1;
4201 +               uint64_t lmc:1;
4202 +               uint64_t l2c:1;
4203 +               uint64_t rint_15:1;
4204 +               uint64_t rint_14:1;
4205 +               uint64_t usb:1;
4206 +               uint64_t pow:1;
4207 +               uint64_t tim:1;
4208 +               uint64_t pko:1;
4209 +               uint64_t ipd:1;
4210 +               uint64_t rint_8:1;
4211 +               uint64_t zip:1;
4212 +               uint64_t dfa:1;
4213 +               uint64_t fpa:1;
4214 +               uint64_t key:1;
4215 +               uint64_t npi:1;
4216 +               uint64_t gmx1:1;
4217 +               uint64_t gmx0:1;
4218 +               uint64_t mio:1;
4219 +       } cn30xx;
4220 +       struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
4221 +       struct cvmx_npi_rsl_int_blocks_cn38xx {
4222 +               uint64_t reserved_32_63:32;
4223 +               uint64_t rint_31:1;
4224 +               uint64_t iob:1;
4225 +               uint64_t rint_29:1;
4226 +               uint64_t rint_28:1;
4227 +               uint64_t rint_27:1;
4228 +               uint64_t rint_26:1;
4229 +               uint64_t rint_25:1;
4230 +               uint64_t rint_24:1;
4231 +               uint64_t asx1:1;
4232 +               uint64_t asx0:1;
4233 +               uint64_t rint_21:1;
4234 +               uint64_t pip:1;
4235 +               uint64_t spx1:1;
4236 +               uint64_t spx0:1;
4237 +               uint64_t lmc:1;
4238 +               uint64_t l2c:1;
4239 +               uint64_t rint_15:1;
4240 +               uint64_t rint_14:1;
4241 +               uint64_t rint_13:1;
4242 +               uint64_t pow:1;
4243 +               uint64_t tim:1;
4244 +               uint64_t pko:1;
4245 +               uint64_t ipd:1;
4246 +               uint64_t rint_8:1;
4247 +               uint64_t zip:1;
4248 +               uint64_t dfa:1;
4249 +               uint64_t fpa:1;
4250 +               uint64_t key:1;
4251 +               uint64_t npi:1;
4252 +               uint64_t gmx1:1;
4253 +               uint64_t gmx0:1;
4254 +               uint64_t mio:1;
4255 +       } cn38xx;
4256 +       struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
4257 +       struct cvmx_npi_rsl_int_blocks_cn50xx {
4258 +               uint64_t reserved_31_63:33;
4259 +               uint64_t iob:1;
4260 +               uint64_t lmc1:1;
4261 +               uint64_t agl:1;
4262 +               uint64_t reserved_24_27:4;
4263 +               uint64_t asx1:1;
4264 +               uint64_t asx0:1;
4265 +               uint64_t reserved_21_21:1;
4266 +               uint64_t pip:1;
4267 +               uint64_t spx1:1;
4268 +               uint64_t spx0:1;
4269 +               uint64_t lmc:1;
4270 +               uint64_t l2c:1;
4271 +               uint64_t reserved_15_15:1;
4272 +               uint64_t rad:1;
4273 +               uint64_t usb:1;
4274 +               uint64_t pow:1;
4275 +               uint64_t tim:1;
4276 +               uint64_t pko:1;
4277 +               uint64_t ipd:1;
4278 +               uint64_t reserved_8_8:1;
4279 +               uint64_t zip:1;
4280 +               uint64_t dfa:1;
4281 +               uint64_t fpa:1;
4282 +               uint64_t key:1;
4283 +               uint64_t npi:1;
4284 +               uint64_t gmx1:1;
4285 +               uint64_t gmx0:1;
4286 +               uint64_t mio:1;
4287 +       } cn50xx;
4288 +       struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
4289 +       struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
4290 +};
4291 +
4292 +union cvmx_npi_size_inputx {
4293 +       uint64_t u64;
4294 +       struct cvmx_npi_size_inputx_s {
4295 +               uint64_t reserved_32_63:32;
4296 +               uint64_t size:32;
4297 +       } s;
4298 +       struct cvmx_npi_size_inputx_s cn30xx;
4299 +       struct cvmx_npi_size_inputx_s cn31xx;
4300 +       struct cvmx_npi_size_inputx_s cn38xx;
4301 +       struct cvmx_npi_size_inputx_s cn38xxp2;
4302 +       struct cvmx_npi_size_inputx_s cn50xx;
4303 +       struct cvmx_npi_size_inputx_s cn58xx;
4304 +       struct cvmx_npi_size_inputx_s cn58xxp1;
4305 +};
4306 +
4307 +union cvmx_npi_win_read_to {
4308 +       uint64_t u64;
4309 +       struct cvmx_npi_win_read_to_s {
4310 +               uint64_t reserved_32_63:32;
4311 +               uint64_t time:32;
4312 +       } s;
4313 +       struct cvmx_npi_win_read_to_s cn30xx;
4314 +       struct cvmx_npi_win_read_to_s cn31xx;
4315 +       struct cvmx_npi_win_read_to_s cn38xx;
4316 +       struct cvmx_npi_win_read_to_s cn38xxp2;
4317 +       struct cvmx_npi_win_read_to_s cn50xx;
4318 +       struct cvmx_npi_win_read_to_s cn58xx;
4319 +       struct cvmx_npi_win_read_to_s cn58xxp1;
4320 +};
4321 +
4322 +#endif
4323 --- /dev/null
4324 +++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
4325 @@ -0,0 +1,1645 @@
4326 +/***********************license start***************
4327 + * Author: Cavium Networks
4328 + *
4329 + * Contact: support@caviumnetworks.com
4330 + * This file is part of the OCTEON SDK
4331 + *
4332 + * Copyright (c) 2003-2008 Cavium Networks
4333 + *
4334 + * This file is free software; you can redistribute it and/or modify
4335 + * it under the terms of the GNU General Public License, Version 2, as
4336 + * published by the Free Software Foundation.
4337 + *
4338 + * This file is distributed in the hope that it will be useful, but
4339 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4340 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4341 + * NONINFRINGEMENT.  See the GNU General Public License for more
4342 + * details.
4343 + *
4344 + * You should have received a copy of the GNU General Public License
4345 + * along with this file; if not, write to the Free Software
4346 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4347 + * or visit http://www.gnu.org/licenses/.
4348 + *
4349 + * This file may also be available under a different license from Cavium.
4350 + * Contact Cavium Networks for more information
4351 + ***********************license end**************************************/
4352 +
4353 +#ifndef __CVMX_PCI_DEFS_H__
4354 +#define __CVMX_PCI_DEFS_H__
4355 +
4356 +#define CVMX_PCI_BAR1_INDEXX(offset) \
4357 +        (0x0000000000000100ull + (((offset) & 31) * 4))
4358 +#define CVMX_PCI_BIST_REG \
4359 +        (0x00000000000001C0ull)
4360 +#define CVMX_PCI_CFG00 \
4361 +        (0x0000000000000000ull)
4362 +#define CVMX_PCI_CFG01 \
4363 +        (0x0000000000000004ull)
4364 +#define CVMX_PCI_CFG02 \
4365 +        (0x0000000000000008ull)
4366 +#define CVMX_PCI_CFG03 \
4367 +        (0x000000000000000Cull)
4368 +#define CVMX_PCI_CFG04 \
4369 +        (0x0000000000000010ull)
4370 +#define CVMX_PCI_CFG05 \
4371 +        (0x0000000000000014ull)
4372 +#define CVMX_PCI_CFG06 \
4373 +        (0x0000000000000018ull)
4374 +#define CVMX_PCI_CFG07 \
4375 +        (0x000000000000001Cull)
4376 +#define CVMX_PCI_CFG08 \
4377 +        (0x0000000000000020ull)
4378 +#define CVMX_PCI_CFG09 \
4379 +        (0x0000000000000024ull)
4380 +#define CVMX_PCI_CFG10 \
4381 +        (0x0000000000000028ull)
4382 +#define CVMX_PCI_CFG11 \
4383 +        (0x000000000000002Cull)
4384 +#define CVMX_PCI_CFG12 \
4385 +        (0x0000000000000030ull)
4386 +#define CVMX_PCI_CFG13 \
4387 +        (0x0000000000000034ull)
4388 +#define CVMX_PCI_CFG15 \
4389 +        (0x000000000000003Cull)
4390 +#define CVMX_PCI_CFG16 \
4391 +        (0x0000000000000040ull)
4392 +#define CVMX_PCI_CFG17 \
4393 +        (0x0000000000000044ull)
4394 +#define CVMX_PCI_CFG18 \
4395 +        (0x0000000000000048ull)
4396 +#define CVMX_PCI_CFG19 \
4397 +        (0x000000000000004Cull)
4398 +#define CVMX_PCI_CFG20 \
4399 +        (0x0000000000000050ull)
4400 +#define CVMX_PCI_CFG21 \
4401 +        (0x0000000000000054ull)
4402 +#define CVMX_PCI_CFG22 \
4403 +        (0x0000000000000058ull)
4404 +#define CVMX_PCI_CFG56 \
4405 +        (0x00000000000000E0ull)
4406 +#define CVMX_PCI_CFG57 \
4407 +        (0x00000000000000E4ull)
4408 +#define CVMX_PCI_CFG58 \
4409 +        (0x00000000000000E8ull)
4410 +#define CVMX_PCI_CFG59 \
4411 +        (0x00000000000000ECull)
4412 +#define CVMX_PCI_CFG60 \
4413 +        (0x00000000000000F0ull)
4414 +#define CVMX_PCI_CFG61 \
4415 +        (0x00000000000000F4ull)
4416 +#define CVMX_PCI_CFG62 \
4417 +        (0x00000000000000F8ull)
4418 +#define CVMX_PCI_CFG63 \
4419 +        (0x00000000000000FCull)
4420 +#define CVMX_PCI_CNT_REG \
4421 +        (0x00000000000001B8ull)
4422 +#define CVMX_PCI_CTL_STATUS_2 \
4423 +        (0x000000000000018Cull)
4424 +#define CVMX_PCI_DBELL_0 \
4425 +        (0x0000000000000080ull)
4426 +#define CVMX_PCI_DBELL_1 \
4427 +        (0x0000000000000088ull)
4428 +#define CVMX_PCI_DBELL_2 \
4429 +        (0x0000000000000090ull)
4430 +#define CVMX_PCI_DBELL_3 \
4431 +        (0x0000000000000098ull)
4432 +#define CVMX_PCI_DBELL_X(offset) \
4433 +        (0x0000000000000080ull + (((offset) & 3) * 8))
4434 +#define CVMX_PCI_DMA_CNT0 \
4435 +        (0x00000000000000A0ull)
4436 +#define CVMX_PCI_DMA_CNT1 \
4437 +        (0x00000000000000A8ull)
4438 +#define CVMX_PCI_DMA_CNTX(offset) \
4439 +        (0x00000000000000A0ull + (((offset) & 1) * 8))
4440 +#define CVMX_PCI_DMA_INT_LEV0 \
4441 +        (0x00000000000000A4ull)
4442 +#define CVMX_PCI_DMA_INT_LEV1 \
4443 +        (0x00000000000000ACull)
4444 +#define CVMX_PCI_DMA_INT_LEVX(offset) \
4445 +        (0x00000000000000A4ull + (((offset) & 1) * 8))
4446 +#define CVMX_PCI_DMA_TIME0 \
4447 +        (0x00000000000000B0ull)
4448 +#define CVMX_PCI_DMA_TIME1 \
4449 +        (0x00000000000000B4ull)
4450 +#define CVMX_PCI_DMA_TIMEX(offset) \
4451 +        (0x00000000000000B0ull + (((offset) & 1) * 4))
4452 +#define CVMX_PCI_INSTR_COUNT0 \
4453 +        (0x0000000000000084ull)
4454 +#define CVMX_PCI_INSTR_COUNT1 \
4455 +        (0x000000000000008Cull)
4456 +#define CVMX_PCI_INSTR_COUNT2 \
4457 +        (0x0000000000000094ull)
4458 +#define CVMX_PCI_INSTR_COUNT3 \
4459 +        (0x000000000000009Cull)
4460 +#define CVMX_PCI_INSTR_COUNTX(offset) \
4461 +        (0x0000000000000084ull + (((offset) & 3) * 8))
4462 +#define CVMX_PCI_INT_ENB \
4463 +        (0x0000000000000038ull)
4464 +#define CVMX_PCI_INT_ENB2 \
4465 +        (0x00000000000001A0ull)
4466 +#define CVMX_PCI_INT_SUM \
4467 +        (0x0000000000000030ull)
4468 +#define CVMX_PCI_INT_SUM2 \
4469 +        (0x0000000000000198ull)
4470 +#define CVMX_PCI_MSI_RCV \
4471 +        (0x00000000000000F0ull)
4472 +#define CVMX_PCI_PKTS_SENT0 \
4473 +        (0x0000000000000040ull)
4474 +#define CVMX_PCI_PKTS_SENT1 \
4475 +        (0x0000000000000050ull)
4476 +#define CVMX_PCI_PKTS_SENT2 \
4477 +        (0x0000000000000060ull)
4478 +#define CVMX_PCI_PKTS_SENT3 \
4479 +        (0x0000000000000070ull)
4480 +#define CVMX_PCI_PKTS_SENTX(offset) \
4481 +        (0x0000000000000040ull + (((offset) & 3) * 16))
4482 +#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
4483 +        (0x0000000000000048ull)
4484 +#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
4485 +        (0x0000000000000058ull)
4486 +#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
4487 +        (0x0000000000000068ull)
4488 +#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
4489 +        (0x0000000000000078ull)
4490 +#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
4491 +        (0x0000000000000048ull + (((offset) & 3) * 16))
4492 +#define CVMX_PCI_PKTS_SENT_TIME0 \
4493 +        (0x000000000000004Cull)
4494 +#define CVMX_PCI_PKTS_SENT_TIME1 \
4495 +        (0x000000000000005Cull)
4496 +#define CVMX_PCI_PKTS_SENT_TIME2 \
4497 +        (0x000000000000006Cull)
4498 +#define CVMX_PCI_PKTS_SENT_TIME3 \
4499 +        (0x000000000000007Cull)
4500 +#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
4501 +        (0x000000000000004Cull + (((offset) & 3) * 16))
4502 +#define CVMX_PCI_PKT_CREDITS0 \
4503 +        (0x0000000000000044ull)
4504 +#define CVMX_PCI_PKT_CREDITS1 \
4505 +        (0x0000000000000054ull)
4506 +#define CVMX_PCI_PKT_CREDITS2 \
4507 +        (0x0000000000000064ull)
4508 +#define CVMX_PCI_PKT_CREDITS3 \
4509 +        (0x0000000000000074ull)
4510 +#define CVMX_PCI_PKT_CREDITSX(offset) \
4511 +        (0x0000000000000044ull + (((offset) & 3) * 16))
4512 +#define CVMX_PCI_READ_CMD_6 \
4513 +        (0x0000000000000180ull)
4514 +#define CVMX_PCI_READ_CMD_C \
4515 +        (0x0000000000000184ull)
4516 +#define CVMX_PCI_READ_CMD_E \
4517 +        (0x0000000000000188ull)
4518 +#define CVMX_PCI_READ_TIMEOUT \
4519 +        CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
4520 +#define CVMX_PCI_SCM_REG \
4521 +        (0x00000000000001A8ull)
4522 +#define CVMX_PCI_TSR_REG \
4523 +        (0x00000000000001B0ull)
4524 +#define CVMX_PCI_WIN_RD_ADDR \
4525 +        (0x0000000000000008ull)
4526 +#define CVMX_PCI_WIN_RD_DATA \
4527 +        (0x0000000000000020ull)
4528 +#define CVMX_PCI_WIN_WR_ADDR \
4529 +        (0x0000000000000000ull)
4530 +#define CVMX_PCI_WIN_WR_DATA \
4531 +        (0x0000000000000010ull)
4532 +#define CVMX_PCI_WIN_WR_MASK \
4533 +        (0x0000000000000018ull)
4534 +
4535 +union cvmx_pci_bar1_indexx {
4536 +       uint32_t u32;
4537 +       struct cvmx_pci_bar1_indexx_s {
4538 +               uint32_t reserved_18_31:14;
4539 +               uint32_t addr_idx:14;
4540 +               uint32_t ca:1;
4541 +               uint32_t end_swp:2;
4542 +               uint32_t addr_v:1;
4543 +       } s;
4544 +       struct cvmx_pci_bar1_indexx_s cn30xx;
4545 +       struct cvmx_pci_bar1_indexx_s cn31xx;
4546 +       struct cvmx_pci_bar1_indexx_s cn38xx;
4547 +       struct cvmx_pci_bar1_indexx_s cn38xxp2;
4548 +       struct cvmx_pci_bar1_indexx_s cn50xx;
4549 +       struct cvmx_pci_bar1_indexx_s cn58xx;
4550 +       struct cvmx_pci_bar1_indexx_s cn58xxp1;
4551 +};
4552 +
4553 +union cvmx_pci_bist_reg {
4554 +       uint64_t u64;
4555 +       struct cvmx_pci_bist_reg_s {
4556 +               uint64_t reserved_10_63:54;
4557 +               uint64_t rsp_bs:1;
4558 +               uint64_t dma0_bs:1;
4559 +               uint64_t cmd0_bs:1;
4560 +               uint64_t cmd_bs:1;
4561 +               uint64_t csr2p_bs:1;
4562 +               uint64_t csrr_bs:1;
4563 +               uint64_t rsp2p_bs:1;
4564 +               uint64_t csr2n_bs:1;
4565 +               uint64_t dat2n_bs:1;
4566 +               uint64_t dbg2n_bs:1;
4567 +       } s;
4568 +       struct cvmx_pci_bist_reg_s cn50xx;
4569 +};
4570 +
4571 +union cvmx_pci_cfg00 {
4572 +       uint32_t u32;
4573 +       struct cvmx_pci_cfg00_s {
4574 +               uint32_t devid:16;
4575 +               uint32_t vendid:16;
4576 +       } s;
4577 +       struct cvmx_pci_cfg00_s cn30xx;
4578 +       struct cvmx_pci_cfg00_s cn31xx;
4579 +       struct cvmx_pci_cfg00_s cn38xx;
4580 +       struct cvmx_pci_cfg00_s cn38xxp2;
4581 +       struct cvmx_pci_cfg00_s cn50xx;
4582 +       struct cvmx_pci_cfg00_s cn58xx;
4583 +       struct cvmx_pci_cfg00_s cn58xxp1;
4584 +};
4585 +
4586 +union cvmx_pci_cfg01 {
4587 +       uint32_t u32;
4588 +       struct cvmx_pci_cfg01_s {
4589 +               uint32_t dpe:1;
4590 +               uint32_t sse:1;
4591 +               uint32_t rma:1;
4592 +               uint32_t rta:1;
4593 +               uint32_t sta:1;
4594 +               uint32_t devt:2;
4595 +               uint32_t mdpe:1;
4596 +               uint32_t fbb:1;
4597 +               uint32_t reserved_22_22:1;
4598 +               uint32_t m66:1;
4599 +               uint32_t cle:1;
4600 +               uint32_t i_stat:1;
4601 +               uint32_t reserved_11_18:8;
4602 +               uint32_t i_dis:1;
4603 +               uint32_t fbbe:1;
4604 +               uint32_t see:1;
4605 +               uint32_t ads:1;
4606 +               uint32_t pee:1;
4607 +               uint32_t vps:1;
4608 +               uint32_t mwice:1;
4609 +               uint32_t scse:1;
4610 +               uint32_t me:1;
4611 +               uint32_t msae:1;
4612 +               uint32_t isae:1;
4613 +       } s;
4614 +       struct cvmx_pci_cfg01_s cn30xx;
4615 +       struct cvmx_pci_cfg01_s cn31xx;
4616 +       struct cvmx_pci_cfg01_s cn38xx;
4617 +       struct cvmx_pci_cfg01_s cn38xxp2;
4618 +       struct cvmx_pci_cfg01_s cn50xx;
4619 +       struct cvmx_pci_cfg01_s cn58xx;
4620 +       struct cvmx_pci_cfg01_s cn58xxp1;
4621 +};
4622 +
4623 +union cvmx_pci_cfg02 {
4624 +       uint32_t u32;
4625 +       struct cvmx_pci_cfg02_s {
4626 +               uint32_t cc:24;
4627 +               uint32_t rid:8;
4628 +       } s;
4629 +       struct cvmx_pci_cfg02_s cn30xx;
4630 +       struct cvmx_pci_cfg02_s cn31xx;
4631 +       struct cvmx_pci_cfg02_s cn38xx;
4632 +       struct cvmx_pci_cfg02_s cn38xxp2;
4633 +       struct cvmx_pci_cfg02_s cn50xx;
4634 +       struct cvmx_pci_cfg02_s cn58xx;
4635 +       struct cvmx_pci_cfg02_s cn58xxp1;
4636 +};
4637 +
4638 +union cvmx_pci_cfg03 {
4639 +       uint32_t u32;
4640 +       struct cvmx_pci_cfg03_s {
4641 +               uint32_t bcap:1;
4642 +               uint32_t brb:1;
4643 +               uint32_t reserved_28_29:2;
4644 +               uint32_t bcod:4;
4645 +               uint32_t ht:8;
4646 +               uint32_t lt:8;
4647 +               uint32_t cls:8;
4648 +       } s;
4649 +       struct cvmx_pci_cfg03_s cn30xx;
4650 +       struct cvmx_pci_cfg03_s cn31xx;
4651 +       struct cvmx_pci_cfg03_s cn38xx;
4652 +       struct cvmx_pci_cfg03_s cn38xxp2;
4653 +       struct cvmx_pci_cfg03_s cn50xx;
4654 +       struct cvmx_pci_cfg03_s cn58xx;
4655 +       struct cvmx_pci_cfg03_s cn58xxp1;
4656 +};
4657 +
4658 +union cvmx_pci_cfg04 {
4659 +       uint32_t u32;
4660 +       struct cvmx_pci_cfg04_s {
4661 +               uint32_t lbase:20;
4662 +               uint32_t lbasez:8;
4663 +               uint32_t pf:1;
4664 +               uint32_t typ:2;
4665 +               uint32_t mspc:1;
4666 +       } s;
4667 +       struct cvmx_pci_cfg04_s cn30xx;
4668 +       struct cvmx_pci_cfg04_s cn31xx;
4669 +       struct cvmx_pci_cfg04_s cn38xx;
4670 +       struct cvmx_pci_cfg04_s cn38xxp2;
4671 +       struct cvmx_pci_cfg04_s cn50xx;
4672 +       struct cvmx_pci_cfg04_s cn58xx;
4673 +       struct cvmx_pci_cfg04_s cn58xxp1;
4674 +};
4675 +
4676 +union cvmx_pci_cfg05 {
4677 +       uint32_t u32;
4678 +       struct cvmx_pci_cfg05_s {
4679 +               uint32_t hbase:32;
4680 +       } s;
4681 +       struct cvmx_pci_cfg05_s cn30xx;
4682 +       struct cvmx_pci_cfg05_s cn31xx;
4683 +       struct cvmx_pci_cfg05_s cn38xx;
4684 +       struct cvmx_pci_cfg05_s cn38xxp2;
4685 +       struct cvmx_pci_cfg05_s cn50xx;
4686 +       struct cvmx_pci_cfg05_s cn58xx;
4687 +       struct cvmx_pci_cfg05_s cn58xxp1;
4688 +};
4689 +
4690 +union cvmx_pci_cfg06 {
4691 +       uint32_t u32;
4692 +       struct cvmx_pci_cfg06_s {
4693 +               uint32_t lbase:5;
4694 +               uint32_t lbasez:23;
4695 +               uint32_t pf:1;
4696 +               uint32_t typ:2;
4697 +               uint32_t mspc:1;
4698 +       } s;
4699 +       struct cvmx_pci_cfg06_s cn30xx;
4700 +       struct cvmx_pci_cfg06_s cn31xx;
4701 +       struct cvmx_pci_cfg06_s cn38xx;
4702 +       struct cvmx_pci_cfg06_s cn38xxp2;
4703 +       struct cvmx_pci_cfg06_s cn50xx;
4704 +       struct cvmx_pci_cfg06_s cn58xx;
4705 +       struct cvmx_pci_cfg06_s cn58xxp1;
4706 +};
4707 +
4708 +union cvmx_pci_cfg07 {
4709 +       uint32_t u32;
4710 +       struct cvmx_pci_cfg07_s {
4711 +               uint32_t hbase:32;
4712 +       } s;
4713 +       struct cvmx_pci_cfg07_s cn30xx;
4714 +       struct cvmx_pci_cfg07_s cn31xx;
4715 +       struct cvmx_pci_cfg07_s cn38xx;
4716 +       struct cvmx_pci_cfg07_s cn38xxp2;
4717 +       struct cvmx_pci_cfg07_s cn50xx;
4718 +       struct cvmx_pci_cfg07_s cn58xx;
4719 +       struct cvmx_pci_cfg07_s cn58xxp1;
4720 +};
4721 +
4722 +union cvmx_pci_cfg08 {
4723 +       uint32_t u32;
4724 +       struct cvmx_pci_cfg08_s {
4725 +               uint32_t lbasez:28;
4726 +               uint32_t pf:1;
4727 +               uint32_t typ:2;
4728 +               uint32_t mspc:1;
4729 +       } s;
4730 +       struct cvmx_pci_cfg08_s cn30xx;
4731 +       struct cvmx_pci_cfg08_s cn31xx;
4732 +       struct cvmx_pci_cfg08_s cn38xx;
4733 +       struct cvmx_pci_cfg08_s cn38xxp2;
4734 +       struct cvmx_pci_cfg08_s cn50xx;
4735 +       struct cvmx_pci_cfg08_s cn58xx;
4736 +       struct cvmx_pci_cfg08_s cn58xxp1;
4737 +};
4738 +
4739 +union cvmx_pci_cfg09 {
4740 +       uint32_t u32;
4741 +       struct cvmx_pci_cfg09_s {
4742 +               uint32_t hbase:25;
4743 +               uint32_t hbasez:7;
4744 +       } s;
4745 +       struct cvmx_pci_cfg09_s cn30xx;
4746 +       struct cvmx_pci_cfg09_s cn31xx;
4747 +       struct cvmx_pci_cfg09_s cn38xx;
4748 +       struct cvmx_pci_cfg09_s cn38xxp2;
4749 +       struct cvmx_pci_cfg09_s cn50xx;
4750 +       struct cvmx_pci_cfg09_s cn58xx;
4751 +       struct cvmx_pci_cfg09_s cn58xxp1;
4752 +};
4753 +
4754 +union cvmx_pci_cfg10 {
4755 +       uint32_t u32;
4756 +       struct cvmx_pci_cfg10_s {
4757 +               uint32_t cisp:32;
4758 +       } s;
4759 +       struct cvmx_pci_cfg10_s cn30xx;
4760 +       struct cvmx_pci_cfg10_s cn31xx;
4761 +       struct cvmx_pci_cfg10_s cn38xx;
4762 +       struct cvmx_pci_cfg10_s cn38xxp2;
4763 +       struct cvmx_pci_cfg10_s cn50xx;
4764 +       struct cvmx_pci_cfg10_s cn58xx;
4765 +       struct cvmx_pci_cfg10_s cn58xxp1;
4766 +};
4767 +
4768 +union cvmx_pci_cfg11 {
4769 +       uint32_t u32;
4770 +       struct cvmx_pci_cfg11_s {
4771 +               uint32_t ssid:16;
4772 +               uint32_t ssvid:16;
4773 +       } s;
4774 +       struct cvmx_pci_cfg11_s cn30xx;
4775 +       struct cvmx_pci_cfg11_s cn31xx;
4776 +       struct cvmx_pci_cfg11_s cn38xx;
4777 +       struct cvmx_pci_cfg11_s cn38xxp2;
4778 +       struct cvmx_pci_cfg11_s cn50xx;
4779 +       struct cvmx_pci_cfg11_s cn58xx;
4780 +       struct cvmx_pci_cfg11_s cn58xxp1;
4781 +};
4782 +
4783 +union cvmx_pci_cfg12 {
4784 +       uint32_t u32;
4785 +       struct cvmx_pci_cfg12_s {
4786 +               uint32_t erbar:16;
4787 +               uint32_t erbarz:5;
4788 +               uint32_t reserved_1_10:10;
4789 +               uint32_t erbar_en:1;
4790 +       } s;
4791 +       struct cvmx_pci_cfg12_s cn30xx;
4792 +       struct cvmx_pci_cfg12_s cn31xx;
4793 +       struct cvmx_pci_cfg12_s cn38xx;
4794 +       struct cvmx_pci_cfg12_s cn38xxp2;
4795 +       struct cvmx_pci_cfg12_s cn50xx;
4796 +       struct cvmx_pci_cfg12_s cn58xx;
4797 +       struct cvmx_pci_cfg12_s cn58xxp1;
4798 +};
4799 +
4800 +union cvmx_pci_cfg13 {
4801 +       uint32_t u32;
4802 +       struct cvmx_pci_cfg13_s {
4803 +               uint32_t reserved_8_31:24;
4804 +               uint32_t cp:8;
4805 +       } s;
4806 +       struct cvmx_pci_cfg13_s cn30xx;
4807 +       struct cvmx_pci_cfg13_s cn31xx;
4808 +       struct cvmx_pci_cfg13_s cn38xx;
4809 +       struct cvmx_pci_cfg13_s cn38xxp2;
4810 +       struct cvmx_pci_cfg13_s cn50xx;
4811 +       struct cvmx_pci_cfg13_s cn58xx;
4812 +       struct cvmx_pci_cfg13_s cn58xxp1;
4813 +};
4814 +
4815 +union cvmx_pci_cfg15 {
4816 +       uint32_t u32;
4817 +       struct cvmx_pci_cfg15_s {
4818 +               uint32_t ml:8;
4819 +               uint32_t mg:8;
4820 +               uint32_t inta:8;
4821 +               uint32_t il:8;
4822 +       } s;
4823 +       struct cvmx_pci_cfg15_s cn30xx;
4824 +       struct cvmx_pci_cfg15_s cn31xx;
4825 +       struct cvmx_pci_cfg15_s cn38xx;
4826 +       struct cvmx_pci_cfg15_s cn38xxp2;
4827 +       struct cvmx_pci_cfg15_s cn50xx;
4828 +       struct cvmx_pci_cfg15_s cn58xx;
4829 +       struct cvmx_pci_cfg15_s cn58xxp1;
4830 +};
4831 +
4832 +union cvmx_pci_cfg16 {
4833 +       uint32_t u32;
4834 +       struct cvmx_pci_cfg16_s {
4835 +               uint32_t trdnpr:1;
4836 +               uint32_t trdard:1;
4837 +               uint32_t rdsati:1;
4838 +               uint32_t trdrs:1;
4839 +               uint32_t trtae:1;
4840 +               uint32_t twsei:1;
4841 +               uint32_t twsen:1;
4842 +               uint32_t twtae:1;
4843 +               uint32_t tmae:1;
4844 +               uint32_t tslte:3;
4845 +               uint32_t tilt:4;
4846 +               uint32_t pbe:12;
4847 +               uint32_t dppmr:1;
4848 +               uint32_t reserved_2_2:1;
4849 +               uint32_t tswc:1;
4850 +               uint32_t mltd:1;
4851 +       } s;
4852 +       struct cvmx_pci_cfg16_s cn30xx;
4853 +       struct cvmx_pci_cfg16_s cn31xx;
4854 +       struct cvmx_pci_cfg16_s cn38xx;
4855 +       struct cvmx_pci_cfg16_s cn38xxp2;
4856 +       struct cvmx_pci_cfg16_s cn50xx;
4857 +       struct cvmx_pci_cfg16_s cn58xx;
4858 +       struct cvmx_pci_cfg16_s cn58xxp1;
4859 +};
4860 +
4861 +union cvmx_pci_cfg17 {
4862 +       uint32_t u32;
4863 +       struct cvmx_pci_cfg17_s {
4864 +               uint32_t tscme:32;
4865 +       } s;
4866 +       struct cvmx_pci_cfg17_s cn30xx;
4867 +       struct cvmx_pci_cfg17_s cn31xx;
4868 +       struct cvmx_pci_cfg17_s cn38xx;
4869 +       struct cvmx_pci_cfg17_s cn38xxp2;
4870 +       struct cvmx_pci_cfg17_s cn50xx;
4871 +       struct cvmx_pci_cfg17_s cn58xx;
4872 +       struct cvmx_pci_cfg17_s cn58xxp1;
4873 +};
4874 +
4875 +union cvmx_pci_cfg18 {
4876 +       uint32_t u32;
4877 +       struct cvmx_pci_cfg18_s {
4878 +               uint32_t tdsrps:32;
4879 +       } s;
4880 +       struct cvmx_pci_cfg18_s cn30xx;
4881 +       struct cvmx_pci_cfg18_s cn31xx;
4882 +       struct cvmx_pci_cfg18_s cn38xx;
4883 +       struct cvmx_pci_cfg18_s cn38xxp2;
4884 +       struct cvmx_pci_cfg18_s cn50xx;
4885 +       struct cvmx_pci_cfg18_s cn58xx;
4886 +       struct cvmx_pci_cfg18_s cn58xxp1;
4887 +};
4888 +
4889 +union cvmx_pci_cfg19 {
4890 +       uint32_t u32;
4891 +       struct cvmx_pci_cfg19_s {
4892 +               uint32_t mrbcm:1;
4893 +               uint32_t mrbci:1;
4894 +               uint32_t mdwe:1;
4895 +               uint32_t mdre:1;
4896 +               uint32_t mdrimc:1;
4897 +               uint32_t mdrrmc:3;
4898 +               uint32_t tmes:8;
4899 +               uint32_t teci:1;
4900 +               uint32_t tmei:1;
4901 +               uint32_t tmse:1;
4902 +               uint32_t tmdpes:1;
4903 +               uint32_t tmapes:1;
4904 +               uint32_t reserved_9_10:2;
4905 +               uint32_t tibcd:1;
4906 +               uint32_t tibde:1;
4907 +               uint32_t reserved_6_6:1;
4908 +               uint32_t tidomc:1;
4909 +               uint32_t tdomc:5;
4910 +       } s;
4911 +       struct cvmx_pci_cfg19_s cn30xx;
4912 +       struct cvmx_pci_cfg19_s cn31xx;
4913 +       struct cvmx_pci_cfg19_s cn38xx;
4914 +       struct cvmx_pci_cfg19_s cn38xxp2;
4915 +       struct cvmx_pci_cfg19_s cn50xx;
4916 +       struct cvmx_pci_cfg19_s cn58xx;
4917 +       struct cvmx_pci_cfg19_s cn58xxp1;
4918 +};
4919 +
4920 +union cvmx_pci_cfg20 {
4921 +       uint32_t u32;
4922 +       struct cvmx_pci_cfg20_s {
4923 +               uint32_t mdsp:32;
4924 +       } s;
4925 +       struct cvmx_pci_cfg20_s cn30xx;
4926 +       struct cvmx_pci_cfg20_s cn31xx;
4927 +       struct cvmx_pci_cfg20_s cn38xx;
4928 +       struct cvmx_pci_cfg20_s cn38xxp2;
4929 +       struct cvmx_pci_cfg20_s cn50xx;
4930 +       struct cvmx_pci_cfg20_s cn58xx;
4931 +       struct cvmx_pci_cfg20_s cn58xxp1;
4932 +};
4933 +
4934 +union cvmx_pci_cfg21 {
4935 +       uint32_t u32;
4936 +       struct cvmx_pci_cfg21_s {
4937 +               uint32_t scmre:32;
4938 +       } s;
4939 +       struct cvmx_pci_cfg21_s cn30xx;
4940 +       struct cvmx_pci_cfg21_s cn31xx;
4941 +       struct cvmx_pci_cfg21_s cn38xx;
4942 +       struct cvmx_pci_cfg21_s cn38xxp2;
4943 +       struct cvmx_pci_cfg21_s cn50xx;
4944 +       struct cvmx_pci_cfg21_s cn58xx;
4945 +       struct cvmx_pci_cfg21_s cn58xxp1;
4946 +};
4947 +
4948 +union cvmx_pci_cfg22 {
4949 +       uint32_t u32;
4950 +       struct cvmx_pci_cfg22_s {
4951 +               uint32_t mac:7;
4952 +               uint32_t reserved_19_24:6;
4953 +               uint32_t flush:1;
4954 +               uint32_t mra:1;
4955 +               uint32_t mtta:1;
4956 +               uint32_t mrv:8;
4957 +               uint32_t mttv:8;
4958 +       } s;
4959 +       struct cvmx_pci_cfg22_s cn30xx;
4960 +       struct cvmx_pci_cfg22_s cn31xx;
4961 +       struct cvmx_pci_cfg22_s cn38xx;
4962 +       struct cvmx_pci_cfg22_s cn38xxp2;
4963 +       struct cvmx_pci_cfg22_s cn50xx;
4964 +       struct cvmx_pci_cfg22_s cn58xx;
4965 +       struct cvmx_pci_cfg22_s cn58xxp1;
4966 +};
4967 +
4968 +union cvmx_pci_cfg56 {
4969 +       uint32_t u32;
4970 +       struct cvmx_pci_cfg56_s {
4971 +               uint32_t reserved_23_31:9;
4972 +               uint32_t most:3;
4973 +               uint32_t mmbc:2;
4974 +               uint32_t roe:1;
4975 +               uint32_t dpere:1;
4976 +               uint32_t ncp:8;
4977 +               uint32_t pxcid:8;
4978 +       } s;
4979 +       struct cvmx_pci_cfg56_s cn30xx;
4980 +       struct cvmx_pci_cfg56_s cn31xx;
4981 +       struct cvmx_pci_cfg56_s cn38xx;
4982 +       struct cvmx_pci_cfg56_s cn38xxp2;
4983 +       struct cvmx_pci_cfg56_s cn50xx;
4984 +       struct cvmx_pci_cfg56_s cn58xx;
4985 +       struct cvmx_pci_cfg56_s cn58xxp1;
4986 +};
4987 +
4988 +union cvmx_pci_cfg57 {
4989 +       uint32_t u32;
4990 +       struct cvmx_pci_cfg57_s {
4991 +               uint32_t reserved_30_31:2;
4992 +               uint32_t scemr:1;
4993 +               uint32_t mcrsd:3;
4994 +               uint32_t mostd:3;
4995 +               uint32_t mmrbcd:2;
4996 +               uint32_t dc:1;
4997 +               uint32_t usc:1;
4998 +               uint32_t scd:1;
4999 +               uint32_t m133:1;
5000 +               uint32_t w64:1;
5001 +               uint32_t bn:8;
5002 +               uint32_t dn:5;
5003 +               uint32_t fn:3;
5004 +       } s;
5005 +       struct cvmx_pci_cfg57_s cn30xx;
5006 +       struct cvmx_pci_cfg57_s cn31xx;
5007 +       struct cvmx_pci_cfg57_s cn38xx;
5008 +       struct cvmx_pci_cfg57_s cn38xxp2;
5009 +       struct cvmx_pci_cfg57_s cn50xx;
5010 +       struct cvmx_pci_cfg57_s cn58xx;
5011 +       struct cvmx_pci_cfg57_s cn58xxp1;
5012 +};
5013 +
5014 +union cvmx_pci_cfg58 {
5015 +       uint32_t u32;
5016 +       struct cvmx_pci_cfg58_s {
5017 +               uint32_t pmes:5;
5018 +               uint32_t d2s:1;
5019 +               uint32_t d1s:1;
5020 +               uint32_t auxc:3;
5021 +               uint32_t dsi:1;
5022 +               uint32_t reserved_20_20:1;
5023 +               uint32_t pmec:1;
5024 +               uint32_t pcimiv:3;
5025 +               uint32_t ncp:8;
5026 +               uint32_t pmcid:8;
5027 +       } s;
5028 +       struct cvmx_pci_cfg58_s cn30xx;
5029 +       struct cvmx_pci_cfg58_s cn31xx;
5030 +       struct cvmx_pci_cfg58_s cn38xx;
5031 +       struct cvmx_pci_cfg58_s cn38xxp2;
5032 +       struct cvmx_pci_cfg58_s cn50xx;
5033 +       struct cvmx_pci_cfg58_s cn58xx;
5034 +       struct cvmx_pci_cfg58_s cn58xxp1;
5035 +};
5036 +
5037 +union cvmx_pci_cfg59 {
5038 +       uint32_t u32;
5039 +       struct cvmx_pci_cfg59_s {
5040 +               uint32_t pmdia:8;
5041 +               uint32_t bpccen:1;
5042 +               uint32_t bd3h:1;
5043 +               uint32_t reserved_16_21:6;
5044 +               uint32_t pmess:1;
5045 +               uint32_t pmedsia:2;
5046 +               uint32_t pmds:4;
5047 +               uint32_t pmeens:1;
5048 +               uint32_t reserved_2_7:6;
5049 +               uint32_t ps:2;
5050 +       } s;
5051 +       struct cvmx_pci_cfg59_s cn30xx;
5052 +       struct cvmx_pci_cfg59_s cn31xx;
5053 +       struct cvmx_pci_cfg59_s cn38xx;
5054 +       struct cvmx_pci_cfg59_s cn38xxp2;
5055 +       struct cvmx_pci_cfg59_s cn50xx;
5056 +       struct cvmx_pci_cfg59_s cn58xx;
5057 +       struct cvmx_pci_cfg59_s cn58xxp1;
5058 +};
5059 +
5060 +union cvmx_pci_cfg60 {
5061 +       uint32_t u32;
5062 +       struct cvmx_pci_cfg60_s {
5063 +               uint32_t reserved_24_31:8;
5064 +               uint32_t m64:1;
5065 +               uint32_t mme:3;
5066 +               uint32_t mmc:3;
5067 +               uint32_t msien:1;
5068 +               uint32_t ncp:8;
5069 +               uint32_t msicid:8;
5070 +       } s;
5071 +       struct cvmx_pci_cfg60_s cn30xx;
5072 +       struct cvmx_pci_cfg60_s cn31xx;
5073 +       struct cvmx_pci_cfg60_s cn38xx;
5074 +       struct cvmx_pci_cfg60_s cn38xxp2;
5075 +       struct cvmx_pci_cfg60_s cn50xx;
5076 +       struct cvmx_pci_cfg60_s cn58xx;
5077 +       struct cvmx_pci_cfg60_s cn58xxp1;
5078 +};
5079 +
5080 +union cvmx_pci_cfg61 {
5081 +       uint32_t u32;
5082 +       struct cvmx_pci_cfg61_s {
5083 +               uint32_t msi31t2:30;
5084 +               uint32_t reserved_0_1:2;
5085 +       } s;
5086 +       struct cvmx_pci_cfg61_s cn30xx;
5087 +       struct cvmx_pci_cfg61_s cn31xx;
5088 +       struct cvmx_pci_cfg61_s cn38xx;
5089 +       struct cvmx_pci_cfg61_s cn38xxp2;
5090 +       struct cvmx_pci_cfg61_s cn50xx;
5091 +       struct cvmx_pci_cfg61_s cn58xx;
5092 +       struct cvmx_pci_cfg61_s cn58xxp1;
5093 +};
5094 +
5095 +union cvmx_pci_cfg62 {
5096 +       uint32_t u32;
5097 +       struct cvmx_pci_cfg62_s {
5098 +               uint32_t msi:32;
5099 +       } s;
5100 +       struct cvmx_pci_cfg62_s cn30xx;
5101 +       struct cvmx_pci_cfg62_s cn31xx;
5102 +       struct cvmx_pci_cfg62_s cn38xx;
5103 +       struct cvmx_pci_cfg62_s cn38xxp2;
5104 +       struct cvmx_pci_cfg62_s cn50xx;
5105 +       struct cvmx_pci_cfg62_s cn58xx;
5106 +       struct cvmx_pci_cfg62_s cn58xxp1;
5107 +};
5108 +
5109 +union cvmx_pci_cfg63 {
5110 +       uint32_t u32;
5111 +       struct cvmx_pci_cfg63_s {
5112 +               uint32_t reserved_16_31:16;
5113 +               uint32_t msimd:16;
5114 +       } s;
5115 +       struct cvmx_pci_cfg63_s cn30xx;
5116 +       struct cvmx_pci_cfg63_s cn31xx;
5117 +       struct cvmx_pci_cfg63_s cn38xx;
5118 +       struct cvmx_pci_cfg63_s cn38xxp2;
5119 +       struct cvmx_pci_cfg63_s cn50xx;
5120 +       struct cvmx_pci_cfg63_s cn58xx;
5121 +       struct cvmx_pci_cfg63_s cn58xxp1;
5122 +};
5123 +
5124 +union cvmx_pci_cnt_reg {
5125 +       uint64_t u64;
5126 +       struct cvmx_pci_cnt_reg_s {
5127 +               uint64_t reserved_38_63:26;
5128 +               uint64_t hm_pcix:1;
5129 +               uint64_t hm_speed:2;
5130 +               uint64_t ap_pcix:1;
5131 +               uint64_t ap_speed:2;
5132 +               uint64_t pcicnt:32;
5133 +       } s;
5134 +       struct cvmx_pci_cnt_reg_s cn50xx;
5135 +       struct cvmx_pci_cnt_reg_s cn58xx;
5136 +       struct cvmx_pci_cnt_reg_s cn58xxp1;
5137 +};
5138 +
5139 +union cvmx_pci_ctl_status_2 {
5140 +       uint32_t u32;
5141 +       struct cvmx_pci_ctl_status_2_s {
5142 +               uint32_t reserved_29_31:3;
5143 +               uint32_t bb1_hole:3;
5144 +               uint32_t bb1_siz:1;
5145 +               uint32_t bb_ca:1;
5146 +               uint32_t bb_es:2;
5147 +               uint32_t bb1:1;
5148 +               uint32_t bb0:1;
5149 +               uint32_t erst_n:1;
5150 +               uint32_t bar2pres:1;
5151 +               uint32_t scmtyp:1;
5152 +               uint32_t scm:1;
5153 +               uint32_t en_wfilt:1;
5154 +               uint32_t reserved_14_14:1;
5155 +               uint32_t ap_pcix:1;
5156 +               uint32_t ap_64ad:1;
5157 +               uint32_t b12_bist:1;
5158 +               uint32_t pmo_amod:1;
5159 +               uint32_t pmo_fpc:3;
5160 +               uint32_t tsr_hwm:3;
5161 +               uint32_t bar2_enb:1;
5162 +               uint32_t bar2_esx:2;
5163 +               uint32_t bar2_cax:1;
5164 +       } s;
5165 +       struct cvmx_pci_ctl_status_2_s cn30xx;
5166 +       struct cvmx_pci_ctl_status_2_cn31xx {
5167 +               uint32_t reserved_20_31:12;
5168 +               uint32_t erst_n:1;
5169 +               uint32_t bar2pres:1;
5170 +               uint32_t scmtyp:1;
5171 +               uint32_t scm:1;
5172 +               uint32_t en_wfilt:1;
5173 +               uint32_t reserved_14_14:1;
5174 +               uint32_t ap_pcix:1;
5175 +               uint32_t ap_64ad:1;
5176 +               uint32_t b12_bist:1;
5177 +               uint32_t pmo_amod:1;
5178 +               uint32_t pmo_fpc:3;
5179 +               uint32_t tsr_hwm:3;
5180 +               uint32_t bar2_enb:1;
5181 +               uint32_t bar2_esx:2;
5182 +               uint32_t bar2_cax:1;
5183 +       } cn31xx;
5184 +       struct cvmx_pci_ctl_status_2_s cn38xx;
5185 +       struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2;
5186 +       struct cvmx_pci_ctl_status_2_s cn50xx;
5187 +       struct cvmx_pci_ctl_status_2_s cn58xx;
5188 +       struct cvmx_pci_ctl_status_2_s cn58xxp1;
5189 +};
5190 +
5191 +union cvmx_pci_dbellx {
5192 +       uint32_t u32;
5193 +       struct cvmx_pci_dbellx_s {
5194 +               uint32_t reserved_16_31:16;
5195 +               uint32_t inc_val:16;
5196 +       } s;
5197 +       struct cvmx_pci_dbellx_s cn30xx;
5198 +       struct cvmx_pci_dbellx_s cn31xx;
5199 +       struct cvmx_pci_dbellx_s cn38xx;
5200 +       struct cvmx_pci_dbellx_s cn38xxp2;
5201 +       struct cvmx_pci_dbellx_s cn50xx;
5202 +       struct cvmx_pci_dbellx_s cn58xx;
5203 +       struct cvmx_pci_dbellx_s cn58xxp1;
5204 +};
5205 +
5206 +union cvmx_pci_dma_cntx {
5207 +       uint32_t u32;
5208 +       struct cvmx_pci_dma_cntx_s {
5209 +               uint32_t dma_cnt:32;
5210 +       } s;
5211 +       struct cvmx_pci_dma_cntx_s cn30xx;
5212 +       struct cvmx_pci_dma_cntx_s cn31xx;
5213 +       struct cvmx_pci_dma_cntx_s cn38xx;
5214 +       struct cvmx_pci_dma_cntx_s cn38xxp2;
5215 +       struct cvmx_pci_dma_cntx_s cn50xx;
5216 +       struct cvmx_pci_dma_cntx_s cn58xx;
5217 +       struct cvmx_pci_dma_cntx_s cn58xxp1;
5218 +};
5219 +
5220 +union cvmx_pci_dma_int_levx {
5221 +       uint32_t u32;
5222 +       struct cvmx_pci_dma_int_levx_s {
5223 +               uint32_t pkt_cnt:32;
5224 +       } s;
5225 +       struct cvmx_pci_dma_int_levx_s cn30xx;
5226 +       struct cvmx_pci_dma_int_levx_s cn31xx;
5227 +       struct cvmx_pci_dma_int_levx_s cn38xx;
5228 +       struct cvmx_pci_dma_int_levx_s cn38xxp2;
5229 +       struct cvmx_pci_dma_int_levx_s cn50xx;
5230 +       struct cvmx_pci_dma_int_levx_s cn58xx;
5231 +       struct cvmx_pci_dma_int_levx_s cn58xxp1;
5232 +};
5233 +
5234 +union cvmx_pci_dma_timex {
5235 +       uint32_t u32;
5236 +       struct cvmx_pci_dma_timex_s {
5237 +               uint32_t dma_time:32;
5238 +       } s;
5239 +       struct cvmx_pci_dma_timex_s cn30xx;
5240 +       struct cvmx_pci_dma_timex_s cn31xx;
5241 +       struct cvmx_pci_dma_timex_s cn38xx;
5242 +       struct cvmx_pci_dma_timex_s cn38xxp2;
5243 +       struct cvmx_pci_dma_timex_s cn50xx;
5244 +       struct cvmx_pci_dma_timex_s cn58xx;
5245 +       struct cvmx_pci_dma_timex_s cn58xxp1;
5246 +};
5247 +
5248 +union cvmx_pci_instr_countx {
5249 +       uint32_t u32;
5250 +       struct cvmx_pci_instr_countx_s {
5251 +               uint32_t icnt:32;
5252 +       } s;
5253 +       struct cvmx_pci_instr_countx_s cn30xx;
5254 +       struct cvmx_pci_instr_countx_s cn31xx;
5255 +       struct cvmx_pci_instr_countx_s cn38xx;
5256 +       struct cvmx_pci_instr_countx_s cn38xxp2;
5257 +       struct cvmx_pci_instr_countx_s cn50xx;
5258 +       struct cvmx_pci_instr_countx_s cn58xx;
5259 +       struct cvmx_pci_instr_countx_s cn58xxp1;
5260 +};
5261 +
5262 +union cvmx_pci_int_enb {
5263 +       uint64_t u64;
5264 +       struct cvmx_pci_int_enb_s {
5265 +               uint64_t reserved_34_63:30;
5266 +               uint64_t ill_rd:1;
5267 +               uint64_t ill_wr:1;
5268 +               uint64_t win_wr:1;
5269 +               uint64_t dma1_fi:1;
5270 +               uint64_t dma0_fi:1;
5271 +               uint64_t idtime1:1;
5272 +               uint64_t idtime0:1;
5273 +               uint64_t idcnt1:1;
5274 +               uint64_t idcnt0:1;
5275 +               uint64_t iptime3:1;
5276 +               uint64_t iptime2:1;
5277 +               uint64_t iptime1:1;
5278 +               uint64_t iptime0:1;
5279 +               uint64_t ipcnt3:1;
5280 +               uint64_t ipcnt2:1;
5281 +               uint64_t ipcnt1:1;
5282 +               uint64_t ipcnt0:1;
5283 +               uint64_t irsl_int:1;
5284 +               uint64_t ill_rrd:1;
5285 +               uint64_t ill_rwr:1;
5286 +               uint64_t idperr:1;
5287 +               uint64_t iaperr:1;
5288 +               uint64_t iserr:1;
5289 +               uint64_t itsr_abt:1;
5290 +               uint64_t imsc_msg:1;
5291 +               uint64_t imsi_mabt:1;
5292 +               uint64_t imsi_tabt:1;
5293 +               uint64_t imsi_per:1;
5294 +               uint64_t imr_tto:1;
5295 +               uint64_t imr_abt:1;
5296 +               uint64_t itr_abt:1;
5297 +               uint64_t imr_wtto:1;
5298 +               uint64_t imr_wabt:1;
5299 +               uint64_t itr_wabt:1;
5300 +       } s;
5301 +       struct cvmx_pci_int_enb_cn30xx {
5302 +               uint64_t reserved_34_63:30;
5303 +               uint64_t ill_rd:1;
5304 +               uint64_t ill_wr:1;
5305 +               uint64_t win_wr:1;
5306 +               uint64_t dma1_fi:1;
5307 +               uint64_t dma0_fi:1;
5308 +               uint64_t idtime1:1;
5309 +               uint64_t idtime0:1;
5310 +               uint64_t idcnt1:1;
5311 +               uint64_t idcnt0:1;
5312 +               uint64_t reserved_22_24:3;
5313 +               uint64_t iptime0:1;
5314 +               uint64_t reserved_18_20:3;
5315 +               uint64_t ipcnt0:1;
5316 +               uint64_t irsl_int:1;
5317 +               uint64_t ill_rrd:1;
5318 +               uint64_t ill_rwr:1;
5319 +               uint64_t idperr:1;
5320 +               uint64_t iaperr:1;
5321 +               uint64_t iserr:1;
5322 +               uint64_t itsr_abt:1;
5323 +               uint64_t imsc_msg:1;
5324 +               uint64_t imsi_mabt:1;
5325 +               uint64_t imsi_tabt:1;
5326 +               uint64_t imsi_per:1;
5327 +               uint64_t imr_tto:1;
5328 +               uint64_t imr_abt:1;
5329 +               uint64_t itr_abt:1;
5330 +               uint64_t imr_wtto:1;
5331 +               uint64_t imr_wabt:1;
5332 +               uint64_t itr_wabt:1;
5333 +       } cn30xx;
5334 +       struct cvmx_pci_int_enb_cn31xx {
5335 +               uint64_t reserved_34_63:30;
5336 +               uint64_t ill_rd:1;
5337 +               uint64_t ill_wr:1;
5338 +               uint64_t win_wr:1;
5339 +               uint64_t dma1_fi:1;
5340 +               uint64_t dma0_fi:1;
5341 +               uint64_t idtime1:1;
5342 +               uint64_t idtime0:1;
5343 +               uint64_t idcnt1:1;
5344 +               uint64_t idcnt0:1;
5345 +               uint64_t reserved_23_24:2;
5346 +               uint64_t iptime1:1;
5347 +               uint64_t iptime0:1;
5348 +               uint64_t reserved_19_20:2;
5349 +               uint64_t ipcnt1:1;
5350 +               uint64_t ipcnt0:1;
5351 +               uint64_t irsl_int:1;
5352 +               uint64_t ill_rrd:1;
5353 +               uint64_t ill_rwr:1;
5354 +               uint64_t idperr:1;
5355 +               uint64_t iaperr:1;
5356 +               uint64_t iserr:1;
5357 +               uint64_t itsr_abt:1;
5358 +               uint64_t imsc_msg:1;
5359 +               uint64_t imsi_mabt:1;
5360 +               uint64_t imsi_tabt:1;
5361 +               uint64_t imsi_per:1;
5362 +               uint64_t imr_tto:1;
5363 +               uint64_t imr_abt:1;
5364 +               uint64_t itr_abt:1;
5365 +               uint64_t imr_wtto:1;
5366 +               uint64_t imr_wabt:1;
5367 +               uint64_t itr_wabt:1;
5368 +       } cn31xx;
5369 +       struct cvmx_pci_int_enb_s cn38xx;
5370 +       struct cvmx_pci_int_enb_s cn38xxp2;
5371 +       struct cvmx_pci_int_enb_cn31xx cn50xx;
5372 +       struct cvmx_pci_int_enb_s cn58xx;
5373 +       struct cvmx_pci_int_enb_s cn58xxp1;
5374 +};
5375 +
5376 +union cvmx_pci_int_enb2 {
5377 +       uint64_t u64;
5378 +       struct cvmx_pci_int_enb2_s {
5379 +               uint64_t reserved_34_63:30;
5380 +               uint64_t ill_rd:1;
5381 +               uint64_t ill_wr:1;
5382 +               uint64_t win_wr:1;
5383 +               uint64_t dma1_fi:1;
5384 +               uint64_t dma0_fi:1;
5385 +               uint64_t rdtime1:1;
5386 +               uint64_t rdtime0:1;
5387 +               uint64_t rdcnt1:1;
5388 +               uint64_t rdcnt0:1;
5389 +               uint64_t rptime3:1;
5390 +               uint64_t rptime2:1;
5391 +               uint64_t rptime1:1;
5392 +               uint64_t rptime0:1;
5393 +               uint64_t rpcnt3:1;
5394 +               uint64_t rpcnt2:1;
5395 +               uint64_t rpcnt1:1;
5396 +               uint64_t rpcnt0:1;
5397 +               uint64_t rrsl_int:1;
5398 +               uint64_t ill_rrd:1;
5399 +               uint64_t ill_rwr:1;
5400 +               uint64_t rdperr:1;
5401 +               uint64_t raperr:1;
5402 +               uint64_t rserr:1;
5403 +               uint64_t rtsr_abt:1;
5404 +               uint64_t rmsc_msg:1;
5405 +               uint64_t rmsi_mabt:1;
5406 +               uint64_t rmsi_tabt:1;
5407 +               uint64_t rmsi_per:1;
5408 +               uint64_t rmr_tto:1;
5409 +               uint64_t rmr_abt:1;
5410 +               uint64_t rtr_abt:1;
5411 +               uint64_t rmr_wtto:1;
5412 +               uint64_t rmr_wabt:1;
5413 +               uint64_t rtr_wabt:1;
5414 +       } s;
5415 +       struct cvmx_pci_int_enb2_cn30xx {
5416 +               uint64_t reserved_34_63:30;
5417 +               uint64_t ill_rd:1;
5418 +               uint64_t ill_wr:1;
5419 +               uint64_t win_wr:1;
5420 +               uint64_t dma1_fi:1;
5421 +               uint64_t dma0_fi:1;
5422 +               uint64_t rdtime1:1;
5423 +               uint64_t rdtime0:1;
5424 +               uint64_t rdcnt1:1;
5425 +               uint64_t rdcnt0:1;
5426 +               uint64_t reserved_22_24:3;
5427 +               uint64_t rptime0:1;
5428 +               uint64_t reserved_18_20:3;
5429 +               uint64_t rpcnt0:1;
5430 +               uint64_t rrsl_int:1;
5431 +               uint64_t ill_rrd:1;
5432 +               uint64_t ill_rwr:1;
5433 +               uint64_t rdperr:1;
5434 +               uint64_t raperr:1;
5435 +               uint64_t rserr:1;
5436 +               uint64_t rtsr_abt:1;
5437 +               uint64_t rmsc_msg:1;
5438 +               uint64_t rmsi_mabt:1;
5439 +               uint64_t rmsi_tabt:1;
5440 +               uint64_t rmsi_per:1;
5441 +               uint64_t rmr_tto:1;
5442 +               uint64_t rmr_abt:1;
5443 +               uint64_t rtr_abt:1;
5444 +               uint64_t rmr_wtto:1;
5445 +               uint64_t rmr_wabt:1;
5446 +               uint64_t rtr_wabt:1;
5447 +       } cn30xx;
5448 +       struct cvmx_pci_int_enb2_cn31xx {
5449 +               uint64_t reserved_34_63:30;
5450 +               uint64_t ill_rd:1;
5451 +               uint64_t ill_wr:1;
5452 +               uint64_t win_wr:1;
5453 +               uint64_t dma1_fi:1;
5454 +               uint64_t dma0_fi:1;
5455 +               uint64_t rdtime1:1;
5456 +               uint64_t rdtime0:1;
5457 +               uint64_t rdcnt1:1;
5458 +               uint64_t rdcnt0:1;
5459 +               uint64_t reserved_23_24:2;
5460 +               uint64_t rptime1:1;
5461 +               uint64_t rptime0:1;
5462 +               uint64_t reserved_19_20:2;
5463 +               uint64_t rpcnt1:1;
5464 +               uint64_t rpcnt0:1;
5465 +               uint64_t rrsl_int:1;
5466 +               uint64_t ill_rrd:1;
5467 +               uint64_t ill_rwr:1;
5468 +               uint64_t rdperr:1;
5469 +               uint64_t raperr:1;
5470 +               uint64_t rserr:1;
5471 +               uint64_t rtsr_abt:1;
5472 +               uint64_t rmsc_msg:1;
5473 +               uint64_t rmsi_mabt:1;
5474 +               uint64_t rmsi_tabt:1;
5475 +               uint64_t rmsi_per:1;
5476 +               uint64_t rmr_tto:1;
5477 +               uint64_t rmr_abt:1;
5478 +               uint64_t rtr_abt:1;
5479 +               uint64_t rmr_wtto:1;
5480 +               uint64_t rmr_wabt:1;
5481 +               uint64_t rtr_wabt:1;
5482 +       } cn31xx;
5483 +       struct cvmx_pci_int_enb2_s cn38xx;
5484 +       struct cvmx_pci_int_enb2_s cn38xxp2;
5485 +       struct cvmx_pci_int_enb2_cn31xx cn50xx;
5486 +       struct cvmx_pci_int_enb2_s cn58xx;
5487 +       struct cvmx_pci_int_enb2_s cn58xxp1;
5488 +};
5489 +
5490 +union cvmx_pci_int_sum {
5491 +       uint64_t u64;
5492 +       struct cvmx_pci_int_sum_s {
5493 +               uint64_t reserved_34_63:30;
5494 +               uint64_t ill_rd:1;
5495 +               uint64_t ill_wr:1;
5496 +               uint64_t win_wr:1;
5497 +               uint64_t dma1_fi:1;
5498 +               uint64_t dma0_fi:1;
5499 +               uint64_t dtime1:1;
5500 +               uint64_t dtime0:1;
5501 +               uint64_t dcnt1:1;
5502 +               uint64_t dcnt0:1;
5503 +               uint64_t ptime3:1;
5504 +               uint64_t ptime2:1;
5505 +               uint64_t ptime1:1;
5506 +               uint64_t ptime0:1;
5507 +               uint64_t pcnt3:1;
5508 +               uint64_t pcnt2:1;
5509 +               uint64_t pcnt1:1;
5510 +               uint64_t pcnt0:1;
5511 +               uint64_t rsl_int:1;
5512 +               uint64_t ill_rrd:1;
5513 +               uint64_t ill_rwr:1;
5514 +               uint64_t dperr:1;
5515 +               uint64_t aperr:1;
5516 +               uint64_t serr:1;
5517 +               uint64_t tsr_abt:1;
5518 +               uint64_t msc_msg:1;
5519 +               uint64_t msi_mabt:1;
5520 +               uint64_t msi_tabt:1;
5521 +               uint64_t msi_per:1;
5522 +               uint64_t mr_tto:1;
5523 +               uint64_t mr_abt:1;
5524 +               uint64_t tr_abt:1;
5525 +               uint64_t mr_wtto:1;
5526 +               uint64_t mr_wabt:1;
5527 +               uint64_t tr_wabt:1;
5528 +       } s;
5529 +       struct cvmx_pci_int_sum_cn30xx {
5530 +               uint64_t reserved_34_63:30;
5531 +               uint64_t ill_rd:1;
5532 +               uint64_t ill_wr:1;
5533 +               uint64_t win_wr:1;
5534 +               uint64_t dma1_fi:1;
5535 +               uint64_t dma0_fi:1;
5536 +               uint64_t dtime1:1;
5537 +               uint64_t dtime0:1;
5538 +               uint64_t dcnt1:1;
5539 +               uint64_t dcnt0:1;
5540 +               uint64_t reserved_22_24:3;
5541 +               uint64_t ptime0:1;
5542 +               uint64_t reserved_18_20:3;
5543 +               uint64_t pcnt0:1;
5544 +               uint64_t rsl_int:1;
5545 +               uint64_t ill_rrd:1;
5546 +               uint64_t ill_rwr:1;
5547 +               uint64_t dperr:1;
5548 +               uint64_t aperr:1;
5549 +               uint64_t serr:1;
5550 +               uint64_t tsr_abt:1;
5551 +               uint64_t msc_msg:1;
5552 +               uint64_t msi_mabt:1;
5553 +               uint64_t msi_tabt:1;
5554 +               uint64_t msi_per:1;
5555 +               uint64_t mr_tto:1;
5556 +               uint64_t mr_abt:1;
5557 +               uint64_t tr_abt:1;
5558 +               uint64_t mr_wtto:1;
5559 +               uint64_t mr_wabt:1;
5560 +               uint64_t tr_wabt:1;
5561 +       } cn30xx;
5562 +       struct cvmx_pci_int_sum_cn31xx {
5563 +               uint64_t reserved_34_63:30;
5564 +               uint64_t ill_rd:1;
5565 +               uint64_t ill_wr:1;
5566 +               uint64_t win_wr:1;
5567 +               uint64_t dma1_fi:1;
5568 +               uint64_t dma0_fi:1;
5569 +               uint64_t dtime1:1;
5570 +               uint64_t dtime0:1;
5571 +               uint64_t dcnt1:1;
5572 +               uint64_t dcnt0:1;
5573 +               uint64_t reserved_23_24:2;
5574 +               uint64_t ptime1:1;
5575 +               uint64_t ptime0:1;
5576 +               uint64_t reserved_19_20:2;
5577 +               uint64_t pcnt1:1;
5578 +               uint64_t pcnt0:1;
5579 +               uint64_t rsl_int:1;
5580 +               uint64_t ill_rrd:1;
5581 +               uint64_t ill_rwr:1;
5582 +               uint64_t dperr:1;
5583 +               uint64_t aperr:1;
5584 +               uint64_t serr:1;
5585 +               uint64_t tsr_abt:1;
5586 +               uint64_t msc_msg:1;
5587 +               uint64_t msi_mabt:1;
5588 +               uint64_t msi_tabt:1;
5589 +               uint64_t msi_per:1;
5590 +               uint64_t mr_tto:1;
5591 +               uint64_t mr_abt:1;
5592 +               uint64_t tr_abt:1;
5593 +               uint64_t mr_wtto:1;
5594 +               uint64_t mr_wabt:1;
5595 +               uint64_t tr_wabt:1;
5596 +       } cn31xx;
5597 +       struct cvmx_pci_int_sum_s cn38xx;
5598 +       struct cvmx_pci_int_sum_s cn38xxp2;
5599 +       struct cvmx_pci_int_sum_cn31xx cn50xx;
5600 +       struct cvmx_pci_int_sum_s cn58xx;
5601 +       struct cvmx_pci_int_sum_s cn58xxp1;
5602 +};
5603 +
5604 +union cvmx_pci_int_sum2 {
5605 +       uint64_t u64;
5606 +       struct cvmx_pci_int_sum2_s {
5607 +               uint64_t reserved_34_63:30;
5608 +               uint64_t ill_rd:1;
5609 +               uint64_t ill_wr:1;
5610 +               uint64_t win_wr:1;
5611 +               uint64_t dma1_fi:1;
5612 +               uint64_t dma0_fi:1;
5613 +               uint64_t dtime1:1;
5614 +               uint64_t dtime0:1;
5615 +               uint64_t dcnt1:1;
5616 +               uint64_t dcnt0:1;
5617 +               uint64_t ptime3:1;
5618 +               uint64_t ptime2:1;
5619 +               uint64_t ptime1:1;
5620 +               uint64_t ptime0:1;
5621 +               uint64_t pcnt3:1;
5622 +               uint64_t pcnt2:1;
5623 +               uint64_t pcnt1:1;
5624 +               uint64_t pcnt0:1;
5625 +               uint64_t rsl_int:1;
5626 +               uint64_t ill_rrd:1;
5627 +               uint64_t ill_rwr:1;
5628 +               uint64_t dperr:1;
5629 +               uint64_t aperr:1;
5630 +               uint64_t serr:1;
5631 +               uint64_t tsr_abt:1;
5632 +               uint64_t msc_msg:1;
5633 +               uint64_t msi_mabt:1;
5634 +               uint64_t msi_tabt:1;
5635 +               uint64_t msi_per:1;
5636 +               uint64_t mr_tto:1;
5637 +               uint64_t mr_abt:1;
5638 +               uint64_t tr_abt:1;
5639 +               uint64_t mr_wtto:1;
5640 +               uint64_t mr_wabt:1;
5641 +               uint64_t tr_wabt:1;
5642 +       } s;
5643 +       struct cvmx_pci_int_sum2_cn30xx {
5644 +               uint64_t reserved_34_63:30;
5645 +               uint64_t ill_rd:1;
5646 +               uint64_t ill_wr:1;
5647 +               uint64_t win_wr:1;
5648 +               uint64_t dma1_fi:1;
5649 +               uint64_t dma0_fi:1;
5650 +               uint64_t dtime1:1;
5651 +               uint64_t dtime0:1;
5652 +               uint64_t dcnt1:1;
5653 +               uint64_t dcnt0:1;
5654 +               uint64_t reserved_22_24:3;
5655 +               uint64_t ptime0:1;
5656 +               uint64_t reserved_18_20:3;
5657 +               uint64_t pcnt0:1;
5658 +               uint64_t rsl_int:1;
5659 +               uint64_t ill_rrd:1;
5660 +               uint64_t ill_rwr:1;
5661 +               uint64_t dperr:1;
5662 +               uint64_t aperr:1;
5663 +               uint64_t serr:1;
5664 +               uint64_t tsr_abt:1;
5665 +               uint64_t msc_msg:1;
5666 +               uint64_t msi_mabt:1;
5667 +               uint64_t msi_tabt:1;
5668 +               uint64_t msi_per:1;
5669 +               uint64_t mr_tto:1;
5670 +               uint64_t mr_abt:1;
5671 +               uint64_t tr_abt:1;
5672 +               uint64_t mr_wtto:1;
5673 +               uint64_t mr_wabt:1;
5674 +               uint64_t tr_wabt:1;
5675 +       } cn30xx;
5676 +       struct cvmx_pci_int_sum2_cn31xx {
5677 +               uint64_t reserved_34_63:30;
5678 +               uint64_t ill_rd:1;
5679 +               uint64_t ill_wr:1;
5680 +               uint64_t win_wr:1;
5681 +               uint64_t dma1_fi:1;
5682 +               uint64_t dma0_fi:1;
5683 +               uint64_t dtime1:1;
5684 +               uint64_t dtime0:1;
5685 +               uint64_t dcnt1:1;
5686 +               uint64_t dcnt0:1;
5687 +               uint64_t reserved_23_24:2;
5688 +               uint64_t ptime1:1;
5689 +               uint64_t ptime0:1;
5690 +               uint64_t reserved_19_20:2;
5691 +               uint64_t pcnt1:1;
5692 +               uint64_t pcnt0:1;
5693 +               uint64_t rsl_int:1;
5694 +               uint64_t ill_rrd:1;
5695 +               uint64_t ill_rwr:1;
5696 +               uint64_t dperr:1;
5697 +               uint64_t aperr:1;
5698 +               uint64_t serr:1;
5699 +               uint64_t tsr_abt:1;
5700 +               uint64_t msc_msg:1;
5701 +               uint64_t msi_mabt:1;
5702 +               uint64_t msi_tabt:1;
5703 +               uint64_t msi_per:1;
5704 +               uint64_t mr_tto:1;
5705 +               uint64_t mr_abt:1;
5706 +               uint64_t tr_abt:1;
5707 +               uint64_t mr_wtto:1;
5708 +               uint64_t mr_wabt:1;
5709 +               uint64_t tr_wabt:1;
5710 +       } cn31xx;
5711 +       struct cvmx_pci_int_sum2_s cn38xx;
5712 +       struct cvmx_pci_int_sum2_s cn38xxp2;
5713 +       struct cvmx_pci_int_sum2_cn31xx cn50xx;
5714 +       struct cvmx_pci_int_sum2_s cn58xx;
5715 +       struct cvmx_pci_int_sum2_s cn58xxp1;
5716 +};
5717 +
5718 +union cvmx_pci_msi_rcv {
5719 +       uint32_t u32;
5720 +       struct cvmx_pci_msi_rcv_s {
5721 +               uint32_t reserved_6_31:26;
5722 +               uint32_t intr:6;
5723 +       } s;
5724 +       struct cvmx_pci_msi_rcv_s cn30xx;
5725 +       struct cvmx_pci_msi_rcv_s cn31xx;
5726 +       struct cvmx_pci_msi_rcv_s cn38xx;
5727 +       struct cvmx_pci_msi_rcv_s cn38xxp2;
5728 +       struct cvmx_pci_msi_rcv_s cn50xx;
5729 +       struct cvmx_pci_msi_rcv_s cn58xx;
5730 +       struct cvmx_pci_msi_rcv_s cn58xxp1;
5731 +};
5732 +
5733 +union cvmx_pci_pkt_creditsx {
5734 +       uint32_t u32;
5735 +       struct cvmx_pci_pkt_creditsx_s {
5736 +               uint32_t pkt_cnt:16;
5737 +               uint32_t ptr_cnt:16;
5738 +       } s;
5739 +       struct cvmx_pci_pkt_creditsx_s cn30xx;
5740 +       struct cvmx_pci_pkt_creditsx_s cn31xx;
5741 +       struct cvmx_pci_pkt_creditsx_s cn38xx;
5742 +       struct cvmx_pci_pkt_creditsx_s cn38xxp2;
5743 +       struct cvmx_pci_pkt_creditsx_s cn50xx;
5744 +       struct cvmx_pci_pkt_creditsx_s cn58xx;
5745 +       struct cvmx_pci_pkt_creditsx_s cn58xxp1;
5746 +};
5747 +
5748 +union cvmx_pci_pkts_sentx {
5749 +       uint32_t u32;
5750 +       struct cvmx_pci_pkts_sentx_s {
5751 +               uint32_t pkt_cnt:32;
5752 +       } s;
5753 +       struct cvmx_pci_pkts_sentx_s cn30xx;
5754 +       struct cvmx_pci_pkts_sentx_s cn31xx;
5755 +       struct cvmx_pci_pkts_sentx_s cn38xx;
5756 +       struct cvmx_pci_pkts_sentx_s cn38xxp2;
5757 +       struct cvmx_pci_pkts_sentx_s cn50xx;
5758 +       struct cvmx_pci_pkts_sentx_s cn58xx;
5759 +       struct cvmx_pci_pkts_sentx_s cn58xxp1;
5760 +};
5761 +
5762 +union cvmx_pci_pkts_sent_int_levx {
5763 +       uint32_t u32;
5764 +       struct cvmx_pci_pkts_sent_int_levx_s {
5765 +               uint32_t pkt_cnt:32;
5766 +       } s;
5767 +       struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
5768 +       struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
5769 +       struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
5770 +       struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
5771 +       struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
5772 +       struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
5773 +       struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
5774 +};
5775 +
5776 +union cvmx_pci_pkts_sent_timex {
5777 +       uint32_t u32;
5778 +       struct cvmx_pci_pkts_sent_timex_s {
5779 +               uint32_t pkt_time:32;
5780 +       } s;
5781 +       struct cvmx_pci_pkts_sent_timex_s cn30xx;
5782 +       struct cvmx_pci_pkts_sent_timex_s cn31xx;
5783 +       struct cvmx_pci_pkts_sent_timex_s cn38xx;
5784 +       struct cvmx_pci_pkts_sent_timex_s cn38xxp2;
5785 +       struct cvmx_pci_pkts_sent_timex_s cn50xx;
5786 +       struct cvmx_pci_pkts_sent_timex_s cn58xx;
5787 +       struct cvmx_pci_pkts_sent_timex_s cn58xxp1;
5788 +};
5789 +
5790 +union cvmx_pci_read_cmd_6 {
5791 +       uint32_t u32;
5792 +       struct cvmx_pci_read_cmd_6_s {
5793 +               uint32_t reserved_9_31:23;
5794 +               uint32_t min_data:6;
5795 +               uint32_t prefetch:3;
5796 +       } s;
5797 +       struct cvmx_pci_read_cmd_6_s cn30xx;
5798 +       struct cvmx_pci_read_cmd_6_s cn31xx;
5799 +       struct cvmx_pci_read_cmd_6_s cn38xx;
5800 +       struct cvmx_pci_read_cmd_6_s cn38xxp2;
5801 +       struct cvmx_pci_read_cmd_6_s cn50xx;
5802 +       struct cvmx_pci_read_cmd_6_s cn58xx;
5803 +       struct cvmx_pci_read_cmd_6_s cn58xxp1;
5804 +};
5805 +
5806 +union cvmx_pci_read_cmd_c {
5807 +       uint32_t u32;
5808 +       struct cvmx_pci_read_cmd_c_s {
5809 +               uint32_t reserved_9_31:23;
5810 +               uint32_t min_data:6;
5811 +               uint32_t prefetch:3;
5812 +       } s;
5813 +       struct cvmx_pci_read_cmd_c_s cn30xx;
5814 +       struct cvmx_pci_read_cmd_c_s cn31xx;
5815 +       struct cvmx_pci_read_cmd_c_s cn38xx;
5816 +       struct cvmx_pci_read_cmd_c_s cn38xxp2;
5817 +       struct cvmx_pci_read_cmd_c_s cn50xx;
5818 +       struct cvmx_pci_read_cmd_c_s cn58xx;
5819 +       struct cvmx_pci_read_cmd_c_s cn58xxp1;
5820 +};
5821 +
5822 +union cvmx_pci_read_cmd_e {
5823 +       uint32_t u32;
5824 +       struct cvmx_pci_read_cmd_e_s {
5825 +               uint32_t reserved_9_31:23;
5826 +               uint32_t min_data:6;
5827 +               uint32_t prefetch:3;
5828 +       } s;
5829 +       struct cvmx_pci_read_cmd_e_s cn30xx;
5830 +       struct cvmx_pci_read_cmd_e_s cn31xx;
5831 +       struct cvmx_pci_read_cmd_e_s cn38xx;
5832 +       struct cvmx_pci_read_cmd_e_s cn38xxp2;
5833 +       struct cvmx_pci_read_cmd_e_s cn50xx;
5834 +       struct cvmx_pci_read_cmd_e_s cn58xx;
5835 +       struct cvmx_pci_read_cmd_e_s cn58xxp1;
5836 +};
5837 +
5838 +union cvmx_pci_read_timeout {
5839 +       uint64_t u64;
5840 +       struct cvmx_pci_read_timeout_s {
5841 +               uint64_t reserved_32_63:32;
5842 +               uint64_t enb:1;
5843 +               uint64_t cnt:31;
5844 +       } s;
5845 +       struct cvmx_pci_read_timeout_s cn30xx;
5846 +       struct cvmx_pci_read_timeout_s cn31xx;
5847 +       struct cvmx_pci_read_timeout_s cn38xx;
5848 +       struct cvmx_pci_read_timeout_s cn38xxp2;
5849 +       struct cvmx_pci_read_timeout_s cn50xx;
5850 +       struct cvmx_pci_read_timeout_s cn58xx;
5851 +       struct cvmx_pci_read_timeout_s cn58xxp1;
5852 +};
5853 +
5854 +union cvmx_pci_scm_reg {
5855 +       uint64_t u64;
5856 +       struct cvmx_pci_scm_reg_s {
5857 +               uint64_t reserved_32_63:32;
5858 +               uint64_t scm:32;
5859 +       } s;
5860 +       struct cvmx_pci_scm_reg_s cn30xx;
5861 +       struct cvmx_pci_scm_reg_s cn31xx;
5862 +       struct cvmx_pci_scm_reg_s cn38xx;
5863 +       struct cvmx_pci_scm_reg_s cn38xxp2;
5864 +       struct cvmx_pci_scm_reg_s cn50xx;
5865 +       struct cvmx_pci_scm_reg_s cn58xx;
5866 +       struct cvmx_pci_scm_reg_s cn58xxp1;
5867 +};
5868 +
5869 +union cvmx_pci_tsr_reg {
5870 +       uint64_t u64;
5871 +       struct cvmx_pci_tsr_reg_s {
5872 +               uint64_t reserved_36_63:28;
5873 +               uint64_t tsr:36;
5874 +       } s;
5875 +       struct cvmx_pci_tsr_reg_s cn30xx;
5876 +       struct cvmx_pci_tsr_reg_s cn31xx;
5877 +       struct cvmx_pci_tsr_reg_s cn38xx;
5878 +       struct cvmx_pci_tsr_reg_s cn38xxp2;
5879 +       struct cvmx_pci_tsr_reg_s cn50xx;
5880 +       struct cvmx_pci_tsr_reg_s cn58xx;
5881 +       struct cvmx_pci_tsr_reg_s cn58xxp1;
5882 +};
5883 +
5884 +union cvmx_pci_win_rd_addr {
5885 +       uint64_t u64;
5886 +       struct cvmx_pci_win_rd_addr_s {
5887 +               uint64_t reserved_49_63:15;
5888 +               uint64_t iobit:1;
5889 +               uint64_t reserved_0_47:48;
5890 +       } s;
5891 +       struct cvmx_pci_win_rd_addr_cn30xx {
5892 +               uint64_t reserved_49_63:15;
5893 +               uint64_t iobit:1;
5894 +               uint64_t rd_addr:46;
5895 +               uint64_t reserved_0_1:2;
5896 +       } cn30xx;
5897 +       struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
5898 +       struct cvmx_pci_win_rd_addr_cn38xx {
5899 +               uint64_t reserved_49_63:15;
5900 +               uint64_t iobit:1;
5901 +               uint64_t rd_addr:45;
5902 +               uint64_t reserved_0_2:3;
5903 +       } cn38xx;
5904 +       struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2;
5905 +       struct cvmx_pci_win_rd_addr_cn30xx cn50xx;
5906 +       struct cvmx_pci_win_rd_addr_cn38xx cn58xx;
5907 +       struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1;
5908 +};
5909 +
5910 +union cvmx_pci_win_rd_data {
5911 +       uint64_t u64;
5912 +       struct cvmx_pci_win_rd_data_s {
5913 +               uint64_t rd_data:64;
5914 +       } s;
5915 +       struct cvmx_pci_win_rd_data_s cn30xx;
5916 +       struct cvmx_pci_win_rd_data_s cn31xx;
5917 +       struct cvmx_pci_win_rd_data_s cn38xx;
5918 +       struct cvmx_pci_win_rd_data_s cn38xxp2;
5919 +       struct cvmx_pci_win_rd_data_s cn50xx;
5920 +       struct cvmx_pci_win_rd_data_s cn58xx;
5921 +       struct cvmx_pci_win_rd_data_s cn58xxp1;
5922 +};
5923 +
5924 +union cvmx_pci_win_wr_addr {
5925 +       uint64_t u64;
5926 +       struct cvmx_pci_win_wr_addr_s {
5927 +               uint64_t reserved_49_63:15;
5928 +               uint64_t iobit:1;
5929 +               uint64_t wr_addr:45;
5930 +               uint64_t reserved_0_2:3;
5931 +       } s;
5932 +       struct cvmx_pci_win_wr_addr_s cn30xx;
5933 +       struct cvmx_pci_win_wr_addr_s cn31xx;
5934 +       struct cvmx_pci_win_wr_addr_s cn38xx;
5935 +       struct cvmx_pci_win_wr_addr_s cn38xxp2;
5936 +       struct cvmx_pci_win_wr_addr_s cn50xx;
5937 +       struct cvmx_pci_win_wr_addr_s cn58xx;
5938 +       struct cvmx_pci_win_wr_addr_s cn58xxp1;
5939 +};
5940 +
5941 +union cvmx_pci_win_wr_data {
5942 +       uint64_t u64;
5943 +       struct cvmx_pci_win_wr_data_s {
5944 +               uint64_t wr_data:64;
5945 +       } s;
5946 +       struct cvmx_pci_win_wr_data_s cn30xx;
5947 +       struct cvmx_pci_win_wr_data_s cn31xx;
5948 +       struct cvmx_pci_win_wr_data_s cn38xx;
5949 +       struct cvmx_pci_win_wr_data_s cn38xxp2;
5950 +       struct cvmx_pci_win_wr_data_s cn50xx;
5951 +       struct cvmx_pci_win_wr_data_s cn58xx;
5952 +       struct cvmx_pci_win_wr_data_s cn58xxp1;
5953 +};
5954 +
5955 +union cvmx_pci_win_wr_mask {
5956 +       uint64_t u64;
5957 +       struct cvmx_pci_win_wr_mask_s {
5958 +               uint64_t reserved_8_63:56;
5959 +               uint64_t wr_mask:8;
5960 +       } s;
5961 +       struct cvmx_pci_win_wr_mask_s cn30xx;
5962 +       struct cvmx_pci_win_wr_mask_s cn31xx;
5963 +       struct cvmx_pci_win_wr_mask_s cn38xx;
5964 +       struct cvmx_pci_win_wr_mask_s cn38xxp2;
5965 +       struct cvmx_pci_win_wr_mask_s cn50xx;
5966 +       struct cvmx_pci_win_wr_mask_s cn58xx;
5967 +       struct cvmx_pci_win_wr_mask_s cn58xxp1;
5968 +};
5969 +
5970 +#endif
5971 --- /dev/null
5972 +++ b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
5973 @@ -0,0 +1,1365 @@
5974 +/***********************license start***************
5975 + * Author: Cavium Networks
5976 + *
5977 + * Contact: support@caviumnetworks.com
5978 + * This file is part of the OCTEON SDK
5979 + *
5980 + * Copyright (c) 2003-2008 Cavium Networks
5981 + *
5982 + * This file is free software; you can redistribute it and/or modify
5983 + * it under the terms of the GNU General Public License, Version 2, as
5984 + * published by the Free Software Foundation.
5985 + *
5986 + * This file is distributed in the hope that it will be useful, but
5987 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
5988 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
5989 + * NONINFRINGEMENT.  See the GNU General Public License for more
5990 + * details.
5991 + *
5992 + * You should have received a copy of the GNU General Public License
5993 + * along with this file; if not, write to the Free Software
5994 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
5995 + * or visit http://www.gnu.org/licenses/.
5996 + *
5997 + * This file may also be available under a different license from Cavium.
5998 + * Contact Cavium Networks for more information
5999 + ***********************license end**************************************/
6000 +
6001 +#ifndef __CVMX_PCIEEP_DEFS_H__
6002 +#define __CVMX_PCIEEP_DEFS_H__
6003 +
6004 +#define CVMX_PCIEEP_CFG000 \
6005 +        (0x0000000000000000ull)
6006 +#define CVMX_PCIEEP_CFG001 \
6007 +        (0x0000000000000004ull)
6008 +#define CVMX_PCIEEP_CFG002 \
6009 +        (0x0000000000000008ull)
6010 +#define CVMX_PCIEEP_CFG003 \
6011 +        (0x000000000000000Cull)
6012 +#define CVMX_PCIEEP_CFG004 \
6013 +        (0x0000000000000010ull)
6014 +#define CVMX_PCIEEP_CFG004_MASK \
6015 +        (0x0000000080000010ull)
6016 +#define CVMX_PCIEEP_CFG005 \
6017 +        (0x0000000000000014ull)
6018 +#define CVMX_PCIEEP_CFG005_MASK \
6019 +        (0x0000000080000014ull)
6020 +#define CVMX_PCIEEP_CFG006 \
6021 +        (0x0000000000000018ull)
6022 +#define CVMX_PCIEEP_CFG006_MASK \
6023 +        (0x0000000080000018ull)
6024 +#define CVMX_PCIEEP_CFG007 \
6025 +        (0x000000000000001Cull)
6026 +#define CVMX_PCIEEP_CFG007_MASK \
6027 +        (0x000000008000001Cull)
6028 +#define CVMX_PCIEEP_CFG008 \
6029 +        (0x0000000000000020ull)
6030 +#define CVMX_PCIEEP_CFG008_MASK \
6031 +        (0x0000000080000020ull)
6032 +#define CVMX_PCIEEP_CFG009 \
6033 +        (0x0000000000000024ull)
6034 +#define CVMX_PCIEEP_CFG009_MASK \
6035 +        (0x0000000080000024ull)
6036 +#define CVMX_PCIEEP_CFG010 \
6037 +        (0x0000000000000028ull)
6038 +#define CVMX_PCIEEP_CFG011 \
6039 +        (0x000000000000002Cull)
6040 +#define CVMX_PCIEEP_CFG012 \
6041 +        (0x0000000000000030ull)
6042 +#define CVMX_PCIEEP_CFG012_MASK \
6043 +        (0x0000000080000030ull)
6044 +#define CVMX_PCIEEP_CFG013 \
6045 +        (0x0000000000000034ull)
6046 +#define CVMX_PCIEEP_CFG015 \
6047 +        (0x000000000000003Cull)
6048 +#define CVMX_PCIEEP_CFG016 \
6049 +        (0x0000000000000040ull)
6050 +#define CVMX_PCIEEP_CFG017 \
6051 +        (0x0000000000000044ull)
6052 +#define CVMX_PCIEEP_CFG020 \
6053 +        (0x0000000000000050ull)
6054 +#define CVMX_PCIEEP_CFG021 \
6055 +        (0x0000000000000054ull)
6056 +#define CVMX_PCIEEP_CFG022 \
6057 +        (0x0000000000000058ull)
6058 +#define CVMX_PCIEEP_CFG023 \
6059 +        (0x000000000000005Cull)
6060 +#define CVMX_PCIEEP_CFG028 \
6061 +        (0x0000000000000070ull)
6062 +#define CVMX_PCIEEP_CFG029 \
6063 +        (0x0000000000000074ull)
6064 +#define CVMX_PCIEEP_CFG030 \
6065 +        (0x0000000000000078ull)
6066 +#define CVMX_PCIEEP_CFG031 \
6067 +        (0x000000000000007Cull)
6068 +#define CVMX_PCIEEP_CFG032 \
6069 +        (0x0000000000000080ull)
6070 +#define CVMX_PCIEEP_CFG033 \
6071 +        (0x0000000000000084ull)
6072 +#define CVMX_PCIEEP_CFG034 \
6073 +        (0x0000000000000088ull)
6074 +#define CVMX_PCIEEP_CFG037 \
6075 +        (0x0000000000000094ull)
6076 +#define CVMX_PCIEEP_CFG038 \
6077 +        (0x0000000000000098ull)
6078 +#define CVMX_PCIEEP_CFG039 \
6079 +        (0x000000000000009Cull)
6080 +#define CVMX_PCIEEP_CFG040 \
6081 +        (0x00000000000000A0ull)
6082 +#define CVMX_PCIEEP_CFG041 \
6083 +        (0x00000000000000A4ull)
6084 +#define CVMX_PCIEEP_CFG042 \
6085 +        (0x00000000000000A8ull)
6086 +#define CVMX_PCIEEP_CFG064 \
6087 +        (0x0000000000000100ull)
6088 +#define CVMX_PCIEEP_CFG065 \
6089 +        (0x0000000000000104ull)
6090 +#define CVMX_PCIEEP_CFG066 \
6091 +        (0x0000000000000108ull)
6092 +#define CVMX_PCIEEP_CFG067 \
6093 +        (0x000000000000010Cull)
6094 +#define CVMX_PCIEEP_CFG068 \
6095 +        (0x0000000000000110ull)
6096 +#define CVMX_PCIEEP_CFG069 \
6097 +        (0x0000000000000114ull)
6098 +#define CVMX_PCIEEP_CFG070 \
6099 +        (0x0000000000000118ull)
6100 +#define CVMX_PCIEEP_CFG071 \
6101 +        (0x000000000000011Cull)
6102 +#define CVMX_PCIEEP_CFG072 \
6103 +        (0x0000000000000120ull)
6104 +#define CVMX_PCIEEP_CFG073 \
6105 +        (0x0000000000000124ull)
6106 +#define CVMX_PCIEEP_CFG074 \
6107 +        (0x0000000000000128ull)
6108 +#define CVMX_PCIEEP_CFG448 \
6109 +        (0x0000000000000700ull)
6110 +#define CVMX_PCIEEP_CFG449 \
6111 +        (0x0000000000000704ull)
6112 +#define CVMX_PCIEEP_CFG450 \
6113 +        (0x0000000000000708ull)
6114 +#define CVMX_PCIEEP_CFG451 \
6115 +        (0x000000000000070Cull)
6116 +#define CVMX_PCIEEP_CFG452 \
6117 +        (0x0000000000000710ull)
6118 +#define CVMX_PCIEEP_CFG453 \
6119 +        (0x0000000000000714ull)
6120 +#define CVMX_PCIEEP_CFG454 \
6121 +        (0x0000000000000718ull)
6122 +#define CVMX_PCIEEP_CFG455 \
6123 +        (0x000000000000071Cull)
6124 +#define CVMX_PCIEEP_CFG456 \
6125 +        (0x0000000000000720ull)
6126 +#define CVMX_PCIEEP_CFG458 \
6127 +        (0x0000000000000728ull)
6128 +#define CVMX_PCIEEP_CFG459 \
6129 +        (0x000000000000072Cull)
6130 +#define CVMX_PCIEEP_CFG460 \
6131 +        (0x0000000000000730ull)
6132 +#define CVMX_PCIEEP_CFG461 \
6133 +        (0x0000000000000734ull)
6134 +#define CVMX_PCIEEP_CFG462 \
6135 +        (0x0000000000000738ull)
6136 +#define CVMX_PCIEEP_CFG463 \
6137 +        (0x000000000000073Cull)
6138 +#define CVMX_PCIEEP_CFG464 \
6139 +        (0x0000000000000740ull)
6140 +#define CVMX_PCIEEP_CFG465 \
6141 +        (0x0000000000000744ull)
6142 +#define CVMX_PCIEEP_CFG466 \
6143 +        (0x0000000000000748ull)
6144 +#define CVMX_PCIEEP_CFG467 \
6145 +        (0x000000000000074Cull)
6146 +#define CVMX_PCIEEP_CFG468 \
6147 +        (0x0000000000000750ull)
6148 +#define CVMX_PCIEEP_CFG490 \
6149 +        (0x00000000000007A8ull)
6150 +#define CVMX_PCIEEP_CFG491 \
6151 +        (0x00000000000007ACull)
6152 +#define CVMX_PCIEEP_CFG492 \
6153 +        (0x00000000000007B0ull)
6154 +#define CVMX_PCIEEP_CFG516 \
6155 +        (0x0000000000000810ull)
6156 +#define CVMX_PCIEEP_CFG517 \
6157 +        (0x0000000000000814ull)
6158 +
6159 +union cvmx_pcieep_cfg000 {
6160 +       uint32_t u32;
6161 +       struct cvmx_pcieep_cfg000_s {
6162 +               uint32_t devid:16;
6163 +               uint32_t vendid:16;
6164 +       } s;
6165 +       struct cvmx_pcieep_cfg000_s cn52xx;
6166 +       struct cvmx_pcieep_cfg000_s cn52xxp1;
6167 +       struct cvmx_pcieep_cfg000_s cn56xx;
6168 +       struct cvmx_pcieep_cfg000_s cn56xxp1;
6169 +};
6170 +
6171 +union cvmx_pcieep_cfg001 {
6172 +       uint32_t u32;
6173 +       struct cvmx_pcieep_cfg001_s {
6174 +               uint32_t dpe:1;
6175 +               uint32_t sse:1;
6176 +               uint32_t rma:1;
6177 +               uint32_t rta:1;
6178 +               uint32_t sta:1;
6179 +               uint32_t devt:2;
6180 +               uint32_t mdpe:1;
6181 +               uint32_t fbb:1;
6182 +               uint32_t reserved_22_22:1;
6183 +               uint32_t m66:1;
6184 +               uint32_t cl:1;
6185 +               uint32_t i_stat:1;
6186 +               uint32_t reserved_11_18:8;
6187 +               uint32_t i_dis:1;
6188 +               uint32_t fbbe:1;
6189 +               uint32_t see:1;
6190 +               uint32_t ids_wcc:1;
6191 +               uint32_t per:1;
6192 +               uint32_t vps:1;
6193 +               uint32_t mwice:1;
6194 +               uint32_t scse:1;
6195 +               uint32_t me:1;
6196 +               uint32_t msae:1;
6197 +               uint32_t isae:1;
6198 +       } s;
6199 +       struct cvmx_pcieep_cfg001_s cn52xx;
6200 +       struct cvmx_pcieep_cfg001_s cn52xxp1;
6201 +       struct cvmx_pcieep_cfg001_s cn56xx;
6202 +       struct cvmx_pcieep_cfg001_s cn56xxp1;
6203 +};
6204 +
6205 +union cvmx_pcieep_cfg002 {
6206 +       uint32_t u32;
6207 +       struct cvmx_pcieep_cfg002_s {
6208 +               uint32_t bcc:8;
6209 +               uint32_t sc:8;
6210 +               uint32_t pi:8;
6211 +               uint32_t rid:8;
6212 +       } s;
6213 +       struct cvmx_pcieep_cfg002_s cn52xx;
6214 +       struct cvmx_pcieep_cfg002_s cn52xxp1;
6215 +       struct cvmx_pcieep_cfg002_s cn56xx;
6216 +       struct cvmx_pcieep_cfg002_s cn56xxp1;
6217 +};
6218 +
6219 +union cvmx_pcieep_cfg003 {
6220 +       uint32_t u32;
6221 +       struct cvmx_pcieep_cfg003_s {
6222 +               uint32_t bist:8;
6223 +               uint32_t mfd:1;
6224 +               uint32_t chf:7;
6225 +               uint32_t lt:8;
6226 +               uint32_t cls:8;
6227 +       } s;
6228 +       struct cvmx_pcieep_cfg003_s cn52xx;
6229 +       struct cvmx_pcieep_cfg003_s cn52xxp1;
6230 +       struct cvmx_pcieep_cfg003_s cn56xx;
6231 +       struct cvmx_pcieep_cfg003_s cn56xxp1;
6232 +};
6233 +
6234 +union cvmx_pcieep_cfg004 {
6235 +       uint32_t u32;
6236 +       struct cvmx_pcieep_cfg004_s {
6237 +               uint32_t lbab:18;
6238 +               uint32_t reserved_4_13:10;
6239 +               uint32_t pf:1;
6240 +               uint32_t typ:2;
6241 +               uint32_t mspc:1;
6242 +       } s;
6243 +       struct cvmx_pcieep_cfg004_s cn52xx;
6244 +       struct cvmx_pcieep_cfg004_s cn52xxp1;
6245 +       struct cvmx_pcieep_cfg004_s cn56xx;
6246 +       struct cvmx_pcieep_cfg004_s cn56xxp1;
6247 +};
6248 +
6249 +union cvmx_pcieep_cfg004_mask {
6250 +       uint32_t u32;
6251 +       struct cvmx_pcieep_cfg004_mask_s {
6252 +               uint32_t lmask:31;
6253 +               uint32_t enb:1;
6254 +       } s;
6255 +       struct cvmx_pcieep_cfg004_mask_s cn52xx;
6256 +       struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
6257 +       struct cvmx_pcieep_cfg004_mask_s cn56xx;
6258 +       struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
6259 +};
6260 +
6261 +union cvmx_pcieep_cfg005 {
6262 +       uint32_t u32;
6263 +       struct cvmx_pcieep_cfg005_s {
6264 +               uint32_t ubab:32;
6265 +       } s;
6266 +       struct cvmx_pcieep_cfg005_s cn52xx;
6267 +       struct cvmx_pcieep_cfg005_s cn52xxp1;
6268 +       struct cvmx_pcieep_cfg005_s cn56xx;
6269 +       struct cvmx_pcieep_cfg005_s cn56xxp1;
6270 +};
6271 +
6272 +union cvmx_pcieep_cfg005_mask {
6273 +       uint32_t u32;
6274 +       struct cvmx_pcieep_cfg005_mask_s {
6275 +               uint32_t umask:32;
6276 +       } s;
6277 +       struct cvmx_pcieep_cfg005_mask_s cn52xx;
6278 +       struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
6279 +       struct cvmx_pcieep_cfg005_mask_s cn56xx;
6280 +       struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
6281 +};
6282 +
6283 +union cvmx_pcieep_cfg006 {
6284 +       uint32_t u32;
6285 +       struct cvmx_pcieep_cfg006_s {
6286 +               uint32_t lbab:6;
6287 +               uint32_t reserved_4_25:22;
6288 +               uint32_t pf:1;
6289 +               uint32_t typ:2;
6290 +               uint32_t mspc:1;
6291 +       } s;
6292 +       struct cvmx_pcieep_cfg006_s cn52xx;
6293 +       struct cvmx_pcieep_cfg006_s cn52xxp1;
6294 +       struct cvmx_pcieep_cfg006_s cn56xx;
6295 +       struct cvmx_pcieep_cfg006_s cn56xxp1;
6296 +};
6297 +
6298 +union cvmx_pcieep_cfg006_mask {
6299 +       uint32_t u32;
6300 +       struct cvmx_pcieep_cfg006_mask_s {
6301 +               uint32_t lmask:31;
6302 +               uint32_t enb:1;
6303 +       } s;
6304 +       struct cvmx_pcieep_cfg006_mask_s cn52xx;
6305 +       struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
6306 +       struct cvmx_pcieep_cfg006_mask_s cn56xx;
6307 +       struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
6308 +};
6309 +
6310 +union cvmx_pcieep_cfg007 {
6311 +       uint32_t u32;
6312 +       struct cvmx_pcieep_cfg007_s {
6313 +               uint32_t ubab:32;
6314 +       } s;
6315 +       struct cvmx_pcieep_cfg007_s cn52xx;
6316 +       struct cvmx_pcieep_cfg007_s cn52xxp1;
6317 +       struct cvmx_pcieep_cfg007_s cn56xx;
6318 +       struct cvmx_pcieep_cfg007_s cn56xxp1;
6319 +};
6320 +
6321 +union cvmx_pcieep_cfg007_mask {
6322 +       uint32_t u32;
6323 +       struct cvmx_pcieep_cfg007_mask_s {
6324 +               uint32_t umask:32;
6325 +       } s;
6326 +       struct cvmx_pcieep_cfg007_mask_s cn52xx;
6327 +       struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
6328 +       struct cvmx_pcieep_cfg007_mask_s cn56xx;
6329 +       struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
6330 +};
6331 +
6332 +union cvmx_pcieep_cfg008 {
6333 +       uint32_t u32;
6334 +       struct cvmx_pcieep_cfg008_s {
6335 +               uint32_t reserved_4_31:28;
6336 +               uint32_t pf:1;
6337 +               uint32_t typ:2;
6338 +               uint32_t mspc:1;
6339 +       } s;
6340 +       struct cvmx_pcieep_cfg008_s cn52xx;
6341 +       struct cvmx_pcieep_cfg008_s cn52xxp1;
6342 +       struct cvmx_pcieep_cfg008_s cn56xx;
6343 +       struct cvmx_pcieep_cfg008_s cn56xxp1;
6344 +};
6345 +
6346 +union cvmx_pcieep_cfg008_mask {
6347 +       uint32_t u32;
6348 +       struct cvmx_pcieep_cfg008_mask_s {
6349 +               uint32_t lmask:31;
6350 +               uint32_t enb:1;
6351 +       } s;
6352 +       struct cvmx_pcieep_cfg008_mask_s cn52xx;
6353 +       struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
6354 +       struct cvmx_pcieep_cfg008_mask_s cn56xx;
6355 +       struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
6356 +};
6357 +
6358 +union cvmx_pcieep_cfg009 {
6359 +       uint32_t u32;
6360 +       struct cvmx_pcieep_cfg009_s {
6361 +               uint32_t ubab:25;
6362 +               uint32_t reserved_0_6:7;
6363 +       } s;
6364 +       struct cvmx_pcieep_cfg009_s cn52xx;
6365 +       struct cvmx_pcieep_cfg009_s cn52xxp1;
6366 +       struct cvmx_pcieep_cfg009_s cn56xx;
6367 +       struct cvmx_pcieep_cfg009_s cn56xxp1;
6368 +};
6369 +
6370 +union cvmx_pcieep_cfg009_mask {
6371 +       uint32_t u32;
6372 +       struct cvmx_pcieep_cfg009_mask_s {
6373 +               uint32_t umask:32;
6374 +       } s;
6375 +       struct cvmx_pcieep_cfg009_mask_s cn52xx;
6376 +       struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
6377 +       struct cvmx_pcieep_cfg009_mask_s cn56xx;
6378 +       struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
6379 +};
6380 +
6381 +union cvmx_pcieep_cfg010 {
6382 +       uint32_t u32;
6383 +       struct cvmx_pcieep_cfg010_s {
6384 +               uint32_t cisp:32;
6385 +       } s;
6386 +       struct cvmx_pcieep_cfg010_s cn52xx;
6387 +       struct cvmx_pcieep_cfg010_s cn52xxp1;
6388 +       struct cvmx_pcieep_cfg010_s cn56xx;
6389 +       struct cvmx_pcieep_cfg010_s cn56xxp1;
6390 +};
6391 +
6392 +union cvmx_pcieep_cfg011 {
6393 +       uint32_t u32;
6394 +       struct cvmx_pcieep_cfg011_s {
6395 +               uint32_t ssid:16;
6396 +               uint32_t ssvid:16;
6397 +       } s;
6398 +       struct cvmx_pcieep_cfg011_s cn52xx;
6399 +       struct cvmx_pcieep_cfg011_s cn52xxp1;
6400 +       struct cvmx_pcieep_cfg011_s cn56xx;
6401 +       struct cvmx_pcieep_cfg011_s cn56xxp1;
6402 +};
6403 +
6404 +union cvmx_pcieep_cfg012 {
6405 +       uint32_t u32;
6406 +       struct cvmx_pcieep_cfg012_s {
6407 +               uint32_t eraddr:16;
6408 +               uint32_t reserved_1_15:15;
6409 +               uint32_t er_en:1;
6410 +       } s;
6411 +       struct cvmx_pcieep_cfg012_s cn52xx;
6412 +       struct cvmx_pcieep_cfg012_s cn52xxp1;
6413 +       struct cvmx_pcieep_cfg012_s cn56xx;
6414 +       struct cvmx_pcieep_cfg012_s cn56xxp1;
6415 +};
6416 +
6417 +union cvmx_pcieep_cfg012_mask {
6418 +       uint32_t u32;
6419 +       struct cvmx_pcieep_cfg012_mask_s {
6420 +               uint32_t mask:31;
6421 +               uint32_t enb:1;
6422 +       } s;
6423 +       struct cvmx_pcieep_cfg012_mask_s cn52xx;
6424 +       struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
6425 +       struct cvmx_pcieep_cfg012_mask_s cn56xx;
6426 +       struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
6427 +};
6428 +
6429 +union cvmx_pcieep_cfg013 {
6430 +       uint32_t u32;
6431 +       struct cvmx_pcieep_cfg013_s {
6432 +               uint32_t reserved_8_31:24;
6433 +               uint32_t cp:8;
6434 +       } s;
6435 +       struct cvmx_pcieep_cfg013_s cn52xx;
6436 +       struct cvmx_pcieep_cfg013_s cn52xxp1;
6437 +       struct cvmx_pcieep_cfg013_s cn56xx;
6438 +       struct cvmx_pcieep_cfg013_s cn56xxp1;
6439 +};
6440 +
6441 +union cvmx_pcieep_cfg015 {
6442 +       uint32_t u32;
6443 +       struct cvmx_pcieep_cfg015_s {
6444 +               uint32_t ml:8;
6445 +               uint32_t mg:8;
6446 +               uint32_t inta:8;
6447 +               uint32_t il:8;
6448 +       } s;
6449 +       struct cvmx_pcieep_cfg015_s cn52xx;
6450 +       struct cvmx_pcieep_cfg015_s cn52xxp1;
6451 +       struct cvmx_pcieep_cfg015_s cn56xx;
6452 +       struct cvmx_pcieep_cfg015_s cn56xxp1;
6453 +};
6454 +
6455 +union cvmx_pcieep_cfg016 {
6456 +       uint32_t u32;
6457 +       struct cvmx_pcieep_cfg016_s {
6458 +               uint32_t pmes:5;
6459 +               uint32_t d2s:1;
6460 +               uint32_t d1s:1;
6461 +               uint32_t auxc:3;
6462 +               uint32_t dsi:1;
6463 +               uint32_t reserved_20_20:1;
6464 +               uint32_t pme_clock:1;
6465 +               uint32_t pmsv:3;
6466 +               uint32_t ncp:8;
6467 +               uint32_t pmcid:8;
6468 +       } s;
6469 +       struct cvmx_pcieep_cfg016_s cn52xx;
6470 +       struct cvmx_pcieep_cfg016_s cn52xxp1;
6471 +       struct cvmx_pcieep_cfg016_s cn56xx;
6472 +       struct cvmx_pcieep_cfg016_s cn56xxp1;
6473 +};
6474 +
6475 +union cvmx_pcieep_cfg017 {
6476 +       uint32_t u32;
6477 +       struct cvmx_pcieep_cfg017_s {
6478 +               uint32_t pmdia:8;
6479 +               uint32_t bpccee:1;
6480 +               uint32_t bd3h:1;
6481 +               uint32_t reserved_16_21:6;
6482 +               uint32_t pmess:1;
6483 +               uint32_t pmedsia:2;
6484 +               uint32_t pmds:4;
6485 +               uint32_t pmeens:1;
6486 +               uint32_t reserved_4_7:4;
6487 +               uint32_t nsr:1;
6488 +               uint32_t reserved_2_2:1;
6489 +               uint32_t ps:2;
6490 +       } s;
6491 +       struct cvmx_pcieep_cfg017_s cn52xx;
6492 +       struct cvmx_pcieep_cfg017_s cn52xxp1;
6493 +       struct cvmx_pcieep_cfg017_s cn56xx;
6494 +       struct cvmx_pcieep_cfg017_s cn56xxp1;
6495 +};
6496 +
6497 +union cvmx_pcieep_cfg020 {
6498 +       uint32_t u32;
6499 +       struct cvmx_pcieep_cfg020_s {
6500 +               uint32_t reserved_24_31:8;
6501 +               uint32_t m64:1;
6502 +               uint32_t mme:3;
6503 +               uint32_t mmc:3;
6504 +               uint32_t msien:1;
6505 +               uint32_t ncp:8;
6506 +               uint32_t msicid:8;
6507 +       } s;
6508 +       struct cvmx_pcieep_cfg020_s cn52xx;
6509 +       struct cvmx_pcieep_cfg020_s cn52xxp1;
6510 +       struct cvmx_pcieep_cfg020_s cn56xx;
6511 +       struct cvmx_pcieep_cfg020_s cn56xxp1;
6512 +};
6513 +
6514 +union cvmx_pcieep_cfg021 {
6515 +       uint32_t u32;
6516 +       struct cvmx_pcieep_cfg021_s {
6517 +               uint32_t lmsi:30;
6518 +               uint32_t reserved_0_1:2;
6519 +       } s;
6520 +       struct cvmx_pcieep_cfg021_s cn52xx;
6521 +       struct cvmx_pcieep_cfg021_s cn52xxp1;
6522 +       struct cvmx_pcieep_cfg021_s cn56xx;
6523 +       struct cvmx_pcieep_cfg021_s cn56xxp1;
6524 +};
6525 +
6526 +union cvmx_pcieep_cfg022 {
6527 +       uint32_t u32;
6528 +       struct cvmx_pcieep_cfg022_s {
6529 +               uint32_t umsi:32;
6530 +       } s;
6531 +       struct cvmx_pcieep_cfg022_s cn52xx;
6532 +       struct cvmx_pcieep_cfg022_s cn52xxp1;
6533 +       struct cvmx_pcieep_cfg022_s cn56xx;
6534 +       struct cvmx_pcieep_cfg022_s cn56xxp1;
6535 +};
6536 +
6537 +union cvmx_pcieep_cfg023 {
6538 +       uint32_t u32;
6539 +       struct cvmx_pcieep_cfg023_s {
6540 +               uint32_t reserved_16_31:16;
6541 +               uint32_t msimd:16;
6542 +       } s;
6543 +       struct cvmx_pcieep_cfg023_s cn52xx;
6544 +       struct cvmx_pcieep_cfg023_s cn52xxp1;
6545 +       struct cvmx_pcieep_cfg023_s cn56xx;
6546 +       struct cvmx_pcieep_cfg023_s cn56xxp1;
6547 +};
6548 +
6549 +union cvmx_pcieep_cfg028 {
6550 +       uint32_t u32;
6551 +       struct cvmx_pcieep_cfg028_s {
6552 +               uint32_t reserved_30_31:2;
6553 +               uint32_t imn:5;
6554 +               uint32_t si:1;
6555 +               uint32_t dpt:4;
6556 +               uint32_t pciecv:4;
6557 +               uint32_t ncp:8;
6558 +               uint32_t pcieid:8;
6559 +       } s;
6560 +       struct cvmx_pcieep_cfg028_s cn52xx;
6561 +       struct cvmx_pcieep_cfg028_s cn52xxp1;
6562 +       struct cvmx_pcieep_cfg028_s cn56xx;
6563 +       struct cvmx_pcieep_cfg028_s cn56xxp1;
6564 +};
6565 +
6566 +union cvmx_pcieep_cfg029 {
6567 +       uint32_t u32;
6568 +       struct cvmx_pcieep_cfg029_s {
6569 +               uint32_t reserved_28_31:4;
6570 +               uint32_t cspls:2;
6571 +               uint32_t csplv:8;
6572 +               uint32_t reserved_16_17:2;
6573 +               uint32_t rber:1;
6574 +               uint32_t reserved_12_14:3;
6575 +               uint32_t el1al:3;
6576 +               uint32_t el0al:3;
6577 +               uint32_t etfs:1;
6578 +               uint32_t pfs:2;
6579 +               uint32_t mpss:3;
6580 +       } s;
6581 +       struct cvmx_pcieep_cfg029_s cn52xx;
6582 +       struct cvmx_pcieep_cfg029_s cn52xxp1;
6583 +       struct cvmx_pcieep_cfg029_s cn56xx;
6584 +       struct cvmx_pcieep_cfg029_s cn56xxp1;
6585 +};
6586 +
6587 +union cvmx_pcieep_cfg030 {
6588 +       uint32_t u32;
6589 +       struct cvmx_pcieep_cfg030_s {
6590 +               uint32_t reserved_22_31:10;
6591 +               uint32_t tp:1;
6592 +               uint32_t ap_d:1;
6593 +               uint32_t ur_d:1;
6594 +               uint32_t fe_d:1;
6595 +               uint32_t nfe_d:1;
6596 +               uint32_t ce_d:1;
6597 +               uint32_t reserved_15_15:1;
6598 +               uint32_t mrrs:3;
6599 +               uint32_t ns_en:1;
6600 +               uint32_t ap_en:1;
6601 +               uint32_t pf_en:1;
6602 +               uint32_t etf_en:1;
6603 +               uint32_t mps:3;
6604 +               uint32_t ro_en:1;
6605 +               uint32_t ur_en:1;
6606 +               uint32_t fe_en:1;
6607 +               uint32_t nfe_en:1;
6608 +               uint32_t ce_en:1;
6609 +       } s;
6610 +       struct cvmx_pcieep_cfg030_s cn52xx;
6611 +       struct cvmx_pcieep_cfg030_s cn52xxp1;
6612 +       struct cvmx_pcieep_cfg030_s cn56xx;
6613 +       struct cvmx_pcieep_cfg030_s cn56xxp1;
6614 +};
6615 +
6616 +union cvmx_pcieep_cfg031 {
6617 +       uint32_t u32;
6618 +       struct cvmx_pcieep_cfg031_s {
6619 +               uint32_t pnum:8;
6620 +               uint32_t reserved_22_23:2;
6621 +               uint32_t lbnc:1;
6622 +               uint32_t dllarc:1;
6623 +               uint32_t sderc:1;
6624 +               uint32_t cpm:1;
6625 +               uint32_t l1el:3;
6626 +               uint32_t l0el:3;
6627 +               uint32_t aslpms:2;
6628 +               uint32_t mlw:6;
6629 +               uint32_t mls:4;
6630 +       } s;
6631 +       struct cvmx_pcieep_cfg031_s cn52xx;
6632 +       struct cvmx_pcieep_cfg031_s cn52xxp1;
6633 +       struct cvmx_pcieep_cfg031_s cn56xx;
6634 +       struct cvmx_pcieep_cfg031_s cn56xxp1;
6635 +};
6636 +
6637 +union cvmx_pcieep_cfg032 {
6638 +       uint32_t u32;
6639 +       struct cvmx_pcieep_cfg032_s {
6640 +               uint32_t reserved_30_31:2;
6641 +               uint32_t dlla:1;
6642 +               uint32_t scc:1;
6643 +               uint32_t lt:1;
6644 +               uint32_t reserved_26_26:1;
6645 +               uint32_t nlw:6;
6646 +               uint32_t ls:4;
6647 +               uint32_t reserved_10_15:6;
6648 +               uint32_t hawd:1;
6649 +               uint32_t ecpm:1;
6650 +               uint32_t es:1;
6651 +               uint32_t ccc:1;
6652 +               uint32_t rl:1;
6653 +               uint32_t ld:1;
6654 +               uint32_t rcb:1;
6655 +               uint32_t reserved_2_2:1;
6656 +               uint32_t aslpc:2;
6657 +       } s;
6658 +       struct cvmx_pcieep_cfg032_s cn52xx;
6659 +       struct cvmx_pcieep_cfg032_s cn52xxp1;
6660 +       struct cvmx_pcieep_cfg032_s cn56xx;
6661 +       struct cvmx_pcieep_cfg032_s cn56xxp1;
6662 +};
6663 +
6664 +union cvmx_pcieep_cfg033 {
6665 +       uint32_t u32;
6666 +       struct cvmx_pcieep_cfg033_s {
6667 +               uint32_t ps_num:13;
6668 +               uint32_t nccs:1;
6669 +               uint32_t emip:1;
6670 +               uint32_t sp_ls:2;
6671 +               uint32_t sp_lv:8;
6672 +               uint32_t hp_c:1;
6673 +               uint32_t hp_s:1;
6674 +               uint32_t pip:1;
6675 +               uint32_t aip:1;
6676 +               uint32_t mrlsp:1;
6677 +               uint32_t pcp:1;
6678 +               uint32_t abp:1;
6679 +       } s;
6680 +       struct cvmx_pcieep_cfg033_s cn52xx;
6681 +       struct cvmx_pcieep_cfg033_s cn52xxp1;
6682 +       struct cvmx_pcieep_cfg033_s cn56xx;
6683 +       struct cvmx_pcieep_cfg033_s cn56xxp1;
6684 +};
6685 +
6686 +union cvmx_pcieep_cfg034 {
6687 +       uint32_t u32;
6688 +       struct cvmx_pcieep_cfg034_s {
6689 +               uint32_t reserved_25_31:7;
6690 +               uint32_t dlls_c:1;
6691 +               uint32_t emis:1;
6692 +               uint32_t pds:1;
6693 +               uint32_t mrlss:1;
6694 +               uint32_t ccint_d:1;
6695 +               uint32_t pd_c:1;
6696 +               uint32_t mrls_c:1;
6697 +               uint32_t pf_d:1;
6698 +               uint32_t abp_d:1;
6699 +               uint32_t reserved_13_15:3;
6700 +               uint32_t dlls_en:1;
6701 +               uint32_t emic:1;
6702 +               uint32_t pcc:1;
6703 +               uint32_t pic:2;
6704 +               uint32_t aic:2;
6705 +               uint32_t hpint_en:1;
6706 +               uint32_t ccint_en:1;
6707 +               uint32_t pd_en:1;
6708 +               uint32_t mrls_en:1;
6709 +               uint32_t pf_en:1;
6710 +               uint32_t abp_en:1;
6711 +       } s;
6712 +       struct cvmx_pcieep_cfg034_s cn52xx;
6713 +       struct cvmx_pcieep_cfg034_s cn52xxp1;
6714 +       struct cvmx_pcieep_cfg034_s cn56xx;
6715 +       struct cvmx_pcieep_cfg034_s cn56xxp1;
6716 +};
6717 +
6718 +union cvmx_pcieep_cfg037 {
6719 +       uint32_t u32;
6720 +       struct cvmx_pcieep_cfg037_s {
6721 +               uint32_t reserved_5_31:27;
6722 +               uint32_t ctds:1;
6723 +               uint32_t ctrs:4;
6724 +       } s;
6725 +       struct cvmx_pcieep_cfg037_s cn52xx;
6726 +       struct cvmx_pcieep_cfg037_s cn52xxp1;
6727 +       struct cvmx_pcieep_cfg037_s cn56xx;
6728 +       struct cvmx_pcieep_cfg037_s cn56xxp1;
6729 +};
6730 +
6731 +union cvmx_pcieep_cfg038 {
6732 +       uint32_t u32;
6733 +       struct cvmx_pcieep_cfg038_s {
6734 +               uint32_t reserved_5_31:27;
6735 +               uint32_t ctd:1;
6736 +               uint32_t ctv:4;
6737 +       } s;
6738 +       struct cvmx_pcieep_cfg038_s cn52xx;
6739 +       struct cvmx_pcieep_cfg038_s cn52xxp1;
6740 +       struct cvmx_pcieep_cfg038_s cn56xx;
6741 +       struct cvmx_pcieep_cfg038_s cn56xxp1;
6742 +};
6743 +
6744 +union cvmx_pcieep_cfg039 {
6745 +       uint32_t u32;
6746 +       struct cvmx_pcieep_cfg039_s {
6747 +               uint32_t reserved_0_31:32;
6748 +       } s;
6749 +       struct cvmx_pcieep_cfg039_s cn52xx;
6750 +       struct cvmx_pcieep_cfg039_s cn52xxp1;
6751 +       struct cvmx_pcieep_cfg039_s cn56xx;
6752 +       struct cvmx_pcieep_cfg039_s cn56xxp1;
6753 +};
6754 +
6755 +union cvmx_pcieep_cfg040 {
6756 +       uint32_t u32;
6757 +       struct cvmx_pcieep_cfg040_s {
6758 +               uint32_t reserved_0_31:32;
6759 +       } s;
6760 +       struct cvmx_pcieep_cfg040_s cn52xx;
6761 +       struct cvmx_pcieep_cfg040_s cn52xxp1;
6762 +       struct cvmx_pcieep_cfg040_s cn56xx;
6763 +       struct cvmx_pcieep_cfg040_s cn56xxp1;
6764 +};
6765 +
6766 +union cvmx_pcieep_cfg041 {
6767 +       uint32_t u32;
6768 +       struct cvmx_pcieep_cfg041_s {
6769 +               uint32_t reserved_0_31:32;
6770 +       } s;
6771 +       struct cvmx_pcieep_cfg041_s cn52xx;
6772 +       struct cvmx_pcieep_cfg041_s cn52xxp1;
6773 +       struct cvmx_pcieep_cfg041_s cn56xx;
6774 +       struct cvmx_pcieep_cfg041_s cn56xxp1;
6775 +};
6776 +
6777 +union cvmx_pcieep_cfg042 {
6778 +       uint32_t u32;
6779 +       struct cvmx_pcieep_cfg042_s {
6780 +               uint32_t reserved_0_31:32;
6781 +       } s;
6782 +       struct cvmx_pcieep_cfg042_s cn52xx;
6783 +       struct cvmx_pcieep_cfg042_s cn52xxp1;
6784 +       struct cvmx_pcieep_cfg042_s cn56xx;
6785 +       struct cvmx_pcieep_cfg042_s cn56xxp1;
6786 +};
6787 +
6788 +union cvmx_pcieep_cfg064 {
6789 +       uint32_t u32;
6790 +       struct cvmx_pcieep_cfg064_s {
6791 +               uint32_t nco:12;
6792 +               uint32_t cv:4;
6793 +               uint32_t pcieec:16;
6794 +       } s;
6795 +       struct cvmx_pcieep_cfg064_s cn52xx;
6796 +       struct cvmx_pcieep_cfg064_s cn52xxp1;
6797 +       struct cvmx_pcieep_cfg064_s cn56xx;
6798 +       struct cvmx_pcieep_cfg064_s cn56xxp1;
6799 +};
6800 +
6801 +union cvmx_pcieep_cfg065 {
6802 +       uint32_t u32;
6803 +       struct cvmx_pcieep_cfg065_s {
6804 +               uint32_t reserved_21_31:11;
6805 +               uint32_t ures:1;
6806 +               uint32_t ecrces:1;
6807 +               uint32_t mtlps:1;
6808 +               uint32_t ros:1;
6809 +               uint32_t ucs:1;
6810 +               uint32_t cas:1;
6811 +               uint32_t cts:1;
6812 +               uint32_t fcpes:1;
6813 +               uint32_t ptlps:1;
6814 +               uint32_t reserved_6_11:6;
6815 +               uint32_t sdes:1;
6816 +               uint32_t dlpes:1;
6817 +               uint32_t reserved_0_3:4;
6818 +       } s;
6819 +       struct cvmx_pcieep_cfg065_s cn52xx;
6820 +       struct cvmx_pcieep_cfg065_s cn52xxp1;
6821 +       struct cvmx_pcieep_cfg065_s cn56xx;
6822 +       struct cvmx_pcieep_cfg065_s cn56xxp1;
6823 +};
6824 +
6825 +union cvmx_pcieep_cfg066 {
6826 +       uint32_t u32;
6827 +       struct cvmx_pcieep_cfg066_s {
6828 +               uint32_t reserved_21_31:11;
6829 +               uint32_t urem:1;
6830 +               uint32_t ecrcem:1;
6831 +               uint32_t mtlpm:1;
6832 +               uint32_t rom:1;
6833 +               uint32_t ucm:1;
6834 +               uint32_t cam:1;
6835 +               uint32_t ctm:1;
6836 +               uint32_t fcpem:1;
6837 +               uint32_t ptlpm:1;
6838 +               uint32_t reserved_6_11:6;
6839 +               uint32_t sdem:1;
6840 +               uint32_t dlpem:1;
6841 +               uint32_t reserved_0_3:4;
6842 +       } s;
6843 +       struct cvmx_pcieep_cfg066_s cn52xx;
6844 +       struct cvmx_pcieep_cfg066_s cn52xxp1;
6845 +       struct cvmx_pcieep_cfg066_s cn56xx;
6846 +       struct cvmx_pcieep_cfg066_s cn56xxp1;
6847 +};
6848 +
6849 +union cvmx_pcieep_cfg067 {
6850 +       uint32_t u32;
6851 +       struct cvmx_pcieep_cfg067_s {
6852 +               uint32_t reserved_21_31:11;
6853 +               uint32_t ures:1;
6854 +               uint32_t ecrces:1;
6855 +               uint32_t mtlps:1;
6856 +               uint32_t ros:1;
6857 +               uint32_t ucs:1;
6858 +               uint32_t cas:1;
6859 +               uint32_t cts:1;
6860 +               uint32_t fcpes:1;
6861 +               uint32_t ptlps:1;
6862 +               uint32_t reserved_6_11:6;
6863 +               uint32_t sdes:1;
6864 +               uint32_t dlpes:1;
6865 +               uint32_t reserved_0_3:4;
6866 +       } s;
6867 +       struct cvmx_pcieep_cfg067_s cn52xx;
6868 +       struct cvmx_pcieep_cfg067_s cn52xxp1;
6869 +       struct cvmx_pcieep_cfg067_s cn56xx;
6870 +       struct cvmx_pcieep_cfg067_s cn56xxp1;
6871 +};
6872 +
6873 +union cvmx_pcieep_cfg068 {
6874 +       uint32_t u32;
6875 +       struct cvmx_pcieep_cfg068_s {
6876 +               uint32_t reserved_14_31:18;
6877 +               uint32_t anfes:1;
6878 +               uint32_t rtts:1;
6879 +               uint32_t reserved_9_11:3;
6880 +               uint32_t rnrs:1;
6881 +               uint32_t bdllps:1;
6882 +               uint32_t btlps:1;
6883 +               uint32_t reserved_1_5:5;
6884 +               uint32_t res:1;
6885 +       } s;
6886 +       struct cvmx_pcieep_cfg068_s cn52xx;
6887 +       struct cvmx_pcieep_cfg068_s cn52xxp1;
6888 +       struct cvmx_pcieep_cfg068_s cn56xx;
6889 +       struct cvmx_pcieep_cfg068_s cn56xxp1;
6890 +};
6891 +
6892 +union cvmx_pcieep_cfg069 {
6893 +       uint32_t u32;
6894 +       struct cvmx_pcieep_cfg069_s {
6895 +               uint32_t reserved_14_31:18;
6896 +               uint32_t anfem:1;
6897 +               uint32_t rttm:1;
6898 +               uint32_t reserved_9_11:3;
6899 +               uint32_t rnrm:1;
6900 +               uint32_t bdllpm:1;
6901 +               uint32_t btlpm:1;
6902 +               uint32_t reserved_1_5:5;
6903 +               uint32_t rem:1;
6904 +       } s;
6905 +       struct cvmx_pcieep_cfg069_s cn52xx;
6906 +       struct cvmx_pcieep_cfg069_s cn52xxp1;
6907 +       struct cvmx_pcieep_cfg069_s cn56xx;
6908 +       struct cvmx_pcieep_cfg069_s cn56xxp1;
6909 +};
6910 +
6911 +union cvmx_pcieep_cfg070 {
6912 +       uint32_t u32;
6913 +       struct cvmx_pcieep_cfg070_s {
6914 +               uint32_t reserved_9_31:23;
6915 +               uint32_t ce:1;
6916 +               uint32_t cc:1;
6917 +               uint32_t ge:1;
6918 +               uint32_t gc:1;
6919 +               uint32_t fep:5;
6920 +       } s;
6921 +       struct cvmx_pcieep_cfg070_s cn52xx;
6922 +       struct cvmx_pcieep_cfg070_s cn52xxp1;
6923 +       struct cvmx_pcieep_cfg070_s cn56xx;
6924 +       struct cvmx_pcieep_cfg070_s cn56xxp1;
6925 +};
6926 +
6927 +union cvmx_pcieep_cfg071 {
6928 +       uint32_t u32;
6929 +       struct cvmx_pcieep_cfg071_s {
6930 +               uint32_t dword1:32;
6931 +       } s;
6932 +       struct cvmx_pcieep_cfg071_s cn52xx;
6933 +       struct cvmx_pcieep_cfg071_s cn52xxp1;
6934 +       struct cvmx_pcieep_cfg071_s cn56xx;
6935 +       struct cvmx_pcieep_cfg071_s cn56xxp1;
6936 +};
6937 +
6938 +union cvmx_pcieep_cfg072 {
6939 +       uint32_t u32;
6940 +       struct cvmx_pcieep_cfg072_s {
6941 +               uint32_t dword2:32;
6942 +       } s;
6943 +       struct cvmx_pcieep_cfg072_s cn52xx;
6944 +       struct cvmx_pcieep_cfg072_s cn52xxp1;
6945 +       struct cvmx_pcieep_cfg072_s cn56xx;
6946 +       struct cvmx_pcieep_cfg072_s cn56xxp1;
6947 +};
6948 +
6949 +union cvmx_pcieep_cfg073 {
6950 +       uint32_t u32;
6951 +       struct cvmx_pcieep_cfg073_s {
6952 +               uint32_t dword3:32;
6953 +       } s;
6954 +       struct cvmx_pcieep_cfg073_s cn52xx;
6955 +       struct cvmx_pcieep_cfg073_s cn52xxp1;
6956 +       struct cvmx_pcieep_cfg073_s cn56xx;
6957 +       struct cvmx_pcieep_cfg073_s cn56xxp1;
6958 +};
6959 +
6960 +union cvmx_pcieep_cfg074 {
6961 +       uint32_t u32;
6962 +       struct cvmx_pcieep_cfg074_s {
6963 +               uint32_t dword4:32;
6964 +       } s;
6965 +       struct cvmx_pcieep_cfg074_s cn52xx;
6966 +       struct cvmx_pcieep_cfg074_s cn52xxp1;
6967 +       struct cvmx_pcieep_cfg074_s cn56xx;
6968 +       struct cvmx_pcieep_cfg074_s cn56xxp1;
6969 +};
6970 +
6971 +union cvmx_pcieep_cfg448 {
6972 +       uint32_t u32;
6973 +       struct cvmx_pcieep_cfg448_s {
6974 +               uint32_t rtl:16;
6975 +               uint32_t rtltl:16;
6976 +       } s;
6977 +       struct cvmx_pcieep_cfg448_s cn52xx;
6978 +       struct cvmx_pcieep_cfg448_s cn52xxp1;
6979 +       struct cvmx_pcieep_cfg448_s cn56xx;
6980 +       struct cvmx_pcieep_cfg448_s cn56xxp1;
6981 +};
6982 +
6983 +union cvmx_pcieep_cfg449 {
6984 +       uint32_t u32;
6985 +       struct cvmx_pcieep_cfg449_s {
6986 +               uint32_t omr:32;
6987 +       } s;
6988 +       struct cvmx_pcieep_cfg449_s cn52xx;
6989 +       struct cvmx_pcieep_cfg449_s cn52xxp1;
6990 +       struct cvmx_pcieep_cfg449_s cn56xx;
6991 +       struct cvmx_pcieep_cfg449_s cn56xxp1;
6992 +};
6993 +
6994 +union cvmx_pcieep_cfg450 {
6995 +       uint32_t u32;
6996 +       struct cvmx_pcieep_cfg450_s {
6997 +               uint32_t lpec:8;
6998 +               uint32_t reserved_22_23:2;
6999 +               uint32_t link_state:6;
7000 +               uint32_t force_link:1;
7001 +               uint32_t reserved_8_14:7;
7002 +               uint32_t link_num:8;
7003 +       } s;
7004 +       struct cvmx_pcieep_cfg450_s cn52xx;
7005 +       struct cvmx_pcieep_cfg450_s cn52xxp1;
7006 +       struct cvmx_pcieep_cfg450_s cn56xx;
7007 +       struct cvmx_pcieep_cfg450_s cn56xxp1;
7008 +};
7009 +
7010 +union cvmx_pcieep_cfg451 {
7011 +       uint32_t u32;
7012 +       struct cvmx_pcieep_cfg451_s {
7013 +               uint32_t reserved_30_31:2;
7014 +               uint32_t l1el:3;
7015 +               uint32_t l0el:3;
7016 +               uint32_t n_fts_cc:8;
7017 +               uint32_t n_fts:8;
7018 +               uint32_t ack_freq:8;
7019 +       } s;
7020 +       struct cvmx_pcieep_cfg451_s cn52xx;
7021 +       struct cvmx_pcieep_cfg451_s cn52xxp1;
7022 +       struct cvmx_pcieep_cfg451_s cn56xx;
7023 +       struct cvmx_pcieep_cfg451_s cn56xxp1;
7024 +};
7025 +
7026 +union cvmx_pcieep_cfg452 {
7027 +       uint32_t u32;
7028 +       struct cvmx_pcieep_cfg452_s {
7029 +               uint32_t reserved_26_31:6;
7030 +               uint32_t eccrc:1;
7031 +               uint32_t reserved_22_24:3;
7032 +               uint32_t lme:6;
7033 +               uint32_t reserved_8_15:8;
7034 +               uint32_t flm:1;
7035 +               uint32_t reserved_6_6:1;
7036 +               uint32_t dllle:1;
7037 +               uint32_t reserved_4_4:1;
7038 +               uint32_t ra:1;
7039 +               uint32_t le:1;
7040 +               uint32_t sd:1;
7041 +               uint32_t omr:1;
7042 +       } s;
7043 +       struct cvmx_pcieep_cfg452_s cn52xx;
7044 +       struct cvmx_pcieep_cfg452_s cn52xxp1;
7045 +       struct cvmx_pcieep_cfg452_s cn56xx;
7046 +       struct cvmx_pcieep_cfg452_s cn56xxp1;
7047 +};
7048 +
7049 +union cvmx_pcieep_cfg453 {
7050 +       uint32_t u32;
7051 +       struct cvmx_pcieep_cfg453_s {
7052 +               uint32_t dlld:1;
7053 +               uint32_t reserved_26_30:5;
7054 +               uint32_t ack_nak:1;
7055 +               uint32_t fcd:1;
7056 +               uint32_t ilst:24;
7057 +       } s;
7058 +       struct cvmx_pcieep_cfg453_s cn52xx;
7059 +       struct cvmx_pcieep_cfg453_s cn52xxp1;
7060 +       struct cvmx_pcieep_cfg453_s cn56xx;
7061 +       struct cvmx_pcieep_cfg453_s cn56xxp1;
7062 +};
7063 +
7064 +union cvmx_pcieep_cfg454 {
7065 +       uint32_t u32;
7066 +       struct cvmx_pcieep_cfg454_s {
7067 +               uint32_t reserved_29_31:3;
7068 +               uint32_t tmfcwt:5;
7069 +               uint32_t tmanlt:5;
7070 +               uint32_t tmrt:5;
7071 +               uint32_t reserved_11_13:3;
7072 +               uint32_t nskps:3;
7073 +               uint32_t reserved_4_7:4;
7074 +               uint32_t ntss:4;
7075 +       } s;
7076 +       struct cvmx_pcieep_cfg454_s cn52xx;
7077 +       struct cvmx_pcieep_cfg454_s cn52xxp1;
7078 +       struct cvmx_pcieep_cfg454_s cn56xx;
7079 +       struct cvmx_pcieep_cfg454_s cn56xxp1;
7080 +};
7081 +
7082 +union cvmx_pcieep_cfg455 {
7083 +       uint32_t u32;
7084 +       struct cvmx_pcieep_cfg455_s {
7085 +               uint32_t m_cfg0_filt:1;
7086 +               uint32_t m_io_filt:1;
7087 +               uint32_t msg_ctrl:1;
7088 +               uint32_t m_cpl_ecrc_filt:1;
7089 +               uint32_t m_ecrc_filt:1;
7090 +               uint32_t m_cpl_len_err:1;
7091 +               uint32_t m_cpl_attr_err:1;
7092 +               uint32_t m_cpl_tc_err:1;
7093 +               uint32_t m_cpl_fun_err:1;
7094 +               uint32_t m_cpl_rid_err:1;
7095 +               uint32_t m_cpl_tag_err:1;
7096 +               uint32_t m_lk_filt:1;
7097 +               uint32_t m_cfg1_filt:1;
7098 +               uint32_t m_bar_match:1;
7099 +               uint32_t m_pois_filt:1;
7100 +               uint32_t m_fun:1;
7101 +               uint32_t dfcwt:1;
7102 +               uint32_t reserved_11_14:4;
7103 +               uint32_t skpiv:11;
7104 +       } s;
7105 +       struct cvmx_pcieep_cfg455_s cn52xx;
7106 +       struct cvmx_pcieep_cfg455_s cn52xxp1;
7107 +       struct cvmx_pcieep_cfg455_s cn56xx;
7108 +       struct cvmx_pcieep_cfg455_s cn56xxp1;
7109 +};
7110 +
7111 +union cvmx_pcieep_cfg456 {
7112 +       uint32_t u32;
7113 +       struct cvmx_pcieep_cfg456_s {
7114 +               uint32_t reserved_2_31:30;
7115 +               uint32_t m_vend1_drp:1;
7116 +               uint32_t m_vend0_drp:1;
7117 +       } s;
7118 +       struct cvmx_pcieep_cfg456_s cn52xx;
7119 +       struct cvmx_pcieep_cfg456_s cn52xxp1;
7120 +       struct cvmx_pcieep_cfg456_s cn56xx;
7121 +       struct cvmx_pcieep_cfg456_s cn56xxp1;
7122 +};
7123 +
7124 +union cvmx_pcieep_cfg458 {
7125 +       uint32_t u32;
7126 +       struct cvmx_pcieep_cfg458_s {
7127 +               uint32_t dbg_info_l32:32;
7128 +       } s;
7129 +       struct cvmx_pcieep_cfg458_s cn52xx;
7130 +       struct cvmx_pcieep_cfg458_s cn52xxp1;
7131 +       struct cvmx_pcieep_cfg458_s cn56xx;
7132 +       struct cvmx_pcieep_cfg458_s cn56xxp1;
7133 +};
7134 +
7135 +union cvmx_pcieep_cfg459 {
7136 +       uint32_t u32;
7137 +       struct cvmx_pcieep_cfg459_s {
7138 +               uint32_t dbg_info_u32:32;
7139 +       } s;
7140 +       struct cvmx_pcieep_cfg459_s cn52xx;
7141 +       struct cvmx_pcieep_cfg459_s cn52xxp1;
7142 +       struct cvmx_pcieep_cfg459_s cn56xx;
7143 +       struct cvmx_pcieep_cfg459_s cn56xxp1;
7144 +};
7145 +
7146 +union cvmx_pcieep_cfg460 {
7147 +       uint32_t u32;
7148 +       struct cvmx_pcieep_cfg460_s {
7149 +               uint32_t reserved_20_31:12;
7150 +               uint32_t tphfcc:8;
7151 +               uint32_t tpdfcc:12;
7152 +       } s;
7153 +       struct cvmx_pcieep_cfg460_s cn52xx;
7154 +       struct cvmx_pcieep_cfg460_s cn52xxp1;
7155 +       struct cvmx_pcieep_cfg460_s cn56xx;
7156 +       struct cvmx_pcieep_cfg460_s cn56xxp1;
7157 +};
7158 +
7159 +union cvmx_pcieep_cfg461 {
7160 +       uint32_t u32;
7161 +       struct cvmx_pcieep_cfg461_s {
7162 +               uint32_t reserved_20_31:12;
7163 +               uint32_t tchfcc:8;
7164 +               uint32_t tcdfcc:12;
7165 +       } s;
7166 +       struct cvmx_pcieep_cfg461_s cn52xx;
7167 +       struct cvmx_pcieep_cfg461_s cn52xxp1;
7168 +       struct cvmx_pcieep_cfg461_s cn56xx;
7169 +       struct cvmx_pcieep_cfg461_s cn56xxp1;
7170 +};
7171 +
7172 +union cvmx_pcieep_cfg462 {
7173 +       uint32_t u32;
7174 +       struct cvmx_pcieep_cfg462_s {
7175 +               uint32_t reserved_20_31:12;
7176 +               uint32_t tchfcc:8;
7177 +               uint32_t tcdfcc:12;
7178 +       } s;
7179 +       struct cvmx_pcieep_cfg462_s cn52xx;
7180 +       struct cvmx_pcieep_cfg462_s cn52xxp1;
7181 +       struct cvmx_pcieep_cfg462_s cn56xx;
7182 +       struct cvmx_pcieep_cfg462_s cn56xxp1;
7183 +};
7184 +
7185 +union cvmx_pcieep_cfg463 {
7186 +       uint32_t u32;
7187 +       struct cvmx_pcieep_cfg463_s {
7188 +               uint32_t reserved_3_31:29;
7189 +               uint32_t rqne:1;
7190 +               uint32_t trbne:1;
7191 +               uint32_t rtlpfccnr:1;
7192 +       } s;
7193 +       struct cvmx_pcieep_cfg463_s cn52xx;
7194 +       struct cvmx_pcieep_cfg463_s cn52xxp1;
7195 +       struct cvmx_pcieep_cfg463_s cn56xx;
7196 +       struct cvmx_pcieep_cfg463_s cn56xxp1;
7197 +};
7198 +
7199 +union cvmx_pcieep_cfg464 {
7200 +       uint32_t u32;
7201 +       struct cvmx_pcieep_cfg464_s {
7202 +               uint32_t wrr_vc3:8;
7203 +               uint32_t wrr_vc2:8;
7204 +               uint32_t wrr_vc1:8;
7205 +               uint32_t wrr_vc0:8;
7206 +       } s;
7207 +       struct cvmx_pcieep_cfg464_s cn52xx;
7208 +       struct cvmx_pcieep_cfg464_s cn52xxp1;
7209 +       struct cvmx_pcieep_cfg464_s cn56xx;
7210 +       struct cvmx_pcieep_cfg464_s cn56xxp1;
7211 +};
7212 +
7213 +union cvmx_pcieep_cfg465 {
7214 +       uint32_t u32;
7215 +       struct cvmx_pcieep_cfg465_s {
7216 +               uint32_t wrr_vc7:8;
7217 +               uint32_t wrr_vc6:8;
7218 +               uint32_t wrr_vc5:8;
7219 +               uint32_t wrr_vc4:8;
7220 +       } s;
7221 +       struct cvmx_pcieep_cfg465_s cn52xx;
7222 +       struct cvmx_pcieep_cfg465_s cn52xxp1;
7223 +       struct cvmx_pcieep_cfg465_s cn56xx;
7224 +       struct cvmx_pcieep_cfg465_s cn56xxp1;
7225 +};
7226 +
7227 +union cvmx_pcieep_cfg466 {
7228 +       uint32_t u32;
7229 +       struct cvmx_pcieep_cfg466_s {
7230 +               uint32_t rx_queue_order:1;
7231 +               uint32_t type_ordering:1;
7232 +               uint32_t reserved_24_29:6;
7233 +               uint32_t queue_mode:3;
7234 +               uint32_t reserved_20_20:1;
7235 +               uint32_t header_credits:8;
7236 +               uint32_t data_credits:12;
7237 +       } s;
7238 +       struct cvmx_pcieep_cfg466_s cn52xx;
7239 +       struct cvmx_pcieep_cfg466_s cn52xxp1;
7240 +       struct cvmx_pcieep_cfg466_s cn56xx;
7241 +       struct cvmx_pcieep_cfg466_s cn56xxp1;
7242 +};
7243 +
7244 +union cvmx_pcieep_cfg467 {
7245 +       uint32_t u32;
7246 +       struct cvmx_pcieep_cfg467_s {
7247 +               uint32_t reserved_24_31:8;
7248 +               uint32_t queue_mode:3;
7249 +               uint32_t reserved_20_20:1;
7250 +               uint32_t header_credits:8;
7251 +               uint32_t data_credits:12;
7252 +       } s;
7253 +       struct cvmx_pcieep_cfg467_s cn52xx;
7254 +       struct cvmx_pcieep_cfg467_s cn52xxp1;
7255 +       struct cvmx_pcieep_cfg467_s cn56xx;
7256 +       struct cvmx_pcieep_cfg467_s cn56xxp1;
7257 +};
7258 +
7259 +union cvmx_pcieep_cfg468 {
7260 +       uint32_t u32;
7261 +       struct cvmx_pcieep_cfg468_s {
7262 +               uint32_t reserved_24_31:8;
7263 +               uint32_t queue_mode:3;
7264 +               uint32_t reserved_20_20:1;
7265 +               uint32_t header_credits:8;
7266 +               uint32_t data_credits:12;
7267 +       } s;
7268 +       struct cvmx_pcieep_cfg468_s cn52xx;
7269 +       struct cvmx_pcieep_cfg468_s cn52xxp1;
7270 +       struct cvmx_pcieep_cfg468_s cn56xx;
7271 +       struct cvmx_pcieep_cfg468_s cn56xxp1;
7272 +};
7273 +
7274 +union cvmx_pcieep_cfg490 {
7275 +       uint32_t u32;
7276 +       struct cvmx_pcieep_cfg490_s {
7277 +               uint32_t reserved_26_31:6;
7278 +               uint32_t header_depth:10;
7279 +               uint32_t reserved_14_15:2;
7280 +               uint32_t data_depth:14;
7281 +       } s;
7282 +       struct cvmx_pcieep_cfg490_s cn52xx;
7283 +       struct cvmx_pcieep_cfg490_s cn52xxp1;
7284 +       struct cvmx_pcieep_cfg490_s cn56xx;
7285 +       struct cvmx_pcieep_cfg490_s cn56xxp1;
7286 +};
7287 +
7288 +union cvmx_pcieep_cfg491 {
7289 +       uint32_t u32;
7290 +       struct cvmx_pcieep_cfg491_s {
7291 +               uint32_t reserved_26_31:6;
7292 +               uint32_t header_depth:10;
7293 +               uint32_t reserved_14_15:2;
7294 +               uint32_t data_depth:14;
7295 +       } s;
7296 +       struct cvmx_pcieep_cfg491_s cn52xx;
7297 +       struct cvmx_pcieep_cfg491_s cn52xxp1;
7298 +       struct cvmx_pcieep_cfg491_s cn56xx;
7299 +       struct cvmx_pcieep_cfg491_s cn56xxp1;
7300 +};
7301 +
7302 +union cvmx_pcieep_cfg492 {
7303 +       uint32_t u32;
7304 +       struct cvmx_pcieep_cfg492_s {
7305 +               uint32_t reserved_26_31:6;
7306 +               uint32_t header_depth:10;
7307 +               uint32_t reserved_14_15:2;
7308 +               uint32_t data_depth:14;
7309 +       } s;
7310 +       struct cvmx_pcieep_cfg492_s cn52xx;
7311 +       struct cvmx_pcieep_cfg492_s cn52xxp1;
7312 +       struct cvmx_pcieep_cfg492_s cn56xx;
7313 +       struct cvmx_pcieep_cfg492_s cn56xxp1;
7314 +};
7315 +
7316 +union cvmx_pcieep_cfg516 {
7317 +       uint32_t u32;
7318 +       struct cvmx_pcieep_cfg516_s {
7319 +               uint32_t phy_stat:32;
7320 +       } s;
7321 +       struct cvmx_pcieep_cfg516_s cn52xx;
7322 +       struct cvmx_pcieep_cfg516_s cn52xxp1;
7323 +       struct cvmx_pcieep_cfg516_s cn56xx;
7324 +       struct cvmx_pcieep_cfg516_s cn56xxp1;
7325 +};
7326 +
7327 +union cvmx_pcieep_cfg517 {
7328 +       uint32_t u32;
7329 +       struct cvmx_pcieep_cfg517_s {
7330 +               uint32_t phy_ctrl:32;
7331 +       } s;
7332 +       struct cvmx_pcieep_cfg517_s cn52xx;
7333 +       struct cvmx_pcieep_cfg517_s cn52xxp1;
7334 +       struct cvmx_pcieep_cfg517_s cn56xx;
7335 +       struct cvmx_pcieep_cfg517_s cn56xxp1;
7336 +};
7337 +
7338 +#endif
7339 --- /dev/null
7340 +++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
7341 @@ -0,0 +1,1397 @@
7342 +/***********************license start***************
7343 + * Author: Cavium Networks
7344 + *
7345 + * Contact: support@caviumnetworks.com
7346 + * This file is part of the OCTEON SDK
7347 + *
7348 + * Copyright (c) 2003-2008 Cavium Networks
7349 + *
7350 + * This file is free software; you can redistribute it and/or modify
7351 + * it under the terms of the GNU General Public License, Version 2, as
7352 + * published by the Free Software Foundation.
7353 + *
7354 + * This file is distributed in the hope that it will be useful, but
7355 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
7356 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
7357 + * NONINFRINGEMENT.  See the GNU General Public License for more
7358 + * details.
7359 + *
7360 + * You should have received a copy of the GNU General Public License
7361 + * along with this file; if not, write to the Free Software
7362 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
7363 + * or visit http://www.gnu.org/licenses/.
7364 + *
7365 + * This file may also be available under a different license from Cavium.
7366 + * Contact Cavium Networks for more information
7367 + ***********************license end**************************************/
7368 +
7369 +#ifndef __CVMX_PCIERCX_DEFS_H__
7370 +#define __CVMX_PCIERCX_DEFS_H__
7371 +
7372 +#define CVMX_PCIERCX_CFG000(offset) \
7373 +        (0x0000000000000000ull + (((offset) & 1) * 0))
7374 +#define CVMX_PCIERCX_CFG001(offset) \
7375 +        (0x0000000000000004ull + (((offset) & 1) * 0))
7376 +#define CVMX_PCIERCX_CFG002(offset) \
7377 +        (0x0000000000000008ull + (((offset) & 1) * 0))
7378 +#define CVMX_PCIERCX_CFG003(offset) \
7379 +        (0x000000000000000Cull + (((offset) & 1) * 0))
7380 +#define CVMX_PCIERCX_CFG004(offset) \
7381 +        (0x0000000000000010ull + (((offset) & 1) * 0))
7382 +#define CVMX_PCIERCX_CFG005(offset) \
7383 +        (0x0000000000000014ull + (((offset) & 1) * 0))
7384 +#define CVMX_PCIERCX_CFG006(offset) \
7385 +        (0x0000000000000018ull + (((offset) & 1) * 0))
7386 +#define CVMX_PCIERCX_CFG007(offset) \
7387 +        (0x000000000000001Cull + (((offset) & 1) * 0))
7388 +#define CVMX_PCIERCX_CFG008(offset) \
7389 +        (0x0000000000000020ull + (((offset) & 1) * 0))
7390 +#define CVMX_PCIERCX_CFG009(offset) \
7391 +        (0x0000000000000024ull + (((offset) & 1) * 0))
7392 +#define CVMX_PCIERCX_CFG010(offset) \
7393 +        (0x0000000000000028ull + (((offset) & 1) * 0))
7394 +#define CVMX_PCIERCX_CFG011(offset) \
7395 +        (0x000000000000002Cull + (((offset) & 1) * 0))
7396 +#define CVMX_PCIERCX_CFG012(offset) \
7397 +        (0x0000000000000030ull + (((offset) & 1) * 0))
7398 +#define CVMX_PCIERCX_CFG013(offset) \
7399 +        (0x0000000000000034ull + (((offset) & 1) * 0))
7400 +#define CVMX_PCIERCX_CFG014(offset) \
7401 +        (0x0000000000000038ull + (((offset) & 1) * 0))
7402 +#define CVMX_PCIERCX_CFG015(offset) \
7403 +        (0x000000000000003Cull + (((offset) & 1) * 0))
7404 +#define CVMX_PCIERCX_CFG016(offset) \
7405 +        (0x0000000000000040ull + (((offset) & 1) * 0))
7406 +#define CVMX_PCIERCX_CFG017(offset) \
7407 +        (0x0000000000000044ull + (((offset) & 1) * 0))
7408 +#define CVMX_PCIERCX_CFG020(offset) \
7409 +        (0x0000000000000050ull + (((offset) & 1) * 0))
7410 +#define CVMX_PCIERCX_CFG021(offset) \
7411 +        (0x0000000000000054ull + (((offset) & 1) * 0))
7412 +#define CVMX_PCIERCX_CFG022(offset) \
7413 +        (0x0000000000000058ull + (((offset) & 1) * 0))
7414 +#define CVMX_PCIERCX_CFG023(offset) \
7415 +        (0x000000000000005Cull + (((offset) & 1) * 0))
7416 +#define CVMX_PCIERCX_CFG028(offset) \
7417 +        (0x0000000000000070ull + (((offset) & 1) * 0))
7418 +#define CVMX_PCIERCX_CFG029(offset) \
7419 +        (0x0000000000000074ull + (((offset) & 1) * 0))
7420 +#define CVMX_PCIERCX_CFG030(offset) \
7421 +        (0x0000000000000078ull + (((offset) & 1) * 0))
7422 +#define CVMX_PCIERCX_CFG031(offset) \
7423 +        (0x000000000000007Cull + (((offset) & 1) * 0))
7424 +#define CVMX_PCIERCX_CFG032(offset) \
7425 +        (0x0000000000000080ull + (((offset) & 1) * 0))
7426 +#define CVMX_PCIERCX_CFG033(offset) \
7427 +        (0x0000000000000084ull + (((offset) & 1) * 0))
7428 +#define CVMX_PCIERCX_CFG034(offset) \
7429 +        (0x0000000000000088ull + (((offset) & 1) * 0))
7430 +#define CVMX_PCIERCX_CFG035(offset) \
7431 +        (0x000000000000008Cull + (((offset) & 1) * 0))
7432 +#define CVMX_PCIERCX_CFG036(offset) \
7433 +        (0x0000000000000090ull + (((offset) & 1) * 0))
7434 +#define CVMX_PCIERCX_CFG037(offset) \
7435 +        (0x0000000000000094ull + (((offset) & 1) * 0))
7436 +#define CVMX_PCIERCX_CFG038(offset) \
7437 +        (0x0000000000000098ull + (((offset) & 1) * 0))
7438 +#define CVMX_PCIERCX_CFG039(offset) \
7439 +        (0x000000000000009Cull + (((offset) & 1) * 0))
7440 +#define CVMX_PCIERCX_CFG040(offset) \
7441 +        (0x00000000000000A0ull + (((offset) & 1) * 0))
7442 +#define CVMX_PCIERCX_CFG041(offset) \
7443 +        (0x00000000000000A4ull + (((offset) & 1) * 0))
7444 +#define CVMX_PCIERCX_CFG042(offset) \
7445 +        (0x00000000000000A8ull + (((offset) & 1) * 0))
7446 +#define CVMX_PCIERCX_CFG064(offset) \
7447 +        (0x0000000000000100ull + (((offset) & 1) * 0))
7448 +#define CVMX_PCIERCX_CFG065(offset) \
7449 +        (0x0000000000000104ull + (((offset) & 1) * 0))
7450 +#define CVMX_PCIERCX_CFG066(offset) \
7451 +        (0x0000000000000108ull + (((offset) & 1) * 0))
7452 +#define CVMX_PCIERCX_CFG067(offset) \
7453 +        (0x000000000000010Cull + (((offset) & 1) * 0))
7454 +#define CVMX_PCIERCX_CFG068(offset) \
7455 +        (0x0000000000000110ull + (((offset) & 1) * 0))
7456 +#define CVMX_PCIERCX_CFG069(offset) \
7457 +        (0x0000000000000114ull + (((offset) & 1) * 0))
7458 +#define CVMX_PCIERCX_CFG070(offset) \
7459 +        (0x0000000000000118ull + (((offset) & 1) * 0))
7460 +#define CVMX_PCIERCX_CFG071(offset) \
7461 +        (0x000000000000011Cull + (((offset) & 1) * 0))
7462 +#define CVMX_PCIERCX_CFG072(offset) \
7463 +        (0x0000000000000120ull + (((offset) & 1) * 0))
7464 +#define CVMX_PCIERCX_CFG073(offset) \
7465 +        (0x0000000000000124ull + (((offset) & 1) * 0))
7466 +#define CVMX_PCIERCX_CFG074(offset) \
7467 +        (0x0000000000000128ull + (((offset) & 1) * 0))
7468 +#define CVMX_PCIERCX_CFG075(offset) \
7469 +        (0x000000000000012Cull + (((offset) & 1) * 0))
7470 +#define CVMX_PCIERCX_CFG076(offset) \
7471 +        (0x0000000000000130ull + (((offset) & 1) * 0))
7472 +#define CVMX_PCIERCX_CFG077(offset) \
7473 +        (0x0000000000000134ull + (((offset) & 1) * 0))
7474 +#define CVMX_PCIERCX_CFG448(offset) \
7475 +        (0x0000000000000700ull + (((offset) & 1) * 0))
7476 +#define CVMX_PCIERCX_CFG449(offset) \
7477 +        (0x0000000000000704ull + (((offset) & 1) * 0))
7478 +#define CVMX_PCIERCX_CFG450(offset) \
7479 +        (0x0000000000000708ull + (((offset) & 1) * 0))
7480 +#define CVMX_PCIERCX_CFG451(offset) \
7481 +        (0x000000000000070Cull + (((offset) & 1) * 0))
7482 +#define CVMX_PCIERCX_CFG452(offset) \
7483 +        (0x0000000000000710ull + (((offset) & 1) * 0))
7484 +#define CVMX_PCIERCX_CFG453(offset) \
7485 +        (0x0000000000000714ull + (((offset) & 1) * 0))
7486 +#define CVMX_PCIERCX_CFG454(offset) \
7487 +        (0x0000000000000718ull + (((offset) & 1) * 0))
7488 +#define CVMX_PCIERCX_CFG455(offset) \
7489 +        (0x000000000000071Cull + (((offset) & 1) * 0))
7490 +#define CVMX_PCIERCX_CFG456(offset) \
7491 +        (0x0000000000000720ull + (((offset) & 1) * 0))
7492 +#define CVMX_PCIERCX_CFG458(offset) \
7493 +        (0x0000000000000728ull + (((offset) & 1) * 0))
7494 +#define CVMX_PCIERCX_CFG459(offset) \
7495 +        (0x000000000000072Cull + (((offset) & 1) * 0))
7496 +#define CVMX_PCIERCX_CFG460(offset) \
7497 +        (0x0000000000000730ull + (((offset) & 1) * 0))
7498 +#define CVMX_PCIERCX_CFG461(offset) \
7499 +        (0x0000000000000734ull + (((offset) & 1) * 0))
7500 +#define CVMX_PCIERCX_CFG462(offset) \
7501 +        (0x0000000000000738ull + (((offset) & 1) * 0))
7502 +#define CVMX_PCIERCX_CFG463(offset) \
7503 +        (0x000000000000073Cull + (((offset) & 1) * 0))
7504 +#define CVMX_PCIERCX_CFG464(offset) \
7505 +        (0x0000000000000740ull + (((offset) & 1) * 0))
7506 +#define CVMX_PCIERCX_CFG465(offset) \
7507 +        (0x0000000000000744ull + (((offset) & 1) * 0))
7508 +#define CVMX_PCIERCX_CFG466(offset) \
7509 +        (0x0000000000000748ull + (((offset) & 1) * 0))
7510 +#define CVMX_PCIERCX_CFG467(offset) \
7511 +        (0x000000000000074Cull + (((offset) & 1) * 0))
7512 +#define CVMX_PCIERCX_CFG468(offset) \
7513 +        (0x0000000000000750ull + (((offset) & 1) * 0))
7514 +#define CVMX_PCIERCX_CFG490(offset) \
7515 +        (0x00000000000007A8ull + (((offset) & 1) * 0))
7516 +#define CVMX_PCIERCX_CFG491(offset) \
7517 +        (0x00000000000007ACull + (((offset) & 1) * 0))
7518 +#define CVMX_PCIERCX_CFG492(offset) \
7519 +        (0x00000000000007B0ull + (((offset) & 1) * 0))
7520 +#define CVMX_PCIERCX_CFG516(offset) \
7521 +        (0x0000000000000810ull + (((offset) & 1) * 0))
7522 +#define CVMX_PCIERCX_CFG517(offset) \
7523 +        (0x0000000000000814ull + (((offset) & 1) * 0))
7524 +
7525 +union cvmx_pciercx_cfg000 {
7526 +       uint32_t u32;
7527 +       struct cvmx_pciercx_cfg000_s {
7528 +               uint32_t devid:16;
7529 +               uint32_t vendid:16;
7530 +       } s;
7531 +       struct cvmx_pciercx_cfg000_s cn52xx;
7532 +       struct cvmx_pciercx_cfg000_s cn52xxp1;
7533 +       struct cvmx_pciercx_cfg000_s cn56xx;
7534 +       struct cvmx_pciercx_cfg000_s cn56xxp1;
7535 +};
7536 +
7537 +union cvmx_pciercx_cfg001 {
7538 +       uint32_t u32;
7539 +       struct cvmx_pciercx_cfg001_s {
7540 +               uint32_t dpe:1;
7541 +               uint32_t sse:1;
7542 +               uint32_t rma:1;
7543 +               uint32_t rta:1;
7544 +               uint32_t sta:1;
7545 +               uint32_t devt:2;
7546 +               uint32_t mdpe:1;
7547 +               uint32_t fbb:1;
7548 +               uint32_t reserved_22_22:1;
7549 +               uint32_t m66:1;
7550 +               uint32_t cl:1;
7551 +               uint32_t i_stat:1;
7552 +               uint32_t reserved_11_18:8;
7553 +               uint32_t i_dis:1;
7554 +               uint32_t fbbe:1;
7555 +               uint32_t see:1;
7556 +               uint32_t ids_wcc:1;
7557 +               uint32_t per:1;
7558 +               uint32_t vps:1;
7559 +               uint32_t mwice:1;
7560 +               uint32_t scse:1;
7561 +               uint32_t me:1;
7562 +               uint32_t msae:1;
7563 +               uint32_t isae:1;
7564 +       } s;
7565 +       struct cvmx_pciercx_cfg001_s cn52xx;
7566 +       struct cvmx_pciercx_cfg001_s cn52xxp1;
7567 +       struct cvmx_pciercx_cfg001_s cn56xx;
7568 +       struct cvmx_pciercx_cfg001_s cn56xxp1;
7569 +};
7570 +
7571 +union cvmx_pciercx_cfg002 {
7572 +       uint32_t u32;
7573 +       struct cvmx_pciercx_cfg002_s {
7574 +               uint32_t bcc:8;
7575 +               uint32_t sc:8;
7576 +               uint32_t pi:8;
7577 +               uint32_t rid:8;
7578 +       } s;
7579 +       struct cvmx_pciercx_cfg002_s cn52xx;
7580 +       struct cvmx_pciercx_cfg002_s cn52xxp1;
7581 +       struct cvmx_pciercx_cfg002_s cn56xx;
7582 +       struct cvmx_pciercx_cfg002_s cn56xxp1;
7583 +};
7584 +
7585 +union cvmx_pciercx_cfg003 {
7586 +       uint32_t u32;
7587 +       struct cvmx_pciercx_cfg003_s {
7588 +               uint32_t bist:8;
7589 +               uint32_t mfd:1;
7590 +               uint32_t chf:7;
7591 +               uint32_t lt:8;
7592 +               uint32_t cls:8;
7593 +       } s;
7594 +       struct cvmx_pciercx_cfg003_s cn52xx;
7595 +       struct cvmx_pciercx_cfg003_s cn52xxp1;
7596 +       struct cvmx_pciercx_cfg003_s cn56xx;
7597 +       struct cvmx_pciercx_cfg003_s cn56xxp1;
7598 +};
7599 +
7600 +union cvmx_pciercx_cfg004 {
7601 +       uint32_t u32;
7602 +       struct cvmx_pciercx_cfg004_s {
7603 +               uint32_t reserved_0_31:32;
7604 +       } s;
7605 +       struct cvmx_pciercx_cfg004_s cn52xx;
7606 +       struct cvmx_pciercx_cfg004_s cn52xxp1;
7607 +       struct cvmx_pciercx_cfg004_s cn56xx;
7608 +       struct cvmx_pciercx_cfg004_s cn56xxp1;
7609 +};
7610 +
7611 +union cvmx_pciercx_cfg005 {
7612 +       uint32_t u32;
7613 +       struct cvmx_pciercx_cfg005_s {
7614 +               uint32_t reserved_0_31:32;
7615 +       } s;
7616 +       struct cvmx_pciercx_cfg005_s cn52xx;
7617 +       struct cvmx_pciercx_cfg005_s cn52xxp1;
7618 +       struct cvmx_pciercx_cfg005_s cn56xx;
7619 +       struct cvmx_pciercx_cfg005_s cn56xxp1;
7620 +};
7621 +
7622 +union cvmx_pciercx_cfg006 {
7623 +       uint32_t u32;
7624 +       struct cvmx_pciercx_cfg006_s {
7625 +               uint32_t slt:8;
7626 +               uint32_t subbnum:8;
7627 +               uint32_t sbnum:8;
7628 +               uint32_t pbnum:8;
7629 +       } s;
7630 +       struct cvmx_pciercx_cfg006_s cn52xx;
7631 +       struct cvmx_pciercx_cfg006_s cn52xxp1;
7632 +       struct cvmx_pciercx_cfg006_s cn56xx;
7633 +       struct cvmx_pciercx_cfg006_s cn56xxp1;
7634 +};
7635 +
7636 +union cvmx_pciercx_cfg007 {
7637 +       uint32_t u32;
7638 +       struct cvmx_pciercx_cfg007_s {
7639 +               uint32_t dpe:1;
7640 +               uint32_t sse:1;
7641 +               uint32_t rma:1;
7642 +               uint32_t rta:1;
7643 +               uint32_t sta:1;
7644 +               uint32_t devt:2;
7645 +               uint32_t mdpe:1;
7646 +               uint32_t fbb:1;
7647 +               uint32_t reserved_22_22:1;
7648 +               uint32_t m66:1;
7649 +               uint32_t reserved_16_20:5;
7650 +               uint32_t lio_limi:4;
7651 +               uint32_t reserved_9_11:3;
7652 +               uint32_t io32b:1;
7653 +               uint32_t lio_base:4;
7654 +               uint32_t reserved_1_3:3;
7655 +               uint32_t io32a:1;
7656 +       } s;
7657 +       struct cvmx_pciercx_cfg007_s cn52xx;
7658 +       struct cvmx_pciercx_cfg007_s cn52xxp1;
7659 +       struct cvmx_pciercx_cfg007_s cn56xx;
7660 +       struct cvmx_pciercx_cfg007_s cn56xxp1;
7661 +};
7662 +
7663 +union cvmx_pciercx_cfg008 {
7664 +       uint32_t u32;
7665 +       struct cvmx_pciercx_cfg008_s {
7666 +               uint32_t ml_addr:12;
7667 +               uint32_t reserved_16_19:4;
7668 +               uint32_t mb_addr:12;
7669 +               uint32_t reserved_0_3:4;
7670 +       } s;
7671 +       struct cvmx_pciercx_cfg008_s cn52xx;
7672 +       struct cvmx_pciercx_cfg008_s cn52xxp1;
7673 +       struct cvmx_pciercx_cfg008_s cn56xx;
7674 +       struct cvmx_pciercx_cfg008_s cn56xxp1;
7675 +};
7676 +
7677 +union cvmx_pciercx_cfg009 {
7678 +       uint32_t u32;
7679 +       struct cvmx_pciercx_cfg009_s {
7680 +               uint32_t lmem_limit:12;
7681 +               uint32_t reserved_17_19:3;
7682 +               uint32_t mem64b:1;
7683 +               uint32_t lmem_base:12;
7684 +               uint32_t reserved_1_3:3;
7685 +               uint32_t mem64a:1;
7686 +       } s;
7687 +       struct cvmx_pciercx_cfg009_s cn52xx;
7688 +       struct cvmx_pciercx_cfg009_s cn52xxp1;
7689 +       struct cvmx_pciercx_cfg009_s cn56xx;
7690 +       struct cvmx_pciercx_cfg009_s cn56xxp1;
7691 +};
7692 +
7693 +union cvmx_pciercx_cfg010 {
7694 +       uint32_t u32;
7695 +       struct cvmx_pciercx_cfg010_s {
7696 +               uint32_t umem_base:32;
7697 +       } s;
7698 +       struct cvmx_pciercx_cfg010_s cn52xx;
7699 +       struct cvmx_pciercx_cfg010_s cn52xxp1;
7700 +       struct cvmx_pciercx_cfg010_s cn56xx;
7701 +       struct cvmx_pciercx_cfg010_s cn56xxp1;
7702 +};
7703 +
7704 +union cvmx_pciercx_cfg011 {
7705 +       uint32_t u32;
7706 +       struct cvmx_pciercx_cfg011_s {
7707 +               uint32_t umem_limit:32;
7708 +       } s;
7709 +       struct cvmx_pciercx_cfg011_s cn52xx;
7710 +       struct cvmx_pciercx_cfg011_s cn52xxp1;
7711 +       struct cvmx_pciercx_cfg011_s cn56xx;
7712 +       struct cvmx_pciercx_cfg011_s cn56xxp1;
7713 +};
7714 +
7715 +union cvmx_pciercx_cfg012 {
7716 +       uint32_t u32;
7717 +       struct cvmx_pciercx_cfg012_s {
7718 +               uint32_t uio_limit:16;
7719 +               uint32_t uio_base:16;
7720 +       } s;
7721 +       struct cvmx_pciercx_cfg012_s cn52xx;
7722 +       struct cvmx_pciercx_cfg012_s cn52xxp1;
7723 +       struct cvmx_pciercx_cfg012_s cn56xx;
7724 +       struct cvmx_pciercx_cfg012_s cn56xxp1;
7725 +};
7726 +
7727 +union cvmx_pciercx_cfg013 {
7728 +       uint32_t u32;
7729 +       struct cvmx_pciercx_cfg013_s {
7730 +               uint32_t reserved_8_31:24;
7731 +               uint32_t cp:8;
7732 +       } s;
7733 +       struct cvmx_pciercx_cfg013_s cn52xx;
7734 +       struct cvmx_pciercx_cfg013_s cn52xxp1;
7735 +       struct cvmx_pciercx_cfg013_s cn56xx;
7736 +       struct cvmx_pciercx_cfg013_s cn56xxp1;
7737 +};
7738 +
7739 +union cvmx_pciercx_cfg014 {
7740 +       uint32_t u32;
7741 +       struct cvmx_pciercx_cfg014_s {
7742 +               uint32_t reserved_0_31:32;
7743 +       } s;
7744 +       struct cvmx_pciercx_cfg014_s cn52xx;
7745 +       struct cvmx_pciercx_cfg014_s cn52xxp1;
7746 +       struct cvmx_pciercx_cfg014_s cn56xx;
7747 +       struct cvmx_pciercx_cfg014_s cn56xxp1;
7748 +};
7749 +
7750 +union cvmx_pciercx_cfg015 {
7751 +       uint32_t u32;
7752 +       struct cvmx_pciercx_cfg015_s {
7753 +               uint32_t reserved_28_31:4;
7754 +               uint32_t dtsees:1;
7755 +               uint32_t dts:1;
7756 +               uint32_t sdt:1;
7757 +               uint32_t pdt:1;
7758 +               uint32_t fbbe:1;
7759 +               uint32_t sbrst:1;
7760 +               uint32_t mam:1;
7761 +               uint32_t vga16d:1;
7762 +               uint32_t vgae:1;
7763 +               uint32_t isae:1;
7764 +               uint32_t see:1;
7765 +               uint32_t pere:1;
7766 +               uint32_t inta:8;
7767 +               uint32_t il:8;
7768 +       } s;
7769 +       struct cvmx_pciercx_cfg015_s cn52xx;
7770 +       struct cvmx_pciercx_cfg015_s cn52xxp1;
7771 +       struct cvmx_pciercx_cfg015_s cn56xx;
7772 +       struct cvmx_pciercx_cfg015_s cn56xxp1;
7773 +};
7774 +
7775 +union cvmx_pciercx_cfg016 {
7776 +       uint32_t u32;
7777 +       struct cvmx_pciercx_cfg016_s {
7778 +               uint32_t pmes:5;
7779 +               uint32_t d2s:1;
7780 +               uint32_t d1s:1;
7781 +               uint32_t auxc:3;
7782 +               uint32_t dsi:1;
7783 +               uint32_t reserved_20_20:1;
7784 +               uint32_t pme_clock:1;
7785 +               uint32_t pmsv:3;
7786 +               uint32_t ncp:8;
7787 +               uint32_t pmcid:8;
7788 +       } s;
7789 +       struct cvmx_pciercx_cfg016_s cn52xx;
7790 +       struct cvmx_pciercx_cfg016_s cn52xxp1;
7791 +       struct cvmx_pciercx_cfg016_s cn56xx;
7792 +       struct cvmx_pciercx_cfg016_s cn56xxp1;
7793 +};
7794 +
7795 +union cvmx_pciercx_cfg017 {
7796 +       uint32_t u32;
7797 +       struct cvmx_pciercx_cfg017_s {
7798 +               uint32_t pmdia:8;
7799 +               uint32_t bpccee:1;
7800 +               uint32_t bd3h:1;
7801 +               uint32_t reserved_16_21:6;
7802 +               uint32_t pmess:1;
7803 +               uint32_t pmedsia:2;
7804 +               uint32_t pmds:4;
7805 +               uint32_t pmeens:1;
7806 +               uint32_t reserved_4_7:4;
7807 +               uint32_t nsr:1;
7808 +               uint32_t reserved_2_2:1;
7809 +               uint32_t ps:2;
7810 +       } s;
7811 +       struct cvmx_pciercx_cfg017_s cn52xx;
7812 +       struct cvmx_pciercx_cfg017_s cn52xxp1;
7813 +       struct cvmx_pciercx_cfg017_s cn56xx;
7814 +       struct cvmx_pciercx_cfg017_s cn56xxp1;
7815 +};
7816 +
7817 +union cvmx_pciercx_cfg020 {
7818 +       uint32_t u32;
7819 +       struct cvmx_pciercx_cfg020_s {
7820 +               uint32_t reserved_24_31:8;
7821 +               uint32_t m64:1;
7822 +               uint32_t mme:3;
7823 +               uint32_t mmc:3;
7824 +               uint32_t msien:1;
7825 +               uint32_t ncp:8;
7826 +               uint32_t msicid:8;
7827 +       } s;
7828 +       struct cvmx_pciercx_cfg020_s cn52xx;
7829 +       struct cvmx_pciercx_cfg020_s cn52xxp1;
7830 +       struct cvmx_pciercx_cfg020_s cn56xx;
7831 +       struct cvmx_pciercx_cfg020_s cn56xxp1;
7832 +};
7833 +
7834 +union cvmx_pciercx_cfg021 {
7835 +       uint32_t u32;
7836 +       struct cvmx_pciercx_cfg021_s {
7837 +               uint32_t lmsi:30;
7838 +               uint32_t reserved_0_1:2;
7839 +       } s;
7840 +       struct cvmx_pciercx_cfg021_s cn52xx;
7841 +       struct cvmx_pciercx_cfg021_s cn52xxp1;
7842 +       struct cvmx_pciercx_cfg021_s cn56xx;
7843 +       struct cvmx_pciercx_cfg021_s cn56xxp1;
7844 +};
7845 +
7846 +union cvmx_pciercx_cfg022 {
7847 +       uint32_t u32;
7848 +       struct cvmx_pciercx_cfg022_s {
7849 +               uint32_t umsi:32;
7850 +       } s;
7851 +       struct cvmx_pciercx_cfg022_s cn52xx;
7852 +       struct cvmx_pciercx_cfg022_s cn52xxp1;
7853 +       struct cvmx_pciercx_cfg022_s cn56xx;
7854 +       struct cvmx_pciercx_cfg022_s cn56xxp1;
7855 +};
7856 +
7857 +union cvmx_pciercx_cfg023 {
7858 +       uint32_t u32;
7859 +       struct cvmx_pciercx_cfg023_s {
7860 +               uint32_t reserved_16_31:16;
7861 +               uint32_t msimd:16;
7862 +       } s;
7863 +       struct cvmx_pciercx_cfg023_s cn52xx;
7864 +       struct cvmx_pciercx_cfg023_s cn52xxp1;
7865 +       struct cvmx_pciercx_cfg023_s cn56xx;
7866 +       struct cvmx_pciercx_cfg023_s cn56xxp1;
7867 +};
7868 +
7869 +union cvmx_pciercx_cfg028 {
7870 +       uint32_t u32;
7871 +       struct cvmx_pciercx_cfg028_s {
7872 +               uint32_t reserved_30_31:2;
7873 +               uint32_t imn:5;
7874 +               uint32_t si:1;
7875 +               uint32_t dpt:4;
7876 +               uint32_t pciecv:4;
7877 +               uint32_t ncp:8;
7878 +               uint32_t pcieid:8;
7879 +       } s;
7880 +       struct cvmx_pciercx_cfg028_s cn52xx;
7881 +       struct cvmx_pciercx_cfg028_s cn52xxp1;
7882 +       struct cvmx_pciercx_cfg028_s cn56xx;
7883 +       struct cvmx_pciercx_cfg028_s cn56xxp1;
7884 +};
7885 +
7886 +union cvmx_pciercx_cfg029 {
7887 +       uint32_t u32;
7888 +       struct cvmx_pciercx_cfg029_s {
7889 +               uint32_t reserved_28_31:4;
7890 +               uint32_t cspls:2;
7891 +               uint32_t csplv:8;
7892 +               uint32_t reserved_16_17:2;
7893 +               uint32_t rber:1;
7894 +               uint32_t reserved_12_14:3;
7895 +               uint32_t el1al:3;
7896 +               uint32_t el0al:3;
7897 +               uint32_t etfs:1;
7898 +               uint32_t pfs:2;
7899 +               uint32_t mpss:3;
7900 +       } s;
7901 +       struct cvmx_pciercx_cfg029_s cn52xx;
7902 +       struct cvmx_pciercx_cfg029_s cn52xxp1;
7903 +       struct cvmx_pciercx_cfg029_s cn56xx;
7904 +       struct cvmx_pciercx_cfg029_s cn56xxp1;
7905 +};
7906 +
7907 +union cvmx_pciercx_cfg030 {
7908 +       uint32_t u32;
7909 +       struct cvmx_pciercx_cfg030_s {
7910 +               uint32_t reserved_22_31:10;
7911 +               uint32_t tp:1;
7912 +               uint32_t ap_d:1;
7913 +               uint32_t ur_d:1;
7914 +               uint32_t fe_d:1;
7915 +               uint32_t nfe_d:1;
7916 +               uint32_t ce_d:1;
7917 +               uint32_t reserved_15_15:1;
7918 +               uint32_t mrrs:3;
7919 +               uint32_t ns_en:1;
7920 +               uint32_t ap_en:1;
7921 +               uint32_t pf_en:1;
7922 +               uint32_t etf_en:1;
7923 +               uint32_t mps:3;
7924 +               uint32_t ro_en:1;
7925 +               uint32_t ur_en:1;
7926 +               uint32_t fe_en:1;
7927 +               uint32_t nfe_en:1;
7928 +               uint32_t ce_en:1;
7929 +       } s;
7930 +       struct cvmx_pciercx_cfg030_s cn52xx;
7931 +       struct cvmx_pciercx_cfg030_s cn52xxp1;
7932 +       struct cvmx_pciercx_cfg030_s cn56xx;
7933 +       struct cvmx_pciercx_cfg030_s cn56xxp1;
7934 +};
7935 +
7936 +union cvmx_pciercx_cfg031 {
7937 +       uint32_t u32;
7938 +       struct cvmx_pciercx_cfg031_s {
7939 +               uint32_t pnum:8;
7940 +               uint32_t reserved_22_23:2;
7941 +               uint32_t lbnc:1;
7942 +               uint32_t dllarc:1;
7943 +               uint32_t sderc:1;
7944 +               uint32_t cpm:1;
7945 +               uint32_t l1el:3;
7946 +               uint32_t l0el:3;
7947 +               uint32_t aslpms:2;
7948 +               uint32_t mlw:6;
7949 +               uint32_t mls:4;
7950 +       } s;
7951 +       struct cvmx_pciercx_cfg031_s cn52xx;
7952 +       struct cvmx_pciercx_cfg031_s cn52xxp1;
7953 +       struct cvmx_pciercx_cfg031_s cn56xx;
7954 +       struct cvmx_pciercx_cfg031_s cn56xxp1;
7955 +};
7956 +
7957 +union cvmx_pciercx_cfg032 {
7958 +       uint32_t u32;
7959 +       struct cvmx_pciercx_cfg032_s {
7960 +               uint32_t lab:1;
7961 +               uint32_t lbm:1;
7962 +               uint32_t dlla:1;
7963 +               uint32_t scc:1;
7964 +               uint32_t lt:1;
7965 +               uint32_t reserved_26_26:1;
7966 +               uint32_t nlw:6;
7967 +               uint32_t ls:4;
7968 +               uint32_t reserved_12_15:4;
7969 +               uint32_t lab_int_enb:1;
7970 +               uint32_t lbm_int_enb:1;
7971 +               uint32_t hawd:1;
7972 +               uint32_t ecpm:1;
7973 +               uint32_t es:1;
7974 +               uint32_t ccc:1;
7975 +               uint32_t rl:1;
7976 +               uint32_t ld:1;
7977 +               uint32_t rcb:1;
7978 +               uint32_t reserved_2_2:1;
7979 +               uint32_t aslpc:2;
7980 +       } s;
7981 +       struct cvmx_pciercx_cfg032_s cn52xx;
7982 +       struct cvmx_pciercx_cfg032_s cn52xxp1;
7983 +       struct cvmx_pciercx_cfg032_s cn56xx;
7984 +       struct cvmx_pciercx_cfg032_s cn56xxp1;
7985 +};
7986 +
7987 +union cvmx_pciercx_cfg033 {
7988 +       uint32_t u32;
7989 +       struct cvmx_pciercx_cfg033_s {
7990 +               uint32_t ps_num:13;
7991 +               uint32_t nccs:1;
7992 +               uint32_t emip:1;
7993 +               uint32_t sp_ls:2;
7994 +               uint32_t sp_lv:8;
7995 +               uint32_t hp_c:1;
7996 +               uint32_t hp_s:1;
7997 +               uint32_t pip:1;
7998 +               uint32_t aip:1;
7999 +               uint32_t mrlsp:1;
8000 +               uint32_t pcp:1;
8001 +               uint32_t abp:1;
8002 +       } s;
8003 +       struct cvmx_pciercx_cfg033_s cn52xx;
8004 +       struct cvmx_pciercx_cfg033_s cn52xxp1;
8005 +       struct cvmx_pciercx_cfg033_s cn56xx;
8006 +       struct cvmx_pciercx_cfg033_s cn56xxp1;
8007 +};
8008 +
8009 +union cvmx_pciercx_cfg034 {
8010 +       uint32_t u32;
8011 +       struct cvmx_pciercx_cfg034_s {
8012 +               uint32_t reserved_25_31:7;
8013 +               uint32_t dlls_c:1;
8014 +               uint32_t emis:1;
8015 +               uint32_t pds:1;
8016 +               uint32_t mrlss:1;
8017 +               uint32_t ccint_d:1;
8018 +               uint32_t pd_c:1;
8019 +               uint32_t mrls_c:1;
8020 +               uint32_t pf_d:1;
8021 +               uint32_t abp_d:1;
8022 +               uint32_t reserved_13_15:3;
8023 +               uint32_t dlls_en:1;
8024 +               uint32_t emic:1;
8025 +               uint32_t pcc:1;
8026 +               uint32_t pic:2;
8027 +               uint32_t aic:2;
8028 +               uint32_t hpint_en:1;
8029 +               uint32_t ccint_en:1;
8030 +               uint32_t pd_en:1;
8031 +               uint32_t mrls_en:1;
8032 +               uint32_t pf_en:1;
8033 +               uint32_t abp_en:1;
8034 +       } s;
8035 +       struct cvmx_pciercx_cfg034_s cn52xx;
8036 +       struct cvmx_pciercx_cfg034_s cn52xxp1;
8037 +       struct cvmx_pciercx_cfg034_s cn56xx;
8038 +       struct cvmx_pciercx_cfg034_s cn56xxp1;
8039 +};
8040 +
8041 +union cvmx_pciercx_cfg035 {
8042 +       uint32_t u32;
8043 +       struct cvmx_pciercx_cfg035_s {
8044 +               uint32_t reserved_17_31:15;
8045 +               uint32_t crssv:1;
8046 +               uint32_t reserved_5_15:11;
8047 +               uint32_t crssve:1;
8048 +               uint32_t pmeie:1;
8049 +               uint32_t sefee:1;
8050 +               uint32_t senfee:1;
8051 +               uint32_t secee:1;
8052 +       } s;
8053 +       struct cvmx_pciercx_cfg035_s cn52xx;
8054 +       struct cvmx_pciercx_cfg035_s cn52xxp1;
8055 +       struct cvmx_pciercx_cfg035_s cn56xx;
8056 +       struct cvmx_pciercx_cfg035_s cn56xxp1;
8057 +};
8058 +
8059 +union cvmx_pciercx_cfg036 {
8060 +       uint32_t u32;
8061 +       struct cvmx_pciercx_cfg036_s {
8062 +               uint32_t reserved_18_31:14;
8063 +               uint32_t pme_pend:1;
8064 +               uint32_t pme_stat:1;
8065 +               uint32_t pme_rid:16;
8066 +       } s;
8067 +       struct cvmx_pciercx_cfg036_s cn52xx;
8068 +       struct cvmx_pciercx_cfg036_s cn52xxp1;
8069 +       struct cvmx_pciercx_cfg036_s cn56xx;
8070 +       struct cvmx_pciercx_cfg036_s cn56xxp1;
8071 +};
8072 +
8073 +union cvmx_pciercx_cfg037 {
8074 +       uint32_t u32;
8075 +       struct cvmx_pciercx_cfg037_s {
8076 +               uint32_t reserved_5_31:27;
8077 +               uint32_t ctds:1;
8078 +               uint32_t ctrs:4;
8079 +       } s;
8080 +       struct cvmx_pciercx_cfg037_s cn52xx;
8081 +       struct cvmx_pciercx_cfg037_s cn52xxp1;
8082 +       struct cvmx_pciercx_cfg037_s cn56xx;
8083 +       struct cvmx_pciercx_cfg037_s cn56xxp1;
8084 +};
8085 +
8086 +union cvmx_pciercx_cfg038 {
8087 +       uint32_t u32;
8088 +       struct cvmx_pciercx_cfg038_s {
8089 +               uint32_t reserved_5_31:27;
8090 +               uint32_t ctd:1;
8091 +               uint32_t ctv:4;
8092 +       } s;
8093 +       struct cvmx_pciercx_cfg038_s cn52xx;
8094 +       struct cvmx_pciercx_cfg038_s cn52xxp1;
8095 +       struct cvmx_pciercx_cfg038_s cn56xx;
8096 +       struct cvmx_pciercx_cfg038_s cn56xxp1;
8097 +};
8098 +
8099 +union cvmx_pciercx_cfg039 {
8100 +       uint32_t u32;
8101 +       struct cvmx_pciercx_cfg039_s {
8102 +               uint32_t reserved_0_31:32;
8103 +       } s;
8104 +       struct cvmx_pciercx_cfg039_s cn52xx;
8105 +       struct cvmx_pciercx_cfg039_s cn52xxp1;
8106 +       struct cvmx_pciercx_cfg039_s cn56xx;
8107 +       struct cvmx_pciercx_cfg039_s cn56xxp1;
8108 +};
8109 +
8110 +union cvmx_pciercx_cfg040 {
8111 +       uint32_t u32;
8112 +       struct cvmx_pciercx_cfg040_s {
8113 +               uint32_t reserved_0_31:32;
8114 +       } s;
8115 +       struct cvmx_pciercx_cfg040_s cn52xx;
8116 +       struct cvmx_pciercx_cfg040_s cn52xxp1;
8117 +       struct cvmx_pciercx_cfg040_s cn56xx;
8118 +       struct cvmx_pciercx_cfg040_s cn56xxp1;
8119 +};
8120 +
8121 +union cvmx_pciercx_cfg041 {
8122 +       uint32_t u32;
8123 +       struct cvmx_pciercx_cfg041_s {
8124 +               uint32_t reserved_0_31:32;
8125 +       } s;
8126 +       struct cvmx_pciercx_cfg041_s cn52xx;
8127 +       struct cvmx_pciercx_cfg041_s cn52xxp1;
8128 +       struct cvmx_pciercx_cfg041_s cn56xx;
8129 +       struct cvmx_pciercx_cfg041_s cn56xxp1;
8130 +};
8131 +
8132 +union cvmx_pciercx_cfg042 {
8133 +       uint32_t u32;
8134 +       struct cvmx_pciercx_cfg042_s {
8135 +               uint32_t reserved_0_31:32;
8136 +       } s;
8137 +       struct cvmx_pciercx_cfg042_s cn52xx;
8138 +       struct cvmx_pciercx_cfg042_s cn52xxp1;
8139 +       struct cvmx_pciercx_cfg042_s cn56xx;
8140 +       struct cvmx_pciercx_cfg042_s cn56xxp1;
8141 +};
8142 +
8143 +union cvmx_pciercx_cfg064 {
8144 +       uint32_t u32;
8145 +       struct cvmx_pciercx_cfg064_s {
8146 +               uint32_t nco:12;
8147 +               uint32_t cv:4;
8148 +               uint32_t pcieec:16;
8149 +       } s;
8150 +       struct cvmx_pciercx_cfg064_s cn52xx;
8151 +       struct cvmx_pciercx_cfg064_s cn52xxp1;
8152 +       struct cvmx_pciercx_cfg064_s cn56xx;
8153 +       struct cvmx_pciercx_cfg064_s cn56xxp1;
8154 +};
8155 +
8156 +union cvmx_pciercx_cfg065 {
8157 +       uint32_t u32;
8158 +       struct cvmx_pciercx_cfg065_s {
8159 +               uint32_t reserved_21_31:11;
8160 +               uint32_t ures:1;
8161 +               uint32_t ecrces:1;
8162 +               uint32_t mtlps:1;
8163 +               uint32_t ros:1;
8164 +               uint32_t ucs:1;
8165 +               uint32_t cas:1;
8166 +               uint32_t cts:1;
8167 +               uint32_t fcpes:1;
8168 +               uint32_t ptlps:1;
8169 +               uint32_t reserved_6_11:6;
8170 +               uint32_t sdes:1;
8171 +               uint32_t dlpes:1;
8172 +               uint32_t reserved_0_3:4;
8173 +       } s;
8174 +       struct cvmx_pciercx_cfg065_s cn52xx;
8175 +       struct cvmx_pciercx_cfg065_s cn52xxp1;
8176 +       struct cvmx_pciercx_cfg065_s cn56xx;
8177 +       struct cvmx_pciercx_cfg065_s cn56xxp1;
8178 +};
8179 +
8180 +union cvmx_pciercx_cfg066 {
8181 +       uint32_t u32;
8182 +       struct cvmx_pciercx_cfg066_s {
8183 +               uint32_t reserved_21_31:11;
8184 +               uint32_t urem:1;
8185 +               uint32_t ecrcem:1;
8186 +               uint32_t mtlpm:1;
8187 +               uint32_t rom:1;
8188 +               uint32_t ucm:1;
8189 +               uint32_t cam:1;
8190 +               uint32_t ctm:1;
8191 +               uint32_t fcpem:1;
8192 +               uint32_t ptlpm:1;
8193 +               uint32_t reserved_6_11:6;
8194 +               uint32_t sdem:1;
8195 +               uint32_t dlpem:1;
8196 +               uint32_t reserved_0_3:4;
8197 +       } s;
8198 +       struct cvmx_pciercx_cfg066_s cn52xx;
8199 +       struct cvmx_pciercx_cfg066_s cn52xxp1;
8200 +       struct cvmx_pciercx_cfg066_s cn56xx;
8201 +       struct cvmx_pciercx_cfg066_s cn56xxp1;
8202 +};
8203 +
8204 +union cvmx_pciercx_cfg067 {
8205 +       uint32_t u32;
8206 +       struct cvmx_pciercx_cfg067_s {
8207 +               uint32_t reserved_21_31:11;
8208 +               uint32_t ures:1;
8209 +               uint32_t ecrces:1;
8210 +               uint32_t mtlps:1;
8211 +               uint32_t ros:1;
8212 +               uint32_t ucs:1;
8213 +               uint32_t cas:1;
8214 +               uint32_t cts:1;
8215 +               uint32_t fcpes:1;
8216 +               uint32_t ptlps:1;
8217 +               uint32_t reserved_6_11:6;
8218 +               uint32_t sdes:1;
8219 +               uint32_t dlpes:1;
8220 +               uint32_t reserved_0_3:4;
8221 +       } s;
8222 +       struct cvmx_pciercx_cfg067_s cn52xx;
8223 +       struct cvmx_pciercx_cfg067_s cn52xxp1;
8224 +       struct cvmx_pciercx_cfg067_s cn56xx;
8225 +       struct cvmx_pciercx_cfg067_s cn56xxp1;
8226 +};
8227 +
8228 +union cvmx_pciercx_cfg068 {
8229 +       uint32_t u32;
8230 +       struct cvmx_pciercx_cfg068_s {
8231 +               uint32_t reserved_14_31:18;
8232 +               uint32_t anfes:1;
8233 +               uint32_t rtts:1;
8234 +               uint32_t reserved_9_11:3;
8235 +               uint32_t rnrs:1;
8236 +               uint32_t bdllps:1;
8237 +               uint32_t btlps:1;
8238 +               uint32_t reserved_1_5:5;
8239 +               uint32_t res:1;
8240 +       } s;
8241 +       struct cvmx_pciercx_cfg068_s cn52xx;
8242 +       struct cvmx_pciercx_cfg068_s cn52xxp1;
8243 +       struct cvmx_pciercx_cfg068_s cn56xx;
8244 +       struct cvmx_pciercx_cfg068_s cn56xxp1;
8245 +};
8246 +
8247 +union cvmx_pciercx_cfg069 {
8248 +       uint32_t u32;
8249 +       struct cvmx_pciercx_cfg069_s {
8250 +               uint32_t reserved_14_31:18;
8251 +               uint32_t anfem:1;
8252 +               uint32_t rttm:1;
8253 +               uint32_t reserved_9_11:3;
8254 +               uint32_t rnrm:1;
8255 +               uint32_t bdllpm:1;
8256 +               uint32_t btlpm:1;
8257 +               uint32_t reserved_1_5:5;
8258 +               uint32_t rem:1;
8259 +       } s;
8260 +       struct cvmx_pciercx_cfg069_s cn52xx;
8261 +       struct cvmx_pciercx_cfg069_s cn52xxp1;
8262 +       struct cvmx_pciercx_cfg069_s cn56xx;
8263 +       struct cvmx_pciercx_cfg069_s cn56xxp1;
8264 +};
8265 +
8266 +union cvmx_pciercx_cfg070 {
8267 +       uint32_t u32;
8268 +       struct cvmx_pciercx_cfg070_s {
8269 +               uint32_t reserved_9_31:23;
8270 +               uint32_t ce:1;
8271 +               uint32_t cc:1;
8272 +               uint32_t ge:1;
8273 +               uint32_t gc:1;
8274 +               uint32_t fep:5;
8275 +       } s;
8276 +       struct cvmx_pciercx_cfg070_s cn52xx;
8277 +       struct cvmx_pciercx_cfg070_s cn52xxp1;
8278 +       struct cvmx_pciercx_cfg070_s cn56xx;
8279 +       struct cvmx_pciercx_cfg070_s cn56xxp1;
8280 +};
8281 +
8282 +union cvmx_pciercx_cfg071 {
8283 +       uint32_t u32;
8284 +       struct cvmx_pciercx_cfg071_s {
8285 +               uint32_t dword1:32;
8286 +       } s;
8287 +       struct cvmx_pciercx_cfg071_s cn52xx;
8288 +       struct cvmx_pciercx_cfg071_s cn52xxp1;
8289 +       struct cvmx_pciercx_cfg071_s cn56xx;
8290 +       struct cvmx_pciercx_cfg071_s cn56xxp1;
8291 +};
8292 +
8293 +union cvmx_pciercx_cfg072 {
8294 +       uint32_t u32;
8295 +       struct cvmx_pciercx_cfg072_s {
8296 +               uint32_t dword2:32;
8297 +       } s;
8298 +       struct cvmx_pciercx_cfg072_s cn52xx;
8299 +       struct cvmx_pciercx_cfg072_s cn52xxp1;
8300 +       struct cvmx_pciercx_cfg072_s cn56xx;
8301 +       struct cvmx_pciercx_cfg072_s cn56xxp1;
8302 +};
8303 +
8304 +union cvmx_pciercx_cfg073 {
8305 +       uint32_t u32;
8306 +       struct cvmx_pciercx_cfg073_s {
8307 +               uint32_t dword3:32;
8308 +       } s;
8309 +       struct cvmx_pciercx_cfg073_s cn52xx;
8310 +       struct cvmx_pciercx_cfg073_s cn52xxp1;
8311 +       struct cvmx_pciercx_cfg073_s cn56xx;
8312 +       struct cvmx_pciercx_cfg073_s cn56xxp1;
8313 +};
8314 +
8315 +union cvmx_pciercx_cfg074 {
8316 +       uint32_t u32;
8317 +       struct cvmx_pciercx_cfg074_s {
8318 +               uint32_t dword4:32;
8319 +       } s;
8320 +       struct cvmx_pciercx_cfg074_s cn52xx;
8321 +       struct cvmx_pciercx_cfg074_s cn52xxp1;
8322 +       struct cvmx_pciercx_cfg074_s cn56xx;
8323 +       struct cvmx_pciercx_cfg074_s cn56xxp1;
8324 +};
8325 +
8326 +union cvmx_pciercx_cfg075 {
8327 +       uint32_t u32;
8328 +       struct cvmx_pciercx_cfg075_s {
8329 +               uint32_t reserved_3_31:29;
8330 +               uint32_t fere:1;
8331 +               uint32_t nfere:1;
8332 +               uint32_t cere:1;
8333 +       } s;
8334 +       struct cvmx_pciercx_cfg075_s cn52xx;
8335 +       struct cvmx_pciercx_cfg075_s cn52xxp1;
8336 +       struct cvmx_pciercx_cfg075_s cn56xx;
8337 +       struct cvmx_pciercx_cfg075_s cn56xxp1;
8338 +};
8339 +
8340 +union cvmx_pciercx_cfg076 {
8341 +       uint32_t u32;
8342 +       struct cvmx_pciercx_cfg076_s {
8343 +               uint32_t aeimn:5;
8344 +               uint32_t reserved_7_26:20;
8345 +               uint32_t femr:1;
8346 +               uint32_t nfemr:1;
8347 +               uint32_t fuf:1;
8348 +               uint32_t multi_efnfr:1;
8349 +               uint32_t efnfr:1;
8350 +               uint32_t multi_ecr:1;
8351 +               uint32_t ecr:1;
8352 +       } s;
8353 +       struct cvmx_pciercx_cfg076_s cn52xx;
8354 +       struct cvmx_pciercx_cfg076_s cn52xxp1;
8355 +       struct cvmx_pciercx_cfg076_s cn56xx;
8356 +       struct cvmx_pciercx_cfg076_s cn56xxp1;
8357 +};
8358 +
8359 +union cvmx_pciercx_cfg077 {
8360 +       uint32_t u32;
8361 +       struct cvmx_pciercx_cfg077_s {
8362 +               uint32_t efnfsi:16;
8363 +               uint32_t ecsi:16;
8364 +       } s;
8365 +       struct cvmx_pciercx_cfg077_s cn52xx;
8366 +       struct cvmx_pciercx_cfg077_s cn52xxp1;
8367 +       struct cvmx_pciercx_cfg077_s cn56xx;
8368 +       struct cvmx_pciercx_cfg077_s cn56xxp1;
8369 +};
8370 +
8371 +union cvmx_pciercx_cfg448 {
8372 +       uint32_t u32;
8373 +       struct cvmx_pciercx_cfg448_s {
8374 +               uint32_t rtl:16;
8375 +               uint32_t rtltl:16;
8376 +       } s;
8377 +       struct cvmx_pciercx_cfg448_s cn52xx;
8378 +       struct cvmx_pciercx_cfg448_s cn52xxp1;
8379 +       struct cvmx_pciercx_cfg448_s cn56xx;
8380 +       struct cvmx_pciercx_cfg448_s cn56xxp1;
8381 +};
8382 +
8383 +union cvmx_pciercx_cfg449 {
8384 +       uint32_t u32;
8385 +       struct cvmx_pciercx_cfg449_s {
8386 +               uint32_t omr:32;
8387 +       } s;
8388 +       struct cvmx_pciercx_cfg449_s cn52xx;
8389 +       struct cvmx_pciercx_cfg449_s cn52xxp1;
8390 +       struct cvmx_pciercx_cfg449_s cn56xx;
8391 +       struct cvmx_pciercx_cfg449_s cn56xxp1;
8392 +};
8393 +
8394 +union cvmx_pciercx_cfg450 {
8395 +       uint32_t u32;
8396 +       struct cvmx_pciercx_cfg450_s {
8397 +               uint32_t lpec:8;
8398 +               uint32_t reserved_22_23:2;
8399 +               uint32_t link_state:6;
8400 +               uint32_t force_link:1;
8401 +               uint32_t reserved_8_14:7;
8402 +               uint32_t link_num:8;
8403 +       } s;
8404 +       struct cvmx_pciercx_cfg450_s cn52xx;
8405 +       struct cvmx_pciercx_cfg450_s cn52xxp1;
8406 +       struct cvmx_pciercx_cfg450_s cn56xx;
8407 +       struct cvmx_pciercx_cfg450_s cn56xxp1;
8408 +};
8409 +
8410 +union cvmx_pciercx_cfg451 {
8411 +       uint32_t u32;
8412 +       struct cvmx_pciercx_cfg451_s {
8413 +               uint32_t reserved_30_31:2;
8414 +               uint32_t l1el:3;
8415 +               uint32_t l0el:3;
8416 +               uint32_t n_fts_cc:8;
8417 +               uint32_t n_fts:8;
8418 +               uint32_t ack_freq:8;
8419 +       } s;
8420 +       struct cvmx_pciercx_cfg451_s cn52xx;
8421 +       struct cvmx_pciercx_cfg451_s cn52xxp1;
8422 +       struct cvmx_pciercx_cfg451_s cn56xx;
8423 +       struct cvmx_pciercx_cfg451_s cn56xxp1;
8424 +};
8425 +
8426 +union cvmx_pciercx_cfg452 {
8427 +       uint32_t u32;
8428 +       struct cvmx_pciercx_cfg452_s {
8429 +               uint32_t reserved_26_31:6;
8430 +               uint32_t eccrc:1;
8431 +               uint32_t reserved_22_24:3;
8432 +               uint32_t lme:6;
8433 +               uint32_t reserved_8_15:8;
8434 +               uint32_t flm:1;
8435 +               uint32_t reserved_6_6:1;
8436 +               uint32_t dllle:1;
8437 +               uint32_t reserved_4_4:1;
8438 +               uint32_t ra:1;
8439 +               uint32_t le:1;
8440 +               uint32_t sd:1;
8441 +               uint32_t omr:1;
8442 +       } s;
8443 +       struct cvmx_pciercx_cfg452_s cn52xx;
8444 +       struct cvmx_pciercx_cfg452_s cn52xxp1;
8445 +       struct cvmx_pciercx_cfg452_s cn56xx;
8446 +       struct cvmx_pciercx_cfg452_s cn56xxp1;
8447 +};
8448 +
8449 +union cvmx_pciercx_cfg453 {
8450 +       uint32_t u32;
8451 +       struct cvmx_pciercx_cfg453_s {
8452 +               uint32_t dlld:1;
8453 +               uint32_t reserved_26_30:5;
8454 +               uint32_t ack_nak:1;
8455 +               uint32_t fcd:1;
8456 +               uint32_t ilst:24;
8457 +       } s;
8458 +       struct cvmx_pciercx_cfg453_s cn52xx;
8459 +       struct cvmx_pciercx_cfg453_s cn52xxp1;
8460 +       struct cvmx_pciercx_cfg453_s cn56xx;
8461 +       struct cvmx_pciercx_cfg453_s cn56xxp1;
8462 +};
8463 +
8464 +union cvmx_pciercx_cfg454 {
8465 +       uint32_t u32;
8466 +       struct cvmx_pciercx_cfg454_s {
8467 +               uint32_t reserved_29_31:3;
8468 +               uint32_t tmfcwt:5;
8469 +               uint32_t tmanlt:5;
8470 +               uint32_t tmrt:5;
8471 +               uint32_t reserved_11_13:3;
8472 +               uint32_t nskps:3;
8473 +               uint32_t reserved_4_7:4;
8474 +               uint32_t ntss:4;
8475 +       } s;
8476 +       struct cvmx_pciercx_cfg454_s cn52xx;
8477 +       struct cvmx_pciercx_cfg454_s cn52xxp1;
8478 +       struct cvmx_pciercx_cfg454_s cn56xx;
8479 +       struct cvmx_pciercx_cfg454_s cn56xxp1;
8480 +};
8481 +
8482 +union cvmx_pciercx_cfg455 {
8483 +       uint32_t u32;
8484 +       struct cvmx_pciercx_cfg455_s {
8485 +               uint32_t m_cfg0_filt:1;
8486 +               uint32_t m_io_filt:1;
8487 +               uint32_t msg_ctrl:1;
8488 +               uint32_t m_cpl_ecrc_filt:1;
8489 +               uint32_t m_ecrc_filt:1;
8490 +               uint32_t m_cpl_len_err:1;
8491 +               uint32_t m_cpl_attr_err:1;
8492 +               uint32_t m_cpl_tc_err:1;
8493 +               uint32_t m_cpl_fun_err:1;
8494 +               uint32_t m_cpl_rid_err:1;
8495 +               uint32_t m_cpl_tag_err:1;
8496 +               uint32_t m_lk_filt:1;
8497 +               uint32_t m_cfg1_filt:1;
8498 +               uint32_t m_bar_match:1;
8499 +               uint32_t m_pois_filt:1;
8500 +               uint32_t m_fun:1;
8501 +               uint32_t dfcwt:1;
8502 +               uint32_t reserved_11_14:4;
8503 +               uint32_t skpiv:11;
8504 +       } s;
8505 +       struct cvmx_pciercx_cfg455_s cn52xx;
8506 +       struct cvmx_pciercx_cfg455_s cn52xxp1;
8507 +       struct cvmx_pciercx_cfg455_s cn56xx;
8508 +       struct cvmx_pciercx_cfg455_s cn56xxp1;
8509 +};
8510 +
8511 +union cvmx_pciercx_cfg456 {
8512 +       uint32_t u32;
8513 +       struct cvmx_pciercx_cfg456_s {
8514 +               uint32_t reserved_2_31:30;
8515 +               uint32_t m_vend1_drp:1;
8516 +               uint32_t m_vend0_drp:1;
8517 +       } s;
8518 +       struct cvmx_pciercx_cfg456_s cn52xx;
8519 +       struct cvmx_pciercx_cfg456_s cn52xxp1;
8520 +       struct cvmx_pciercx_cfg456_s cn56xx;
8521 +       struct cvmx_pciercx_cfg456_s cn56xxp1;
8522 +};
8523 +
8524 +union cvmx_pciercx_cfg458 {
8525 +       uint32_t u32;
8526 +       struct cvmx_pciercx_cfg458_s {
8527 +               uint32_t dbg_info_l32:32;
8528 +       } s;
8529 +       struct cvmx_pciercx_cfg458_s cn52xx;
8530 +       struct cvmx_pciercx_cfg458_s cn52xxp1;
8531 +       struct cvmx_pciercx_cfg458_s cn56xx;
8532 +       struct cvmx_pciercx_cfg458_s cn56xxp1;
8533 +};
8534 +
8535 +union cvmx_pciercx_cfg459 {
8536 +       uint32_t u32;
8537 +       struct cvmx_pciercx_cfg459_s {
8538 +               uint32_t dbg_info_u32:32;
8539 +       } s;
8540 +       struct cvmx_pciercx_cfg459_s cn52xx;
8541 +       struct cvmx_pciercx_cfg459_s cn52xxp1;
8542 +       struct cvmx_pciercx_cfg459_s cn56xx;
8543 +       struct cvmx_pciercx_cfg459_s cn56xxp1;
8544 +};
8545 +
8546 +union cvmx_pciercx_cfg460 {
8547 +       uint32_t u32;
8548 +       struct cvmx_pciercx_cfg460_s {
8549 +               uint32_t reserved_20_31:12;
8550 +               uint32_t tphfcc:8;
8551 +               uint32_t tpdfcc:12;
8552 +       } s;
8553 +       struct cvmx_pciercx_cfg460_s cn52xx;
8554 +       struct cvmx_pciercx_cfg460_s cn52xxp1;
8555 +       struct cvmx_pciercx_cfg460_s cn56xx;
8556 +       struct cvmx_pciercx_cfg460_s cn56xxp1;
8557 +};
8558 +
8559 +union cvmx_pciercx_cfg461 {
8560 +       uint32_t u32;
8561 +       struct cvmx_pciercx_cfg461_s {
8562 +               uint32_t reserved_20_31:12;
8563 +               uint32_t tchfcc:8;
8564 +               uint32_t tcdfcc:12;
8565 +       } s;
8566 +       struct cvmx_pciercx_cfg461_s cn52xx;
8567 +       struct cvmx_pciercx_cfg461_s cn52xxp1;
8568 +       struct cvmx_pciercx_cfg461_s cn56xx;
8569 +       struct cvmx_pciercx_cfg461_s cn56xxp1;
8570 +};
8571 +
8572 +union cvmx_pciercx_cfg462 {
8573 +       uint32_t u32;
8574 +       struct cvmx_pciercx_cfg462_s {
8575 +               uint32_t reserved_20_31:12;
8576 +               uint32_t tchfcc:8;
8577 +               uint32_t tcdfcc:12;
8578 +       } s;
8579 +       struct cvmx_pciercx_cfg462_s cn52xx;
8580 +       struct cvmx_pciercx_cfg462_s cn52xxp1;
8581 +       struct cvmx_pciercx_cfg462_s cn56xx;
8582 +       struct cvmx_pciercx_cfg462_s cn56xxp1;
8583 +};
8584 +
8585 +union cvmx_pciercx_cfg463 {
8586 +       uint32_t u32;
8587 +       struct cvmx_pciercx_cfg463_s {
8588 +               uint32_t reserved_3_31:29;
8589 +               uint32_t rqne:1;
8590 +               uint32_t trbne:1;
8591 +               uint32_t rtlpfccnr:1;
8592 +       } s;
8593 +       struct cvmx_pciercx_cfg463_s cn52xx;
8594 +       struct cvmx_pciercx_cfg463_s cn52xxp1;
8595 +       struct cvmx_pciercx_cfg463_s cn56xx;
8596 +       struct cvmx_pciercx_cfg463_s cn56xxp1;
8597 +};
8598 +
8599 +union cvmx_pciercx_cfg464 {
8600 +       uint32_t u32;
8601 +       struct cvmx_pciercx_cfg464_s {
8602 +               uint32_t wrr_vc3:8;
8603 +               uint32_t wrr_vc2:8;
8604 +               uint32_t wrr_vc1:8;
8605 +               uint32_t wrr_vc0:8;
8606 +       } s;
8607 +       struct cvmx_pciercx_cfg464_s cn52xx;
8608 +       struct cvmx_pciercx_cfg464_s cn52xxp1;
8609 +       struct cvmx_pciercx_cfg464_s cn56xx;
8610 +       struct cvmx_pciercx_cfg464_s cn56xxp1;
8611 +};
8612 +
8613 +union cvmx_pciercx_cfg465 {
8614 +       uint32_t u32;
8615 +       struct cvmx_pciercx_cfg465_s {
8616 +               uint32_t wrr_vc7:8;
8617 +               uint32_t wrr_vc6:8;
8618 +               uint32_t wrr_vc5:8;
8619 +               uint32_t wrr_vc4:8;
8620 +       } s;
8621 +       struct cvmx_pciercx_cfg465_s cn52xx;
8622 +       struct cvmx_pciercx_cfg465_s cn52xxp1;
8623 +       struct cvmx_pciercx_cfg465_s cn56xx;
8624 +       struct cvmx_pciercx_cfg465_s cn56xxp1;
8625 +};
8626 +
8627 +union cvmx_pciercx_cfg466 {
8628 +       uint32_t u32;
8629 +       struct cvmx_pciercx_cfg466_s {
8630 +               uint32_t rx_queue_order:1;
8631 +               uint32_t type_ordering:1;
8632 +               uint32_t reserved_24_29:6;
8633 +               uint32_t queue_mode:3;
8634 +               uint32_t reserved_20_20:1;
8635 +               uint32_t header_credits:8;
8636 +               uint32_t data_credits:12;
8637 +       } s;
8638 +       struct cvmx_pciercx_cfg466_s cn52xx;
8639 +       struct cvmx_pciercx_cfg466_s cn52xxp1;
8640 +       struct cvmx_pciercx_cfg466_s cn56xx;
8641 +       struct cvmx_pciercx_cfg466_s cn56xxp1;
8642 +};
8643 +
8644 +union cvmx_pciercx_cfg467 {
8645 +       uint32_t u32;
8646 +       struct cvmx_pciercx_cfg467_s {
8647 +               uint32_t reserved_24_31:8;
8648 +               uint32_t queue_mode:3;
8649 +               uint32_t reserved_20_20:1;
8650 +               uint32_t header_credits:8;
8651 +               uint32_t data_credits:12;
8652 +       } s;
8653 +       struct cvmx_pciercx_cfg467_s cn52xx;
8654 +       struct cvmx_pciercx_cfg467_s cn52xxp1;
8655 +       struct cvmx_pciercx_cfg467_s cn56xx;
8656 +       struct cvmx_pciercx_cfg467_s cn56xxp1;
8657 +};
8658 +
8659 +union cvmx_pciercx_cfg468 {
8660 +       uint32_t u32;
8661 +       struct cvmx_pciercx_cfg468_s {
8662 +               uint32_t reserved_24_31:8;
8663 +               uint32_t queue_mode:3;
8664 +               uint32_t reserved_20_20:1;
8665 +               uint32_t header_credits:8;
8666 +               uint32_t data_credits:12;
8667 +       } s;
8668 +       struct cvmx_pciercx_cfg468_s cn52xx;
8669 +       struct cvmx_pciercx_cfg468_s cn52xxp1;
8670 +       struct cvmx_pciercx_cfg468_s cn56xx;
8671 +       struct cvmx_pciercx_cfg468_s cn56xxp1;
8672 +};
8673 +
8674 +union cvmx_pciercx_cfg490 {
8675 +       uint32_t u32;
8676 +       struct cvmx_pciercx_cfg490_s {
8677 +               uint32_t reserved_26_31:6;
8678 +               uint32_t header_depth:10;
8679 +               uint32_t reserved_14_15:2;
8680 +               uint32_t data_depth:14;
8681 +       } s;
8682 +       struct cvmx_pciercx_cfg490_s cn52xx;
8683 +       struct cvmx_pciercx_cfg490_s cn52xxp1;
8684 +       struct cvmx_pciercx_cfg490_s cn56xx;
8685 +       struct cvmx_pciercx_cfg490_s cn56xxp1;
8686 +};
8687 +
8688 +union cvmx_pciercx_cfg491 {
8689 +       uint32_t u32;
8690 +       struct cvmx_pciercx_cfg491_s {
8691 +               uint32_t reserved_26_31:6;
8692 +               uint32_t header_depth:10;
8693 +               uint32_t reserved_14_15:2;
8694 +               uint32_t data_depth:14;
8695 +       } s;
8696 +       struct cvmx_pciercx_cfg491_s cn52xx;
8697 +       struct cvmx_pciercx_cfg491_s cn52xxp1;
8698 +       struct cvmx_pciercx_cfg491_s cn56xx;
8699 +       struct cvmx_pciercx_cfg491_s cn56xxp1;
8700 +};
8701 +
8702 +union cvmx_pciercx_cfg492 {
8703 +       uint32_t u32;
8704 +       struct cvmx_pciercx_cfg492_s {
8705 +               uint32_t reserved_26_31:6;
8706 +               uint32_t header_depth:10;
8707 +               uint32_t reserved_14_15:2;
8708 +               uint32_t data_depth:14;
8709 +       } s;
8710 +       struct cvmx_pciercx_cfg492_s cn52xx;
8711 +       struct cvmx_pciercx_cfg492_s cn52xxp1;
8712 +       struct cvmx_pciercx_cfg492_s cn56xx;
8713 +       struct cvmx_pciercx_cfg492_s cn56xxp1;
8714 +};
8715 +
8716 +union cvmx_pciercx_cfg516 {
8717 +       uint32_t u32;
8718 +       struct cvmx_pciercx_cfg516_s {
8719 +               uint32_t phy_stat:32;
8720 +       } s;
8721 +       struct cvmx_pciercx_cfg516_s cn52xx;
8722 +       struct cvmx_pciercx_cfg516_s cn52xxp1;
8723 +       struct cvmx_pciercx_cfg516_s cn56xx;
8724 +       struct cvmx_pciercx_cfg516_s cn56xxp1;
8725 +};
8726 +
8727 +union cvmx_pciercx_cfg517 {
8728 +       uint32_t u32;
8729 +       struct cvmx_pciercx_cfg517_s {
8730 +               uint32_t phy_ctrl:32;
8731 +       } s;
8732 +       struct cvmx_pciercx_cfg517_s cn52xx;
8733 +       struct cvmx_pciercx_cfg517_s cn52xxp1;
8734 +       struct cvmx_pciercx_cfg517_s cn56xx;
8735 +       struct cvmx_pciercx_cfg517_s cn56xxp1;
8736 +};
8737 +
8738 +#endif
8739 --- /dev/null
8740 +++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
8741 @@ -0,0 +1,410 @@
8742 +/***********************license start***************
8743 + * Author: Cavium Networks
8744 + *
8745 + * Contact: support@caviumnetworks.com
8746 + * This file is part of the OCTEON SDK
8747 + *
8748 + * Copyright (c) 2003-2008 Cavium Networks
8749 + *
8750 + * This file is free software; you can redistribute it and/or modify
8751 + * it under the terms of the GNU General Public License, Version 2, as
8752 + * published by the Free Software Foundation.
8753 + *
8754 + * This file is distributed in the hope that it will be useful, but
8755 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
8756 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
8757 + * NONINFRINGEMENT.  See the GNU General Public License for more
8758 + * details.
8759 + *
8760 + * You should have received a copy of the GNU General Public License
8761 + * along with this file; if not, write to the Free Software
8762 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
8763 + * or visit http://www.gnu.org/licenses/.
8764 + *
8765 + * This file may also be available under a different license from Cavium.
8766 + * Contact Cavium Networks for more information
8767 + ***********************license end**************************************/
8768 +
8769 +#ifndef __CVMX_PESCX_DEFS_H__
8770 +#define __CVMX_PESCX_DEFS_H__
8771 +
8772 +#define CVMX_PESCX_BIST_STATUS(block_id) \
8773 +        CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
8774 +#define CVMX_PESCX_BIST_STATUS2(block_id) \
8775 +        CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
8776 +#define CVMX_PESCX_CFG_RD(block_id) \
8777 +        CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
8778 +#define CVMX_PESCX_CFG_WR(block_id) \
8779 +        CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
8780 +#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
8781 +        CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
8782 +#define CVMX_PESCX_CTL_STATUS(block_id) \
8783 +        CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
8784 +#define CVMX_PESCX_CTL_STATUS2(block_id) \
8785 +        CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
8786 +#define CVMX_PESCX_DBG_INFO(block_id) \
8787 +        CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
8788 +#define CVMX_PESCX_DBG_INFO_EN(block_id) \
8789 +        CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
8790 +#define CVMX_PESCX_DIAG_STATUS(block_id) \
8791 +        CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
8792 +#define CVMX_PESCX_P2N_BAR0_START(block_id) \
8793 +        CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
8794 +#define CVMX_PESCX_P2N_BAR1_START(block_id) \
8795 +        CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
8796 +#define CVMX_PESCX_P2N_BAR2_START(block_id) \
8797 +        CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
8798 +#define CVMX_PESCX_P2P_BARX_END(offset,block_id) \
8799 +        CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
8800 +#define CVMX_PESCX_P2P_BARX_START(offset,block_id) \
8801 +        CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
8802 +#define CVMX_PESCX_TLP_CREDITS(block_id) \
8803 +        CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
8804 +
8805 +union cvmx_pescx_bist_status {
8806 +       uint64_t u64;
8807 +       struct cvmx_pescx_bist_status_s {
8808 +               uint64_t reserved_13_63:51;
8809 +               uint64_t rqdata5:1;
8810 +               uint64_t ctlp_or:1;
8811 +               uint64_t ntlp_or:1;
8812 +               uint64_t ptlp_or:1;
8813 +               uint64_t retry:1;
8814 +               uint64_t rqdata0:1;
8815 +               uint64_t rqdata1:1;
8816 +               uint64_t rqdata2:1;
8817 +               uint64_t rqdata3:1;
8818 +               uint64_t rqdata4:1;
8819 +               uint64_t rqhdr1:1;
8820 +               uint64_t rqhdr0:1;
8821 +               uint64_t sot:1;
8822 +       } s;
8823 +       struct cvmx_pescx_bist_status_s cn52xx;
8824 +       struct cvmx_pescx_bist_status_cn52xxp1 {
8825 +               uint64_t reserved_12_63:52;
8826 +               uint64_t ctlp_or:1;
8827 +               uint64_t ntlp_or:1;
8828 +               uint64_t ptlp_or:1;
8829 +               uint64_t retry:1;
8830 +               uint64_t rqdata0:1;
8831 +               uint64_t rqdata1:1;
8832 +               uint64_t rqdata2:1;
8833 +               uint64_t rqdata3:1;
8834 +               uint64_t rqdata4:1;
8835 +               uint64_t rqhdr1:1;
8836 +               uint64_t rqhdr0:1;
8837 +               uint64_t sot:1;
8838 +       } cn52xxp1;
8839 +       struct cvmx_pescx_bist_status_s cn56xx;
8840 +       struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
8841 +};
8842 +
8843 +union cvmx_pescx_bist_status2 {
8844 +       uint64_t u64;
8845 +       struct cvmx_pescx_bist_status2_s {
8846 +               uint64_t reserved_14_63:50;
8847 +               uint64_t cto_p2e:1;
8848 +               uint64_t e2p_cpl:1;
8849 +               uint64_t e2p_n:1;
8850 +               uint64_t e2p_p:1;
8851 +               uint64_t e2p_rsl:1;
8852 +               uint64_t dbg_p2e:1;
8853 +               uint64_t peai_p2e:1;
8854 +               uint64_t rsl_p2e:1;
8855 +               uint64_t pef_tpf1:1;
8856 +               uint64_t pef_tpf0:1;
8857 +               uint64_t pef_tnf:1;
8858 +               uint64_t pef_tcf1:1;
8859 +               uint64_t pef_tc0:1;
8860 +               uint64_t ppf:1;
8861 +       } s;
8862 +       struct cvmx_pescx_bist_status2_s cn52xx;
8863 +       struct cvmx_pescx_bist_status2_s cn52xxp1;
8864 +       struct cvmx_pescx_bist_status2_s cn56xx;
8865 +       struct cvmx_pescx_bist_status2_s cn56xxp1;
8866 +};
8867 +
8868 +union cvmx_pescx_cfg_rd {
8869 +       uint64_t u64;
8870 +       struct cvmx_pescx_cfg_rd_s {
8871 +               uint64_t data:32;
8872 +               uint64_t addr:32;
8873 +       } s;
8874 +       struct cvmx_pescx_cfg_rd_s cn52xx;
8875 +       struct cvmx_pescx_cfg_rd_s cn52xxp1;
8876 +       struct cvmx_pescx_cfg_rd_s cn56xx;
8877 +       struct cvmx_pescx_cfg_rd_s cn56xxp1;
8878 +};
8879 +
8880 +union cvmx_pescx_cfg_wr {
8881 +       uint64_t u64;
8882 +       struct cvmx_pescx_cfg_wr_s {
8883 +               uint64_t data:32;
8884 +               uint64_t addr:32;
8885 +       } s;
8886 +       struct cvmx_pescx_cfg_wr_s cn52xx;
8887 +       struct cvmx_pescx_cfg_wr_s cn52xxp1;
8888 +       struct cvmx_pescx_cfg_wr_s cn56xx;
8889 +       struct cvmx_pescx_cfg_wr_s cn56xxp1;
8890 +};
8891 +
8892 +union cvmx_pescx_cpl_lut_valid {
8893 +       uint64_t u64;
8894 +       struct cvmx_pescx_cpl_lut_valid_s {
8895 +               uint64_t reserved_32_63:32;
8896 +               uint64_t tag:32;
8897 +       } s;
8898 +       struct cvmx_pescx_cpl_lut_valid_s cn52xx;
8899 +       struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
8900 +       struct cvmx_pescx_cpl_lut_valid_s cn56xx;
8901 +       struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
8902 +};
8903 +
8904 +union cvmx_pescx_ctl_status {
8905 +       uint64_t u64;
8906 +       struct cvmx_pescx_ctl_status_s {
8907 +               uint64_t reserved_28_63:36;
8908 +               uint64_t dnum:5;
8909 +               uint64_t pbus:8;
8910 +               uint64_t qlm_cfg:2;
8911 +               uint64_t lane_swp:1;
8912 +               uint64_t pm_xtoff:1;
8913 +               uint64_t pm_xpme:1;
8914 +               uint64_t ob_p_cmd:1;
8915 +               uint64_t reserved_7_8:2;
8916 +               uint64_t nf_ecrc:1;
8917 +               uint64_t dly_one:1;
8918 +               uint64_t lnk_enb:1;
8919 +               uint64_t ro_ctlp:1;
8920 +               uint64_t reserved_2_2:1;
8921 +               uint64_t inv_ecrc:1;
8922 +               uint64_t inv_lcrc:1;
8923 +       } s;
8924 +       struct cvmx_pescx_ctl_status_s cn52xx;
8925 +       struct cvmx_pescx_ctl_status_s cn52xxp1;
8926 +       struct cvmx_pescx_ctl_status_cn56xx {
8927 +               uint64_t reserved_28_63:36;
8928 +               uint64_t dnum:5;
8929 +               uint64_t pbus:8;
8930 +               uint64_t qlm_cfg:2;
8931 +               uint64_t reserved_12_12:1;
8932 +               uint64_t pm_xtoff:1;
8933 +               uint64_t pm_xpme:1;
8934 +               uint64_t ob_p_cmd:1;
8935 +               uint64_t reserved_7_8:2;
8936 +               uint64_t nf_ecrc:1;
8937 +               uint64_t dly_one:1;
8938 +               uint64_t lnk_enb:1;
8939 +               uint64_t ro_ctlp:1;
8940 +               uint64_t reserved_2_2:1;
8941 +               uint64_t inv_ecrc:1;
8942 +               uint64_t inv_lcrc:1;
8943 +       } cn56xx;
8944 +       struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
8945 +};
8946 +
8947 +union cvmx_pescx_ctl_status2 {
8948 +       uint64_t u64;
8949 +       struct cvmx_pescx_ctl_status2_s {
8950 +               uint64_t reserved_2_63:62;
8951 +               uint64_t pclk_run:1;
8952 +               uint64_t pcierst:1;
8953 +       } s;
8954 +       struct cvmx_pescx_ctl_status2_s cn52xx;
8955 +       struct cvmx_pescx_ctl_status2_cn52xxp1 {
8956 +               uint64_t reserved_1_63:63;
8957 +               uint64_t pcierst:1;
8958 +       } cn52xxp1;
8959 +       struct cvmx_pescx_ctl_status2_s cn56xx;
8960 +       struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
8961 +};
8962 +
8963 +union cvmx_pescx_dbg_info {
8964 +       uint64_t u64;
8965 +       struct cvmx_pescx_dbg_info_s {
8966 +               uint64_t reserved_31_63:33;
8967 +               uint64_t ecrc_e:1;
8968 +               uint64_t rawwpp:1;
8969 +               uint64_t racpp:1;
8970 +               uint64_t ramtlp:1;
8971 +               uint64_t rarwdns:1;
8972 +               uint64_t caar:1;
8973 +               uint64_t racca:1;
8974 +               uint64_t racur:1;
8975 +               uint64_t rauc:1;
8976 +               uint64_t rqo:1;
8977 +               uint64_t fcuv:1;
8978 +               uint64_t rpe:1;
8979 +               uint64_t fcpvwt:1;
8980 +               uint64_t dpeoosd:1;
8981 +               uint64_t rtwdle:1;
8982 +               uint64_t rdwdle:1;
8983 +               uint64_t mre:1;
8984 +               uint64_t rte:1;
8985 +               uint64_t acto:1;
8986 +               uint64_t rvdm:1;
8987 +               uint64_t rumep:1;
8988 +               uint64_t rptamrc:1;
8989 +               uint64_t rpmerc:1;
8990 +               uint64_t rfemrc:1;
8991 +               uint64_t rnfemrc:1;
8992 +               uint64_t rcemrc:1;
8993 +               uint64_t rpoison:1;
8994 +               uint64_t recrce:1;
8995 +               uint64_t rtlplle:1;
8996 +               uint64_t rtlpmal:1;
8997 +               uint64_t spoison:1;
8998 +       } s;
8999 +       struct cvmx_pescx_dbg_info_s cn52xx;
9000 +       struct cvmx_pescx_dbg_info_s cn52xxp1;
9001 +       struct cvmx_pescx_dbg_info_s cn56xx;
9002 +       struct cvmx_pescx_dbg_info_s cn56xxp1;
9003 +};
9004 +
9005 +union cvmx_pescx_dbg_info_en {
9006 +       uint64_t u64;
9007 +       struct cvmx_pescx_dbg_info_en_s {
9008 +               uint64_t reserved_31_63:33;
9009 +               uint64_t ecrc_e:1;
9010 +               uint64_t rawwpp:1;
9011 +               uint64_t racpp:1;
9012 +               uint64_t ramtlp:1;
9013 +               uint64_t rarwdns:1;
9014 +               uint64_t caar:1;
9015 +               uint64_t racca:1;
9016 +               uint64_t racur:1;
9017 +               uint64_t rauc:1;
9018 +               uint64_t rqo:1;
9019 +               uint64_t fcuv:1;
9020 +               uint64_t rpe:1;
9021 +               uint64_t fcpvwt:1;
9022 +               uint64_t dpeoosd:1;
9023 +               uint64_t rtwdle:1;
9024 +               uint64_t rdwdle:1;
9025 +               uint64_t mre:1;
9026 +               uint64_t rte:1;
9027 +               uint64_t acto:1;
9028 +               uint64_t rvdm:1;
9029 +               uint64_t rumep:1;
9030 +               uint64_t rptamrc:1;
9031 +               uint64_t rpmerc:1;
9032 +               uint64_t rfemrc:1;
9033 +               uint64_t rnfemrc:1;
9034 +               uint64_t rcemrc:1;
9035 +               uint64_t rpoison:1;
9036 +               uint64_t recrce:1;
9037 +               uint64_t rtlplle:1;
9038 +               uint64_t rtlpmal:1;
9039 +               uint64_t spoison:1;
9040 +       } s;
9041 +       struct cvmx_pescx_dbg_info_en_s cn52xx;
9042 +       struct cvmx_pescx_dbg_info_en_s cn52xxp1;
9043 +       struct cvmx_pescx_dbg_info_en_s cn56xx;
9044 +       struct cvmx_pescx_dbg_info_en_s cn56xxp1;
9045 +};
9046 +
9047 +union cvmx_pescx_diag_status {
9048 +       uint64_t u64;
9049 +       struct cvmx_pescx_diag_status_s {
9050 +               uint64_t reserved_4_63:60;
9051 +               uint64_t pm_dst:1;
9052 +               uint64_t pm_stat:1;
9053 +               uint64_t pm_en:1;
9054 +               uint64_t aux_en:1;
9055 +       } s;
9056 +       struct cvmx_pescx_diag_status_s cn52xx;
9057 +       struct cvmx_pescx_diag_status_s cn52xxp1;
9058 +       struct cvmx_pescx_diag_status_s cn56xx;
9059 +       struct cvmx_pescx_diag_status_s cn56xxp1;
9060 +};
9061 +
9062 +union cvmx_pescx_p2n_bar0_start {
9063 +       uint64_t u64;
9064 +       struct cvmx_pescx_p2n_bar0_start_s {
9065 +               uint64_t addr:50;
9066 +               uint64_t reserved_0_13:14;
9067 +       } s;
9068 +       struct cvmx_pescx_p2n_bar0_start_s cn52xx;
9069 +       struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
9070 +       struct cvmx_pescx_p2n_bar0_start_s cn56xx;
9071 +       struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
9072 +};
9073 +
9074 +union cvmx_pescx_p2n_bar1_start {
9075 +       uint64_t u64;
9076 +       struct cvmx_pescx_p2n_bar1_start_s {
9077 +               uint64_t addr:38;
9078 +               uint64_t reserved_0_25:26;
9079 +       } s;
9080 +       struct cvmx_pescx_p2n_bar1_start_s cn52xx;
9081 +       struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
9082 +       struct cvmx_pescx_p2n_bar1_start_s cn56xx;
9083 +       struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
9084 +};
9085 +
9086 +union cvmx_pescx_p2n_bar2_start {
9087 +       uint64_t u64;
9088 +       struct cvmx_pescx_p2n_bar2_start_s {
9089 +               uint64_t addr:25;
9090 +               uint64_t reserved_0_38:39;
9091 +       } s;
9092 +       struct cvmx_pescx_p2n_bar2_start_s cn52xx;
9093 +       struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
9094 +       struct cvmx_pescx_p2n_bar2_start_s cn56xx;
9095 +       struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
9096 +};
9097 +
9098 +union cvmx_pescx_p2p_barx_end {
9099 +       uint64_t u64;
9100 +       struct cvmx_pescx_p2p_barx_end_s {
9101 +               uint64_t addr:52;
9102 +               uint64_t reserved_0_11:12;
9103 +       } s;
9104 +       struct cvmx_pescx_p2p_barx_end_s cn52xx;
9105 +       struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
9106 +       struct cvmx_pescx_p2p_barx_end_s cn56xx;
9107 +       struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
9108 +};
9109 +
9110 +union cvmx_pescx_p2p_barx_start {
9111 +       uint64_t u64;
9112 +       struct cvmx_pescx_p2p_barx_start_s {
9113 +               uint64_t addr:52;
9114 +               uint64_t reserved_0_11:12;
9115 +       } s;
9116 +       struct cvmx_pescx_p2p_barx_start_s cn52xx;
9117 +       struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
9118 +       struct cvmx_pescx_p2p_barx_start_s cn56xx;
9119 +       struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
9120 +};
9121 +
9122 +union cvmx_pescx_tlp_credits {
9123 +       uint64_t u64;
9124 +       struct cvmx_pescx_tlp_credits_s {
9125 +               uint64_t reserved_0_63:64;
9126 +       } s;
9127 +       struct cvmx_pescx_tlp_credits_cn52xx {
9128 +               uint64_t reserved_56_63:8;
9129 +               uint64_t peai_ppf:8;
9130 +               uint64_t pesc_cpl:8;
9131 +               uint64_t pesc_np:8;
9132 +               uint64_t pesc_p:8;
9133 +               uint64_t npei_cpl:8;
9134 +               uint64_t npei_np:8;
9135 +               uint64_t npei_p:8;
9136 +       } cn52xx;
9137 +       struct cvmx_pescx_tlp_credits_cn52xxp1 {
9138 +               uint64_t reserved_38_63:26;
9139 +               uint64_t peai_ppf:8;
9140 +               uint64_t pesc_cpl:5;
9141 +               uint64_t pesc_np:5;
9142 +               uint64_t pesc_p:5;
9143 +               uint64_t npei_cpl:5;
9144 +               uint64_t npei_np:5;
9145 +               uint64_t npei_p:5;
9146 +       } cn52xxp1;
9147 +       struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
9148 +       struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
9149 +};
9150 +
9151 +#endif
9152 --- /dev/null
9153 +++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
9154 @@ -0,0 +1,229 @@
9155 +/***********************license start***************
9156 + * Author: Cavium Networks
9157 + *
9158 + * Contact: support@caviumnetworks.com
9159 + * This file is part of the OCTEON SDK
9160 + *
9161 + * Copyright (c) 2003-2008 Cavium Networks
9162 + *
9163 + * This file is free software; you can redistribute it and/or modify
9164 + * it under the terms of the GNU General Public License, Version 2, as
9165 + * published by the Free Software Foundation.
9166 + *
9167 + * This file is distributed in the hope that it will be useful, but
9168 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
9169 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
9170 + * NONINFRINGEMENT.  See the GNU General Public License for more
9171 + * details.
9172 + *
9173 + * You should have received a copy of the GNU General Public License
9174 + * along with this file; if not, write to the Free Software
9175 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
9176 + * or visit http://www.gnu.org/licenses/.
9177 + *
9178 + * This file may also be available under a different license from Cavium.
9179 + * Contact Cavium Networks for more information
9180 + ***********************license end**************************************/
9181 +
9182 +/**
9183 + * cvmx-pexp-defs.h
9184 + *
9185 + * Configuration and status register (CSR) definitions for
9186 + * OCTEON PEXP.
9187 + *
9188 + */
9189 +#ifndef __CVMX_PEXP_DEFS_H__
9190 +#define __CVMX_PEXP_DEFS_H__
9191 +
9192 +#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
9193 +        CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
9194 +#define CVMX_PEXP_NPEI_BIST_STATUS \
9195 +        CVMX_ADD_IO_SEG(0x00011F0000008580ull)
9196 +#define CVMX_PEXP_NPEI_BIST_STATUS2 \
9197 +        CVMX_ADD_IO_SEG(0x00011F0000008680ull)
9198 +#define CVMX_PEXP_NPEI_CTL_PORT0 \
9199 +        CVMX_ADD_IO_SEG(0x00011F0000008250ull)
9200 +#define CVMX_PEXP_NPEI_CTL_PORT1 \
9201 +        CVMX_ADD_IO_SEG(0x00011F0000008260ull)
9202 +#define CVMX_PEXP_NPEI_CTL_STATUS \
9203 +        CVMX_ADD_IO_SEG(0x00011F0000008570ull)
9204 +#define CVMX_PEXP_NPEI_CTL_STATUS2 \
9205 +        CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
9206 +#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
9207 +        CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
9208 +#define CVMX_PEXP_NPEI_DBG_DATA \
9209 +        CVMX_ADD_IO_SEG(0x00011F0000008510ull)
9210 +#define CVMX_PEXP_NPEI_DBG_SELECT \
9211 +        CVMX_ADD_IO_SEG(0x00011F0000008500ull)
9212 +#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
9213 +        CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
9214 +#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
9215 +        CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
9216 +#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
9217 +        CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
9218 +#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
9219 +        CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
9220 +#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
9221 +        CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
9222 +#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
9223 +        CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
9224 +#define CVMX_PEXP_NPEI_DMA_CNTS \
9225 +        CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
9226 +#define CVMX_PEXP_NPEI_DMA_CONTROL \
9227 +        CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
9228 +#define CVMX_PEXP_NPEI_INT_A_ENB \
9229 +        CVMX_ADD_IO_SEG(0x00011F0000008560ull)
9230 +#define CVMX_PEXP_NPEI_INT_A_ENB2 \
9231 +        CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
9232 +#define CVMX_PEXP_NPEI_INT_A_SUM \
9233 +        CVMX_ADD_IO_SEG(0x00011F0000008550ull)
9234 +#define CVMX_PEXP_NPEI_INT_ENB \
9235 +        CVMX_ADD_IO_SEG(0x00011F0000008540ull)
9236 +#define CVMX_PEXP_NPEI_INT_ENB2 \
9237 +        CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
9238 +#define CVMX_PEXP_NPEI_INT_INFO \
9239 +        CVMX_ADD_IO_SEG(0x00011F0000008590ull)
9240 +#define CVMX_PEXP_NPEI_INT_SUM \
9241 +        CVMX_ADD_IO_SEG(0x00011F0000008530ull)
9242 +#define CVMX_PEXP_NPEI_INT_SUM2 \
9243 +        CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
9244 +#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
9245 +        CVMX_ADD_IO_SEG(0x00011F0000008600ull)
9246 +#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
9247 +        CVMX_ADD_IO_SEG(0x00011F0000008610ull)
9248 +#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
9249 +        CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
9250 +#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
9251 +        CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
9252 +#define CVMX_PEXP_NPEI_MSI_ENB0 \
9253 +        CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
9254 +#define CVMX_PEXP_NPEI_MSI_ENB1 \
9255 +        CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
9256 +#define CVMX_PEXP_NPEI_MSI_ENB2 \
9257 +        CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
9258 +#define CVMX_PEXP_NPEI_MSI_ENB3 \
9259 +        CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
9260 +#define CVMX_PEXP_NPEI_MSI_RCV0 \
9261 +        CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
9262 +#define CVMX_PEXP_NPEI_MSI_RCV1 \
9263 +        CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
9264 +#define CVMX_PEXP_NPEI_MSI_RCV2 \
9265 +        CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
9266 +#define CVMX_PEXP_NPEI_MSI_RCV3 \
9267 +        CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
9268 +#define CVMX_PEXP_NPEI_MSI_RD_MAP \
9269 +        CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
9270 +#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
9271 +        CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
9272 +#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
9273 +        CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
9274 +#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
9275 +        CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
9276 +#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
9277 +        CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
9278 +#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
9279 +        CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
9280 +#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
9281 +        CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
9282 +#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
9283 +        CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
9284 +#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
9285 +        CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
9286 +#define CVMX_PEXP_NPEI_MSI_WR_MAP \
9287 +        CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
9288 +#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
9289 +        CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
9290 +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
9291 +        CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
9292 +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
9293 +        CVMX_ADD_IO_SEG(0x00011F0000008650ull)
9294 +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
9295 +        CVMX_ADD_IO_SEG(0x00011F0000008660ull)
9296 +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
9297 +        CVMX_ADD_IO_SEG(0x00011F0000008670ull)
9298 +#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
9299 +        CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
9300 +#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
9301 +        CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
9302 +#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
9303 +        CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
9304 +#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
9305 +        CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
9306 +#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
9307 +        CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
9308 +#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
9309 +        CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
9310 +#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
9311 +        CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
9312 +#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
9313 +        CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
9314 +#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
9315 +        CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
9316 +#define CVMX_PEXP_NPEI_PKT_CNT_INT \
9317 +        CVMX_ADD_IO_SEG(0x00011F0000009110ull)
9318 +#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
9319 +        CVMX_ADD_IO_SEG(0x00011F0000009130ull)
9320 +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
9321 +        CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
9322 +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
9323 +        CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
9324 +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
9325 +        CVMX_ADD_IO_SEG(0x00011F0000009090ull)
9326 +#define CVMX_PEXP_NPEI_PKT_DPADDR \
9327 +        CVMX_ADD_IO_SEG(0x00011F0000009080ull)
9328 +#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
9329 +        CVMX_ADD_IO_SEG(0x00011F0000009150ull)
9330 +#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
9331 +        CVMX_ADD_IO_SEG(0x00011F0000009000ull)
9332 +#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
9333 +        CVMX_ADD_IO_SEG(0x00011F0000009190ull)
9334 +#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
9335 +        CVMX_ADD_IO_SEG(0x00011F0000009020ull)
9336 +#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
9337 +        CVMX_ADD_IO_SEG(0x00011F0000009100ull)
9338 +#define CVMX_PEXP_NPEI_PKT_IN_BP \
9339 +        CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
9340 +#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
9341 +        CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
9342 +#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
9343 +        CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
9344 +#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
9345 +        CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
9346 +#define CVMX_PEXP_NPEI_PKT_IPTR \
9347 +        CVMX_ADD_IO_SEG(0x00011F0000009070ull)
9348 +#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
9349 +        CVMX_ADD_IO_SEG(0x00011F0000009160ull)
9350 +#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
9351 +        CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
9352 +#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
9353 +        CVMX_ADD_IO_SEG(0x00011F0000009010ull)
9354 +#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
9355 +        CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
9356 +#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
9357 +        CVMX_ADD_IO_SEG(0x00011F0000008690ull)
9358 +#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
9359 +        CVMX_ADD_IO_SEG(0x00011F0000009050ull)
9360 +#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
9361 +        CVMX_ADD_IO_SEG(0x00011F0000009180ull)
9362 +#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
9363 +        CVMX_ADD_IO_SEG(0x00011F0000009040ull)
9364 +#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
9365 +        CVMX_ADD_IO_SEG(0x00011F0000009030ull)
9366 +#define CVMX_PEXP_NPEI_PKT_TIME_INT \
9367 +        CVMX_ADD_IO_SEG(0x00011F0000009120ull)
9368 +#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
9369 +        CVMX_ADD_IO_SEG(0x00011F0000009140ull)
9370 +#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
9371 +        CVMX_ADD_IO_SEG(0x00011F0000008520ull)
9372 +#define CVMX_PEXP_NPEI_SCRATCH_1 \
9373 +        CVMX_ADD_IO_SEG(0x00011F0000008270ull)
9374 +#define CVMX_PEXP_NPEI_STATE1 \
9375 +        CVMX_ADD_IO_SEG(0x00011F0000008620ull)
9376 +#define CVMX_PEXP_NPEI_STATE2 \
9377 +        CVMX_ADD_IO_SEG(0x00011F0000008630ull)
9378 +#define CVMX_PEXP_NPEI_STATE3 \
9379 +        CVMX_ADD_IO_SEG(0x00011F0000008640ull)
9380 +#define CVMX_PEXP_NPEI_WINDOW_CTL \
9381 +        CVMX_ADD_IO_SEG(0x00011F0000008380ull)
9382 +
9383 +#endif