target/linux/mvebu/patches-3.10/0058-ARM-mvebu-Relocate-Armada-370-XP-DeviceBus-device-tr.patch

   1 From bcb0e54d62804f1f986ad478a11235dadb1b61bb Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Fri, 14 Jun 2013 10:44:57 -0300
   4 Subject: [PATCH 058/203] ARM: mvebu: Relocate Armada 370/XP DeviceBus device
   5  tree nodes
   6
   7 Now that mbus has been added to the device tree, it's possible to
   8 move the DeviceBus out of internal registers, placing it directly
   9 below the mbus. This is a more accurate representation of the hardware.
  10
  11 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  12 Tested-by: Andrew Lunn <andrew@lunn.ch>
  13 Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  14 ---
  15  arch/arm/boot/dts/armada-370-xp.dtsi             | 94 +++++++++++++-----------
  16  arch/arm/boot/dts/armada-xp-db.dts               | 59 +++++++--------
  17  arch/arm/boot/dts/armada-xp-gp.dts               | 60 +++++++--------
  18  arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 60 +++++++--------
  19  4 files changed, 140 insertions(+), 133 deletions(-)
  20
  21 --- a/arch/arm/boot/dts/armada-370-xp.dtsi
  22 +++ b/arch/arm/boot/dts/armada-370-xp.dtsi
  23 @@ -36,6 +36,56 @@
  24                 controller = <&mbusc>;
  25                 interrupt-parent = <&mpic>;
  26
  27 +               devbus-bootcs {
  28 +                       compatible = "marvell,mvebu-devbus";
  29 +                       reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  30 +                       ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  31 +                       #address-cells = <1>;
  32 +                       #size-cells = <1>;
  33 +                       clocks = <&coreclk 0>;
  34 +                       status = "disabled";
  35 +               };
  36 +
  37 +               devbus-cs0 {
  38 +                       compatible = "marvell,mvebu-devbus";
  39 +                       reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
  40 +                       ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
  41 +                       #address-cells = <1>;
  42 +                       #size-cells = <1>;
  43 +                       clocks = <&coreclk 0>;
  44 +                       status = "disabled";
  45 +               };
  46 +
  47 +               devbus-cs1 {
  48 +                       compatible = "marvell,mvebu-devbus";
  49 +                       reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
  50 +                       ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
  51 +                       #address-cells = <1>;
  52 +                       #size-cells = <1>;
  53 +                       clocks = <&coreclk 0>;
  54 +                       status = "disabled";
  55 +               };
  56 +
  57 +               devbus-cs2 {
  58 +                       compatible = "marvell,mvebu-devbus";
  59 +                       reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
  60 +                       ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
  61 +                       #address-cells = <1>;
  62 +                       #size-cells = <1>;
  63 +                       clocks = <&coreclk 0>;
  64 +                       status = "disabled";
  65 +               };
  66 +
  67 +               devbus-cs3 {
  68 +                       compatible = "marvell,mvebu-devbus";
  69 +                       reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
  70 +                       ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
  71 +                       #address-cells = <1>;
  72 +                       #size-cells = <1>;
  73 +                       clocks = <&coreclk 0>;
  74 +                       status = "disabled";
  75 +               };
  76 +
  77                 internal-regs {
  78                         compatible = "simple-bus";
  79                         #address-cells = <1>;
  80 @@ -191,50 +241,6 @@
  81                                 status = "disabled";
  82                         };
  83
  84 -                       devbus-bootcs@10400 {
  85 -                               compatible = "marvell,mvebu-devbus";
  86 -                               reg = <0x10400 0x8>;
  87 -                               #address-cells = <1>;
  88 -                               #size-cells = <1>;
  89 -                               clocks = <&coreclk 0>;
  90 -                               status = "disabled";
  91 -                       };
  92 -
  93 -                       devbus-cs0@10408 {
  94 -                               compatible = "marvell,mvebu-devbus";
  95 -                               reg = <0x10408 0x8>;
  96 -                               #address-cells = <1>;
  97 -                               #size-cells = <1>;
  98 -                               clocks = <&coreclk 0>;
  99 -                               status = "disabled";
 100 -                       };
 101 -
 102 -                       devbus-cs1@10410 {
 103 -                               compatible = "marvell,mvebu-devbus";
 104 -                               reg = <0x10410 0x8>;
 105 -                               #address-cells = <1>;
 106 -                               #size-cells = <1>;
 107 -                               clocks = <&coreclk 0>;
 108 -                               status = "disabled";
 109 -                       };
 110 -
 111 -                       devbus-cs2@10418 {
 112 -                               compatible = "marvell,mvebu-devbus";
 113 -                               reg = <0x10418 0x8>;
 114 -                               #address-cells = <1>;
 115 -                               #size-cells = <1>;
 116 -                               clocks = <&coreclk 0>;
 117 -                               status = "disabled";
 118 -                       };
 119 -
 120 -                       devbus-cs3@10420 {
 121 -                               compatible = "marvell,mvebu-devbus";
 122 -                               reg = <0x10420 0x8>;
 123 -                               #address-cells = <1>;
 124 -                               #size-cells = <1>;
 125 -                               clocks = <&coreclk 0>;
 126 -                               status = "disabled";
 127 -                       };
 128                 };
 129         };
 130   };
 131 --- a/arch/arm/boot/dts/armada-xp-db.dts
 132 +++ b/arch/arm/boot/dts/armada-xp-db.dts
 133 @@ -31,7 +31,36 @@
 134
 135         soc {
 136                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
 137 -                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
 138 +                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
 139 +                         MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
 140 +
 141 +               devbus-bootcs {
 142 +                       status = "okay";
 143 +
 144 +                       /* Device Bus parameters are required */
 145 +
 146 +                       /* Read parameters */
 147 +                       devbus,bus-width    = <8>;
 148 +                       devbus,turn-off-ps  = <60000>;
 149 +                       devbus,badr-skew-ps = <0>;
 150 +                       devbus,acc-first-ps = <124000>;
 151 +                       devbus,acc-next-ps  = <248000>;
 152 +                       devbus,rd-setup-ps  = <0>;
 153 +                       devbus,rd-hold-ps   = <0>;
 154 +
 155 +                       /* Write parameters */
 156 +                       devbus,sync-enable = <0>;
 157 +                       devbus,wr-high-ps  = <60000>;
 158 +                       devbus,wr-low-ps   = <60000>;
 159 +                       devbus,ale-wr-ps   = <60000>;
 160 +
 161 +                       /* NOR 16 MiB */
 162 +                       nor@0 {
 163 +                               compatible = "cfi-flash";
 164 +                               reg = <0 0x1000000>;
 165 +                               bank-width = <2>;
 166 +                       };
 167 +               };
 168
 169                 internal-regs {
 170                         serial@12000 {
 171 @@ -160,34 +189,6 @@
 172                                 };
 173                         };
 174
 175 -                       devbus-bootcs@10400 {
 176 -                               status = "okay";
 177 -                               ranges = <0 0xf0000000 0x1000000>;
 178 -
 179 -                               /* Device Bus parameters are required */
 180 -
 181 -                               /* Read parameters */
 182 -                               devbus,bus-width    = <8>;
 183 -                               devbus,turn-off-ps  = <60000>;
 184 -                               devbus,badr-skew-ps = <0>;
 185 -                               devbus,acc-first-ps = <124000>;
 186 -                               devbus,acc-next-ps  = <248000>;
 187 -                               devbus,rd-setup-ps  = <0>;
 188 -                               devbus,rd-hold-ps   = <0>;
 189 -
 190 -                               /* Write parameters */
 191 -                               devbus,sync-enable = <0>;
 192 -                               devbus,wr-high-ps  = <60000>;
 193 -                               devbus,wr-low-ps   = <60000>;
 194 -                               devbus,ale-wr-ps   = <60000>;
 195 -
 196 -                               /* NOR 16 MiB */
 197 -                               nor@0 {
 198 -                                       compatible = "cfi-flash";
 199 -                                       reg = <0 0x1000000>;
 200 -                                       bank-width = <2>;
 201 -                               };
 202 -                       };
 203                 };
 204         };
 205  };
 206 --- a/arch/arm/boot/dts/armada-xp-gp.dts
 207 +++ b/arch/arm/boot/dts/armada-xp-gp.dts
 208 @@ -40,7 +40,36 @@
 209
 210         soc {
 211                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
 212 -                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
 213 +                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
 214 +                         MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
 215 +
 216 +               devbus-bootcs {
 217 +                       status = "okay";
 218 +
 219 +                       /* Device Bus parameters are required */
 220 +
 221 +                       /* Read parameters */
 222 +                       devbus,bus-width    = <8>;
 223 +                       devbus,turn-off-ps  = <60000>;
 224 +                       devbus,badr-skew-ps = <0>;
 225 +                       devbus,acc-first-ps = <124000>;
 226 +                       devbus,acc-next-ps  = <248000>;
 227 +                       devbus,rd-setup-ps  = <0>;
 228 +                       devbus,rd-hold-ps   = <0>;
 229 +
 230 +                       /* Write parameters */
 231 +                       devbus,sync-enable = <0>;
 232 +                       devbus,wr-high-ps  = <60000>;
 233 +                       devbus,wr-low-ps   = <60000>;
 234 +                       devbus,ale-wr-ps   = <60000>;
 235 +
 236 +                       /* NOR 16 MiB */
 237 +                       nor@0 {
 238 +                               compatible = "cfi-flash";
 239 +                               reg = <0 0x1000000>;
 240 +                               bank-width = <2>;
 241 +                       };
 242 +               };
 243
 244                 internal-regs {
 245                         serial@12000 {
 246 @@ -126,35 +155,6 @@
 247                                 };
 248                         };
 249
 250 -                       devbus-bootcs@10400 {
 251 -                               status = "okay";
 252 -                               ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
 253 -
 254 -                               /* Device Bus parameters are required */
 255 -
 256 -                               /* Read parameters */
 257 -                               devbus,bus-width    = <8>;
 258 -                               devbus,turn-off-ps  = <60000>;
 259 -                               devbus,badr-skew-ps = <0>;
 260 -                               devbus,acc-first-ps = <124000>;
 261 -                               devbus,acc-next-ps  = <248000>;
 262 -                               devbus,rd-setup-ps  = <0>;
 263 -                               devbus,rd-hold-ps   = <0>;
 264 -
 265 -                               /* Write parameters */
 266 -                               devbus,sync-enable = <0>;
 267 -                               devbus,wr-high-ps  = <60000>;
 268 -                               devbus,wr-low-ps   = <60000>;
 269 -                               devbus,ale-wr-ps   = <60000>;
 270 -
 271 -                               /* NOR 16 MiB */
 272 -                               nor@0 {
 273 -                                       compatible = "cfi-flash";
 274 -                                       reg = <0 0x1000000>;
 275 -                                       bank-width = <2>;
 276 -                               };
 277 -                       };
 278 -
 279                         pcie-controller {
 280                                 status = "okay";
 281
 282 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
 283 +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
 284 @@ -28,7 +28,36 @@
 285
 286         soc {
 287                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
 288 -                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
 289 +                         MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
 290 +                         MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
 291 +
 292 +               devbus-bootcs {
 293 +                       status = "okay";
 294 +
 295 +                       /* Device Bus parameters are required */
 296 +
 297 +                       /* Read parameters */
 298 +                       devbus,bus-width    = <8>;
 299 +                       devbus,turn-off-ps  = <60000>;
 300 +                       devbus,badr-skew-ps = <0>;
 301 +                       devbus,acc-first-ps = <124000>;
 302 +                       devbus,acc-next-ps  = <248000>;
 303 +                       devbus,rd-setup-ps  = <0>;
 304 +                       devbus,rd-hold-ps   = <0>;
 305 +
 306 +                       /* Write parameters */
 307 +                       devbus,sync-enable = <0>;
 308 +                       devbus,wr-high-ps  = <60000>;
 309 +                       devbus,wr-low-ps   = <60000>;
 310 +                       devbus,ale-wr-ps   = <60000>;
 311 +
 312 +                       /* NOR 128 MiB */
 313 +                       nor@0 {
 314 +                               compatible = "cfi-flash";
 315 +                               reg = <0 0x8000000>;
 316 +                               bank-width = <2>;
 317 +                       };
 318 +               };
 319
 320                 internal-regs {
 321                         serial@12000 {
 322 @@ -144,35 +173,6 @@
 323                                 status = "okay";
 324                         };
 325
 326 -                       devbus-bootcs@10400 {
 327 -                               status = "okay";
 328 -                               ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
 329 -
 330 -                               /* Device Bus parameters are required */
 331 -
 332 -                               /* Read parameters */
 333 -                               devbus,bus-width    = <8>;
 334 -                               devbus,turn-off-ps  = <60000>;
 335 -                               devbus,badr-skew-ps = <0>;
 336 -                               devbus,acc-first-ps = <124000>;
 337 -                               devbus,acc-next-ps  = <248000>;
 338 -                               devbus,rd-setup-ps  = <0>;
 339 -                               devbus,rd-hold-ps   = <0>;
 340 -
 341 -                               /* Write parameters */
 342 -                               devbus,sync-enable = <0>;
 343 -                               devbus,wr-high-ps  = <60000>;
 344 -                               devbus,wr-low-ps   = <60000>;
 345 -                               devbus,ale-wr-ps   = <60000>;
 346 -
 347 -                               /* NOR 128 MiB */
 348 -                               nor@0 {
 349 -                                       compatible = "cfi-flash";
 350 -                                       reg = <0 0x8000000>;
 351 -                                       bank-width = <2>;
 352 -                               };
 353 -                       };
 354 -
 355                         pcie-controller {
 356                                 status = "okay";
 357                                 /* Internal mini-PCIe connector */