target/linux/mpc85xx/patches-3.8/140-powerpc-85xx-tl-wdr4900-v1-support.patch

   1 From 406d86e5990ac171f18ef6e2973672d8fbfe1556 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Wed, 20 Feb 2013 08:40:33 +0100
   4 Subject: [PATCH] powerpc: 85xx: add support for the TP-Link TL-WDR4900 v1
   5  board
   6
   7 This patch adds support for the TP-Link TL-WDR4900 v1
   8 concurrent dual-band wireless router. The devices uses
   9 the Freescale P1014 SoC.
  10
  11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  12 ---
  13  arch/powerpc/boot/Makefile                  |    3 +
  14  arch/powerpc/boot/cuboot-tl-wdr4900-v1.c    |  164 ++++++++++++++++++++++++++
  15  arch/powerpc/boot/dts/tl-wdr4900-v1.dts     |  166 +++++++++++++++++++++++++++
  16  arch/powerpc/boot/wrapper                   |    4 +
  17  arch/powerpc/platforms/85xx/Kconfig         |   11 ++
  18  arch/powerpc/platforms/85xx/Makefile        |    1 +
  19  arch/powerpc/platforms/85xx/tl_wdr4900_v1.c |  145 +++++++++++++++++++++++
  20  7 files changed, 494 insertions(+)
  21  create mode 100644 arch/powerpc/boot/cuboot-tl-wdr4900-v1.c
  22  create mode 100644 arch/powerpc/boot/dts/tl-wdr4900-v1.dts
  23  create mode 100644 arch/powerpc/platforms/85xx/tl_wdr4900_v1.c
  24
  25 --- a/arch/powerpc/boot/Makefile
  26 +++ b/arch/powerpc/boot/Makefile
  27 @@ -98,6 +98,8 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot
  28  src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
  29  src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
  30  src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c
  31 +src-plat-$(CONFIG_TL_WDR4900_V1) += cuboot-tl-wdr4900-v1.c
  32 +
  33
  34  src-wlib := $(sort $(src-wlib-y))
  35  src-plat := $(sort $(src-plat-y))
  36 @@ -278,6 +280,7 @@ image-$(CONFIG_TQM8555)                     += cuImage.tqm
  37  image-$(CONFIG_TQM8560)                        += cuImage.tqm8560
  38  image-$(CONFIG_SBC8548)                        += cuImage.sbc8548
  39  image-$(CONFIG_KSI8560)                        += cuImage.ksi8560
  40 +image-$(CONFIG_TL_WDR4900_V1)          += cuImage.tl-wdr4900-v1
  41
  42  # Board ports in arch/powerpc/platform/embedded6xx/Kconfig
  43  image-$(CONFIG_STORCENTER)             += cuImage.storcenter
  44 --- /dev/null
  45 +++ b/arch/powerpc/boot/cuboot-tl-wdr4900-v1.c
  46 @@ -0,0 +1,164 @@
  47 +/*
  48 + * U-Boot compatibility wrapper for the TP-Link TL-WDR4900 v1 board
  49 + *
  50 + * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
  51 + *
  52 + * Based on:
  53 + *  cuboot-85xx.c
  54 + *     Author: Scott Wood <scottwood@freescale.com>
  55 + *     Copyright (c) 2007 Freescale Semiconductor, Inc.
  56 + *
  57 + *  simpleboot.c
  58 + *     Authors: Scott Wood <scottwood@freescale.com>
  59 + *              Grant Likely <grant.likely@secretlab.ca>
  60 + *     Copyright (c) 2007 Freescale Semiconductor, Inc.
  61 + *     Copyright (c) 2008 Secret Lab Technologies Ltd.
  62 + *
  63 + * This program is free software; you can redistribute it and/or modify it
  64 + * under the terms of the GNU General Public License version 2 as published
  65 + * by the Free Software Foundation.
  66 + */
  67 +
  68 +#include "ops.h"
  69 +#include "types.h"
  70 +#include "io.h"
  71 +#include "stdio.h"
  72 +#include <libfdt.h>
  73 +
  74 +BSS_STACK(4*1024);
  75 +
  76 +static unsigned long bus_freq;
  77 +static unsigned long int_freq;
  78 +static u64 mem_size;
  79 +static unsigned char enetaddr[6];
  80 +
  81 +static void process_boot_dtb(void *boot_dtb)
  82 +{
  83 +       const u32 *na, *ns, *reg, *val32;
  84 +       const char *path;
  85 +       u64 memsize64;
  86 +       int node, size, i;
  87 +
  88 +       /* Make sure FDT blob is sane */
  89 +       if (fdt_check_header(boot_dtb) != 0)
  90 +               fatal("Invalid device tree blob\n");
  91 +
  92 +       /* Find the #address-cells and #size-cells properties */
  93 +       node = fdt_path_offset(boot_dtb, "/");
  94 +       if (node < 0)
  95 +               fatal("Cannot find root node\n");
  96 +       na = fdt_getprop(boot_dtb, node, "#address-cells", &size);
  97 +       if (!na || (size != 4))
  98 +               fatal("Cannot find #address-cells property");
  99 +
 100 +       ns = fdt_getprop(boot_dtb, node, "#size-cells", &size);
 101 +       if (!ns || (size != 4))
 102 +               fatal("Cannot find #size-cells property");
 103 +
 104 +       /* Find the memory range */
 105 +       node = fdt_node_offset_by_prop_value(boot_dtb, -1, "device_type",
 106 +                                            "memory", sizeof("memory"));
 107 +       if (node < 0)
 108 +               fatal("Cannot find memory node\n");
 109 +       reg = fdt_getprop(boot_dtb, node, "reg", &size);
 110 +       if (size < (*na+*ns) * sizeof(u32))
 111 +               fatal("cannot get memory range\n");
 112 +
 113 +       /* Only interested in memory based at 0 */
 114 +       for (i = 0; i < *na; i++)
 115 +               if (*reg++ != 0)
 116 +                       fatal("Memory range is not based at address 0\n");
 117 +
 118 +       /* get the memsize and trucate it to under 4G on 32 bit machines */
 119 +       memsize64 = 0;
 120 +       for (i = 0; i < *ns; i++)
 121 +               memsize64 = (memsize64 << 32) | *reg++;
 122 +       if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL)
 123 +               memsize64 = 0xffffffff;
 124 +
 125 +       mem_size = memsize64;
 126 +
 127 +       /* get clock frequencies */
 128 +       node = fdt_node_offset_by_prop_value(boot_dtb, -1, "device_type",
 129 +                                            "cpu", sizeof("cpu"));
 130 +       if (!node)
 131 +               fatal("Cannot find cpu node\n");
 132 +
 133 +       val32 = fdt_getprop(boot_dtb, node, "clock-frequency", &size);
 134 +       if (!val32 || (size != 4))
 135 +               fatal("Cannot get clock frequency");
 136 +
 137 +       int_freq = *val32;
 138 +
 139 +       val32 = fdt_getprop(boot_dtb, node, "bus-frequency", &size);
 140 +       if (!val32 || (size != 4))
 141 +               fatal("Cannot get bus frequency");
 142 +
 143 +       bus_freq = *val32;
 144 +
 145 +       path = fdt_get_alias(boot_dtb, "ethernet0");
 146 +       if (path) {
 147 +               const void *p;
 148 +
 149 +               node = fdt_path_offset(boot_dtb, path);
 150 +               if (node < 0)
 151 +                       fatal("Cannot find ethernet0 node");
 152 +
 153 +               p = fdt_getprop(boot_dtb, node, "mac-address", &size);
 154 +               if (!p || (size < 6)) {
 155 +                       printf("no mac-address property, finding local\n\r");
 156 +                       p = fdt_getprop(boot_dtb, node, "local-mac-address", &size);
 157 +               }
 158 +
 159 +               if (!p || (size < 6))
 160 +                       fatal("cannot get MAC addres");
 161 +
 162 +               memcpy(enetaddr, p, sizeof(enetaddr));
 163 +       }
 164 +}
 165 +
 166 +static void platform_fixups(void)
 167 +{
 168 +       void *soc;
 169 +
 170 +       dt_fixup_memory(0, mem_size);
 171 +
 172 +       dt_fixup_mac_address_by_alias("ethernet0", enetaddr);
 173 +       dt_fixup_cpu_clocks(int_freq, bus_freq / 8, bus_freq);
 174 +
 175 +       /* Unfortunately, the specific model number is encoded in the
 176 +        * soc node name in existing dts files -- once that is fixed,
 177 +        * this can do a simple path lookup.
 178 +        */
 179 +       soc = find_node_by_devtype(NULL, "soc");
 180 +       if (soc) {
 181 +               void *serial = NULL;
 182 +
 183 +               setprop(soc, "bus-frequency", &bus_freq, sizeof(bus_freq));
 184 +
 185 +               while ((serial = find_node_by_devtype(serial, "serial"))) {
 186 +                       if (get_parent(serial) != soc)
 187 +                               continue;
 188 +
 189 +                       setprop(serial, "clock-frequency", &bus_freq,
 190 +                               sizeof(bus_freq));
 191 +               }
 192 +       }
 193 +}
 194 +
 195 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 196 +                   unsigned long r6, unsigned long r7)
 197 +{
 198 +       mem_size = 64 * 1024 * 1024;
 199 +
 200 +       simple_alloc_init(_end, mem_size - (u32)_end - 1024*1024, 32, 64);
 201 +
 202 +       fdt_init(_dtb_start);
 203 +       serial_console_init();
 204 +
 205 +       printf("\n\r-- TL-WDR4900 v1 boot wrapper --\n\r");
 206 +
 207 +       process_boot_dtb((void *) r3);
 208 +
 209 +       platform_ops.fixups = platform_fixups;
 210 +}
 211 --- /dev/null
 212 +++ b/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
 213 @@ -0,0 +1,208 @@
 214 +/*
 215 + * TP-Link TL-WDR4900 v1 Device Tree Source
 216 + *
 217 + * Copyright 2013 Gabor Juhos <juhosg@openwrt.org>
 218 + *
 219 + * This program is free software; you can redistribute  it and/or modify it
 220 + * under  the terms of  the GNU General  Public License as published by the
 221 + * Free Software Foundation;  either version 2 of the  License, or (at your
 222 + * option) any later version.
 223 + */
 224 +
 225 +/include/ "fsl/p1010si-pre.dtsi"
 226 +
 227 +/ {
 228 +       model = "TP-Link TL-WDR4900 v1";
 229 +       compatible = "tp-link,TL-WDR4900v1";
 230 +
 231 +       chosen {
 232 +               bootargs = "console=ttyS0,115200";
 233 +/*
 234 +               linux,stdout-path = "/soc@ffe00000/serial@4500";
 235 +*/
 236 +       };
 237 +
 238 +       memory {
 239 +               device_type = "memory";
 240 +       };
 241 +
 242 +       soc: soc@ffe00000 {
 243 +               ranges = <0x0 0x0 0xffe00000 0x100000>;
 244 +
 245 +               spi0: spi@7000 {
 246 +                       flash@0 {
 247 +                               #address-cells = <1>;
 248 +                               #size-cells = <1>;
 249 +                               compatible = "spansion,s25fl129p1";
 250 +                               reg = <0>;
 251 +                               spi-max-frequency = <25000000>;
 252 +
 253 +                               u-boot@0 {
 254 +                                       reg = <0x0 0x0050000>;
 255 +                                       label = "u-boot";
 256 +                                       read-only;
 257 +                               };
 258 +
 259 +                               dtb@50000 {
 260 +                                       reg = <0x00050000 0x00010000>;
 261 +                                       label = "dtb";
 262 +                                       read-only;
 263 +                               };
 264 +
 265 +                               kernel@60000 {
 266 +                                       reg = <0x00060000 0x002a0000>;
 267 +                                       label = "kernel";
 268 +                               };
 269 +
 270 +                               rootfs@300000 {
 271 +                                       reg = <0x00300000 0x00ce0000>;
 272 +                                       label = "rootfs";
 273 +                               };
 274 +
 275 +                               config@fe0000 {
 276 +                                       reg = <0x00fe0000 0x00010000>;
 277 +                                       label = "config";
 278 +                                       read-only;
 279 +                               };
 280 +
 281 +                               caldata@ff0000 {
 282 +                                       reg = <0x00ff0000 0x00010000>;
 283 +                                       label = "caldata";
 284 +                                       read-only;
 285 +                               };
 286 +
 287 +                               firmware@60000 {
 288 +                                       reg = <0x00060000 0x00f80000>;
 289 +                                       label = "firmware";
 290 +                               };
 291 +                       };
 292 +               };
 293 +
 294 +               gpio0: gpio-controller@f000 {
 295 +               };
 296 +
 297 +               usb@22000 {
 298 +                       phy_type = "utmi";
 299 +                       dr_mode = "host";
 300 +               };
 301 +
 302 +               mdio@24000 {
 303 +                       phy0: ethernet-phy@0 {
 304 +                               reg = <0x0>;
 305 +                               qca,ar8327-initvals = <
 306 +                                       0x00004 0x07600000 /* PAD0_MODE */
 307 +                                       0x00008 0x00000000 /* PAD5_MODE */
 308 +                                       0x0000c 0x01000000 /* PAD6_MODE */
 309 +                                       0x00010 0x40000000 /* POWER_ON_STRIP */
 310 +                                       0x00050 0xcf35cf35 /* LED_CTRL0 */
 311 +                                       0x00054 0xcf35cf35 /* LED_CTRL1 */
 312 +                                       0x00058 0xcf35cf35 /* LED_CTRL2 */
 313 +                                       0x0005c 0x03ffff00 /* LED_CTRL3 */
 314 +                                       0x0007c 0x0000007e /* PORT0_STATUS */
 315 +                               >;
 316 +                       };
 317 +               };
 318 +
 319 +               mdio@25000 {
 320 +                       status = "disabled";
 321 +               };
 322 +
 323 +               mdio@26000 {
 324 +                       status = "disabled";
 325 +               };
 326 +
 327 +               enet0: ethernet@b0000 {
 328 +                       phy-handle = <&phy0>;
 329 +                       phy-connection-type = "rgmii-id";
 330 +               };
 331 +
 332 +               enet1: ethernet@b1000 {
 333 +                       status = "disabled";
 334 +               };
 335 +
 336 +               enet2: ethernet@b2000 {
 337 +                       status = "disabled";
 338 +               };
 339 +
 340 +               sdhc@2e000 {
 341 +                       status = "disabled";
 342 +               };
 343 +
 344 +               serial1: serial@4600 {
 345 +                       status = "disabled";
 346 +               };
 347 +
 348 +               can0: can@1c000 {
 349 +                       status = "disabled";
 350 +               };
 351 +
 352 +               can1: can@1d000 {
 353 +                       status = "disabled";
 354 +               };
 355 +       };
 356 +
 357 +       pci0: pcie@ffe09000 {
 358 +               reg = <0 0xffe09000 0 0x1000>;
 359 +               ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 360 +                         0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
 361 +               pcie@0 {
 362 +                       ranges = <0x2000000 0x0 0xa0000000
 363 +                                 0x2000000 0x0 0xa0000000
 364 +                                 0x0 0x20000000
 365 +
 366 +                                 0x1000000 0x0 0x0
 367 +                                 0x1000000 0x0 0x0
 368 +                                 0x0 0x100000>;
 369 +               };
 370 +       };
 371 +
 372 +       pci1: pcie@ffe0a000 {
 373 +               reg = <0 0xffe0a000 0 0x1000>;
 374 +               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 375 +                         0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
 376 +               pcie@0 {
 377 +                       ranges = <0x2000000 0x0 0x80000000
 378 +                                 0x2000000 0x0 0x80000000
 379 +                                 0x0 0x20000000
 380 +
 381 +                                 0x1000000 0x0 0x0
 382 +                                 0x1000000 0x0 0x0
 383 +                                 0x0 0x100000>;
 384 +               };
 385 +       };
 386 +
 387 +       ifc: ifc@ffe1e000 {
 388 +               status = "disabled";
 389 +       };
 390 +
 391 +       leds {
 392 +               compatible = "gpio-leds";
 393 +
 394 +               system {
 395 +                       gpios = <&gpio0 2 1>; /* active low */
 396 +                       label = "tp-link:blue:system";
 397 +               };
 398 +
 399 +               usb1 {
 400 +                       gpios = <&gpio0 3 1>; /* active low */
 401 +                       label = "tp-link:green:usb1";
 402 +               };
 403 +
 404 +               usb2 {
 405 +                       gpios = <&gpio0 4 1>; /* active low */
 406 +                       label = "tp-link:green:usb2";
 407 +               };
 408 +       };
 409 +
 410 +       buttons {
 411 +               compatible = "gpio-keys";
 412 +
 413 +               reset {
 414 +                       label = "Reset button";
 415 +                       gpios = <&gpio0 5 1>; /* active low */
 416 +                       linux,code = <0x198>; /* KEY_RESTART */
 417 +               };
 418 +       };
 419 +};
 420 +
 421 +/include/ "fsl/p1010si-post.dtsi"
 422 --- a/arch/powerpc/boot/wrapper
 423 +++ b/arch/powerpc/boot/wrapper
 424 @@ -197,6 +197,10 @@ cuboot*)
 425      *-mpc85*|*-tqm85*|*-sbc85*)
 426          platformo=$object/cuboot-85xx.o
 427          ;;
 428 +    *-tl-wdr4900-v1)
 429 +        platformo=$object/cuboot-tl-wdr4900-v1.o
 430 +       link_address='0x1000000'
 431 +        ;;
 432      *-amigaone)
 433          link_address='0x800000'
 434          ;;
 435 --- a/arch/powerpc/platforms/85xx/Kconfig
 436 +++ b/arch/powerpc/platforms/85xx/Kconfig
 437 @@ -147,6 +147,17 @@ config STX_GP3
 438         select CPM2
 439         select DEFAULT_UIMAGE
 440
 441 +config TL_WDR4900_V1
 442 +       bool "TP-Link TL-WDR4900 v1"
 443 +       select DEFAULT_UIMAGE
 444 +       select ARCH_REQUIRE_GPIOLIB
 445 +       select GPIO_MPC8XXX
 446 +       help
 447 +         This option enables support for the TP-Link TL-WDR4900 v1 board.
 448 +
 449 +         This board is a Concurrent Dual-Band wireless router with a
 450 +         Freescale P1014 SoC.
 451 +
 452  config TQM8540
 453         bool "TQ Components TQM8540"
 454         help
 455 --- a/arch/powerpc/platforms/85xx/Makefile
 456 +++ b/arch/powerpc/platforms/85xx/Makefile
 457 @@ -24,6 +24,7 @@ obj-$(CONFIG_P5020_DS)    += p5020_ds.o
 458  obj-$(CONFIG_P5040_DS)    += p5040_ds.o corenet_ds.o
 459  obj-$(CONFIG_STX_GP3)    += stx_gp3.o
 460  obj-$(CONFIG_TQM85xx)    += tqm85xx.o
 461 +obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o
 462  obj-$(CONFIG_SBC8548)     += sbc8548.o
 463  obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o
 464  obj-$(CONFIG_KSI8560)    += ksi8560.o
 465 --- /dev/null
 466 +++ b/arch/powerpc/platforms/85xx/tl_wdr4900_v1.c
 467 @@ -0,0 +1,145 @@
 468 +/*
 469 + * TL-WDR4900 v1 board setup
 470 + *
 471 + * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
 472 + *
 473 + * Based on:
 474 + *   p1010rdb.c:
 475 + *      P1010RDB Board Setup
 476 + *      Copyright 2011 Freescale Semiconductor Inc.
 477 + *
 478 + * This program is free software; you can redistribute  it and/or modify it
 479 + * under  the terms of  the GNU General  Public License as published by the
 480 + * Free Software Foundation;  either version 2 of the  License, or (at your
 481 + * option) any later version.
 482 + */
 483 +
 484 +#include <linux/stddef.h>
 485 +#include <linux/kernel.h>
 486 +#include <linux/pci.h>
 487 +#include <linux/delay.h>
 488 +#include <linux/interrupt.h>
 489 +#include <linux/of_platform.h>
 490 +#include <linux/ath9k_platform.h>
 491 +#include <linux/leds.h>
 492 +
 493 +#include <asm/time.h>
 494 +#include <asm/machdep.h>
 495 +#include <asm/pci-bridge.h>
 496 +#include <mm/mmu_decl.h>
 497 +#include <asm/prom.h>
 498 +#include <asm/udbg.h>
 499 +#include <asm/mpic.h>
 500 +
 501 +#include <sysdev/fsl_soc.h>
 502 +#include <sysdev/fsl_pci.h>
 503 +
 504 +#include "mpc85xx.h"
 505 +
 506 +void __init tl_wdr4900_v1_pic_init(void)
 507 +{
 508 +       struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
 509 +         MPIC_SINGLE_DEST_CPU,
 510 +         0, 256, " OpenPIC  ");
 511 +
 512 +       BUG_ON(mpic == NULL);
 513 +
 514 +       mpic_init(mpic);
 515 +}
 516 +
 517 +#ifdef CONFIG_PCI
 518 +static struct gpio_led tl_wdr4900_v1_wmac_leds_gpio[] = {
 519 +       {
 520 +               .name           = "tp-link:blue:wps",
 521 +               .gpio           = 1,
 522 +               .active_low     = 1,
 523 +       },
 524 +};
 525 +
 526 +static struct ath9k_platform_data tl_wdr4900_v1_wmac0_data = {
 527 +       .led_pin = 0,
 528 +       .eeprom_name = "pci_wmac0.eeprom",
 529 +       .leds = tl_wdr4900_v1_wmac_leds_gpio,
 530 +       .num_leds = ARRAY_SIZE(tl_wdr4900_v1_wmac_leds_gpio),
 531 +};
 532 +
 533 +static struct ath9k_platform_data tl_wdr4900_v1_wmac1_data = {
 534 +       .led_pin = 0,
 535 +       .eeprom_name = "pci_wmac1.eeprom",
 536 +};
 537 +
 538 +static void tl_wdr4900_v1_pci_wmac_fixup(struct pci_dev *dev)
 539 +{
 540 +       if (!machine_is(tl_wdr4900_v1))
 541 +               return;
 542 +
 543 +       if (dev->bus->number == 1 &&
 544 +           PCI_SLOT(dev->devfn) == 0) {
 545 +               dev->dev.platform_data = &tl_wdr4900_v1_wmac0_data;
 546 +               return;
 547 +       }
 548 +
 549 +       if (dev->bus->number == 3 &&
 550 +           PCI_SLOT(dev->devfn) == 0 &&
 551 +           dev->device == 0xabcd) {
 552 +               dev->dev.platform_data = &tl_wdr4900_v1_wmac1_data;
 553 +
 554 +               /*
 555 +                * The PCI header of the AR9381 chip is not programmed
 556 +                * correctly by the bootloader and the device uses wrong
 557 +                * data due to that. Replace the broken values with the
 558 +                * correct ones.
 559 +                */
 560 +               dev->device = 0x30;
 561 +               dev->class = 0x028000;
 562 +
 563 +               pr_info("pci %s: AR9381 fixup applied\n", pci_name(dev));
 564 +       }
 565 +}
 566 +
 567 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,
 568 +                       tl_wdr4900_v1_pci_wmac_fixup);
 569 +#endif /* CONFIG_PCI */
 570 +
 571 +/*
 572 + * Setup the architecture
 573 + */
 574 +static void __init tl_wdr4900_v1_setup_arch(void)
 575 +{
 576 +       if (ppc_md.progress)
 577 +               ppc_md.progress("tl_wdr4900_v1_setup_arch()", 0);
 578 +
 579 +       fsl_pci_assign_primary();
 580 +
 581 +       printk(KERN_INFO "TL-WDR4900 v1 board from TP-Link\n");
 582 +}
 583 +
 584 +machine_arch_initcall(tl_wdr4900_v1, mpc85xx_common_publish_devices);
 585 +machine_arch_initcall(tl_wdr4900_v1, swiotlb_setup_bus_notifier);
 586 +
 587 +/*
 588 + * Called very early, device-tree isn't unflattened
 589 + */
 590 +static int __init tl_wdr4900_v1_probe(void)
 591 +{
 592 +       unsigned long root = of_get_flat_dt_root();
 593 +
 594 +       if (of_flat_dt_is_compatible(root, "tp-link,TL-WDR4900v1"))
 595 +               return 1;
 596 +
 597 +       return 0;
 598 +}
 599 +
 600 +define_machine(tl_wdr4900_v1) {
 601 +       .name                   = "Freescale P1014",
 602 +       .probe                  = tl_wdr4900_v1_probe,
 603 +       .setup_arch             = tl_wdr4900_v1_setup_arch,
 604 +       .init_IRQ               = tl_wdr4900_v1_pic_init,
 605 +#ifdef CONFIG_PCI
 606 +       .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 607 +#endif
 608 +       .get_irq                = mpic_get_irq,
 609 +       .restart                = fsl_rstcr_restart,
 610 +       .calibrate_decr         = generic_calibrate_decr,
 611 +       .progress               = udbg_progress,
 612 +};