target/linux/mediatek/patches/0071-clk.patch

   1 From c3a3617a8c37b43db7ff622a31f171d3ce870173 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 3 Jul 2015 05:44:57 +0200
   4 Subject: [PATCH 71/76] clk
   5
   6 ---
   7  drivers/clk/mediatek/clk-mt7623.c |  194 ++++++++++++++++---------------------
   8  1 file changed, 83 insertions(+), 111 deletions(-)
   9
  10 --- a/drivers/clk/mediatek/clk-mt7623.c
  11 +++ b/drivers/clk/mediatek/clk-mt7623.c
  12 @@ -20,6 +20,7 @@
  13
  14  #include "clk-mtk.h"
  15  #include "clk-gate.h"
  16 +#include "clk-cpumux.h"
  17
  18  static DEFINE_SPINLOCK(mt7623_clk_lock);
  19
  20 @@ -37,18 +38,11 @@ static void mtk_clk_enable_critical(void
  21         clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
  22  }
  23
  24 -static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
  25 -       FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
  26 -       FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
  27 -       FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
  28 -       FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
  29 -};
  30 -
  31  static const struct mtk_fixed_factor top_divs[] __initconst = {
  32 -       FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_650m", "mainpll", 1, 2),
  33 -       FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_433p3m", "mainpll", 1, 3),
  34 -       FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_260m", "mainpll", 1, 5),
  35 -       FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_185p6m", "mainpll", 1, 7),
  36 +       FACTOR(CLK_TOP_MAINPLL_650M, "mainpll_650m", "mainpll", 1, 2),
  37 +       FACTOR(CLK_TOP_MAINPLL_433P3M, "mainpll_433p3m", "mainpll", 1, 3),
  38 +       FACTOR(CLK_TOP_MAINPLL_260M, "mainpll_260m", "mainpll", 1, 5),
  39 +       FACTOR(CLK_TOP_MAINPLL_185P6M, "mainpll_185p6m", "mainpll", 1, 7),
  40
  41         FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
  42         FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
  43 @@ -61,13 +55,6 @@ static const struct mtk_fixed_factor top
  44         FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll", 1, 16),
  45         FACTOR(CLK_TOP_AUDPLL_24, "audpll_d24", "audpll", 1, 24),
  46
  47 -       FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
  48 -       FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
  49 -       FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
  50 -       FACTOR(CLK_TOP_LVDS_ETH, "lvdspll_eth", "lvdspll", 1, 16),
  51 -
  52 -       FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
  53 -
  54         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
  55
  56         FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll_650m", 1, 2),
  57 @@ -85,9 +72,6 @@ static const struct mtk_fixed_factor top
  58         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_260m", 1, 1),
  59         FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll_185p6m", 1, 1),
  60
  61 -       FACTOR(CLK_TOP_TVDPLL_d2, "tvdpll_d2", "tvdpll", 1, 2),
  62 -       FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
  63 -
  64         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
  65         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
  66         FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
  67 @@ -110,9 +94,6 @@ static const struct mtk_fixed_factor top
  68
  69         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
  70         FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
  71 -
  72 -
  73 -       FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
  74  };
  75
  76  static const char * const axi_parents[] __initconst = {
  77 @@ -155,18 +136,6 @@ static const char * const pwm_parents[]
  78         "univpll1_d4",
  79  };
  80
  81 -static const char * const vdec_parents[] __initconst = {
  82 -       "clk26m",
  83 -       "syspll1_d2",
  84 -       "syspll_d5",
  85 -       "syspll1_d4",
  86 -       "univpll_d5",
  87 -       "univpll2_d2",
  88 -       "univpll2_d4",
  89 -       "msdcpll_d2",
  90 -       "mmpll_d2",
  91 -};
  92 -
  93  static const char * const mfg_parents[] __initconst = {
  94         "clk26m",
  95         "mmpll_ck",
  96 @@ -178,17 +147,6 @@ static const char * const mfg_parents[]
  97         "univpll1_d2",
  98  };
  99
 100 -static const char * const cam_parents[] __initconst = {
 101 -       "clk26m",
 102 -       "univpll_d26",
 103 -       "univpll2_d2",
 104 -       "syspll3_d2",
 105 -       "syspll3_d4",
 106 -       "msdcpll_d2",
 107 -       "mmpll_d2",
 108 -       "clk26m",
 109 -};
 110 -
 111  static const char * const uart_parents[] __initconst = {
 112         "clk26m",
 113         "univpll2_d8",
 114 @@ -277,35 +235,6 @@ static const char * const scp_parents[]
 115         "dmpll_d4",
 116  };
 117
 118 -static const char * const dpi0_parents[] __initconst = {
 119 -       "clk26m",
 120 -       "mipipll",
 121 -       "mipipll_d2",
 122 -       "mipipll_d4",
 123 -       "lvdspll",
 124 -       "lvdspll_d2",
 125 -       "lvdspll_d4",
 126 -       "lvdspll_d8",
 127 -};
 128 -
 129 -static const char * const dpi1_parents[] __initconst = {
 130 -       "clk26m",
 131 -       "tvdpll",
 132 -       "tvdpll_d2",
 133 -       "tvdpll_d4",
 134 -};
 135 -
 136 -static const char * const tve_parents[] __initconst = {
 137 -       "clk26m",
 138 -       "mipipll",
 139 -       "mipipll_d2",
 140 -       "mipipll_d4",
 141 -       "clk26m",
 142 -       "tvdpll",
 143 -       "tvdpll_d2",
 144 -       "tvdpll_d4",
 145 -};
 146 -
 147  static const char * const apll_parents[] __initconst = {
 148         "clk26m",
 149         "audpll",
 150 @@ -317,17 +246,6 @@ static const char * const apll_parents[]
 151         "clk26m",
 152  };
 153
 154 -static const char * const dpilvds_parents[] __initconst = {
 155 -       "clk26m",
 156 -       "lvdspll",
 157 -       "lvdspll_d2",
 158 -       "lvdspll_d4",
 159 -       "lvdspll_d8",
 160 -       "fpc_ck",
 161 -       "clk26m",
 162 -       "clk26m",
 163 -};
 164 -
 165  static const char * const rtc_parents[] __initconst = {
 166         "clk32k",
 167         "external_32k",
 168 @@ -367,9 +285,7 @@ static const struct mtk_composite top_mu
 169                 0x0140, 24, 3, INVALID_MUX_GATE_BIT),
 170         /* CLK_CFG_1 */
 171         MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
 172 -       MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
 173         MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 16, 3, 23),
 174 -       MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0050, 24, 3, 31),
 175         /* CLK_CFG_2 */
 176         MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7),
 177         MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 8, 3, 15),
 178 @@ -384,12 +300,8 @@ static const struct mtk_composite top_mu
 179         /* CLK_CFG_4 */
 180         MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmic_spi_parents, 0x0080, 0, 4, 7),
 181         MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15),
 182 -       MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23),
 183 -       MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0080, 24, 2, 31),
 184         /* CLK_CFG_5 */
 185 -       MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7),
 186         MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0090, 16, 3, 23),
 187 -       MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0090, 24, 3, 31),
 188         /* CLK_CFG_6 */
 189         MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00a0, 0, 2, 7),
 190         MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00a0, 8, 3, 15),
 191 @@ -428,6 +340,17 @@ static const struct mtk_gate infra_clks[
 192         GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
 193  };
 194
 195 +static const char * const ca7_parents[] __initconst = {
 196 +       "clk26m",
 197 +       "armpll",
 198 +       "mainpll",
 199 +       "univpll"
 200 +};
 201 +
 202 +static struct mtk_composite cpu_muxes[] __initdata = {
 203 +       MUX(CLK_INFRA_CA7SEL, "infra_ca7_sel", ca7_parents, 0x0000, 2, 2),
 204 +};
 205 +
 206  static const struct mtk_gate_regs peri0_cg_regs = {
 207         .set_ofs = 0x0008,
 208         .clr_ofs = 0x0010,
 209 @@ -499,6 +422,29 @@ static const struct mtk_gate peri_gates[
 210         GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "axi_sel", 2),
 211  };
 212
 213 +static const struct mtk_gate_regs hifsys_cg_regs = {
 214 +       .set_ofs = 0x0034,
 215 +       .clr_ofs = 0x0014,
 216 +       .sta_ofs = 0x0038,
 217 +};
 218 +
 219 +#define GATE_HIFSYS(_id, _name, _parent, _shift) {             \
 220 +               .id = _id,                                      \
 221 +               .name = _name,                                  \
 222 +               .parent_name = _parent,                         \
 223 +               .regs = &hifsys_cg_regs,                        \
 224 +               .shift = _shift,                                \
 225 +               .ops = &mtk_clk_gate_ops_setclr,                \
 226 +       }
 227 +
 228 +static const struct mtk_gate hifsys_gates[] __initconst = {
 229 +       GATE_HIFSYS(CLK_HIFSYS_USB0_PHY, "usb0_phy_ck", "axi_sel", 21),
 230 +       GATE_HIFSYS(CLK_HIFSYS_USB1_PHY, "usb1_phy_ck", "axi_sel", 22),
 231 +       GATE_HIFSYS(CLK_HIFSYS_PCIE0, "pcie0_ck", "axi_sel", 24),
 232 +       GATE_HIFSYS(CLK_HIFSYS_PCIE1, "pcie1_ck", "axi_sel", 25),
 233 +       GATE_HIFSYS(CLK_HIFSYS_PCIE2, "pcie2_ck", "axi_sel", 26),
 234 +};
 235 +
 236  static const char * const uart_ck_sel_parents[] __initconst = {
 237         "clk26m",
 238         "uart_sel",
 239 @@ -525,10 +471,9 @@ static void __init mtk_topckgen_init(str
 240
 241         mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
 242
 243 -       mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
 244         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
 245         mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
 246 -                       &mt7623_clk_lock, clk_data);
 247 +                                       &mt7623_clk_lock, clk_data);
 248
 249         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 250         if (r)
 251 @@ -547,7 +492,10 @@ static void __init mtk_infrasys_init(str
 252         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
 253
 254         mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 255 -                                               clk_data);
 256 +                               clk_data);
 257 +
 258 +       mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
 259 +                                  clk_data);
 260
 261         clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
 262
 263 @@ -588,35 +536,59 @@ static void __init mtk_pericfg_init(stru
 264  }
 265  CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt7623-pericfg", mtk_pericfg_init);
 266
 267 -#define MT7623_PLL_FMAX                (2000 * MHZ)
 268 -#define CON0_MT7623_RST_BAR    BIT(27)
 269 +static void __init mtk_hifsys_init(struct device_node *node)
 270 +{
 271 +       struct clk_onecell_data *clk_data;
 272 +       int r;
 273 +       void __iomem *base;
 274 +
 275 +       base = of_iomap(node, 0);
 276 +       if (!base) {
 277 +               pr_err("%s(): ioremap failed\n", __func__);
 278 +               return;
 279 +       }
 280 +
 281 +       clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR_CLK);
 282 +
 283 +       mtk_clk_register_gates(node, hifsys_gates, ARRAY_SIZE(hifsys_gates),
 284 +                                               clk_data);
 285 +
 286 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 287 +       if (r)
 288 +               pr_err("%s(): could not register clock provider: %d\n",
 289 +                       __func__, r);
 290 +
 291 +       mtk_register_reset_controller(node, 1, 0x34);
 292 +}
 293 +CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt7623-hifsys", mtk_hifsys_init);
 294 +
 295 +#define MT7623_PLL_FMAX                (1300 * MHZ)
 296 +#define CON0_MT7623_RST_BAR    BIT(24)
 297
 298 -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
 299 +#define PLL(_id, _name, _con0_reg, _con1_reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pcw_shift, _pd_shift) { \
 300                 .id = _id,                                              \
 301                 .name = _name,                                          \
 302 -               .reg = _reg,                                            \
 303 +               .reg = _con0_reg,                                               \
 304                 .pwr_reg = _pwr_reg,                                    \
 305                 .en_mask = _en_mask,                                    \
 306                 .flags = _flags,                                        \
 307                 .rst_bar_mask = CON0_MT7623_RST_BAR,                    \
 308                 .fmax = MT7623_PLL_FMAX,                                \
 309                 .pcwbits = _pcwbits,                                    \
 310 -               .pd_reg = _pd_reg,                                      \
 311 +               .pd_reg = _con0_reg,                                    \
 312                 .pd_shift = _pd_shift,                                  \
 313 -               .tuner_reg = _tuner_reg,                                \
 314 -               .pcw_reg = _pcw_reg,                                    \
 315 +               .pcw_reg = _con1_reg,                                   \
 316                 .pcw_shift = _pcw_shift,                                \
 317         }
 318
 319  static const struct mtk_pll_data plls[] = {
 320 -       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
 321 -       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0x214, 6, 0x0, 0x214, 0),
 322 -       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 0x224, 6, 0x0, 0x224, 0),
 323 -       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 21, 0x254, 6, 0x0, 0x258, 0),
 324 -       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 6, 0x0, 0x244, 0),
 325 -       PLL(CLK_APMIXED_AUDPLL, "audpll", 0x250, 0x25c, 0x00000001, 0, 31, 0x2e8, 6, 0x2f8, 0x254, 0),
 326 -       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x260, 0x26c, 0x00000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
 327 -       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x270, 0x27c, 0x00000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
 328 +       PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x204, 0x20c, 0x00000001, 0, 21, 0, 4 ),
 329 +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x214, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0, 4 ),
 330 +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x224, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 14, 4 ),
 331 +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x244, 0x24c, 0x00000001, 0, 21, 0, 4 ),
 332 +       PLL(CLK_APMIXED_AUDPLL, "audpll", 0x270, 0x274, 0x27c, 0x00000001, 0, 31, 0, 4 ),
 333 +       PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x284, 0x28c, 0x00000001, 0, 31, 0, 4 ),
 334 +       PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x294, 0x29c, 0x00000001, 0, 31, 0, 4 ),
 335  };
 336
 337  static void __init mtk_apmixedsys_init(struct device_node *node)