target/linux/mediatek/patches/0070-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch

   1 From ac825c0dd7370ae1b9a1a4346f895728e09d9cc7 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 1 Jul 2015 07:58:44 +0200
   4 Subject: [PATCH 70/76] clk: mediatek: Export CPU mux clocks for CPU frequency
   5  control
   6
   7 This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
   8 for intermediate clock source switching.
   9
  10 Changes in v3:
  11 - Rebase to 4.2-rc1
  12 - Fix some issues of v2
  13
  14 Changes in v2:
  15 - Remove use of .determine_rate callback
  16
  17 Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  18 ---
  19  drivers/clk/mediatek/Makefile     |    2 +-
  20  drivers/clk/mediatek/clk-cpumux.c |  119 +++++++++++++++++++++++++++++++++++++
  21  drivers/clk/mediatek/clk-cpumux.h |   30 ++++++++++
  22  3 files changed, 150 insertions(+), 1 deletion(-)
  23  create mode 100644 drivers/clk/mediatek/clk-cpumux.c
  24  create mode 100644 drivers/clk/mediatek/clk-cpumux.h
  25
  26 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
  27 index 19a3763..fe07e26 100644
  28 --- a/drivers/clk/mediatek/Makefile
  29 +++ b/drivers/clk/mediatek/Makefile
  30 @@ -1,4 +1,4 @@
  31 -obj-y += clk-mtk.o clk-pll.o clk-gate.o
  32 +obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-cpumux.o
  33  obj-$(CONFIG_RESET_CONTROLLER) += reset.o
  34  obj-y += clk-mt7623.o
  35  obj-y += clk-mt8135.o
  36 diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
  37 new file mode 100644
  38 index 0000000..593df45
  39 --- /dev/null
  40 +++ b/drivers/clk/mediatek/clk-cpumux.c
  41 @@ -0,0 +1,119 @@
  42 +/*
  43 + * Copyright (c) 2015 Linaro Ltd.
  44 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  45 + *
  46 + * This program is free software; you can redistribute it and/or modify
  47 + * it under the terms of the GNU General Public License version 2 as
  48 + * published by the Free Software Foundation.
  49 + *
  50 + * This program is distributed in the hope that it will be useful,
  51 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  52 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  53 + * GNU General Public License for more details.
  54 + */
  55 +
  56 +#include <linux/clk-provider.h>
  57 +#include <linux/mfd/syscon.h>
  58 +#include <linux/slab.h>
  59 +
  60 +#include "clk-mtk.h"
  61 +#include "clk-cpumux.h"
  62 +
  63 +static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
  64 +{
  65 +       return container_of(_hw, struct mtk_clk_cpumux, hw);
  66 +}
  67 +
  68 +static u8 clk_cpumux_get_parent(struct clk_hw *hw)
  69 +{
  70 +       struct mtk_clk_cpumux *mux = to_clk_mux(hw);
  71 +       int num_parents = __clk_get_num_parents(hw->clk);
  72 +       unsigned int val;
  73 +
  74 +       regmap_read(mux->regmap, mux->reg, &val);
  75 +
  76 +       val >>= mux->shift;
  77 +       val &= mux->mask;
  78 +
  79 +       if (val >= num_parents)
  80 +               return -EINVAL;
  81 +
  82 +       return val;
  83 +}
  84 +
  85 +static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
  86 +{
  87 +       struct mtk_clk_cpumux *mux = to_clk_mux(hw);
  88 +       u32 mask, val;
  89 +
  90 +       val = index << mux->shift;
  91 +       mask = mux->mask << mux->shift;
  92 +
  93 +       return regmap_update_bits(mux->regmap, mux->reg, mask, val);
  94 +}
  95 +
  96 +static const struct clk_ops clk_cpumux_ops = {
  97 +       .get_parent = clk_cpumux_get_parent,
  98 +       .set_parent = clk_cpumux_set_parent,
  99 +};
 100 +
 101 +static struct clk *mtk_clk_register_cpumux(const struct mtk_composite *mux,
 102 +                                          struct regmap *regmap)
 103 +{
 104 +       struct mtk_clk_cpumux *cpumux;
 105 +       struct clk *clk;
 106 +       struct clk_init_data init;
 107 +
 108 +       cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
 109 +       if (!cpumux)
 110 +               return ERR_PTR(-ENOMEM);
 111 +
 112 +       init.name = mux->name;
 113 +       init.ops = &clk_cpumux_ops;
 114 +       init.parent_names = mux->parent_names;
 115 +       init.num_parents = mux->num_parents;
 116 +       init.flags = mux->flags;
 117 +
 118 +       cpumux->reg = mux->mux_reg;
 119 +       cpumux->shift = mux->mux_shift;
 120 +       cpumux->mask = BIT(mux->mux_width) - 1;
 121 +       cpumux->regmap = regmap;
 122 +       cpumux->hw.init = &init;
 123 +
 124 +       clk = clk_register(NULL, &cpumux->hw);
 125 +       if (IS_ERR(clk))
 126 +               kfree(cpumux);
 127 +
 128 +       return clk;
 129 +}
 130 +
 131 +int mtk_clk_register_cpumuxes(struct device_node *node,
 132 +                             const struct mtk_composite *clks, int num,
 133 +                             struct clk_onecell_data *clk_data)
 134 +{
 135 +       int i;
 136 +       struct clk *clk;
 137 +       struct regmap *regmap;
 138 +
 139 +       regmap = syscon_node_to_regmap(node);
 140 +       if (IS_ERR(regmap)) {
 141 +               pr_err("Cannot find regmap for %s: %d\n", node->full_name,
 142 +                      PTR_ERR(regmap));
 143 +               return PTR_ERR(regmap);
 144 +       }
 145 +
 146 +       for (i = 0; i < num; i++) {
 147 +               const struct mtk_composite *mux = &clks[i];
 148 +
 149 +               clk = mtk_clk_register_cpumux(mux, regmap);
 150 +               if (IS_ERR(clk)) {
 151 +                       pr_err("Failed to register clk %s: %ld\n",
 152 +                              mux->name, PTR_ERR(clk));
 153 +                       continue;
 154 +               }
 155 +
 156 +               clk_data->clks[mux->id] = clk;
 157 +       }
 158 +
 159 +       return 0;
 160 +}
 161 diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
 162 new file mode 100644
 163 index 0000000..dddaad5
 164 --- /dev/null
 165 +++ b/drivers/clk/mediatek/clk-cpumux.h
 166 @@ -0,0 +1,30 @@
 167 +/*
 168 + * Copyright (c) 2015 Linaro Ltd.
 169 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
 170 + *
 171 + * This program is free software; you can redistribute it and/or modify
 172 + * it under the terms of the GNU General Public License version 2 as
 173 + * published by the Free Software Foundation.
 174 + *
 175 + * This program is distributed in the hope that it will be useful,
 176 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 177 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 178 + * GNU General Public License for more details.
 179 + */
 180 +
 181 +#ifndef __DRV_CLK_CPUMUX_H
 182 +#define __DRV_CLK_CPUMUX_H
 183 +
 184 +struct mtk_clk_cpumux {
 185 +       struct clk_hw   hw;
 186 +       struct regmap   *regmap;
 187 +       u32             reg;
 188 +       u32             mask;
 189 +       u8              shift;
 190 +};
 191 +
 192 +int mtk_clk_register_cpumuxes(struct device_node *node,
 193 +                             const struct mtk_composite *clks, int num,
 194 +                             struct clk_onecell_data *clk_data);
 195 +
 196 +#endif /* __DRV_CLK_CPUMUX_H */
 197 --
 198 1.7.10.4
 199