target/linux/mediatek/patches/0069-arm-mediatek-add-mt7623-support-to-pmic-wrapper.patch

   1 From 0ec1ddd9233579b6d6dc0df325e870c5560344be Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 28 Jun 2015 19:50:51 +0200
   4 Subject: [PATCH 69/76] arm: mediatek: add mt7623 support to pmic-wrapper
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/soc/mediatek/mtk-pmic-wrap.c |  345 +++++++++++++++++++++++++++++-----
   9  1 file changed, 296 insertions(+), 49 deletions(-)
  10
  11 diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
  12 index f432291..9ff02a1 100644
  13 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
  14 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
  15 @@ -31,6 +31,13 @@
  16  #define PWRAP_MT8135_BRIDGE_WDT_UNIT           0x50
  17  #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN         0x54
  18
  19 +#define PWRAP_MT7623_AUXADC_CON21              0x076C
  20 +#define PWRAP_MT7623_AUXADC_ADC12              0x072C
  21 +#define PWRAP_MT7623_AUXADC_ADC13              0x072E
  22 +#define PWRAP_MT7623_AUXADC_ADC14              0x0730
  23 +#define PWRAP_MT7623_AUXADC_CON2               0x0746
  24 +#define PWRAP_MT7623_AUXADC_CON3               0x0748
  25 +
  26  /* macro for wrapper status */
  27  #define PWRAP_GET_WACS_RDATA(x)                (((x) >> 0) & 0x0000ffff)
  28  #define PWRAP_GET_WACS_FSM(x)          (((x) >> 16) & 0x00000007)
  29 @@ -61,32 +68,104 @@
  30  #define PWRAP_MAN_CMD_OP_OUTQ          (0xa << 8)
  31
  32  /* macro for slave device wrapper registers */
  33 -#define PWRAP_DEW_BASE                 0xbc00
  34 -#define PWRAP_DEW_EVENT_OUT_EN         (PWRAP_DEW_BASE + 0x0)
  35 -#define PWRAP_DEW_DIO_EN               (PWRAP_DEW_BASE + 0x2)
  36 -#define PWRAP_DEW_EVENT_SRC_EN         (PWRAP_DEW_BASE + 0x4)
  37 -#define PWRAP_DEW_EVENT_SRC            (PWRAP_DEW_BASE + 0x6)
  38 -#define PWRAP_DEW_EVENT_FLAG           (PWRAP_DEW_BASE + 0x8)
  39 -#define PWRAP_DEW_READ_TEST            (PWRAP_DEW_BASE + 0xa)
  40 -#define PWRAP_DEW_WRITE_TEST           (PWRAP_DEW_BASE + 0xc)
  41 -#define PWRAP_DEW_CRC_EN               (PWRAP_DEW_BASE + 0xe)
  42 -#define PWRAP_DEW_CRC_VAL              (PWRAP_DEW_BASE + 0x10)
  43 -#define PWRAP_DEW_MON_GRP_SEL          (PWRAP_DEW_BASE + 0x12)
  44 -#define PWRAP_DEW_MON_FLAG_SEL         (PWRAP_DEW_BASE + 0x14)
  45 -#define PWRAP_DEW_EVENT_TEST           (PWRAP_DEW_BASE + 0x16)
  46 -#define PWRAP_DEW_CIPHER_KEY_SEL       (PWRAP_DEW_BASE + 0x18)
  47 -#define PWRAP_DEW_CIPHER_IV_SEL                (PWRAP_DEW_BASE + 0x1a)
  48 -#define PWRAP_DEW_CIPHER_LOAD          (PWRAP_DEW_BASE + 0x1c)
  49 -#define PWRAP_DEW_CIPHER_START         (PWRAP_DEW_BASE + 0x1e)
  50 -#define PWRAP_DEW_CIPHER_RDY           (PWRAP_DEW_BASE + 0x20)
  51 -#define PWRAP_DEW_CIPHER_MODE          (PWRAP_DEW_BASE + 0x22)
  52 -#define PWRAP_DEW_CIPHER_SWRST         (PWRAP_DEW_BASE + 0x24)
  53 -#define PWRAP_MT8173_DEW_CIPHER_IV0    (PWRAP_DEW_BASE + 0x26)
  54 -#define PWRAP_MT8173_DEW_CIPHER_IV1    (PWRAP_DEW_BASE + 0x28)
  55 -#define PWRAP_MT8173_DEW_CIPHER_IV2    (PWRAP_DEW_BASE + 0x2a)
  56 -#define PWRAP_MT8173_DEW_CIPHER_IV3    (PWRAP_DEW_BASE + 0x2c)
  57 -#define PWRAP_MT8173_DEW_CIPHER_IV4    (PWRAP_DEW_BASE + 0x2e)
  58 -#define PWRAP_MT8173_DEW_CIPHER_IV5    (PWRAP_DEW_BASE + 0x30)
  59 +enum pwrap_dew_regs {
  60 +       PWRAP_DEW_EVENT_OUT_EN,
  61 +       PWRAP_DEW_DIO_EN,
  62 +       PWRAP_DEW_EVENT_SRC_EN,
  63 +       PWRAP_DEW_EVENT_SRC,
  64 +       PWRAP_DEW_EVENT_FLAG,
  65 +       PWRAP_DEW_READ_TEST,
  66 +       PWRAP_DEW_WRITE_TEST,
  67 +       PWRAP_DEW_CRC_EN,
  68 +       PWRAP_DEW_CRC_VAL,
  69 +       PWRAP_DEW_MON_GRP_SEL,
  70 +       PWRAP_DEW_MON_FLAG_SEL,
  71 +       PWRAP_DEW_EVENT_TEST,
  72 +       PWRAP_DEW_CIPHER_KEY_SEL,
  73 +       PWRAP_DEW_CIPHER_IV_SEL,
  74 +       PWRAP_DEW_CIPHER_LOAD,
  75 +       PWRAP_DEW_CIPHER_START,
  76 +       PWRAP_DEW_CIPHER_RDY,
  77 +       PWRAP_DEW_CIPHER_MODE,
  78 +       PWRAP_DEW_CIPHER_SWRST,
  79 +
  80 +       /* MT7623 only regs */
  81 +       PWRAP_DEW_CIPHER_EN,
  82 +       PWRAP_DEW_RDDMY_NO,
  83 +
  84 +       /* MT8173 only regs */
  85 +       PWRAP_DEW_CIPHER_IV0,
  86 +       PWRAP_DEW_CIPHER_IV1,
  87 +       PWRAP_DEW_CIPHER_IV2,
  88 +       PWRAP_DEW_CIPHER_IV3,
  89 +       PWRAP_DEW_CIPHER_IV4,
  90 +       PWRAP_DEW_CIPHER_IV5,
  91 +};
  92 +
  93 +static int mt7623_dew_regs[] = {
  94 +       [PWRAP_DEW_DIO_EN]              = 0x18a,
  95 +       [PWRAP_DEW_READ_TEST]           = 0x18c,
  96 +       [PWRAP_DEW_WRITE_TEST]          = 0x18e,
  97 +       [PWRAP_DEW_CRC_EN]              = 0x192,
  98 +       [PWRAP_DEW_CRC_VAL]             = 0x194,
  99 +       [PWRAP_DEW_CIPHER_KEY_SEL]      = 0x198,
 100 +       [PWRAP_DEW_CIPHER_IV_SEL]       = 0x19a,
 101 +       [PWRAP_DEW_CIPHER_EN]           = 0x19c,
 102 +       [PWRAP_DEW_CIPHER_RDY]          = 0x19e,
 103 +       [PWRAP_DEW_CIPHER_MODE]         = 0x1a0,
 104 +       [PWRAP_DEW_CIPHER_SWRST]        = 0x1a2,
 105 +       [PWRAP_DEW_RDDMY_NO]            = 0x1a4,
 106 +};
 107 +
 108 +static int mt8135_dew_regs[] = {
 109 +       [PWRAP_DEW_EVENT_OUT_EN]        = 0x0,
 110 +       [PWRAP_DEW_DIO_EN]              = 0x2,
 111 +       [PWRAP_DEW_EVENT_SRC_EN]        = 0x4,
 112 +       [PWRAP_DEW_EVENT_SRC]           = 0x6,
 113 +       [PWRAP_DEW_EVENT_FLAG]          = 0x8,
 114 +       [PWRAP_DEW_READ_TEST]           = 0xa,
 115 +       [PWRAP_DEW_WRITE_TEST]          = 0xc,
 116 +       [PWRAP_DEW_CRC_EN]              = 0xe,
 117 +       [PWRAP_DEW_CRC_VAL]             = 0x10,
 118 +       [PWRAP_DEW_MON_GRP_SEL]         = 0x12,
 119 +       [PWRAP_DEW_MON_FLAG_SEL]        = 0x14,
 120 +       [PWRAP_DEW_EVENT_TEST]          = 0x16,
 121 +       [PWRAP_DEW_CIPHER_KEY_SEL]      = 0x18,
 122 +       [PWRAP_DEW_CIPHER_IV_SEL]       = 0x1a,
 123 +       [PWRAP_DEW_CIPHER_LOAD]         = 0x1c,
 124 +       [PWRAP_DEW_CIPHER_START]        = 0x1e,
 125 +       [PWRAP_DEW_CIPHER_RDY]          = 0x20,
 126 +       [PWRAP_DEW_CIPHER_MODE]         = 0x22,
 127 +       [PWRAP_DEW_CIPHER_SWRST]        = 0x24,
 128 +};
 129 +
 130 +static int mt8173_dew_regs[] = {
 131 +       [PWRAP_DEW_EVENT_OUT_EN]        = 0x0,
 132 +       [PWRAP_DEW_DIO_EN]              = 0x2,
 133 +       [PWRAP_DEW_EVENT_SRC_EN]        = 0x4,
 134 +       [PWRAP_DEW_EVENT_SRC]           = 0x6,
 135 +       [PWRAP_DEW_EVENT_FLAG]          = 0x8,
 136 +       [PWRAP_DEW_READ_TEST]           = 0xa,
 137 +       [PWRAP_DEW_WRITE_TEST]          = 0xc,
 138 +       [PWRAP_DEW_CRC_EN]              = 0xe,
 139 +       [PWRAP_DEW_CRC_VAL]             = 0x10,
 140 +       [PWRAP_DEW_MON_GRP_SEL]         = 0x12,
 141 +       [PWRAP_DEW_MON_FLAG_SEL]        = 0x14,
 142 +       [PWRAP_DEW_EVENT_TEST]          = 0x16,
 143 +       [PWRAP_DEW_CIPHER_KEY_SEL]      = 0x18,
 144 +       [PWRAP_DEW_CIPHER_IV_SEL]       = 0x1a,
 145 +       [PWRAP_DEW_CIPHER_LOAD]         = 0x1c,
 146 +       [PWRAP_DEW_CIPHER_START]        = 0x1e,
 147 +       [PWRAP_DEW_CIPHER_RDY]          = 0x20,
 148 +       [PWRAP_DEW_CIPHER_MODE]         = 0x22,
 149 +       [PWRAP_DEW_CIPHER_SWRST]        = 0x24,
 150 +       [PWRAP_DEW_CIPHER_IV0]          = 0x26,
 151 +       [PWRAP_DEW_CIPHER_IV1]          = 0x28,
 152 +       [PWRAP_DEW_CIPHER_IV2]          = 0x2a,
 153 +       [PWRAP_DEW_CIPHER_IV3]          = 0x2c,
 154 +       [PWRAP_DEW_CIPHER_IV4]          = 0x2e,
 155 +       [PWRAP_DEW_CIPHER_IV5]          = 0x30,
 156 +};
 157
 158  enum pwrap_regs {
 159         PWRAP_MUX_SEL,
 160 @@ -162,7 +241,7 @@ enum pwrap_regs {
 161         PWRAP_CIPHER_LOAD,
 162         PWRAP_CIPHER_START,
 163
 164 -       /* MT8173 only regs */
 165 +       /* MT7623/MT8173 only regs */
 166         PWRAP_RDDMY,
 167         PWRAP_SI_CK_CON,
 168         PWRAP_DVFS_ADR0,
 169 @@ -183,6 +262,107 @@ enum pwrap_regs {
 170         PWRAP_DVFS_WDATA7,
 171         PWRAP_SPMINF_STA,
 172         PWRAP_CIPHER_EN,
 173 +
 174 +       /* MT7623 only regs */
 175 +       PWRAP_OP_TYPE,
 176 +       PWRAP_MSB_FIRST,
 177 +       PWRAP_TOP_CKCON1,
 178 +       PWRAP_TOP_CKCON1_CLR,
 179 +       PWRAP_ADC_CMD_ADDR,
 180 +       PWRAP_ADC_CMD,
 181 +       PWRAP_ADC_RDY_ADDR,
 182 +       PWRAP_ADC_RDATA_ADDR1,
 183 +       PWRAP_ADC_RDATA_ADDR2,
 184 +};
 185 +
 186 +static int mt7623_regs[] = {
 187 +       [PWRAP_MUX_SEL] =               0x0,
 188 +       [PWRAP_WRAP_EN] =               0x4,
 189 +       [PWRAP_DIO_EN] =                0x8,
 190 +       [PWRAP_SIDLY] =                 0xc,
 191 +       [PWRAP_OP_TYPE] =               0x10,
 192 +       [PWRAP_MSB_FIRST] =             0x14,
 193 +       [PWRAP_RDDMY] =                 0x18,
 194 +       [PWRAP_SI_CK_CON] =             0x1c,
 195 +       [PWRAP_CSHEXT_WRITE] =          0x20,
 196 +       [PWRAP_CSHEXT_READ] =           0x24,
 197 +       [PWRAP_CSLEXT_START] =          0x28,
 198 +       [PWRAP_CSLEXT_END] =            0x2c,
 199 +       [PWRAP_STAUPD_PRD] =            0x30,
 200 +       [PWRAP_STAUPD_GRPEN] =          0x34,
 201 +       [PWRAP_STAUPD_MAN_TRIG] =       0x38,
 202 +       [PWRAP_STAUPD_STA] =            0x3C,
 203 +       [PWRAP_WRAP_STA] =              0x44,
 204 +       [PWRAP_HARB_INIT] =             0x48,
 205 +       [PWRAP_HARB_HPRIO] =            0x4c,
 206 +       [PWRAP_HIPRIO_ARB_EN] =         0x50,
 207 +       [PWRAP_HARB_STA0] =             0x54,
 208 +       [PWRAP_HARB_STA1] =             0x58,
 209 +       [PWRAP_MAN_EN] =                0x5c,
 210 +       [PWRAP_MAN_CMD] =               0x60,
 211 +       [PWRAP_MAN_RDATA] =             0x6c,
 212 +       [PWRAP_MAN_VLDCLR] =            0x68,
 213 +       [PWRAP_WACS0_EN] =              0x6c,
 214 +       [PWRAP_INIT_DONE0] =            0x70,
 215 +       [PWRAP_WACS0_CMD] =             0x74,
 216 +       [PWRAP_WACS0_RDATA] =           0x78,
 217 +       [PWRAP_WACS0_VLDCLR] =          0x7c,
 218 +       [PWRAP_WACS1_EN] =              0x80,
 219 +       [PWRAP_INIT_DONE1] =            0x84,
 220 +       [PWRAP_WACS1_CMD] =             0x88,
 221 +       [PWRAP_WACS1_RDATA] =           0x9c,
 222 +       [PWRAP_WACS1_VLDCLR] =          0x90,
 223 +       [PWRAP_WACS2_EN] =              0x94,
 224 +       [PWRAP_INIT_DONE2] =            0x98,
 225 +       [PWRAP_WACS2_CMD] =             0x9c,
 226 +       [PWRAP_WACS2_RDATA] =           0xa0,
 227 +       [PWRAP_WACS2_VLDCLR] =          0xa4,
 228 +       [PWRAP_INT_EN] =                0xa8,
 229 +       [PWRAP_INT_FLG_RAW] =           0xac,
 230 +       [PWRAP_INT_FLG] =               0xb0,
 231 +       [PWRAP_INT_CLR] =               0xb4,
 232 +       [PWRAP_SIG_ADR] =               0xb8,
 233 +       [PWRAP_SIG_MODE] =              0xbc,
 234 +       [PWRAP_SIG_VALUE] =             0xc0,
 235 +       [PWRAP_SIG_ERRVAL] =            0xc4,
 236 +       [PWRAP_CRC_EN] =                0xc8,
 237 +       [PWRAP_TIMER_EN] =              0xcc,
 238 +       [PWRAP_TIMER_STA] =             0xd0,
 239 +       [PWRAP_WDT_UNIT] =              0xd4,
 240 +       [PWRAP_WDT_SRC_EN] =            0xd8,
 241 +       [PWRAP_WDT_FLG] =               0xdc,
 242 +       [PWRAP_DEBUG_INT_SEL] =         0xe0,
 243 +       [PWRAP_DVFS_ADR0] =             0xe4,
 244 +       [PWRAP_DVFS_WDATA0] =           0xe8,
 245 +       [PWRAP_DVFS_ADR1] =             0xec,
 246 +       [PWRAP_DVFS_WDATA1] =           0xf0,
 247 +       [PWRAP_DVFS_ADR2] =             0xf4,
 248 +       [PWRAP_DVFS_WDATA2] =           0xf8,
 249 +       [PWRAP_DVFS_ADR3] =             0xfc,
 250 +       [PWRAP_DVFS_WDATA3] =           0x100,
 251 +       [PWRAP_DVFS_ADR4] =             0x104,
 252 +       [PWRAP_DVFS_WDATA4] =           0x108,
 253 +       [PWRAP_DVFS_ADR5] =             0x10c,
 254 +       [PWRAP_DVFS_WDATA5] =           0x110,
 255 +       [PWRAP_DVFS_ADR6] =             0x114,
 256 +       [PWRAP_DVFS_WDATA6] =           0x118,
 257 +       [PWRAP_DVFS_ADR7] =             0x11c,
 258 +       [PWRAP_DVFS_WDATA7] =           0x120,
 259 +       [PWRAP_CIPHER_KEY_SEL] =        0x124,
 260 +       [PWRAP_TOP_CKCON1] =            0x126,
 261 +       [PWRAP_CIPHER_IV_SEL] =         0x128,
 262 +       [PWRAP_TOP_CKCON1_CLR] =        0x12a,
 263 +       [PWRAP_CIPHER_EN] =             0x12c,
 264 +       [PWRAP_CIPHER_RDY] =            0x130,
 265 +       [PWRAP_CIPHER_MODE] =           0x134,
 266 +       [PWRAP_CIPHER_SWRST] =          0x138,
 267 +       [PWRAP_DCM_EN] =                0x13c,
 268 +       [PWRAP_DCM_DBC_PRD] =           0x140,
 269 +       [PWRAP_ADC_CMD_ADDR] =  0x144,
 270 +       [PWRAP_ADC_CMD] =               0x148,
 271 +       [PWRAP_ADC_RDY_ADDR] =  0x14C,
 272 +       [PWRAP_ADC_RDATA_ADDR1] =       0x150,
 273 +       [PWRAP_ADC_RDATA_ADDR2] =       0x154,
 274  };
 275
 276  static int mt8173_regs[] = {
 277 @@ -341,24 +521,39 @@ static int mt8135_regs[] = {
 278  };
 279
 280  enum pwrap_type {
 281 +       PWRAP_MT7623,
 282         PWRAP_MT8135,
 283         PWRAP_MT8173,
 284  };
 285
 286  struct pmic_wrapper_type {
 287         int *regs;
 288 +       int *dew_regs;
 289 +       u32 dew_base;
 290         enum pwrap_type type;
 291         u32 arb_en_all;
 292  };
 293
 294 +static struct pmic_wrapper_type pwrap_mt7623 = {
 295 +       .regs = mt7623_regs,
 296 +       .dew_regs = mt7623_dew_regs,
 297 +       .dew_base = 0x0,
 298 +       .type = PWRAP_MT7623,
 299 +       .arb_en_all = 0x3f,
 300 +};
 301 +
 302  static struct pmic_wrapper_type pwrap_mt8135 = {
 303         .regs = mt8135_regs,
 304 +       .dew_regs = mt8135_dew_regs,
 305 +       .dew_base = 0xbc00,
 306         .type = PWRAP_MT8135,
 307         .arb_en_all = 0x1ff,
 308  };
 309
 310  static struct pmic_wrapper_type pwrap_mt8173 = {
 311         .regs = mt8173_regs,
 312 +       .dew_regs = mt8173_dew_regs,
 313 +       .dew_base = 0xbc00,
 314         .type = PWRAP_MT8173,
 315         .arb_en_all = 0x3f,
 316  };
 317 @@ -368,6 +563,8 @@ struct pmic_wrapper {
 318         void __iomem *base;
 319         struct regmap *regmap;
 320         int *regs;
 321 +       int *dew_regs;
 322 +       u32 dew_base;
 323         enum pwrap_type type;
 324         u32 arb_en_all;
 325         struct clk *clk_spi;
 326 @@ -378,6 +575,11 @@ struct pmic_wrapper {
 327         void __iomem *bridge_base;
 328  };
 329
 330 +static inline int pwrap_is_mt7623(struct pmic_wrapper *wrp)
 331 +{
 332 +       return wrp->type == PWRAP_MT7623;
 333 +}
 334 +
 335  static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
 336  {
 337         return wrp->type == PWRAP_MT8135;
 338 @@ -475,6 +677,16 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
 339         return 0;
 340  }
 341
 342 +static int pwrap_dew_write(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg, u32 wdata)
 343 +{
 344 +       return pwrap_write(wrp, wrp->dew_base + wrp->dew_regs[reg], wdata);
 345 +}
 346 +
 347 +static int pwrap_dew_read(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg, u32 *rdata)
 348 +{
 349 +       return pwrap_read(wrp, wrp->dew_base + wrp->dew_regs[reg], rdata);
 350 +}
 351 +
 352  static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
 353  {
 354         return pwrap_read(context, adr, rdata);
 355 @@ -535,7 +747,7 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
 356
 357         for (i = 0; i < 4; i++) {
 358                 pwrap_writel(wrp, i, PWRAP_SIDLY);
 359 -               pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
 360 +               pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
 361                 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
 362                         dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
 363                         pass |= 1 << i;
 364 @@ -561,6 +773,14 @@ static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
 365                 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
 366                 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
 367                 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
 368 +       } else if (pwrap_is_mt7623(wrp)) {
 369 +               pwrap_writel(wrp, 0x3, PWRAP_TOP_CKCON1_CLR);
 370 +               pwrap_dew_write(wrp, 0x8, PWRAP_DEW_RDDMY_NO);
 371 +               pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
 372 +               pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
 373 +               pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
 374 +               pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
 375 +               pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
 376         } else {
 377                 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
 378                 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
 379 @@ -581,7 +801,7 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
 380         u32 rdata;
 381         int ret;
 382
 383 -       ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
 384 +       ret = pwrap_dew_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
 385         if (ret)
 386                 return 0;
 387
 388 @@ -606,12 +826,16 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
 389         }
 390
 391         /* Config cipher mode @PMIC */
 392 -       pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
 393 -       pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
 394 -       pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
 395 -       pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
 396 -       pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
 397 -       pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
 398 +       pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
 399 +       pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
 400 +       pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
 401 +       pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
 402 +       if (pwrap_is_mt7623(wrp)) {
 403 +               pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_EN, 0x1);
 404 +       } else {
 405 +               pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
 406 +               pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
 407 +       }
 408
 409         /* wait for cipher data ready@AP */
 410         ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
 411 @@ -628,7 +852,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
 412         }
 413
 414         /* wait for cipher mode idle */
 415 -       pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
 416 +       pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
 417         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
 418         if (ret) {
 419                 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
 420 @@ -638,8 +862,8 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
 421         pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
 422
 423         /* Write Test */
 424 -       if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
 425 -           pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
 426 +       if (pwrap_dew_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
 427 +           pwrap_dew_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
 428                         (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
 429                 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
 430                 return -EFAULT;
 431 @@ -657,12 +881,17 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 432         if (wrp->rstc_bridge)
 433                 reset_control_reset(wrp->rstc_bridge);
 434
 435 -       if (pwrap_is_mt8173(wrp)) {
 436 +       if (pwrap_is_mt7623(wrp) || pwrap_is_mt8173(wrp)) {
 437                 /* Enable DCM */
 438                 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
 439                 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
 440         }
 441
 442 +       if (pwrap_is_mt7623(wrp)) {
 443 +               pwrap_writel(wrp, 0, PWRAP_OP_TYPE);
 444 +               pwrap_writel(wrp, 1, PWRAP_MSB_FIRST);
 445 +       }
 446 +
 447         /* Reset SPI slave */
 448         ret = pwrap_reset_spislave(wrp);
 449         if (ret)
 450 @@ -674,6 +903,9 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 451
 452         pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
 453
 454 +       if (pwrap_is_mt7623(wrp))
 455 +               pwrap_writel(wrp, 0xf, PWRAP_RDDMY);
 456 +
 457         ret = pwrap_init_reg_clock(wrp);
 458         if (ret)
 459                 return ret;
 460 @@ -684,7 +916,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 461                 return ret;
 462
 463         /* Enable dual IO mode */
 464 -       pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
 465 +       pwrap_dew_write(wrp, PWRAP_DEW_DIO_EN, 1);
 466
 467         /* Check IDLE & INIT_DONE in advance */
 468         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
 469 @@ -696,7 +928,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 470         pwrap_writel(wrp, 1, PWRAP_DIO_EN);
 471
 472         /* Read Test */
 473 -       pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
 474 +       pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
 475         if (rdata != PWRAP_DEW_READ_TEST_VAL) {
 476                 dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
 477                                 PWRAP_DEW_READ_TEST_VAL, rdata);
 478 @@ -709,12 +941,13 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 479                 return ret;
 480
 481         /* Signature checking - using CRC */
 482 -       if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
 483 +       if (pwrap_dew_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
 484                 return -EFAULT;
 485
 486         pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
 487         pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
 488 -       pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
 489 +       pwrap_writel(wrp, wrp->dew_base + wrp->dew_regs[PWRAP_DEW_CRC_VAL],
 490 +                    PWRAP_SIG_ADR);
 491         pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
 492
 493         if (pwrap_is_mt8135(wrp))
 494 @@ -728,7 +961,16 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 495         pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
 496         pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN);
 497         pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
 498 -       pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
 499 +//     pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
 500 +       pwrap_writel(wrp, ~(BIT(31) | BIT(2)), PWRAP_INT_EN);
 501 +
 502 +       if (pwrap_is_mt7623(wrp)) {
 503 +               pwrap_writel(wrp, PWRAP_MT7623_AUXADC_CON21, PWRAP_ADC_CMD_ADDR);
 504 +               pwrap_writel(wrp, 0x8000, PWRAP_ADC_CMD);
 505 +               pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC12, PWRAP_ADC_RDY_ADDR);
 506 +               pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC13, PWRAP_ADC_RDATA_ADDR1);
 507 +               pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC14, PWRAP_ADC_RDATA_ADDR2);
 508 +       }
 509
 510         if (pwrap_is_mt8135(wrp)) {
 511                 /* enable pwrap events and pwrap bridge in AP side */
 512 @@ -743,15 +985,15 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 513                 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
 514
 515                 /* enable PMIC event out and sources */
 516 -               if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
 517 -                               pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
 518 +               if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
 519 +                               pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
 520                         dev_err(wrp->dev, "enable dewrap fail\n");
 521                         return -EFAULT;
 522                 }
 523 -       } else {
 524 +       } else if (!pwrap_is_mt7623(wrp)) {
 525                 /* PMIC_DEWRAP enables */
 526 -               if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
 527 -                               pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
 528 +               if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
 529 +                               pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
 530                         dev_err(wrp->dev, "enable dewrap fail\n");
 531                         return -EFAULT;
 532                 }
 533 @@ -795,6 +1037,9 @@ static const struct regmap_config pwrap_regmap_config = {
 534
 535  static struct of_device_id of_pwrap_match_tbl[] = {
 536         {
 537 +               .compatible = "mediatek,mt7623-pwrap",
 538 +               .data = &pwrap_mt7623,
 539 +       }, {
 540                 .compatible = "mediatek,mt8135-pwrap",
 541                 .data = &pwrap_mt8135,
 542         }, {
 543 @@ -824,6 +1069,8 @@ static int pwrap_probe(struct platform_device *pdev)
 544
 545         type = of_id->data;
 546         wrp->regs = type->regs;
 547 +       wrp->dew_regs = type->dew_regs;
 548 +       wrp->dew_base = type->dew_base;
 549         wrp->type = type->type;
 550         wrp->arb_en_all = type->arb_en_all;
 551         wrp->dev = &pdev->dev;
 552 --
 553 1.7.10.4
 554