target/linux/mediatek/patches/0004-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8135.patch

   1 From 242572135fdb513cba0506415c7e26a0909eb4b5 Mon Sep 17 00:00:00 2001
   2 From: James Liao <jamesjj.liao@mediatek.com>
   3 Date: Thu, 23 Apr 2015 10:35:41 +0200
   4 Subject: [PATCH 04/76] clk: mediatek: Add basic clocks for Mediatek MT8135.
   5
   6 This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs,
   7 INFRA and PERI clocks.
   8
   9 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  10 Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
  11 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
  12 ---
  13  drivers/clk/mediatek/Makefile                      |    1 +
  14  drivers/clk/mediatek/clk-mt8135.c                  |  644 ++++++++++++++++++++
  15  include/dt-bindings/clock/mt8135-clk.h             |  194 ++++++
  16  .../dt-bindings/reset-controller/mt8135-resets.h   |   64 ++
  17  4 files changed, 903 insertions(+)
  18  create mode 100644 drivers/clk/mediatek/clk-mt8135.c
  19  create mode 100644 include/dt-bindings/clock/mt8135-clk.h
  20  create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h
  21
  22 --- a/drivers/clk/mediatek/Makefile
  23 +++ b/drivers/clk/mediatek/Makefile
  24 @@ -1,2 +1,3 @@
  25  obj-y += clk-mtk.o clk-pll.o clk-gate.o
  26  obj-$(CONFIG_RESET_CONTROLLER) += reset.o
  27 +obj-y += clk-mt8135.o
  28 --- /dev/null
  29 +++ b/drivers/clk/mediatek/clk-mt8135.c
  30 @@ -0,0 +1,644 @@
  31 +/*
  32 + * Copyright (c) 2014 MediaTek Inc.
  33 + * Author: James Liao <jamesjj.liao@mediatek.com>
  34 + *
  35 + * This program is free software; you can redistribute it and/or modify
  36 + * it under the terms of the GNU General Public License version 2 as
  37 + * published by the Free Software Foundation.
  38 + *
  39 + * This program is distributed in the hope that it will be useful,
  40 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  41 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  42 + * GNU General Public License for more details.
  43 + */
  44 +
  45 +#include <linux/of.h>
  46 +#include <linux/of_address.h>
  47 +#include <linux/slab.h>
  48 +#include <linux/mfd/syscon.h>
  49 +#include <dt-bindings/clock/mt8135-clk.h>
  50 +
  51 +#include "clk-mtk.h"
  52 +#include "clk-gate.h"
  53 +
  54 +static DEFINE_SPINLOCK(mt8135_clk_lock);
  55 +
  56 +static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
  57 +       FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
  58 +       FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
  59 +       FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
  60 +       FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
  61 +};
  62 +
  63 +static const struct mtk_fixed_factor top_divs[] __initconst = {
  64 +       FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
  65 +       FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
  66 +       FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
  67 +       FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
  68 +
  69 +       FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
  70 +       FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
  71 +       FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
  72 +       FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
  73 +       FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
  74 +
  75 +       FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
  76 +       FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
  77 +       FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
  78 +       FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
  79 +       FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
  80 +       FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
  81 +
  82 +       FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
  83 +       FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
  84 +       FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
  85 +       FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
  86 +       FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
  87 +       FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
  88 +       FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
  89 +       FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
  90 +
  91 +       FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
  92 +
  93 +       FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
  94 +       FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
  95 +
  96 +       FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
  97 +
  98 +       FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
  99 +       FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
 100 +       FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
 101 +       FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
 102 +       FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
 103 +
 104 +       FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
 105 +       FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
 106 +       FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
 107 +       FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
 108 +
 109 +       FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
 110 +       FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
 111 +       FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
 112 +       FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
 113 +       FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
 114 +
 115 +       FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
 116 +       FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
 117 +       FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
 118 +       FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
 119 +       FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
 120 +
 121 +       FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
 122 +       FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
 123 +       FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
 124 +
 125 +       FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
 126 +       FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
 127 +
 128 +       FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
 129 +
 130 +       FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
 131 +       FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
 132 +
 133 +       FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
 134 +       FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
 135 +
 136 +       FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
 137 +};
 138 +
 139 +static const char * const axi_parents[] __initconst = {
 140 +       "clk26m",
 141 +       "syspll_d3",
 142 +       "syspll_d4",
 143 +       "syspll_d6",
 144 +       "univpll_d5",
 145 +       "univpll2_d2",
 146 +       "syspll_d3p5"
 147 +};
 148 +
 149 +static const char * const smi_parents[] __initconst = {
 150 +       "clk26m",
 151 +       "clkph_mck",
 152 +       "syspll_d2p5",
 153 +       "syspll_d3",
 154 +       "syspll_d8",
 155 +       "univpll_d5",
 156 +       "univpll1_d2",
 157 +       "univpll1_d6",
 158 +       "mmpll_d3",
 159 +       "mmpll_d4",
 160 +       "mmpll_d5",
 161 +       "mmpll_d6",
 162 +       "mmpll_d7",
 163 +       "vdecpll",
 164 +       "lvdspll"
 165 +};
 166 +
 167 +static const char * const mfg_parents[] __initconst = {
 168 +       "clk26m",
 169 +       "univpll1_d4",
 170 +       "syspll_d2",
 171 +       "syspll_d2p5",
 172 +       "syspll_d3",
 173 +       "univpll_d5",
 174 +       "univpll1_d2",
 175 +       "mmpll_d2",
 176 +       "mmpll_d3",
 177 +       "mmpll_d4",
 178 +       "mmpll_d5",
 179 +       "mmpll_d6",
 180 +       "mmpll_d7"
 181 +};
 182 +
 183 +static const char * const irda_parents[] __initconst = {
 184 +       "clk26m",
 185 +       "univpll2_d8",
 186 +       "univpll1_d6"
 187 +};
 188 +
 189 +static const char * const cam_parents[] __initconst = {
 190 +       "clk26m",
 191 +       "syspll_d3",
 192 +       "syspll_d3p5",
 193 +       "syspll_d4",
 194 +       "univpll_d5",
 195 +       "univpll2_d2",
 196 +       "univpll_d7",
 197 +       "univpll1_d4"
 198 +};
 199 +
 200 +static const char * const aud_intbus_parents[] __initconst = {
 201 +       "clk26m",
 202 +       "syspll_d6",
 203 +       "univpll_d10"
 204 +};
 205 +
 206 +static const char * const jpg_parents[] __initconst = {
 207 +       "clk26m",
 208 +       "syspll_d5",
 209 +       "syspll_d4",
 210 +       "syspll_d3",
 211 +       "univpll_d7",
 212 +       "univpll2_d2",
 213 +       "univpll_d5"
 214 +};
 215 +
 216 +static const char * const disp_parents[] __initconst = {
 217 +       "clk26m",
 218 +       "syspll_d3p5",
 219 +       "syspll_d3",
 220 +       "univpll2_d2",
 221 +       "univpll_d5",
 222 +       "univpll1_d2",
 223 +       "lvdspll",
 224 +       "vdecpll"
 225 +};
 226 +
 227 +static const char * const msdc30_parents[] __initconst = {
 228 +       "clk26m",
 229 +       "syspll_d6",
 230 +       "syspll_d5",
 231 +       "univpll1_d4",
 232 +       "univpll2_d4",
 233 +       "msdcpll"
 234 +};
 235 +
 236 +static const char * const usb20_parents[] __initconst = {
 237 +       "clk26m",
 238 +       "univpll2_d6",
 239 +       "univpll1_d10"
 240 +};
 241 +
 242 +static const char * const venc_parents[] __initconst = {
 243 +       "clk26m",
 244 +       "syspll_d3",
 245 +       "syspll_d8",
 246 +       "univpll_d5",
 247 +       "univpll1_d6",
 248 +       "mmpll_d4",
 249 +       "mmpll_d5",
 250 +       "mmpll_d6"
 251 +};
 252 +
 253 +static const char * const spi_parents[] __initconst = {
 254 +       "clk26m",
 255 +       "syspll_d6",
 256 +       "syspll_d8",
 257 +       "syspll_d10",
 258 +       "univpll1_d6",
 259 +       "univpll1_d8"
 260 +};
 261 +
 262 +static const char * const uart_parents[] __initconst = {
 263 +       "clk26m",
 264 +       "univpll2_d8"
 265 +};
 266 +
 267 +static const char * const mem_parents[] __initconst = {
 268 +       "clk26m",
 269 +       "clkph_mck"
 270 +};
 271 +
 272 +static const char * const camtg_parents[] __initconst = {
 273 +       "clk26m",
 274 +       "univpll_d26",
 275 +       "univpll1_d6",
 276 +       "syspll_d16",
 277 +       "syspll_d8"
 278 +};
 279 +
 280 +static const char * const audio_parents[] __initconst = {
 281 +       "clk26m",
 282 +       "syspll_d24"
 283 +};
 284 +
 285 +static const char * const fix_parents[] __initconst = {
 286 +       "rtc32k",
 287 +       "clk26m",
 288 +       "univpll_d5",
 289 +       "univpll_d7",
 290 +       "univpll1_d2",
 291 +       "univpll1_d4",
 292 +       "univpll1_d6",
 293 +       "univpll1_d8"
 294 +};
 295 +
 296 +static const char * const vdec_parents[] __initconst = {
 297 +       "clk26m",
 298 +       "vdecpll",
 299 +       "clkph_mck",
 300 +       "syspll_d2p5",
 301 +       "syspll_d3",
 302 +       "syspll_d3p5",
 303 +       "syspll_d4",
 304 +       "syspll_d5",
 305 +       "syspll_d6",
 306 +       "syspll_d8",
 307 +       "univpll1_d2",
 308 +       "univpll2_d2",
 309 +       "univpll_d7",
 310 +       "univpll_d10",
 311 +       "univpll2_d4",
 312 +       "lvdspll"
 313 +};
 314 +
 315 +static const char * const ddrphycfg_parents[] __initconst = {
 316 +       "clk26m",
 317 +       "axi_sel",
 318 +       "syspll_d12"
 319 +};
 320 +
 321 +static const char * const dpilvds_parents[] __initconst = {
 322 +       "clk26m",
 323 +       "lvdspll",
 324 +       "lvdspll_d2",
 325 +       "lvdspll_d4",
 326 +       "lvdspll_d8"
 327 +};
 328 +
 329 +static const char * const pmicspi_parents[] __initconst = {
 330 +       "clk26m",
 331 +       "univpll2_d6",
 332 +       "syspll_d8",
 333 +       "syspll_d10",
 334 +       "univpll1_d10",
 335 +       "mempll_mck_d4",
 336 +       "univpll_d26",
 337 +       "syspll_d24"
 338 +};
 339 +
 340 +static const char * const smi_mfg_as_parents[] __initconst = {
 341 +       "clk26m",
 342 +       "smi_sel",
 343 +       "mfg_sel",
 344 +       "mem_sel"
 345 +};
 346 +
 347 +static const char * const gcpu_parents[] __initconst = {
 348 +       "clk26m",
 349 +       "syspll_d4",
 350 +       "univpll_d7",
 351 +       "syspll_d5",
 352 +       "syspll_d6"
 353 +};
 354 +
 355 +static const char * const dpi1_parents[] __initconst = {
 356 +       "clk26m",
 357 +       "tvhdmi_h_ck",
 358 +       "tvhdmi_d2",
 359 +       "tvhdmi_d4"
 360 +};
 361 +
 362 +static const char * const cci_parents[] __initconst = {
 363 +       "clk26m",
 364 +       "mainpll_537p3m",
 365 +       "univpll_d3",
 366 +       "syspll_d2p5",
 367 +       "syspll_d3",
 368 +       "syspll_d5"
 369 +};
 370 +
 371 +static const char * const apll_parents[] __initconst = {
 372 +       "clk26m",
 373 +       "apll_ck",
 374 +       "apll_d4",
 375 +       "apll_d8",
 376 +       "apll_d16",
 377 +       "apll_d24"
 378 +};
 379 +
 380 +static const char * const hdmipll_parents[] __initconst = {
 381 +       "clk26m",
 382 +       "hdmitx_clkdig_cts",
 383 +       "hdmitx_clkdig_d2",
 384 +       "hdmitx_clkdig_d3"
 385 +};
 386 +
 387 +static const struct mtk_composite top_muxes[] __initconst = {
 388 +       /* CLK_CFG_0 */
 389 +       MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 390 +               0x0140, 0, 3, INVALID_MUX_GATE_BIT),
 391 +       MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
 392 +       MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
 393 +       MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
 394 +       /* CLK_CFG_1 */
 395 +       MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
 396 +       MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
 397 +               0x0144, 8, 2, 15),
 398 +       MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
 399 +       MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
 400 +       /* CLK_CFG_2 */
 401 +       MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
 402 +       MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
 403 +       MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
 404 +       MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
 405 +       /* CLK_CFG_3 */
 406 +       MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
 407 +       /* CLK_CFG_4 */
 408 +       MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
 409 +       MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
 410 +       MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
 411 +       /* CLK_CFG_6 */
 412 +       MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
 413 +       MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
 414 +       MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
 415 +       /* CLK_CFG_7 */
 416 +       MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
 417 +       MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
 418 +       MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
 419 +               0x015c, 16, 2, 23),
 420 +       MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
 421 +       /* CLK_CFG_8 */
 422 +       MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
 423 +       MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
 424 +       MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
 425 +               0x0164, 16, 2, 23),
 426 +       MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
 427 +       /* CLK_CFG_9 */
 428 +       MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
 429 +       MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
 430 +       MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
 431 +       MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
 432 +};
 433 +
 434 +static const struct mtk_gate_regs infra_cg_regs = {
 435 +       .set_ofs = 0x0040,
 436 +       .clr_ofs = 0x0044,
 437 +       .sta_ofs = 0x0048,
 438 +};
 439 +
 440 +#define GATE_ICG(_id, _name, _parent, _shift) {        \
 441 +               .id = _id,                                      \
 442 +               .name = _name,                                  \
 443 +               .parent_name = _parent,                         \
 444 +               .regs = &infra_cg_regs,                         \
 445 +               .shift = _shift,                                \
 446 +               .ops = &mtk_clk_gate_ops_setclr,                \
 447 +       }
 448 +
 449 +static const struct mtk_gate infra_clks[] __initconst = {
 450 +       GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
 451 +       GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
 452 +       GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
 453 +       GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
 454 +       GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
 455 +       GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
 456 +       GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
 457 +       GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
 458 +       GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
 459 +       GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
 460 +       GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
 461 +       GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
 462 +       GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
 463 +};
 464 +
 465 +static const struct mtk_gate_regs peri0_cg_regs = {
 466 +       .set_ofs = 0x0008,
 467 +       .clr_ofs = 0x0010,
 468 +       .sta_ofs = 0x0018,
 469 +};
 470 +
 471 +static const struct mtk_gate_regs peri1_cg_regs = {
 472 +       .set_ofs = 0x000c,
 473 +       .clr_ofs = 0x0014,
 474 +       .sta_ofs = 0x001c,
 475 +};
 476 +
 477 +#define GATE_PERI0(_id, _name, _parent, _shift) {      \
 478 +               .id = _id,                                      \
 479 +               .name = _name,                                  \
 480 +               .parent_name = _parent,                         \
 481 +               .regs = &peri0_cg_regs,                         \
 482 +               .shift = _shift,                                \
 483 +               .ops = &mtk_clk_gate_ops_setclr,                \
 484 +       }
 485 +
 486 +#define GATE_PERI1(_id, _name, _parent, _shift) {      \
 487 +               .id = _id,                                      \
 488 +               .name = _name,                                  \
 489 +               .parent_name = _parent,                         \
 490 +               .regs = &peri1_cg_regs,                         \
 491 +               .shift = _shift,                                \
 492 +               .ops = &mtk_clk_gate_ops_setclr,                \
 493 +       }
 494 +
 495 +static const struct mtk_gate peri_gates[] __initconst = {
 496 +       /* PERI0 */
 497 +       GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
 498 +       GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
 499 +       GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
 500 +       GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
 501 +       GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
 502 +       GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
 503 +       GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
 504 +       GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
 505 +       GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
 506 +       GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
 507 +       GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
 508 +       GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
 509 +       GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
 510 +       GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
 511 +       GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
 512 +       GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
 513 +       GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
 514 +       GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
 515 +       GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
 516 +       GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
 517 +       GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
 518 +       GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
 519 +       GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
 520 +       GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
 521 +       GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
 522 +       GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
 523 +       GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
 524 +       GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
 525 +       GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
 526 +       GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
 527 +       GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
 528 +       GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
 529 +       /* PERI1 */
 530 +       GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
 531 +       GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
 532 +       GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
 533 +       GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
 534 +       GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
 535 +       GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
 536 +       GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
 537 +       GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
 538 +       GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
 539 +};
 540 +
 541 +static const char * const uart_ck_sel_parents[] __initconst = {
 542 +       "clk26m",
 543 +       "uart_sel",
 544 +};
 545 +
 546 +static const struct mtk_composite peri_clks[] __initconst = {
 547 +       MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
 548 +       MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
 549 +       MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
 550 +       MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 551 +};
 552 +
 553 +static void __init mtk_topckgen_init(struct device_node *node)
 554 +{
 555 +       struct clk_onecell_data *clk_data;
 556 +       void __iomem *base;
 557 +       int r;
 558 +
 559 +       base = of_iomap(node, 0);
 560 +       if (!base) {
 561 +               pr_err("%s(): ioremap failed\n", __func__);
 562 +               return;
 563 +       }
 564 +
 565 +       clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
 566 +
 567 +       mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
 568 +       mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
 569 +       mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
 570 +                       &mt8135_clk_lock, clk_data);
 571 +
 572 +       clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
 573 +
 574 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 575 +       if (r)
 576 +               pr_err("%s(): could not register clock provider: %d\n",
 577 +                       __func__, r);
 578 +}
 579 +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
 580 +
 581 +static void __init mtk_infrasys_init(struct device_node *node)
 582 +{
 583 +       struct clk_onecell_data *clk_data;
 584 +       int r;
 585 +
 586 +       clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
 587 +
 588 +       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 589 +                                               clk_data);
 590 +
 591 +       clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
 592 +
 593 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 594 +       if (r)
 595 +               pr_err("%s(): could not register clock provider: %d\n",
 596 +                       __func__, r);
 597 +
 598 +       mtk_register_reset_controller(node, 2, 0x30);
 599 +}
 600 +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 601 +
 602 +static void __init mtk_pericfg_init(struct device_node *node)
 603 +{
 604 +       struct clk_onecell_data *clk_data;
 605 +       int r;
 606 +       void __iomem *base;
 607 +
 608 +       base = of_iomap(node, 0);
 609 +       if (!base) {
 610 +               pr_err("%s(): ioremap failed\n", __func__);
 611 +               return;
 612 +       }
 613 +
 614 +       clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
 615 +
 616 +       mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
 617 +                                               clk_data);
 618 +       mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
 619 +                       &mt8135_clk_lock, clk_data);
 620 +
 621 +       r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 622 +       if (r)
 623 +               pr_err("%s(): could not register clock provider: %d\n",
 624 +                       __func__, r);
 625 +
 626 +       mtk_register_reset_controller(node, 2, 0);
 627 +}
 628 +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 629 +
 630 +#define MT8135_PLL_FMAX                (2000 * MHZ)
 631 +#define CON0_MT8135_RST_BAR    BIT(27)
 632 +
 633 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
 634 +               .id = _id,                                              \
 635 +               .name = _name,                                          \
 636 +               .reg = _reg,                                            \
 637 +               .pwr_reg = _pwr_reg,                                    \
 638 +               .en_mask = _en_mask,                                    \
 639 +               .flags = _flags,                                        \
 640 +               .rst_bar_mask = CON0_MT8135_RST_BAR,                    \
 641 +               .fmax = MT8135_PLL_FMAX,                                \
 642 +               .pcwbits = _pcwbits,                                    \
 643 +               .pd_reg = _pd_reg,                                      \
 644 +               .pd_shift = _pd_shift,                                  \
 645 +               .tuner_reg = _tuner_reg,                                \
 646 +               .pcw_reg = _pcw_reg,                                    \
 647 +               .pcw_shift = _pcw_shift,                                \
 648 +       }
 649 +
 650 +static const struct mtk_pll_data plls[] = {
 651 +       PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
 652 +       PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
 653 +       PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
 654 +       PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
 655 +       PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
 656 +       PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
 657 +       PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
 658 +       PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8,       0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
 659 +       PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
 660 +       PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c,       0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
 661 +};
 662 +
 663 +static void __init mtk_apmixedsys_init(struct device_node *node)
 664 +{
 665 +       struct clk_onecell_data *clk_data;
 666 +
 667 +       clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
 668 +       if (!clk_data)
 669 +               return;
 670 +
 671 +       mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 672 +}
 673 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
 674 +               mtk_apmixedsys_init);
 675 --- /dev/null
 676 +++ b/include/dt-bindings/clock/mt8135-clk.h
 677 @@ -0,0 +1,194 @@
 678 +/*
 679 + * Copyright (c) 2014 MediaTek Inc.
 680 + * Author: James Liao <jamesjj.liao@mediatek.com>
 681 + *
 682 + * This program is free software; you can redistribute it and/or modify
 683 + * it under the terms of the GNU General Public License version 2 as
 684 + * published by the Free Software Foundation.
 685 + *
 686 + * This program is distributed in the hope that it will be useful,
 687 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 688 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 689 + * GNU General Public License for more details.
 690 + */
 691 +
 692 +#ifndef _DT_BINDINGS_CLK_MT8135_H
 693 +#define _DT_BINDINGS_CLK_MT8135_H
 694 +
 695 +/* TOPCKGEN */
 696 +
 697 +#define CLK_TOP_DSI0_LNTC_DSICLK       1
 698 +#define CLK_TOP_HDMITX_CLKDIG_CTS      2
 699 +#define CLK_TOP_CLKPH_MCK              3
 700 +#define CLK_TOP_CPUM_TCK_IN            4
 701 +#define CLK_TOP_MAINPLL_806M           5
 702 +#define CLK_TOP_MAINPLL_537P3M         6
 703 +#define CLK_TOP_MAINPLL_322P4M         7
 704 +#define CLK_TOP_MAINPLL_230P3M         8
 705 +#define CLK_TOP_UNIVPLL_624M           9
 706 +#define CLK_TOP_UNIVPLL_416M           10
 707 +#define CLK_TOP_UNIVPLL_249P6M         11
 708 +#define CLK_TOP_UNIVPLL_178P3M         12
 709 +#define CLK_TOP_UNIVPLL_48M            13
 710 +#define CLK_TOP_MMPLL_D2               14
 711 +#define CLK_TOP_MMPLL_D3               15
 712 +#define CLK_TOP_MMPLL_D5               16
 713 +#define CLK_TOP_MMPLL_D7               17
 714 +#define CLK_TOP_MMPLL_D4               18
 715 +#define CLK_TOP_MMPLL_D6               19
 716 +#define CLK_TOP_SYSPLL_D2              20
 717 +#define CLK_TOP_SYSPLL_D4              21
 718 +#define CLK_TOP_SYSPLL_D6              22
 719 +#define CLK_TOP_SYSPLL_D8              23
 720 +#define CLK_TOP_SYSPLL_D10             24
 721 +#define CLK_TOP_SYSPLL_D12             25
 722 +#define CLK_TOP_SYSPLL_D16             26
 723 +#define CLK_TOP_SYSPLL_D24             27
 724 +#define CLK_TOP_SYSPLL_D3              28
 725 +#define CLK_TOP_SYSPLL_D2P5            29
 726 +#define CLK_TOP_SYSPLL_D5              30
 727 +#define CLK_TOP_SYSPLL_D3P5            31
 728 +#define CLK_TOP_UNIVPLL1_D2            32
 729 +#define CLK_TOP_UNIVPLL1_D4            33
 730 +#define CLK_TOP_UNIVPLL1_D6            34
 731 +#define CLK_TOP_UNIVPLL1_D8            35
 732 +#define CLK_TOP_UNIVPLL1_D10           36
 733 +#define CLK_TOP_UNIVPLL2_D2            37
 734 +#define CLK_TOP_UNIVPLL2_D4            38
 735 +#define CLK_TOP_UNIVPLL2_D6            39
 736 +#define CLK_TOP_UNIVPLL2_D8            40
 737 +#define CLK_TOP_UNIVPLL_D3             41
 738 +#define CLK_TOP_UNIVPLL_D5             42
 739 +#define CLK_TOP_UNIVPLL_D7             43
 740 +#define CLK_TOP_UNIVPLL_D10            44
 741 +#define CLK_TOP_UNIVPLL_D26            45
 742 +#define CLK_TOP_APLL                   46
 743 +#define CLK_TOP_APLL_D4                        47
 744 +#define CLK_TOP_APLL_D8                        48
 745 +#define CLK_TOP_APLL_D16               49
 746 +#define CLK_TOP_APLL_D24               50
 747 +#define CLK_TOP_LVDSPLL_D2             51
 748 +#define CLK_TOP_LVDSPLL_D4             52
 749 +#define CLK_TOP_LVDSPLL_D8             53
 750 +#define CLK_TOP_LVDSTX_CLKDIG_CT       54
 751 +#define CLK_TOP_VPLL_DPIX              55
 752 +#define CLK_TOP_TVHDMI_H               56
 753 +#define CLK_TOP_HDMITX_CLKDIG_D2       57
 754 +#define CLK_TOP_HDMITX_CLKDIG_D3       58
 755 +#define CLK_TOP_TVHDMI_D2              59
 756 +#define CLK_TOP_TVHDMI_D4              60
 757 +#define CLK_TOP_MEMPLL_MCK_D4          61
 758 +#define CLK_TOP_AXI_SEL                        62
 759 +#define CLK_TOP_SMI_SEL                        63
 760 +#define CLK_TOP_MFG_SEL                        64
 761 +#define CLK_TOP_IRDA_SEL               65
 762 +#define CLK_TOP_CAM_SEL                        66
 763 +#define CLK_TOP_AUD_INTBUS_SEL         67
 764 +#define CLK_TOP_JPG_SEL                        68
 765 +#define CLK_TOP_DISP_SEL               69
 766 +#define CLK_TOP_MSDC30_1_SEL           70
 767 +#define CLK_TOP_MSDC30_2_SEL           71
 768 +#define CLK_TOP_MSDC30_3_SEL           72
 769 +#define CLK_TOP_MSDC30_4_SEL           73
 770 +#define CLK_TOP_USB20_SEL              74
 771 +#define CLK_TOP_VENC_SEL               75
 772 +#define CLK_TOP_SPI_SEL                        76
 773 +#define CLK_TOP_UART_SEL               77
 774 +#define CLK_TOP_MEM_SEL                        78
 775 +#define CLK_TOP_CAMTG_SEL              79
 776 +#define CLK_TOP_AUDIO_SEL              80
 777 +#define CLK_TOP_FIX_SEL                        81
 778 +#define CLK_TOP_VDEC_SEL               82
 779 +#define CLK_TOP_DDRPHYCFG_SEL          83
 780 +#define CLK_TOP_DPILVDS_SEL            84
 781 +#define CLK_TOP_PMICSPI_SEL            85
 782 +#define CLK_TOP_MSDC30_0_SEL           86
 783 +#define CLK_TOP_SMI_MFG_AS_SEL         87
 784 +#define CLK_TOP_GCPU_SEL               88
 785 +#define CLK_TOP_DPI1_SEL               89
 786 +#define CLK_TOP_CCI_SEL                        90
 787 +#define CLK_TOP_APLL_SEL               91
 788 +#define CLK_TOP_HDMIPLL_SEL            92
 789 +#define CLK_TOP_NR_CLK                 93
 790 +
 791 +/* APMIXED_SYS */
 792 +
 793 +#define CLK_APMIXED_ARMPLL1            1
 794 +#define CLK_APMIXED_ARMPLL2            2
 795 +#define CLK_APMIXED_MAINPLL            3
 796 +#define CLK_APMIXED_UNIVPLL            4
 797 +#define CLK_APMIXED_MMPLL              5
 798 +#define CLK_APMIXED_MSDCPLL            6
 799 +#define CLK_APMIXED_TVDPLL             7
 800 +#define CLK_APMIXED_LVDSPLL            8
 801 +#define CLK_APMIXED_AUDPLL             9
 802 +#define CLK_APMIXED_VDECPLL            10
 803 +#define CLK_APMIXED_NR_CLK             11
 804 +
 805 +/* INFRA_SYS */
 806 +
 807 +#define CLK_INFRA_PMIC_WRAP            1
 808 +#define CLK_INFRA_PMICSPI              2
 809 +#define CLK_INFRA_CCIF1_AP_CTRL                3
 810 +#define CLK_INFRA_CCIF0_AP_CTRL                4
 811 +#define CLK_INFRA_KP                   5
 812 +#define CLK_INFRA_CPUM                 6
 813 +#define CLK_INFRA_M4U                  7
 814 +#define CLK_INFRA_MFGAXI               8
 815 +#define CLK_INFRA_DEVAPC               9
 816 +#define CLK_INFRA_AUDIO                        10
 817 +#define CLK_INFRA_MFG_BUS              11
 818 +#define CLK_INFRA_SMI                  12
 819 +#define CLK_INFRA_DBGCLK               13
 820 +#define CLK_INFRA_NR_CLK               14
 821 +
 822 +/* PERI_SYS */
 823 +
 824 +#define CLK_PERI_I2C5                  1
 825 +#define CLK_PERI_I2C4                  2
 826 +#define CLK_PERI_I2C3                  3
 827 +#define CLK_PERI_I2C2                  4
 828 +#define CLK_PERI_I2C1                  5
 829 +#define CLK_PERI_I2C0                  6
 830 +#define CLK_PERI_UART3                 7
 831 +#define CLK_PERI_UART2                 8
 832 +#define CLK_PERI_UART1                 9
 833 +#define CLK_PERI_UART0                 10
 834 +#define CLK_PERI_IRDA                  11
 835 +#define CLK_PERI_NLI                   12
 836 +#define CLK_PERI_MD_HIF                        13
 837 +#define CLK_PERI_AP_HIF                        14
 838 +#define CLK_PERI_MSDC30_3              15
 839 +#define CLK_PERI_MSDC30_2              16
 840 +#define CLK_PERI_MSDC30_1              17
 841 +#define CLK_PERI_MSDC20_2              18
 842 +#define CLK_PERI_MSDC20_1              19
 843 +#define CLK_PERI_AP_DMA                        20
 844 +#define CLK_PERI_USB1                  21
 845 +#define CLK_PERI_USB0                  22
 846 +#define CLK_PERI_PWM                   23
 847 +#define CLK_PERI_PWM7                  24
 848 +#define CLK_PERI_PWM6                  25
 849 +#define CLK_PERI_PWM5                  26
 850 +#define CLK_PERI_PWM4                  27
 851 +#define CLK_PERI_PWM3                  28
 852 +#define CLK_PERI_PWM2                  29
 853 +#define CLK_PERI_PWM1                  30
 854 +#define CLK_PERI_THERM                 31
 855 +#define CLK_PERI_NFI                   32
 856 +#define CLK_PERI_USBSLV                        33
 857 +#define CLK_PERI_USB1_MCU              34
 858 +#define CLK_PERI_USB0_MCU              35
 859 +#define CLK_PERI_GCPU                  36
 860 +#define CLK_PERI_FHCTL                 37
 861 +#define CLK_PERI_SPI1                  38
 862 +#define CLK_PERI_AUXADC                        39
 863 +#define CLK_PERI_PERI_PWRAP            40
 864 +#define CLK_PERI_I2C6                  41
 865 +#define CLK_PERI_UART0_SEL             42
 866 +#define CLK_PERI_UART1_SEL             43
 867 +#define CLK_PERI_UART2_SEL             44
 868 +#define CLK_PERI_UART3_SEL             45
 869 +#define CLK_PERI_NR_CLK                        46
 870 +
 871 +#endif /* _DT_BINDINGS_CLK_MT8135_H */
 872 --- /dev/null
 873 +++ b/include/dt-bindings/reset-controller/mt8135-resets.h
 874 @@ -0,0 +1,64 @@
 875 +/*
 876 + * Copyright (c) 2014 MediaTek Inc.
 877 + * Author: Flora Fu, MediaTek
 878 + *
 879 + * This program is free software; you can redistribute it and/or modify
 880 + * it under the terms of the GNU General Public License version 2 as
 881 + * published by the Free Software Foundation.
 882 + *
 883 + * This program is distributed in the hope that it will be useful,
 884 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 885 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 886 + * GNU General Public License for more details.
 887 + */
 888 +
 889 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
 890 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8135
 891 +
 892 +/* INFRACFG resets */
 893 +#define MT8135_INFRA_EMI_REG_RST        0
 894 +#define MT8135_INFRA_DRAMC0_A0_RST      1
 895 +#define MT8135_INFRA_CCIF0_RST          2
 896 +#define MT8135_INFRA_APCIRQ_EINT_RST    3
 897 +#define MT8135_INFRA_APXGPT_RST         4
 898 +#define MT8135_INFRA_SCPSYS_RST         5
 899 +#define MT8135_INFRA_CCIF1_RST          6
 900 +#define MT8135_INFRA_PMIC_WRAP_RST      7
 901 +#define MT8135_INFRA_KP_RST             8
 902 +#define MT8135_INFRA_EMI_RST            32
 903 +#define MT8135_INFRA_DRAMC0_RST         34
 904 +#define MT8135_INFRA_SMI_RST            35
 905 +#define MT8135_INFRA_M4U_RST            36
 906 +
 907 +/*  PERICFG resets */
 908 +#define MT8135_PERI_UART0_SW_RST        0
 909 +#define MT8135_PERI_UART1_SW_RST        1
 910 +#define MT8135_PERI_UART2_SW_RST        2
 911 +#define MT8135_PERI_UART3_SW_RST        3
 912 +#define MT8135_PERI_IRDA_SW_RST         4
 913 +#define MT8135_PERI_PTP_SW_RST          5
 914 +#define MT8135_PERI_AP_HIF_SW_RST       6
 915 +#define MT8135_PERI_GPCU_SW_RST         7
 916 +#define MT8135_PERI_MD_HIF_SW_RST       8
 917 +#define MT8135_PERI_NLI_SW_RST          9
 918 +#define MT8135_PERI_AUXADC_SW_RST       10
 919 +#define MT8135_PERI_DMA_SW_RST          11
 920 +#define MT8135_PERI_NFI_SW_RST          14
 921 +#define MT8135_PERI_PWM_SW_RST          15
 922 +#define MT8135_PERI_THERM_SW_RST        16
 923 +#define MT8135_PERI_MSDC0_SW_RST        17
 924 +#define MT8135_PERI_MSDC1_SW_RST        18
 925 +#define MT8135_PERI_MSDC2_SW_RST        19
 926 +#define MT8135_PERI_MSDC3_SW_RST        20
 927 +#define MT8135_PERI_I2C0_SW_RST         22
 928 +#define MT8135_PERI_I2C1_SW_RST         23
 929 +#define MT8135_PERI_I2C2_SW_RST         24
 930 +#define MT8135_PERI_I2C3_SW_RST         25
 931 +#define MT8135_PERI_I2C4_SW_RST         26
 932 +#define MT8135_PERI_I2C5_SW_RST         27
 933 +#define MT8135_PERI_I2C6_SW_RST         28
 934 +#define MT8135_PERI_USB_SW_RST          29
 935 +#define MT8135_PERI_SPI1_SW_RST         33
 936 +#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
 937 +
 938 +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */