target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch

   1 From a4df3e7e4e906a4e9dac1f8c43f6192f22ef6242 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 5 Jan 2016 12:16:17 +0100
   4 Subject: [PATCH 23/78] ARM: dts: mediatek: add MT7623 basic support
   5
   6 This adds basic chip support for Mediatek MT7623.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/arm/boot/dts/Makefile        |    1 +
  11  arch/arm/boot/dts/mt7623-evb.dts  |  459 +++++++++++++++++++++++++++++++++
  12  arch/arm/boot/dts/mt7623.dtsi     |  510 +++++++++++++++++++++++++++++++++++++
  13  arch/arm/mach-mediatek/Kconfig    |    4 +
  14  arch/arm/mach-mediatek/mediatek.c |    1 +
  15  5 files changed, 975 insertions(+)
  16  create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
  17  create mode 100644 arch/arm/boot/dts/mt7623.dtsi
  18
  19 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
  20 index 30bbc37..2bce370 100644
  21 --- a/arch/arm/boot/dts/Makefile
  22 +++ b/arch/arm/boot/dts/Makefile
  23 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  24         mt6580-evbp1.dtb \
  25         mt6589-aquaris5.dtb \
  26         mt6592-evb.dtb \
  27 +       mt7623-evb.dtb \
  28         mt8127-moose.dtb \
  29         mt8135-evbp1.dtb
  30  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
  31 diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
  32 new file mode 100644
  33 index 0000000..5e9381d
  34 --- /dev/null
  35 +++ b/arch/arm/boot/dts/mt7623-evb.dts
  36 @@ -0,0 +1,459 @@
  37 +/*
  38 + * Copyright (c) 2016 MediaTek Inc.
  39 + * Author: John Crispin <blogic@openwrt.org>
  40 + *
  41 + * This program is free software; you can redistribute it and/or modify
  42 + * it under the terms of the GNU General Public License version 2 as
  43 + * published by the Free Software Foundation.
  44 + *
  45 + * This program is distributed in the hope that it will be useful,
  46 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  47 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  48 + * GNU General Public License for more details.
  49 + */
  50 +
  51 +/dts-v1/;
  52 +
  53 +#include "mt7623.dtsi"
  54 +#include <dt-bindings/gpio/gpio.h>
  55 +
  56 +/ {
  57 +       model = "MediaTek MT7623 evaluation board";
  58 +       compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
  59 +
  60 +       chosen {
  61 +               stdout-path = &uart2;
  62 +       };
  63 +
  64 +       memory {
  65 +               reg = <0 0x80000000 0 0x20000000>;
  66 +       };
  67 +
  68 +       usb_p1_vbus: regulator@0 {
  69 +               compatible = "regulator-fixed";
  70 +               regulator-name = "usb_vbus";
  71 +               regulator-min-microvolt = <5000000>;
  72 +               regulator-max-microvolt = <5000000>;
  73 +               gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
  74 +               enable-active-high;
  75 +       };
  76 +};
  77 +
  78 +&pwrap {
  79 +       pmic: mt6323 {
  80 +               compatible = "mediatek,mt6323";
  81 +               interrupt-parent = <&pio>;
  82 +               interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
  83 +               interrupt-controller;
  84 +               #interrupt-cells = <2>;
  85 +
  86 +               mt6323regulator: mt6323regulator{
  87 +                       compatible = "mediatek,mt6323-regulator";
  88 +
  89 +                       mt6323_vproc_reg: buck_vproc{
  90 +                               regulator-name = "vproc";
  91 +                               regulator-min-microvolt = < 700000>;
  92 +                               regulator-max-microvolt = <1350000>;
  93 +                               regulator-ramp-delay = <12500>;
  94 +                               regulator-always-on;
  95 +                               regulator-boot-on;
  96 +                       };
  97 +
  98 +                       mt6323_vsys_reg: buck_vsys{
  99 +                               regulator-name = "vsys";
 100 +                               regulator-min-microvolt = <1400000>;
 101 +                               regulator-max-microvolt = <2987500>;
 102 +                               regulator-ramp-delay = <25000>;
 103 +                               regulator-always-on;
 104 +                               regulator-boot-on;
 105 +                       };
 106 +
 107 +                       mt6323_vpa_reg: buck_vpa{
 108 +                               regulator-name = "vpa";
 109 +                               regulator-min-microvolt = < 500000>;
 110 +                               regulator-max-microvolt = <3650000>;
 111 +                       };
 112 +
 113 +                       mt6323_vtcxo_reg: ldo_vtcxo{
 114 +                               regulator-name = "vtcxo";
 115 +                               regulator-min-microvolt = <2800000>;
 116 +                               regulator-max-microvolt = <2800000>;
 117 +                               regulator-enable-ramp-delay = <90>;
 118 +                               regulator-always-on;
 119 +                               regulator-boot-on;
 120 +                       };
 121 +
 122 +                       mt6323_vcn28_reg: ldo_vcn28{
 123 +                               regulator-name = "vcn28";
 124 +                               regulator-min-microvolt = <2800000>;
 125 +                               regulator-max-microvolt = <2800000>;
 126 +                               regulator-enable-ramp-delay = <185>;
 127 +                       };
 128 +
 129 +                       mt6323_vcn33_bt_reg: ldo_vcn33_bt{
 130 +                               regulator-name = "vcn33_bt";
 131 +                               regulator-min-microvolt = <3300000>;
 132 +                               regulator-max-microvolt = <3600000>;
 133 +                               regulator-enable-ramp-delay = <185>;
 134 +                       };
 135 +
 136 +                       mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
 137 +                               regulator-name = "vcn33_wifi";
 138 +                               regulator-min-microvolt = <3300000>;
 139 +                               regulator-max-microvolt = <3600000>;
 140 +                               regulator-enable-ramp-delay = <185>;
 141 +                       };
 142 +
 143 +                       mt6323_va_reg: ldo_va{
 144 +                               regulator-name = "va";
 145 +                               regulator-min-microvolt = <2800000>;
 146 +                               regulator-max-microvolt = <2800000>;
 147 +                               regulator-enable-ramp-delay = <216>;
 148 +                               regulator-always-on;
 149 +                               regulator-boot-on;
 150 +                       };
 151 +
 152 +                       mt6323_vcama_reg: ldo_vcama{
 153 +                               regulator-name = "vcama";
 154 +                               regulator-min-microvolt = <1500000>;
 155 +                               regulator-max-microvolt = <2800000>;
 156 +                               regulator-enable-ramp-delay = <216>;
 157 +                       };
 158 +
 159 +                       mt6323_vio28_reg: ldo_vio28{
 160 +                               regulator-name = "vio28";
 161 +                               regulator-min-microvolt = <2800000>;
 162 +                               regulator-max-microvolt = <2800000>;
 163 +                               regulator-enable-ramp-delay = <216>;
 164 +                               regulator-always-on;
 165 +                               regulator-boot-on;
 166 +                       };
 167 +
 168 +                       mt6323_vusb_reg: ldo_vusb{
 169 +                               regulator-name = "vusb";
 170 +                               regulator-min-microvolt = <3300000>;
 171 +                               regulator-max-microvolt = <3300000>;
 172 +                               regulator-enable-ramp-delay = <216>;
 173 +                               regulator-boot-on;
 174 +                       };
 175 +
 176 +                       mt6323_vmc_reg: ldo_vmc{
 177 +                               regulator-name = "vmc";
 178 +                               regulator-min-microvolt = <1800000>;
 179 +                               regulator-max-microvolt = <3300000>;
 180 +                               regulator-enable-ramp-delay = <36>;
 181 +                               regulator-boot-on;
 182 +                       };
 183 +
 184 +                       mt6323_vmch_reg: ldo_vmch{
 185 +                               regulator-name = "vmch";
 186 +                               regulator-min-microvolt = <3000000>;
 187 +                               regulator-max-microvolt = <3300000>;
 188 +                               regulator-enable-ramp-delay = <36>;
 189 +                               regulator-boot-on;
 190 +                       };
 191 +
 192 +                       mt6323_vemc3v3_reg: ldo_vemc3v3{
 193 +                               regulator-name = "vemc3v3";
 194 +                               regulator-min-microvolt = <3000000>;
 195 +                               regulator-max-microvolt = <3300000>;
 196 +                               regulator-enable-ramp-delay = <36>;
 197 +                               regulator-boot-on;
 198 +                       };
 199 +
 200 +                       mt6323_vgp1_reg: ldo_vgp1{
 201 +                               regulator-name = "vgp1";
 202 +                               regulator-min-microvolt = <1200000>;
 203 +                               regulator-max-microvolt = <3300000>;
 204 +                               regulator-enable-ramp-delay = <216>;
 205 +                       };
 206 +
 207 +                       mt6323_vgp2_reg: ldo_vgp2{
 208 +                               regulator-name = "vgp2";
 209 +                               regulator-min-microvolt = <1200000>;
 210 +                               regulator-max-microvolt = <3000000>;
 211 +                               regulator-enable-ramp-delay = <216>;
 212 +                       };
 213 +
 214 +                       mt6323_vgp3_reg: ldo_vgp3{
 215 +                               regulator-name = "vgp3";
 216 +                               regulator-min-microvolt = <1200000>;
 217 +                               regulator-max-microvolt = <1800000>;
 218 +                               regulator-enable-ramp-delay = <216>;
 219 +                       };
 220 +
 221 +                       mt6323_vcn18_reg: ldo_vcn18{
 222 +                               regulator-name = "vcn18";
 223 +                               regulator-min-microvolt = <1800000>;
 224 +                               regulator-max-microvolt = <1800000>;
 225 +                               regulator-enable-ramp-delay = <216>;
 226 +                       };
 227 +
 228 +                       mt6323_vsim1_reg: ldo_vsim1{
 229 +                               regulator-name = "vsim1";
 230 +                               regulator-min-microvolt = <1800000>;
 231 +                               regulator-max-microvolt = <3000000>;
 232 +                               regulator-enable-ramp-delay = <216>;
 233 +                       };
 234 +
 235 +                       mt6323_vsim2_reg: ldo_vsim2{
 236 +                               regulator-name = "vsim2";
 237 +                               regulator-min-microvolt = <1800000>;
 238 +                               regulator-max-microvolt = <3000000>;
 239 +                               regulator-enable-ramp-delay = <216>;
 240 +                       };
 241 +
 242 +                       mt6323_vrtc_reg: ldo_vrtc{
 243 +                               regulator-name = "vrtc";
 244 +                               regulator-min-microvolt = <2800000>;
 245 +                               regulator-max-microvolt = <2800000>;
 246 +                               regulator-always-on;
 247 +                               regulator-boot-on;
 248 +                       };
 249 +
 250 +                       mt6323_vcamaf_reg: ldo_vcamaf{
 251 +                               regulator-name = "vcamaf";
 252 +                               regulator-min-microvolt = <1200000>;
 253 +                               regulator-max-microvolt = <3300000>;
 254 +                               regulator-enable-ramp-delay = <216>;
 255 +                       };
 256 +
 257 +                       mt6323_vibr_reg: ldo_vibr{
 258 +                               regulator-name = "vibr";
 259 +                               regulator-min-microvolt = <1200000>;
 260 +                               regulator-max-microvolt = <3300000>;
 261 +                               regulator-enable-ramp-delay = <36>;
 262 +                       };
 263 +
 264 +                       mt6323_vrf18_reg: ldo_vrf18{
 265 +                               regulator-name = "vrf18";
 266 +                               regulator-min-microvolt = <1825000>;
 267 +                               regulator-max-microvolt = <1825000>;
 268 +                               regulator-enable-ramp-delay = <187>;
 269 +                       };
 270 +
 271 +                       mt6323_vm_reg: ldo_vm{
 272 +                               regulator-name = "vm";
 273 +                               regulator-min-microvolt = <1200000>;
 274 +                               regulator-max-microvolt = <1800000>;
 275 +                               regulator-enable-ramp-delay = <216>;
 276 +                               regulator-always-on;
 277 +                               regulator-boot-on;
 278 +                       };
 279 +
 280 +                       mt6323_vio18_reg: ldo_vio18{
 281 +                               regulator-name = "vio18";
 282 +                               regulator-min-microvolt = <1800000>;
 283 +                               regulator-max-microvolt = <1800000>;
 284 +                               regulator-enable-ramp-delay = <216>;
 285 +                               regulator-always-on;
 286 +                               regulator-boot-on;
 287 +                       };
 288 +
 289 +                       mt6323_vcamd_reg: ldo_vcamd{
 290 +                               regulator-name = "vcamd";
 291 +                               regulator-min-microvolt = <1200000>;
 292 +                               regulator-max-microvolt = <1800000>;
 293 +                               regulator-enable-ramp-delay = <216>;
 294 +                       };
 295 +
 296 +                       mt6323_vcamio_reg: ldo_vcamio{
 297 +                               regulator-name = "vcamio";
 298 +                               regulator-min-microvolt = <1800000>;
 299 +                               regulator-max-microvolt = <1800000>;
 300 +                               regulator-enable-ramp-delay = <216>;
 301 +                       };
 302 +               };
 303 +       };
 304 +};
 305 +
 306 +&uart2 {
 307 +       status = "okay";
 308 +};
 309 +
 310 +&mmc0 {
 311 +       status = "okay";
 312 +       pinctrl-names = "default", "state_uhs";
 313 +       pinctrl-0 = <&mmc0_pins_default>;
 314 +       pinctrl-1 = <&mmc0_pins_uhs>;
 315 +       bus-width = <8>;
 316 +       max-frequency = <50000000>;
 317 +       cap-mmc-highspeed;
 318 +       vmmc-supply = <&mt6323_vemc3v3_reg>;
 319 +       vqmmc-supply = <&mt6323_vio18_reg>;
 320 +       non-removable;
 321 +};
 322 +
 323 +&mmc1 {
 324 +       status = "okay";
 325 +       pinctrl-names = "default", "state_uhs";
 326 +       pinctrl-0 = <&mmc1_pins_default>;
 327 +       pinctrl-1 = <&mmc1_pins_uhs>;
 328 +       bus-width = <4>;
 329 +       max-frequency = <50000000>;
 330 +       cap-sd-highspeed;
 331 +       sd-uhs-sdr25;
 332 +//     cd-gpios = <&pio 132 0>;
 333 +       vmmc-supply = <&mt6323_vmch_reg>;
 334 +       vqmmc-supply = <&mt6323_vmc_reg>;
 335 +};
 336 +
 337 +&pio {
 338 +       mmc0_pins_default: mmc0default {
 339 +               pins_cmd_dat {
 340 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 341 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 342 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 343 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 344 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 345 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 346 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 347 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 348 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 349 +                       input-enable;
 350 +                       bias-pull-up;
 351 +               };
 352 +
 353 +               pins_clk {
 354 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 355 +                       bias-pull-down;
 356 +               };
 357 +
 358 +               pins_rst {
 359 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 360 +                       bias-pull-up;
 361 +               };
 362 +       };
 363 +
 364 +       mmc0_pins_uhs: mmc0 {
 365 +               pins_cmd_dat {
 366 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 367 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 368 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 369 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 370 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 371 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 372 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 373 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 374 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 375 +                       input-enable;
 376 +                       drive-strength = <MTK_DRIVE_2mA>;
 377 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 378 +               };
 379 +
 380 +               pins_clk {
 381 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 382 +                       drive-strength = <MTK_DRIVE_2mA>;
 383 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 384 +               };
 385 +
 386 +               pins_rst {
 387 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 388 +                       bias-pull-up;
 389 +               };
 390 +       };
 391 +
 392 +       mmc1_pins_default: mmc1default {
 393 +               pins_cmd_dat {
 394 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
 395 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
 396 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
 397 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
 398 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
 399 +                       input-enable;
 400 +                       drive-strength = <MTK_DRIVE_4mA>;
 401 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 402 +               };
 403 +
 404 +               pins_clk {
 405 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
 406 +                       bias-pull-down;
 407 +                       drive-strength = <MTK_DRIVE_4mA>;
 408 +               };
 409 +
 410 +//             pins_insert {
 411 +//                     pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
 412 +//                     bias-pull-up;
 413 +//             };
 414 +       };
 415 +
 416 +       mmc1_pins_uhs: mmc1 {
 417 +               pins_cmd_dat {
 418 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
 419 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
 420 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
 421 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
 422 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
 423 +                       input-enable;
 424 +                       drive-strength = <MTK_DRIVE_4mA>;
 425 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 426 +               };
 427 +
 428 +               pins_clk {
 429 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
 430 +                       drive-strength = <MTK_DRIVE_4mA>;
 431 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 432 +               };
 433 +       };
 434 +
 435 +       eth_default: eth {
 436 +               pins_eth {
 437 +                       pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
 438 +                                <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
 439 +                                <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
 440 +                                <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
 441 +                                <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
 442 +                                <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
 443 +                                <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
 444 +                                <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
 445 +                                <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
 446 +                                <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
 447 +                                <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
 448 +                                <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
 449 +                                <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
 450 +                                <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
 451 +                                <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
 452 +               };
 453 +
 454 +               pins_eth_rst {
 455 +                       pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
 456 +                       output-low;
 457 +               };
 458 +       };
 459 +};
 460 +
 461 +&usb1 {
 462 +       vusb33-supply = <&mt6323_vusb_reg>;
 463 +       vbus-supply = <&usb_p1_vbus>;
 464 +//     mediatek,wakeup-src = <1>;
 465 +       status = "okay";
 466 +};
 467 +
 468 +&u3phy1 {
 469 +       status = "okay";
 470 +};
 471 +
 472 +&pcie {
 473 +       status = "okay";
 474 +};
 475 +
 476 +&eth {
 477 +       status = "okay";
 478 +};
 479 +
 480 +&gmac1 {
 481 +       mac-address = [00 11 22 33 44 56];
 482 +       status = "okay";
 483 +};
 484 +
 485 +&gmac2 {
 486 +       mac-address = [00 11 22 33 44 55];
 487 +       status = "okay";
 488 +};
 489 +
 490 +&gsw {
 491 +       pinctrl-names = "default";
 492 +       pinctrl-0 = <&eth_default>;
 493 +       mediatek,reset-pin = <&pio 15 0>;
 494 +       status = "okay";
 495 +};
 496 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
 497 new file mode 100644
 498 index 0000000..c53c10d
 499 --- /dev/null
 500 +++ b/arch/arm/boot/dts/mt7623.dtsi
 501 @@ -0,0 +1,510 @@
 502 +/*
 503 + * Copyright (c) 2016 MediaTek Inc.
 504 + * Author: John Crispin <blogic@openwrt.org>
 505 + *
 506 + * This program is free software; you can redistribute it and/or modify
 507 + * it under the terms of the GNU General Public License version 2 as
 508 + * published by the Free Software Foundation.
 509 + *
 510 + * This program is distributed in the hope that it will be useful,
 511 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 512 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 513 + * GNU General Public License for more details.
 514 + */
 515 +
 516 +#include <dt-bindings/interrupt-controller/irq.h>
 517 +#include <dt-bindings/interrupt-controller/arm-gic.h>
 518 +#include <dt-bindings/clock/mt2701-clk.h>
 519 +#include <dt-bindings/power/mt2701-power.h>
 520 +#include <dt-bindings/phy/phy.h>
 521 +#include <dt-bindings/reset-controller/mt2701-resets.h>
 522 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
 523 +#include "skeleton64.dtsi"
 524 +
 525 +
 526 +/ {
 527 +       compatible = "mediatek,mt7623";
 528 +       interrupt-parent = <&sysirq>;
 529 +
 530 +       cpus {
 531 +               #address-cells = <1>;
 532 +               #size-cells = <0>;
 533 +               enable-method = "mediatek,mt6589-smp";
 534 +
 535 +               cpu@0 {
 536 +                       device_type = "cpu";
 537 +                       compatible = "arm,cortex-a7";
 538 +                       reg = <0x0>;
 539 +               };
 540 +               cpu@1 {
 541 +                       device_type = "cpu";
 542 +                       compatible = "arm,cortex-a7";
 543 +                       reg = <0x1>;
 544 +               };
 545 +               cpu@2 {
 546 +                       device_type = "cpu";
 547 +                       compatible = "arm,cortex-a7";
 548 +                       reg = <0x2>;
 549 +               };
 550 +               cpu@3 {
 551 +                       device_type = "cpu";
 552 +                       compatible = "arm,cortex-a7";
 553 +                       reg = <0x3>;
 554 +               };
 555 +       };
 556 +
 557 +       system_clk: dummy13m {
 558 +               compatible = "fixed-clock";
 559 +               clock-frequency = <13000000>;
 560 +               #clock-cells = <0>;
 561 +       };
 562 +
 563 +       rtc_clk: dummy32k {
 564 +               compatible = "fixed-clock";
 565 +               clock-frequency = <32000>;
 566 +               #clock-cells = <0>;
 567 +               clock-output-names = "clk32k";
 568 +       };
 569 +
 570 +       clk26m: dummy26m {
 571 +               compatible = "fixed-clock";
 572 +               clock-frequency = <26000000>;
 573 +               #clock-cells = <0>;
 574 +               clock-output-names = "clk26m";
 575 +       };
 576 +
 577 +       timer {
 578 +               compatible = "arm,armv7-timer";
 579 +               interrupt-parent = <&gic>;
 580 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 581 +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 582 +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 583 +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 584 +       };
 585 +
 586 +       topckgen: power-controller@10000000 {
 587 +               compatible = "mediatek,mt7623-topckgen",
 588 +                            "mediatek,mt2701-topckgen",
 589 +                            "syscon";
 590 +               reg = <0 0x10000000 0 0x1000>;
 591 +               #clock-cells = <1>;
 592 +       };
 593 +
 594 +       infracfg: power-controller@10001000 {
 595 +               compatible = "mediatek,mt7623-infracfg",
 596 +                            "mediatek,mt2701-infracfg",
 597 +                            "syscon";
 598 +               reg = <0 0x10001000 0 0x1000>;
 599 +               #clock-cells = <1>;
 600 +               #reset-cells = <1>;
 601 +       };
 602 +
 603 +       pericfg: pericfg@10003000 {
 604 +               compatible = "mediatek,mt7623-pericfg",
 605 +                            "mediatek,mt2701-pericfg",
 606 +                            "syscon";
 607 +               reg = <0 0x10003000 0 0x1000>;
 608 +               #clock-cells = <1>;
 609 +               #reset-cells = <1>;
 610 +       };
 611 +
 612 +       pio: pinctrl@10005000 {
 613 +               compatible = "mediatek,mt7623-pinctrl";
 614 +               reg = <0 0x1000b000 0 0x1000>;
 615 +               mediatek,pctl-regmap = <&syscfg_pctl_a>;
 616 +               pins-are-numbered;
 617 +               gpio-controller;
 618 +               #gpio-cells = <2>;
 619 +               interrupt-controller;
 620 +               interrupt-parent = <&gic>;
 621 +               #interrupt-cells = <2>;
 622 +               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 623 +                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 624 +       };
 625 +
 626 +       syscfg_pctl_a: syscfg@10005000 {
 627 +               compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 628 +               reg = <0 0x10005000 0 0x1000>;
 629 +       };
 630 +
 631 +       scpsys: scpsys@10006000 {
 632 +               #power-domain-cells = <1>;
 633 +               compatible = "mediatek,mt7623-scpsys",
 634 +                            "mediatek,mt2701-scpsys";
 635 +               reg = <0 0x10006000 0 0x1000>;
 636 +               infracfg = <&infracfg>;
 637 +               clocks = <&clk26m>,
 638 +                        <&topckgen CLK_TOP_MM_SEL>;
 639 +               clock-names = "mfg", "mm";
 640 +       };
 641 +
 642 +       watchdog: watchdog@10007000 {
 643 +               compatible = "mediatek,mt7623-wdt",
 644 +                            "mediatek,mt6589-wdt";
 645 +               reg = <0 0x10007000 0 0x100>;
 646 +       };
 647 +
 648 +       timer: timer@10008000 {
 649 +               compatible = "mediatek,mt7623-timer",
 650 +                            "mediatek,mt6577-timer";
 651 +               reg = <0 0x10008000 0 0x80>;
 652 +               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 653 +               clocks = <&system_clk>, <&rtc_clk>;
 654 +               clock-names = "system-clk", "rtc-clk";
 655 +       };
 656 +
 657 +       pwrap: pwrap@1000d000 {
 658 +               compatible = "mediatek,mt7623-pwrap",
 659 +                            "mediatek,mt2701-pwrap";
 660 +               reg = <0 0x1000d000 0 0x1000>;
 661 +               reg-names = "pwrap";
 662 +               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 663 +               resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 664 +               reset-names = "pwrap";
 665 +               clocks = <&infracfg CLK_INFRA_PMICSPI>,
 666 +                        <&infracfg CLK_INFRA_PMICWRAP>;
 667 +               clock-names = "spi", "wrap";
 668 +       };
 669 +
 670 +       sysirq: interrupt-controller@10200100 {
 671 +               compatible = "mediatek,mt7623-sysirq",
 672 +                            "mediatek,mt6577-sysirq";
 673 +               interrupt-controller;
 674 +               #interrupt-cells = <3>;
 675 +               interrupt-parent = <&gic>;
 676 +               reg = <0 0x10200100 0 0x1c>;
 677 +       };
 678 +
 679 +       apmixedsys: apmixedsys@10209000 {
 680 +               compatible = "mediatek,mt7623-apmixedsys",
 681 +                            "mediatek,mt2701-apmixedsys";
 682 +               reg = <0 0x10209000 0 0x1000>;
 683 +               #clock-cells = <1>;
 684 +       };
 685 +
 686 +       gic: interrupt-controller@10211000 {
 687 +               compatible = "arm,cortex-a7-gic";
 688 +               interrupt-controller;
 689 +               #interrupt-cells = <3>;
 690 +               interrupt-parent = <&gic>;
 691 +               reg = <0 0x10211000 0 0x1000>,
 692 +                     <0 0x10212000 0 0x1000>,
 693 +                     <0 0x10214000 0 0x2000>,
 694 +                     <0 0x10216000 0 0x2000>;
 695 +       };
 696 +
 697 +       i2c0: i2c@11007000 {
 698 +               compatible = "mediatek,mt7623-i2c",
 699 +                            "mediatek,mt6577-i2c";
 700 +               reg = <0 0x11007000 0 0x70>,
 701 +                     <0 0x11000200 0 0x80>;
 702 +               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 703 +               clock-div = <16>;
 704 +               clocks = <&pericfg CLK_PERI_I2C0>,
 705 +                        <&pericfg CLK_PERI_AP_DMA>;
 706 +               clock-names = "main", "dma";
 707 +               #address-cells = <1>;
 708 +               #size-cells = <0>;
 709 +               status = "disabled";
 710 +       };
 711 +
 712 +       i2c1: i2c@11008000 {
 713 +               compatible = "mediatek,mt7623-i2c",
 714 +                            "mediatek,mt6577-i2c";
 715 +               reg = <0 0x11008000 0 0x70>,
 716 +                     <0 0x11000280 0 0x80>;
 717 +               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 718 +               clock-div = <16>;
 719 +               clocks = <&pericfg CLK_PERI_I2C1>,
 720 +                        <&pericfg CLK_PERI_AP_DMA>;
 721 +               clock-names = "main", "dma";
 722 +               #address-cells = <1>;
 723 +               #size-cells = <0>;
 724 +               status = "disabled";
 725 +       };
 726 +
 727 +       i2c2: i2c@11009000 {
 728 +               compatible = "mediatek,mt7623-i2c",
 729 +                            "mediatek,mt6577-i2c";
 730 +               reg = <0 0x11009000 0 0x70>,
 731 +                     <0 0x11000300 0 0x80>;
 732 +               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 733 +               clock-div = <16>;
 734 +               clocks = <&pericfg CLK_PERI_I2C2>,
 735 +                        <&pericfg CLK_PERI_AP_DMA>;
 736 +               clock-names = "main", "dma";
 737 +               #address-cells = <1>;
 738 +               #size-cells = <0>;
 739 +               status = "disabled";
 740 +       };
 741 +
 742 +       uart0: serial@11002000 {
 743 +               compatible = "mediatek,mt7623-uart",
 744 +                            "mediatek,mt6577-uart";
 745 +               reg = <0 0x11002000 0 0x400>;
 746 +               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 747 +               clocks = <&pericfg CLK_PERI_UART0_SEL>,
 748 +                        <&pericfg CLK_PERI_UART0>;
 749 +               clock-names = "baud", "bus";
 750 +               status = "disabled";
 751 +       };
 752 +
 753 +       uart1: serial@11003000 {
 754 +               compatible = "mediatek,mt7623-uart",
 755 +                            "mediatek,mt6577-uart";
 756 +               reg = <0 0x11003000 0 0x400>;
 757 +               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 758 +               clocks = <&pericfg CLK_PERI_UART1_SEL>,
 759 +                        <&pericfg CLK_PERI_UART1>;
 760 +               clock-names = "baud", "bus";
 761 +               status = "disabled";
 762 +       };
 763 +
 764 +       uart2: serial@11004000 {
 765 +               compatible = "mediatek,mt7623-uart",
 766 +                            "mediatek,mt6577-uart";
 767 +               reg = <0 0x11004000 0 0x400>;
 768 +               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 769 +               clocks = <&pericfg CLK_PERI_UART2_SEL>,
 770 +                        <&pericfg CLK_PERI_UART2>;
 771 +               clock-names = "baud", "bus";
 772 +               status = "disabled";
 773 +       };
 774 +
 775 +       uart3: serial@11005000 {
 776 +               compatible = "mediatek,mt7623-uart",
 777 +                            "mediatek,mt6577-uart";
 778 +               reg = <0 0x11005000 0 0x400>;
 779 +               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 780 +               clocks = <&pericfg CLK_PERI_UART3_SEL>,
 781 +                        <&pericfg CLK_PERI_UART3>;
 782 +               clock-names = "baud", "bus";
 783 +               status = "disabled";
 784 +       };
 785 +
 786 +       spi: spi@1100a000 {
 787 +               compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
 788 +               reg = <0 0x1100a000 0 0x1000>;
 789 +               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 790 +               clocks = <&pericfg CLK_PERI_SPI0>;
 791 +               clock-names = "main";
 792 +
 793 +               status = "disabled";
 794 +       };
 795 +
 796 +       mmc0: mmc@11230000 {
 797 +               compatible = "mediatek,mt7623-mmc",
 798 +                            "mediatek,mt8135-mmc";
 799 +               reg = <0 0x11230000 0 0x1000>;
 800 +               interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 801 +               clocks = <&pericfg CLK_PERI_MSDC30_0>,
 802 +                        <&topckgen CLK_TOP_MSDC30_0_SEL>;
 803 +               clock-names = "source", "hclk";
 804 +               status = "disabled";
 805 +       };
 806 +
 807 +       mmc1: mmc@11240000 {
 808 +               compatible = "mediatek,mt7623-mmc",
 809 +                            "mediatek,mt8135-mmc";
 810 +               reg = <0 0x11240000 0 0x1000>;
 811 +               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 812 +               clocks = <&pericfg CLK_PERI_MSDC30_1>,
 813 +                        <&topckgen CLK_TOP_MSDC30_1_SEL>;
 814 +               clock-names = "source", "hclk";
 815 +               status = "disabled";
 816 +       };
 817 +
 818 +       usb1: usb@1a1c0000 {
 819 +               compatible = "mediatek,mt2701-xhci",
 820 +                            "mediatek,mt8173-xhci";
 821 +               reg = <0 0x1a1c0000 0 0x1000>,
 822 +                     <0 0x1a1c4700 0 0x0100>;
 823 +               interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 824 +               clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 825 +                        <&topckgen CLK_TOP_ETHIF_SEL>;
 826 +               clock-names = "sys_ck", "ethif";
 827 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 828 +               phys = <&phy_port0 PHY_TYPE_USB3>;
 829 +               status = "disabled";
 830 +       };
 831 +
 832 +       u3phy1: usb-phy@1a1c4000 {
 833 +               compatible = "mediatek,mt2701-u3phy",
 834 +                            "mediatek,mt8173-u3phy";
 835 +               reg = <0 0x1a1c4000 0 0x0700>;
 836 +               clocks = <&clk26m>;
 837 +               clock-names = "u3phya_ref";
 838 +               #phy-cells = <1>;
 839 +               #address-cells = <2>;
 840 +               #size-cells = <2>;
 841 +               ranges;
 842 +               status = "disabled";
 843 +
 844 +               phy_port0: phy_port0: port@1a1c4800 {
 845 +                       reg = <0 0x1a1c4800 0 0x800>;
 846 +                       #phy-cells = <1>;
 847 +                       status = "okay";
 848 +               };
 849 +       };
 850 +
 851 +       usb2: usb@1a240000 {
 852 +               compatible = "mediatek,mt2701-xhci",
 853 +                            "mediatek,mt8173-xhci";
 854 +               reg = <0 0x1a240000 0 0x1000>,
 855 +                     <0 0x1a244700 0 0x0100>;
 856 +               interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 857 +               clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 858 +                        <&topckgen CLK_TOP_ETHIF_SEL>;
 859 +               clock-names = "sys_ck", "ethif";
 860 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 861 +               phys = <&u3phy2 0>;
 862 +               status = "disabled";
 863 +       };
 864 +
 865 +       u3phy2: usb-phy@1a244000 {
 866 +               compatible = "mediatek,mt2701-u3phy",
 867 +                            "mediatek,mt8173-u3phy";
 868 +               reg = <0 0x1a244000 0 0x0700>,
 869 +                     <0 0x1a244800 0 0x0800>;
 870 +               clocks = <&clk26m>;
 871 +               clock-names = "u3phya_ref";
 872 +               #phy-cells = <1>;
 873 +               status = "disabled";
 874 +       };
 875 +
 876 +       hifsys: clock-controller@1a000000 {
 877 +               compatible = "mediatek,mt7623-hifsys",
 878 +                            "mediatek,mt2701-hifsys",
 879 +                            "syscon";
 880 +               reg = <0 0x1a000000 0 0x1000>;
 881 +               #clock-cells = <1>;
 882 +               #reset-cells = <1>;
 883 +       };
 884 +
 885 +       pcie: pcie@1a140000 {
 886 +               compatible = "mediatek,mt7623-pcie";
 887 +               device_type = "pci";
 888 +               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
 889 +                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
 890 +                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
 891 +                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
 892 +               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
 893 +               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
 894 +                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
 895 +                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 896 +               interrupt-names = "pcie0", "pcie1", "pcie2";
 897 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
 898 +               clock-names = "pcie";
 899 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 900 +               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 901 +                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 902 +                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 903 +               reset-names = "pcie0", "pcie1", "pcie2";
 904 +
 905 +               mediatek,hifsys = <&hifsys>;
 906 +
 907 +               bus-range = <0x00 0xff>;
 908 +               #address-cells = <3>;
 909 +               #size-cells = <2>;
 910 +
 911 +               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
 912 +                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
 913 +
 914 +               status = "disabled";
 915 +
 916 +               pcie@1,0 {
 917 +                       device_type = "pci";
 918 +                       reg = <0x0800 0 0 0 0>;
 919 +
 920 +                       #address-cells = <3>;
 921 +                       #size-cells = <2>;
 922 +                       ranges;
 923 +               };
 924 +
 925 +               pcie@2,0{
 926 +                       device_type = "pci";
 927 +                       reg = <0x1000 0 0 0 0>;
 928 +
 929 +                       #address-cells = <3>;
 930 +                       #size-cells = <2>;
 931 +                       ranges;
 932 +               };
 933 +
 934 +               pcie@3,0{
 935 +                       device_type = "pci";
 936 +                       reg = <0x1800 0 0 0 0>;
 937 +
 938 +                       #address-cells = <3>;
 939 +                       #size-cells = <2>;
 940 +                       ranges;
 941 +               };
 942 +       };
 943 +
 944 +       ethsys: syscon@1b000000 {
 945 +               #address-cells = <1>;
 946 +               #size-cells = <1>;
 947 +               compatible = "mediatek,mt2701-ethsys", "syscon";
 948 +               reg = <0 0x1b000000 0 0x1000>;
 949 +               #clock-cells = <1>;
 950 +       };
 951 +
 952 +       eth: ethernet@1b100000 {
 953 +               compatible = "mediatek,mt7623-eth";
 954 +               reg = <0 0x1b100000 0 0x10000>;
 955 +
 956 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
 957 +               clock-names = "ethif";
 958 +               interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
 959 +                             GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
 960 +                             GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 961 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 962 +
 963 +               mediatek,ethsys = <&ethsys>;
 964 +               mediatek,switch = <&gsw>;
 965 +
 966 +               #address-cells = <1>;
 967 +               #size-cells = <0>;
 968 +
 969 +               status = "disabled";
 970 +
 971 +               gmac1: mac@0 {
 972 +                       compatible = "mediatek,eth-mac";
 973 +                       reg = <0>;
 974 +
 975 +                       status = "disabled";
 976 +               };
 977 +
 978 +               gmac2: mac@1 {
 979 +                       compatible = "mediatek,eth-mac";
 980 +                       reg = <1>;
 981 +
 982 +                       status = "disabled";
 983 +               };
 984 +
 985 +               mdio-bus {
 986 +                       #address-cells = <1>;
 987 +                       #size-cells = <0>;
 988 +
 989 +                       phy1f: ethernet-phy@1f {
 990 +                               reg = <0x1f>;
 991 +                               phy-mode = "rgmii";
 992 +                       };
 993 +               };
 994 +       };
 995 +
 996 +       gsw: switch@1b100000 {
 997 +               compatible = "mediatek,mt7623-gsw";
 998 +               reg = <0 0x1b110000 0 0x300000>;
 999 +               interrupt-parent = <&pio>;
1000 +               interrupts = <168 IRQ_TYPE_EDGE_RISING>;
1001 +               clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
1002 +                        <&ethsys CLK_ETHSYS_ESW>,
1003 +                        <&ethsys CLK_ETHSYS_GP2>,
1004 +                        <&ethsys CLK_ETHSYS_GP1>;
1005 +               clock-names = "trgpll", "esw", "gp2", "gp1";
1006 +               mt7530-supply = <&mt6323_vpa_reg>;
1007 +               mediatek,pctl-regmap = <&syscfg_pctl_a>;
1008 +               mediatek,ethsys = <&ethsys>;
1009 +               status = "disabled";
1010 +       };
1011 +};
1012 diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
1013 index 37dd438..7fb605e 100644
1014 --- a/arch/arm/mach-mediatek/Kconfig
1015 +++ b/arch/arm/mach-mediatek/Kconfig
1016 @@ -21,6 +21,10 @@ config MACH_MT6592
1017         bool "MediaTek MT6592 SoCs support"
1018         default ARCH_MEDIATEK
1019
1020 +config MACH_MT7623
1021 +       bool "MediaTek MT7623 SoCs support"
1022 +       default ARCH_MEDIATEK
1023 +
1024  config MACH_MT8127
1025         bool "MediaTek MT8127 SoCs support"
1026         default ARCH_MEDIATEK
1027 diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
1028 index d019a08..bcfca37 100644
1029 --- a/arch/arm/mach-mediatek/mediatek.c
1030 +++ b/arch/arm/mach-mediatek/mediatek.c
1031 @@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
1032  static const char * const mediatek_board_dt_compat[] = {
1033         "mediatek,mt6589",
1034         "mediatek,mt6592",
1035 +       "mediatek,mt7623",
1036         "mediatek,mt8127",
1037         "mediatek,mt8135",
1038         NULL,
1039 --
1040 1.7.10.4
1041