target/linux/lantiq/patches-3.9/0020-owrt-lantiq-backport-old-timer-code.patch

   1 From 077bcf8dea89b92d9ab8868e8234feb263c26a83 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 13 Mar 2013 10:01:49 +0100
   4 Subject: [PATCH 20/22] owrt: lantiq: backport old timer code
   5
   6 ---
   7  arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
   8  arch/mips/lantiq/xway/Makefile                   |    2 +-
   9  arch/mips/lantiq/xway/timer.c                    |  845 ++++++++++++++++++++++
  10  3 files changed, 1001 insertions(+), 1 deletion(-)
  11  create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  12  create mode 100644 arch/mips/lantiq/xway/timer.c
  13
  14 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  15 new file mode 100644
  16 index 0000000..ef564ab
  17 --- /dev/null
  18 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  19 @@ -0,0 +1,155 @@
  20 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  21 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  22 +
  23 +
  24 +/******************************************************************************
  25 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
  26 +
  27 +                               No Warranty
  28 +   Because the program is licensed free of charge, there is no warranty for
  29 +   the program, to the extent permitted by applicable law.  Except when
  30 +   otherwise stated in writing the copyright holders and/or other parties
  31 +   provide the program "as is" without warranty of any kind, either
  32 +   expressed or implied, including, but not limited to, the implied
  33 +   warranties of merchantability and fitness for a particular purpose. The
  34 +   entire risk as to the quality and performance of the program is with
  35 +   you.  should the program prove defective, you assume the cost of all
  36 +   necessary servicing, repair or correction.
  37 +
  38 +   In no event unless required by applicable law or agreed to in writing
  39 +   will any copyright holder, or any other party who may modify and/or
  40 +   redistribute the program as permitted above, be liable to you for
  41 +   damages, including any general, special, incidental or consequential
  42 +   damages arising out of the use or inability to use the program
  43 +   (including but not limited to loss of data or data being rendered
  44 +   inaccurate or losses sustained by you or third parties or a failure of
  45 +   the program to operate with any other programs), even if such holder or
  46 +   other party has been advised of the possibility of such damages.
  47 +******************************************************************************/
  48 +
  49 +
  50 +/*
  51 + * ####################################
  52 + *              Definition
  53 + * ####################################
  54 + */
  55 +
  56 +/*
  57 + *  Available Timer/Counter Index
  58 + */
  59 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
  60 +#define TIMER_ANY                       0x00
  61 +#define TIMER1A                         TIMER(1, 0)
  62 +#define TIMER1B                         TIMER(1, 1)
  63 +#define TIMER2A                         TIMER(2, 0)
  64 +#define TIMER2B                         TIMER(2, 1)
  65 +#define TIMER3A                         TIMER(3, 0)
  66 +#define TIMER3B                         TIMER(3, 1)
  67 +
  68 +/*
  69 + *  Flag of Timer/Counter
  70 + *  These flags specify the way in which timer is configured.
  71 + */
  72 +/*  Bit size of timer/counter.                      */
  73 +#define TIMER_FLAG_16BIT                0x0000
  74 +#define TIMER_FLAG_32BIT                0x0001
  75 +/*  Switch between timer and counter.               */
  76 +#define TIMER_FLAG_TIMER                0x0000
  77 +#define TIMER_FLAG_COUNTER              0x0002
  78 +/*  Stop or continue when overflowing/underflowing. */
  79 +#define TIMER_FLAG_ONCE                 0x0000
  80 +#define TIMER_FLAG_CYCLIC               0x0004
  81 +/*  Count up or counter down.                       */
  82 +#define TIMER_FLAG_UP                   0x0000
  83 +#define TIMER_FLAG_DOWN                 0x0008
  84 +/*  Count on specific level or edge.                */
  85 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
  86 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
  87 +#define TIMER_FLAG_RISE_EDGE            0x0010
  88 +#define TIMER_FLAG_FALL_EDGE            0x0020
  89 +#define TIMER_FLAG_ANY_EDGE             0x0030
  90 +/*  Signal is syncronous to module clock or not.    */
  91 +#define TIMER_FLAG_UNSYNC               0x0000
  92 +#define TIMER_FLAG_SYNC                 0x0080
  93 +/*  Different interrupt handle type.                */
  94 +#define TIMER_FLAG_NO_HANDLE            0x0000
  95 +#if defined(__KERNEL__)
  96 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
  97 +#endif  //  defined(__KERNEL__)
  98 +#define TIMER_FLAG_SIGNAL               0x0300
  99 +/*  Internal clock source or external clock source  */
 100 +#define TIMER_FLAG_INT_SRC              0x0000
 101 +#define TIMER_FLAG_EXT_SRC              0x1000
 102 +
 103 +
 104 +/*
 105 + *  ioctl Command
 106 + */
 107 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 108 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 109 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 110 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 111 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 112 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 113 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 114 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 115 +
 116 +/*
 117 + *  Data Type Used to Call ioctl
 118 + */
 119 +struct gptu_ioctl_param {
 120 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 121 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 122 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 123 +                                                 *  be dynamically allocated and ID would be stored in  *
 124 +                                                 *  this field.                                         *
 125 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 126 +                                                 *  ignored.                                            *
 127 +                                                 *  In other command, this field is ID of timer/counter *
 128 +                                                 *  allocated.                                          */
 129 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 130 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 131 +                                                 *  specify how to configure timer/counter.             *
 132 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 133 +                                                 *  and non-zero indicate resume timer/counter.         *
 134 +                                                 *  In other command, this field is ignored.            */
 135 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 136 +                                                 *  init/reload value.                                  *
 137 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 138 +                                                 *  frequency (0.001Hz) of timer.                       *
 139 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 140 +                                                 *  value would be stored in this field.                *
 141 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 142 +                                                 *  contains frequency wanted, and after calculation,   *
 143 +                                                 *  divider would be stored in this field to overwrite  *
 144 +                                                 *  the frequency.                                      *
 145 +                                                 *  In other command, this field is ignored.            */
 146 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 147 +                                                 *  if signal is required, this field contains process  *
 148 +                                                 *  ID to which signal would be sent.                   *
 149 +                                                 *  In other command, this field is ignored.            */
 150 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 151 +                                                 *  if signal is required, this field contains signal   *
 152 +                                                 *  number which would be sent.                         *
 153 +                                                 *  In other command, this field is ignored.            */
 154 +};
 155 +
 156 +/*
 157 + * ####################################
 158 + *              Data Type
 159 + * ####################################
 160 + */
 161 +typedef void (*timer_callback)(unsigned long arg);
 162 +
 163 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
 164 +extern int lq_free_timer(unsigned int);
 165 +extern int lq_start_timer(unsigned int, int);
 166 +extern int lq_stop_timer(unsigned int);
 167 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
 168 +extern int lq_get_count_value(unsigned int, unsigned long *);
 169 +extern u32 lq_cal_divider(unsigned long);
 170 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
 171 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
 172 +       u32 reload, unsigned long arg1, unsigned long arg2);
 173 +
 174 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
 175 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
 176 index 3a01d22..ea8706f 100644
 177 --- a/arch/mips/lantiq/xway/Makefile
 178 +++ b/arch/mips/lantiq/xway/Makefile
 179 @@ -1,4 +1,4 @@
 180 -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
 181 +obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o
 182
 183  obj-y += eth_mac.o vmmc.o
 184  obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o
 185 diff --git a/arch/mips/lantiq/xway/timer.c b/arch/mips/lantiq/xway/timer.c
 186 new file mode 100644
 187 index 0000000..1c0fdb8
 188 --- /dev/null
 189 +++ b/arch/mips/lantiq/xway/timer.c
 190 @@ -0,0 +1,845 @@
 191 +#ifndef CONFIG_SOC_AMAZON_SE
 192 +
 193 +#include <linux/kernel.h>
 194 +#include <linux/module.h>
 195 +#include <linux/version.h>
 196 +#include <linux/types.h>
 197 +#include <linux/fs.h>
 198 +#include <linux/miscdevice.h>
 199 +#include <linux/init.h>
 200 +#include <linux/uaccess.h>
 201 +#include <linux/unistd.h>
 202 +#include <linux/errno.h>
 203 +#include <linux/interrupt.h>
 204 +#include <linux/sched.h>
 205 +
 206 +#include <asm/irq.h>
 207 +#include <asm/div64.h>
 208 +#include "../clk.h"
 209 +
 210 +#include <lantiq_soc.h>
 211 +#include <lantiq_irq.h>
 212 +#include <lantiq_timer.h>
 213 +
 214 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
 215 +
 216 +#ifdef TIMER1A
 217 +#define FIRST_TIMER                    TIMER1A
 218 +#else
 219 +#define FIRST_TIMER                    2
 220 +#endif
 221 +
 222 +/*
 223 + *  GPTC divider is set or not.
 224 + */
 225 +#define GPTU_CLC_RMC_IS_SET            0
 226 +
 227 +/*
 228 + *  Timer Interrupt (IRQ)
 229 + */
 230 +/*  Must be adjusted when ICU driver is available */
 231 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
 232 +
 233 +/*
 234 + *  Bits Operation
 235 + */
 236 +#define GET_BITS(x, msb, lsb)          \
 237 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
 238 +#define SET_BITS(x, msb, lsb, value)   \
 239 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
 240 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
 241 +
 242 +/*
 243 + *  GPTU Register Mapping
 244 + */
 245 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
 246 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
 247 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
 248 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 249 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 250 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 251 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 252 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
 253 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
 254 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
 255 +
 256 +/*
 257 + *  Clock Control Register
 258 + */
 259 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
 260 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
 261 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
 262 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
 263 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
 264 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
 265 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
 266 +
 267 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
 268 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
 269 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
 270 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
 271 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
 272 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
 273 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
 274 +
 275 +/*
 276 + *  ID Register
 277 + */
 278 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
 279 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
 280 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
 281 +
 282 +/*
 283 + *  Control Register of Timer/Counter nX
 284 + *    n is the index of block (1 based index)
 285 + *    X is either A or B
 286 + */
 287 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 288 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 289 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 290 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 291 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 292 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 293 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 294 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 295 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 296 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 297 +
 298 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 299 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 300 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 301 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 302 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 303 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 304 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 305 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 306 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 307 +
 308 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 309 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 310 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 311 +
 312 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 313 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 314 +
 315 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 316 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 317 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 318 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 319 +#define TIMER_FLAG_NONE_EDGE           0x0000
 320 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 321 +#define TIMER_FLAG_REAL                        0x0000
 322 +#define TIMER_FLAG_INVERT              0x0040
 323 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 324 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 325 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 326 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 327 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 328 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 329 +
 330 +struct timer_dev_timer {
 331 +       unsigned int f_irq_on;
 332 +       unsigned int irq;
 333 +       unsigned int flag;
 334 +       unsigned long arg1;
 335 +       unsigned long arg2;
 336 +};
 337 +
 338 +struct timer_dev {
 339 +       struct mutex gptu_mutex;
 340 +       unsigned int number_of_timers;
 341 +       unsigned int occupation;
 342 +       unsigned int f_gptu_on;
 343 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 344 +};
 345 +
 346 +
 347 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 348 +       struct clk *clk = clk_get_fpi();
 349 +       return clk_get_rate(clk);
 350 +}
 351 +
 352 +
 353 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 354 +static int gptu_open(struct inode *, struct file *);
 355 +static int gptu_release(struct inode *, struct file *);
 356 +
 357 +static struct file_operations gptu_fops = {
 358 +       .owner = THIS_MODULE,
 359 +       .unlocked_ioctl = gptu_ioctl,
 360 +       .open = gptu_open,
 361 +       .release = gptu_release
 362 +};
 363 +
 364 +static struct miscdevice gptu_miscdev = {
 365 +       .minor = MISC_DYNAMIC_MINOR,
 366 +       .name = "gptu",
 367 +       .fops = &gptu_fops,
 368 +};
 369 +
 370 +static struct timer_dev timer_dev;
 371 +
 372 +static irqreturn_t timer_irq_handler(int irq, void *p)
 373 +{
 374 +       unsigned int timer;
 375 +       unsigned int flag;
 376 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 377 +
 378 +       timer = irq - TIMER_INTERRUPT;
 379 +       if (timer < timer_dev.number_of_timers
 380 +               && dev_timer == &timer_dev.timer[timer]) {
 381 +               /*  Clear interrupt.    */
 382 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 383 +
 384 +               /*  Call user hanler or signal. */
 385 +               flag = dev_timer->flag;
 386 +               if (!(timer & 0x01)
 387 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 388 +                       /* 16-bit timer or timer A of 32-bit timer  */
 389 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 390 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 391 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 392 +                               if (dev_timer->arg1)
 393 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 394 +                               break;
 395 +                       case TIMER_FLAG_SIGNAL:
 396 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 397 +                               break;
 398 +                       }
 399 +               }
 400 +       }
 401 +       return IRQ_HANDLED;
 402 +}
 403 +
 404 +static inline void lq_enable_gptu(void)
 405 +{
 406 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 407 +       clk_enable(clk);
 408 +
 409 +       //ltq_pmu_enable(PMU_GPT);
 410 +
 411 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 412 +       *LQ_GPTU_CLC =
 413 +               GPTU_CLC_SMC_SET(0x00) |
 414 +               GPTU_CLC_RMC_SET(0x01) |
 415 +               GPTU_CLC_FSOE_SET(0) |
 416 +               GPTU_CLC_SBWE_SET(1) |
 417 +               GPTU_CLC_EDIS_SET(0) |
 418 +               GPTU_CLC_SPEN_SET(0) |
 419 +               GPTU_CLC_DISR_SET(0);
 420 +}
 421 +
 422 +static inline void lq_disable_gptu(void)
 423 +{
 424 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 425 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 426 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 427 +
 428 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 429 +       *LQ_GPTU_CLC =
 430 +               GPTU_CLC_SMC_SET(0x00) |
 431 +               GPTU_CLC_RMC_SET(0x00) |
 432 +               GPTU_CLC_FSOE_SET(0) |
 433 +               GPTU_CLC_SBWE_SET(0) |
 434 +               GPTU_CLC_EDIS_SET(0) |
 435 +               GPTU_CLC_SPEN_SET(0) |
 436 +               GPTU_CLC_DISR_SET(1);
 437 +
 438 +       clk_enable(clk);
 439 +}
 440 +
 441 +int lq_request_timer(unsigned int timer, unsigned int flag,
 442 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 443 +{
 444 +       int ret = 0;
 445 +       unsigned int con_reg, irnen_reg;
 446 +       int n, X;
 447 +
 448 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 449 +               return -EINVAL;
 450 +
 451 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 452 +               timer, flag, value);
 453 +
 454 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 455 +               value &= 0xFFFF;
 456 +       else
 457 +               timer &= ~0x01;
 458 +
 459 +       mutex_lock(&timer_dev.gptu_mutex);
 460 +
 461 +       /*
 462 +        *  Allocate timer.
 463 +        */
 464 +       if (timer < FIRST_TIMER) {
 465 +               unsigned int mask;
 466 +               unsigned int shift;
 467 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 468 +               unsigned int offset = TIMER2A;
 469 +
 470 +               /*
 471 +                *  Pick up a free timer.
 472 +                */
 473 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 474 +                       mask = 1 << offset;
 475 +                       shift = 1;
 476 +               } else {
 477 +                       mask = 3 << offset;
 478 +                       shift = 2;
 479 +               }
 480 +               for (timer = offset;
 481 +                    timer < offset + timer_dev.number_of_timers;
 482 +                    timer += shift, mask <<= shift)
 483 +                       if (!(timer_dev.occupation & mask)) {
 484 +                               timer_dev.occupation |= mask;
 485 +                               break;
 486 +                       }
 487 +               if (timer >= offset + timer_dev.number_of_timers) {
 488 +                       printk("failed![%d]\n", __LINE__);
 489 +                       mutex_unlock(&timer_dev.gptu_mutex);
 490 +                       return -EINVAL;
 491 +               } else
 492 +                       ret = timer;
 493 +       } else {
 494 +               register unsigned int mask;
 495 +
 496 +               /*
 497 +                *  Check if the requested timer is free.
 498 +                */
 499 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 500 +               if ((timer_dev.occupation & mask)) {
 501 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 502 +                               __LINE__, mask, timer_dev.occupation);
 503 +                       mutex_unlock(&timer_dev.gptu_mutex);
 504 +                       return -EBUSY;
 505 +               } else {
 506 +                       timer_dev.occupation |= mask;
 507 +                       ret = 0;
 508 +               }
 509 +       }
 510 +
 511 +       /*
 512 +        *  Prepare control register value.
 513 +        */
 514 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 515 +       default:
 516 +       case TIMER_FLAG_NONE_EDGE:
 517 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 518 +               break;
 519 +       case TIMER_FLAG_RISE_EDGE:
 520 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 521 +               break;
 522 +       case TIMER_FLAG_FALL_EDGE:
 523 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 524 +               break;
 525 +       case TIMER_FLAG_ANY_EDGE:
 526 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 527 +               break;
 528 +       }
 529 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 530 +               con_reg |=
 531 +                       TIMER_FLAG_MASK_SRC(flag) ==
 532 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 533 +                       GPTU_CON_SRC_EXT_SET(0);
 534 +       else
 535 +               con_reg |=
 536 +                       TIMER_FLAG_MASK_SRC(flag) ==
 537 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 538 +                       GPTU_CON_SRC_EG_SET(0);
 539 +       con_reg |=
 540 +               TIMER_FLAG_MASK_SYNC(flag) ==
 541 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 542 +               GPTU_CON_SYNC_SET(1);
 543 +       con_reg |=
 544 +               TIMER_FLAG_MASK_INVERT(flag) ==
 545 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 546 +       con_reg |=
 547 +               TIMER_FLAG_MASK_SIZE(flag) ==
 548 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 549 +               GPTU_CON_EXT_SET(1);
 550 +       con_reg |=
 551 +               TIMER_FLAG_MASK_STOP(flag) ==
 552 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 553 +       con_reg |=
 554 +               TIMER_FLAG_MASK_TYPE(flag) ==
 555 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 556 +               GPTU_CON_CNT_SET(1);
 557 +       con_reg |=
 558 +               TIMER_FLAG_MASK_DIR(flag) ==
 559 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 560 +
 561 +       /*
 562 +        *  Fill up running data.
 563 +        */
 564 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 565 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 566 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 567 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 568 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 569 +
 570 +       /*
 571 +        *  Enable GPTU module.
 572 +        */
 573 +       if (!timer_dev.f_gptu_on) {
 574 +               lq_enable_gptu();
 575 +               timer_dev.f_gptu_on = 1;
 576 +       }
 577 +
 578 +       /*
 579 +        *  Enable IRQ.
 580 +        */
 581 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 582 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 583 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 584 +                               (unsigned long) find_task_by_vpid((int) arg1);
 585 +
 586 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 587 +
 588 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 589 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 590 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 591 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 592 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 593 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 594 +               }
 595 +       } else
 596 +               irnen_reg = 0;
 597 +
 598 +       /*
 599 +        *  Write config register, reload value and enable interrupt.
 600 +        */
 601 +       n = timer >> 1;
 602 +       X = timer & 0x01;
 603 +       *LQ_GPTU_CON(n, X) = con_reg;
 604 +       *LQ_GPTU_RELOAD(n, X) = value;
 605 +       /* printk("reload value = %d\n", (u32)value); */
 606 +       *LQ_GPTU_IRNEN |= irnen_reg;
 607 +
 608 +       mutex_unlock(&timer_dev.gptu_mutex);
 609 +       printk("successful!\n");
 610 +       return ret;
 611 +}
 612 +EXPORT_SYMBOL(lq_request_timer);
 613 +
 614 +int lq_free_timer(unsigned int timer)
 615 +{
 616 +       unsigned int flag;
 617 +       unsigned int mask;
 618 +       int n, X;
 619 +
 620 +       if (!timer_dev.f_gptu_on)
 621 +               return -EINVAL;
 622 +
 623 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 624 +               return -EINVAL;
 625 +
 626 +       mutex_lock(&timer_dev.gptu_mutex);
 627 +
 628 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 629 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 630 +               timer &= ~0x01;
 631 +
 632 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 633 +       if (((timer_dev.occupation & mask) ^ mask)) {
 634 +               mutex_unlock(&timer_dev.gptu_mutex);
 635 +               return -EINVAL;
 636 +       }
 637 +
 638 +       n = timer >> 1;
 639 +       X = timer & 0x01;
 640 +
 641 +       if (GPTU_CON_EN(n, X))
 642 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 643 +
 644 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 645 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 646 +
 647 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 648 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 649 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 650 +       }
 651 +
 652 +       timer_dev.occupation &= ~mask;
 653 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 654 +               lq_disable_gptu();
 655 +               timer_dev.f_gptu_on = 0;
 656 +       }
 657 +
 658 +       mutex_unlock(&timer_dev.gptu_mutex);
 659 +
 660 +       return 0;
 661 +}
 662 +EXPORT_SYMBOL(lq_free_timer);
 663 +
 664 +int lq_start_timer(unsigned int timer, int is_resume)
 665 +{
 666 +       unsigned int flag;
 667 +       unsigned int mask;
 668 +       int n, X;
 669 +
 670 +       if (!timer_dev.f_gptu_on)
 671 +               return -EINVAL;
 672 +
 673 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 674 +               return -EINVAL;
 675 +
 676 +       mutex_lock(&timer_dev.gptu_mutex);
 677 +
 678 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 679 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 680 +               timer &= ~0x01;
 681 +
 682 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 683 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 684 +       if (((timer_dev.occupation & mask) ^ mask)) {
 685 +               mutex_unlock(&timer_dev.gptu_mutex);
 686 +               return -EINVAL;
 687 +       }
 688 +
 689 +       n = timer >> 1;
 690 +       X = timer & 0x01;
 691 +
 692 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 693 +
 694 +
 695 +       mutex_unlock(&timer_dev.gptu_mutex);
 696 +
 697 +       return 0;
 698 +}
 699 +EXPORT_SYMBOL(lq_start_timer);
 700 +
 701 +int lq_stop_timer(unsigned int timer)
 702 +{
 703 +       unsigned int flag;
 704 +       unsigned int mask;
 705 +       int n, X;
 706 +
 707 +       if (!timer_dev.f_gptu_on)
 708 +               return -EINVAL;
 709 +
 710 +       if (timer < FIRST_TIMER
 711 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 712 +               return -EINVAL;
 713 +
 714 +       mutex_lock(&timer_dev.gptu_mutex);
 715 +
 716 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 717 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 718 +               timer &= ~0x01;
 719 +
 720 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 721 +       if (((timer_dev.occupation & mask) ^ mask)) {
 722 +               mutex_unlock(&timer_dev.gptu_mutex);
 723 +               return -EINVAL;
 724 +       }
 725 +
 726 +       n = timer >> 1;
 727 +       X = timer & 0x01;
 728 +
 729 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 730 +
 731 +       mutex_unlock(&timer_dev.gptu_mutex);
 732 +
 733 +       return 0;
 734 +}
 735 +EXPORT_SYMBOL(lq_stop_timer);
 736 +
 737 +int lq_reset_counter_flags(u32 timer, u32 flags)
 738 +{
 739 +       unsigned int oflag;
 740 +       unsigned int mask, con_reg;
 741 +       int n, X;
 742 +
 743 +       if (!timer_dev.f_gptu_on)
 744 +               return -EINVAL;
 745 +
 746 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 747 +               return -EINVAL;
 748 +
 749 +       mutex_lock(&timer_dev.gptu_mutex);
 750 +
 751 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 752 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 753 +               timer &= ~0x01;
 754 +
 755 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 756 +       if (((timer_dev.occupation & mask) ^ mask)) {
 757 +               mutex_unlock(&timer_dev.gptu_mutex);
 758 +               return -EINVAL;
 759 +       }
 760 +
 761 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 762 +       default:
 763 +       case TIMER_FLAG_NONE_EDGE:
 764 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 765 +               break;
 766 +       case TIMER_FLAG_RISE_EDGE:
 767 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 768 +               break;
 769 +       case TIMER_FLAG_FALL_EDGE:
 770 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 771 +               break;
 772 +       case TIMER_FLAG_ANY_EDGE:
 773 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 774 +               break;
 775 +       }
 776 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 777 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 778 +       else
 779 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 780 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 781 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 782 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 783 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 784 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 785 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 786 +
 787 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 788 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 789 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 790 +
 791 +       n = timer >> 1;
 792 +       X = timer & 0x01;
 793 +
 794 +       *LQ_GPTU_CON(n, X) = con_reg;
 795 +       smp_wmb();
 796 +       mutex_unlock(&timer_dev.gptu_mutex);
 797 +       return 0;
 798 +}
 799 +EXPORT_SYMBOL(lq_reset_counter_flags);
 800 +
 801 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 802 +{
 803 +       unsigned int flag;
 804 +       unsigned int mask;
 805 +       int n, X;
 806 +
 807 +       if (!timer_dev.f_gptu_on)
 808 +               return -EINVAL;
 809 +
 810 +       if (timer < FIRST_TIMER
 811 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 812 +               return -EINVAL;
 813 +
 814 +       mutex_lock(&timer_dev.gptu_mutex);
 815 +
 816 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 817 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 818 +               timer &= ~0x01;
 819 +
 820 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 821 +       if (((timer_dev.occupation & mask) ^ mask)) {
 822 +               mutex_unlock(&timer_dev.gptu_mutex);
 823 +               return -EINVAL;
 824 +       }
 825 +
 826 +       n = timer >> 1;
 827 +       X = timer & 0x01;
 828 +
 829 +       *value = *LQ_GPTU_COUNT(n, X);
 830 +
 831 +
 832 +       mutex_unlock(&timer_dev.gptu_mutex);
 833 +
 834 +       return 0;
 835 +}
 836 +EXPORT_SYMBOL(lq_get_count_value);
 837 +
 838 +u32 lq_cal_divider(unsigned long freq)
 839 +{
 840 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 841 +       u32 clock_divider = 1;
 842 +       module_freq = fpi * 1000;
 843 +       do_div(module_freq, clock_divider * freq);
 844 +       return module_freq;
 845 +}
 846 +EXPORT_SYMBOL(lq_cal_divider);
 847 +
 848 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 849 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 850 +       unsigned long arg2)
 851 +{
 852 +       unsigned long divider;
 853 +       unsigned int flag;
 854 +
 855 +       divider = lq_cal_divider(freq);
 856 +       if (divider == 0)
 857 +               return -EINVAL;
 858 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 859 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 860 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 861 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 862 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 863 +
 864 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 865 +               timer, freq, divider);
 866 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 867 +}
 868 +EXPORT_SYMBOL(lq_set_timer);
 869 +
 870 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 871 +       unsigned long arg1, unsigned long arg2)
 872 +{
 873 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 874 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 875 +}
 876 +EXPORT_SYMBOL(lq_set_counter);
 877 +
 878 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 879 +       unsigned long arg)
 880 +{
 881 +       int ret;
 882 +       struct gptu_ioctl_param param;
 883 +
 884 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 885 +               return -EFAULT;
 886 +       copy_from_user(&param, (void *) arg, sizeof(param));
 887 +
 888 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 889 +              || GPTU_SET_COUNTER) && param.timer < 2)
 890 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 891 +           && !access_ok(VERIFY_WRITE, arg,
 892 +                          sizeof(struct gptu_ioctl_param)))
 893 +               return -EFAULT;
 894 +
 895 +       switch (cmd) {
 896 +       case GPTU_REQUEST_TIMER:
 897 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 898 +                                    (unsigned long) param.pid,
 899 +                                    (unsigned long) param.sig);
 900 +               if (ret > 0) {
 901 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 902 +                                     timer, &ret, sizeof(&ret));
 903 +                       ret = 0;
 904 +               }
 905 +               break;
 906 +       case GPTU_FREE_TIMER:
 907 +               ret = lq_free_timer(param.timer);
 908 +               break;
 909 +       case GPTU_START_TIMER:
 910 +               ret = lq_start_timer(param.timer, param.flag);
 911 +               break;
 912 +       case GPTU_STOP_TIMER:
 913 +               ret = lq_stop_timer(param.timer);
 914 +               break;
 915 +       case GPTU_GET_COUNT_VALUE:
 916 +               ret = lq_get_count_value(param.timer, &param.value);
 917 +               if (!ret)
 918 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 919 +                                     value, &param.value,
 920 +                                     sizeof(param.value));
 921 +               break;
 922 +       case GPTU_CALCULATE_DIVIDER:
 923 +               param.value = lq_cal_divider(param.value);
 924 +               if (param.value == 0)
 925 +                       ret = -EINVAL;
 926 +               else {
 927 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 928 +                                     value, &param.value,
 929 +                                     sizeof(param.value));
 930 +                       ret = 0;
 931 +               }
 932 +               break;
 933 +       case GPTU_SET_TIMER:
 934 +               ret = lq_set_timer(param.timer, param.value,
 935 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 936 +                                TIMER_FLAG_ONCE ? 1 : 0,
 937 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 938 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 939 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 940 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 941 +                                TIMER_FLAG_NO_HANDLE,
 942 +                                (unsigned long) param.pid,
 943 +                                (unsigned long) param.sig);
 944 +               if (ret > 0) {
 945 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 946 +                                     timer, &ret, sizeof(&ret));
 947 +                       ret = 0;
 948 +               }
 949 +               break;
 950 +       case GPTU_SET_COUNTER:
 951 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 952 +               if (ret > 0) {
 953 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 954 +                                     timer, &ret, sizeof(&ret));
 955 +                       ret = 0;
 956 +               }
 957 +               break;
 958 +       default:
 959 +               ret = -ENOTTY;
 960 +       }
 961 +
 962 +       return ret;
 963 +}
 964 +
 965 +static int gptu_open(struct inode *inode, struct file *file)
 966 +{
 967 +       return 0;
 968 +}
 969 +
 970 +static int gptu_release(struct inode *inode, struct file *file)
 971 +{
 972 +       return 0;
 973 +}
 974 +
 975 +int __init lq_gptu_init(void)
 976 +{
 977 +       int ret;
 978 +       unsigned int i;
 979 +
 980 +       ltq_w32(0, LQ_GPTU_IRNEN);
 981 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 982 +
 983 +       memset(&timer_dev, 0, sizeof(timer_dev));
 984 +       mutex_init(&timer_dev.gptu_mutex);
 985 +
 986 +       lq_enable_gptu();
 987 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 988 +       lq_disable_gptu();
 989 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 990 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 991 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 992 +
 993 +       ret = misc_register(&gptu_miscdev);
 994 +       if (ret) {
 995 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
 996 +               return ret;
 997 +       } else {
 998 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
 999 +       }
1000 +
1001 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1002 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
1003 +               if (ret) {
1004 +                       for (; i >= 0; i--)
1005 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
1006 +                       misc_deregister(&gptu_miscdev);
1007 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
1008 +                       return ret;
1009 +               } else {
1010 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
1011 +                       disable_irq(timer_dev.timer[i].irq);
1012 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
1013 +               }
1014 +       }
1015 +
1016 +       return 0;
1017 +}
1018 +
1019 +void __exit lq_gptu_exit(void)
1020 +{
1021 +       unsigned int i;
1022 +
1023 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1024 +               if (timer_dev.timer[i].f_irq_on)
1025 +                       disable_irq(timer_dev.timer[i].irq);
1026 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1027 +       }
1028 +       lq_disable_gptu();
1029 +       misc_deregister(&gptu_miscdev);
1030 +}
1031 +
1032 +module_init(lq_gptu_init);
1033 +module_exit(lq_gptu_exit);
1034 +
1035 +#endif
1036 --
1037 1.7.10.4
1038