target/linux/lantiq/patches-3.9/0009-NET-PHY-adds-driver-for-lantiq-PHY11G.patch

   1 From 615cd43fa886a79cf717bba38a3243aeb3b66217 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 29 Jun 2013 19:13:39 +0200
   4 Subject: [PATCH 09/22] NET: PHY: adds driver for lantiq PHY11G
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/phy/Kconfig  |    5 ++
   9  drivers/net/phy/Makefile |    1 +
  10  drivers/net/phy/lantiq.c |  220 ++++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 226 insertions(+)
  12  create mode 100644 drivers/net/phy/lantiq.c
  13
  14 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
  15 index 4503452..edc61b0 100644
  16 --- a/drivers/net/phy/Kconfig
  17 +++ b/drivers/net/phy/Kconfig
  18 @@ -106,6 +106,11 @@ config MICREL_PHY
  19         ---help---
  20           Supports the KSZ9021, VSC8201, KS8001 PHYs.
  21
  22 +config LANTIQ_PHY
  23 +       tristate "Driver for Lantiq PHYs"
  24 +       ---help---
  25 +         Supports the 11G and 22E PHYs.
  26 +
  27  config FIXED_PHY
  28         bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
  29         depends on PHYLIB=y
  30 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
  31 index 9645e38..e2eeee3 100644
  32 --- a/drivers/net/phy/Makefile
  33 +++ b/drivers/net/phy/Makefile
  34 @@ -23,6 +23,7 @@ obj-$(CONFIG_NATIONAL_PHY)    += national.o
  35  obj-$(CONFIG_DP83640_PHY)      += dp83640.o
  36  obj-$(CONFIG_STE10XP)          += ste10Xp.o
  37  obj-$(CONFIG_MICREL_PHY)       += micrel.o
  38 +obj-$(CONFIG_LANTIQ_PHY)        += lantiq.o
  39  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  40  obj-$(CONFIG_MICREL_KS8995MA)  += spi_ks8995.o
  41  obj-$(CONFIG_AT803X_PHY)       += at803x.o
  42 diff --git a/drivers/net/phy/lantiq.c b/drivers/net/phy/lantiq.c
  43 new file mode 100644
  44 index 0000000..418dff0
  45 --- /dev/null
  46 +++ b/drivers/net/phy/lantiq.c
  47 @@ -0,0 +1,220 @@
  48 +/*
  49 + *   This program is free software; you can redistribute it and/or modify
  50 + *   it under the terms of the GNU General Public License as published by
  51 + *   the Free Software Foundation; either version 2 of the License, or
  52 + *   (at your option) any later version.
  53 + *
  54 + *   This program is distributed in the hope that it will be useful,
  55 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  56 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  57 + *   GNU General Public License for more details.
  58 + *
  59 + *   You should have received a copy of the GNU General Public License
  60 + *   along with this program; if not, write to the Free Software
  61 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  62 + *
  63 + *   Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  64 + */
  65 +
  66 +#include <linux/module.h>
  67 +#include <linux/phy.h>
  68 +
  69 +#define MII_MMDCTRL            0x0d
  70 +#define MII_MMDDATA            0x0e
  71 +
  72 +#define MII_VR9_11G_IMASK      0x19    /* interrupt mask */
  73 +#define MII_VR9_11G_ISTAT      0x1a    /* interrupt status */
  74 +
  75 +#define INT_VR9_11G_WOL                BIT(15) /* Wake-On-LAN */
  76 +#define INT_VR9_11G_ANE                BIT(11) /* Auto-Neg error */
  77 +#define INT_VR9_11G_ANC                BIT(10) /* Auto-Neg complete */
  78 +#define INT_VR9_11G_ADSC       BIT(5)  /* Link auto-downspeed detect */
  79 +#define INT_VR9_11G_DXMC       BIT(2)  /* Duplex mode change */
  80 +#define INT_VR9_11G_LSPC       BIT(1)  /* Link speed change */
  81 +#define INT_VR9_11G_LSTC       BIT(0)  /* Link state change */
  82 +#define INT_VR9_11G_MASK       (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
  83 +
  84 +#define ADVERTISED_MPD         BIT(10) /* Multi-port device */
  85 +
  86 +#define MMD_DEVAD              0x1f
  87 +#define MMD_ACTYPE_SHIFT       14
  88 +#define MMD_ACTYPE_ADDRESS     (0 << MMD_ACTYPE_SHIFT)
  89 +#define MMD_ACTYPE_DATA                (1 << MMD_ACTYPE_SHIFT)
  90 +#define MMD_ACTYPE_DATA_PI     (2 << MMD_ACTYPE_SHIFT)
  91 +#define MMD_ACTYPE_DATA_PIWR   (3 << MMD_ACTYPE_SHIFT)
  92 +
  93 +static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
  94 +                                               u16 regnum)
  95 +{
  96 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
  97 +       phy_write(phydev, MII_MMDDATA, regnum);
  98 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
  99 +
 100 +       return phy_read(phydev, MII_MMDDATA);
 101 +}
 102 +
 103 +static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
 104 +                                               u16 regnum, u16 val)
 105 +{
 106 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
 107 +       phy_write(phydev, MII_MMDDATA, regnum);
 108 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
 109 +       phy_write(phydev, MII_MMDDATA, val);
 110 +
 111 +       return 0;
 112 +}
 113 +
 114 +static int vr9_gphy_config_init(struct phy_device *phydev)
 115 +{
 116 +       int err;
 117 +
 118 +       dev_dbg(&phydev->dev, "%s\n", __func__);
 119 +
 120 +       /* Mask all interrupts */
 121 +       err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 122 +       if (err)
 123 +               return err;
 124 +
 125 +       /* Clear all pending interrupts */
 126 +       phy_read(phydev, MII_VR9_11G_ISTAT);
 127 +
 128 +       return 0;
 129 +}
 130 +
 131 +static int vr9_gphy_config_aneg(struct phy_device *phydev)
 132 +{
 133 +       int reg, err;
 134 +
 135 +       /* Advertise as multi-port device */
 136 +       reg = phy_read(phydev, MII_CTRL1000);
 137 +       reg |= ADVERTISED_MPD;
 138 +       err = phy_write(phydev, MII_CTRL1000, reg);
 139 +       if (err)
 140 +               return err;
 141 +
 142 +       return genphy_config_aneg(phydev);
 143 +}
 144 +
 145 +static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
 146 +{
 147 +       int reg;
 148 +
 149 +       /*
 150 +        * Possible IRQ numbers:
 151 +        * - IM3_IRL18 for GPHY0
 152 +        * - IM3_IRL17 for GPHY1
 153 +        *
 154 +        * Due to a silicon bug IRQ lines are not really independent from
 155 +        * each other. Sometimes the two lines are driven at the same time
 156 +        * if only one GPHY core raises the interrupt.
 157 +        */
 158 +
 159 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 160 +
 161 +       return (reg < 0) ? reg : 0;
 162 +}
 163 +
 164 +static int vr9_gphy_did_interrupt(struct phy_device *phydev)
 165 +{
 166 +       int reg;
 167 +
 168 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 169 +
 170 +       return reg > 0;
 171 +}
 172 +
 173 +static int vr9_gphy_config_intr(struct phy_device *phydev)
 174 +{
 175 +       int err;
 176 +
 177 +       if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 178 +               err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
 179 +       else
 180 +               err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 181 +
 182 +       return err;
 183 +}
 184 +
 185 +static struct phy_driver lantiq_phy[] = {
 186 +       {
 187 +               .phy_id         = 0xd565a400,
 188 +               .phy_id_mask    = 0xffffffff,
 189 +               .name           = "Lantiq XWAY PEF7071",
 190 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 191 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 192 +               .config_init    = vr9_gphy_config_init,
 193 +               .config_aneg    = vr9_gphy_config_aneg,
 194 +               .read_status    = genphy_read_status,
 195 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 196 +               .did_interrupt  = vr9_gphy_did_interrupt,
 197 +               .config_intr    = vr9_gphy_config_intr,
 198 +               .driver         = { .owner = THIS_MODULE },
 199 +       }, {
 200 +               .phy_id         = 0x030260D0,
 201 +               .phy_id_mask    = 0xfffffff0,
 202 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.3",
 203 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 204 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 205 +               .config_init    = vr9_gphy_config_init,
 206 +               .config_aneg    = vr9_gphy_config_aneg,
 207 +               .read_status    = genphy_read_status,
 208 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 209 +               .did_interrupt  = vr9_gphy_did_interrupt,
 210 +               .config_intr    = vr9_gphy_config_intr,
 211 +               .driver         = { .owner = THIS_MODULE },
 212 +       }, {
 213 +               .phy_id         = 0xd565a408,
 214 +               .phy_id_mask    = 0xfffffff8,
 215 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.4",
 216 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 217 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 218 +               .config_init    = vr9_gphy_config_init,
 219 +               .config_aneg    = vr9_gphy_config_aneg,
 220 +               .read_status    = genphy_read_status,
 221 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 222 +               .did_interrupt  = vr9_gphy_did_interrupt,
 223 +               .config_intr    = vr9_gphy_config_intr,
 224 +               .driver         = { .owner = THIS_MODULE },
 225 +       }, {
 226 +               .phy_id         = 0xd565a418,
 227 +               .phy_id_mask    = 0xfffffff8,
 228 +               .name           = "Lantiq XWAY XRX PHY22F v1.4",
 229 +               .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 230 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 231 +               .config_init    = vr9_gphy_config_init,
 232 +               .config_aneg    = vr9_gphy_config_aneg,
 233 +               .read_status    = genphy_read_status,
 234 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 235 +               .did_interrupt  = vr9_gphy_did_interrupt,
 236 +               .config_intr    = vr9_gphy_config_intr,
 237 +               .driver         = { .owner = THIS_MODULE },
 238 +       },
 239 +};
 240 +
 241 +static int __init ltq_phy_init(void)
 242 +{
 243 +       int i;
 244 +
 245 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
 246 +               int err = phy_driver_register(&lantiq_phy[i]);
 247 +               if (err)
 248 +                       pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
 249 +       }
 250 +
 251 +       return 0;
 252 +}
 253 +
 254 +static void __exit ltq_phy_exit(void)
 255 +{
 256 +       int i;
 257 +
 258 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
 259 +               phy_driver_unregister(&lantiq_phy[i]);
 260 +}
 261 +
 262 +module_init(ltq_phy_init);
 263 +module_exit(ltq_phy_exit);
 264 +
 265 +MODULE_DESCRIPTION("Lantiq PHY drivers");
 266 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
 267 +MODULE_LICENSE("GPL");
 268 --
 269 1.7.10.4
 270