target/linux/lantiq/patches-3.8/0039-owrt-lantiq-backport-old-timer-code.patch

   1 From 225313fe4112a487954e7f7e3be995854b7c9ffa Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 13 Mar 2013 10:01:49 +0100
   4 Subject: [PATCH 39/40] owrt: lantiq: backport old timer code
   5
   6 ---
   7  arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
   8  arch/mips/lantiq/xway/Makefile                   |    2 +-
   9  arch/mips/lantiq/xway/timer.c                    |  845 ++++++++++++++++++++++
  10  3 files changed, 1001 insertions(+), 1 deletion(-)
  11  create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  12  create mode 100644 arch/mips/lantiq/xway/timer.c
  13
  14 --- /dev/null
  15 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  16 @@ -0,0 +1,155 @@
  17 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  18 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  19 +
  20 +
  21 +/******************************************************************************
  22 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
  23 +
  24 +                               No Warranty
  25 +   Because the program is licensed free of charge, there is no warranty for
  26 +   the program, to the extent permitted by applicable law.  Except when
  27 +   otherwise stated in writing the copyright holders and/or other parties
  28 +   provide the program "as is" without warranty of any kind, either
  29 +   expressed or implied, including, but not limited to, the implied
  30 +   warranties of merchantability and fitness for a particular purpose. The
  31 +   entire risk as to the quality and performance of the program is with
  32 +   you.  should the program prove defective, you assume the cost of all
  33 +   necessary servicing, repair or correction.
  34 +
  35 +   In no event unless required by applicable law or agreed to in writing
  36 +   will any copyright holder, or any other party who may modify and/or
  37 +   redistribute the program as permitted above, be liable to you for
  38 +   damages, including any general, special, incidental or consequential
  39 +   damages arising out of the use or inability to use the program
  40 +   (including but not limited to loss of data or data being rendered
  41 +   inaccurate or losses sustained by you or third parties or a failure of
  42 +   the program to operate with any other programs), even if such holder or
  43 +   other party has been advised of the possibility of such damages.
  44 +******************************************************************************/
  45 +
  46 +
  47 +/*
  48 + * ####################################
  49 + *              Definition
  50 + * ####################################
  51 + */
  52 +
  53 +/*
  54 + *  Available Timer/Counter Index
  55 + */
  56 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
  57 +#define TIMER_ANY                       0x00
  58 +#define TIMER1A                         TIMER(1, 0)
  59 +#define TIMER1B                         TIMER(1, 1)
  60 +#define TIMER2A                         TIMER(2, 0)
  61 +#define TIMER2B                         TIMER(2, 1)
  62 +#define TIMER3A                         TIMER(3, 0)
  63 +#define TIMER3B                         TIMER(3, 1)
  64 +
  65 +/*
  66 + *  Flag of Timer/Counter
  67 + *  These flags specify the way in which timer is configured.
  68 + */
  69 +/*  Bit size of timer/counter.                      */
  70 +#define TIMER_FLAG_16BIT                0x0000
  71 +#define TIMER_FLAG_32BIT                0x0001
  72 +/*  Switch between timer and counter.               */
  73 +#define TIMER_FLAG_TIMER                0x0000
  74 +#define TIMER_FLAG_COUNTER              0x0002
  75 +/*  Stop or continue when overflowing/underflowing. */
  76 +#define TIMER_FLAG_ONCE                 0x0000
  77 +#define TIMER_FLAG_CYCLIC               0x0004
  78 +/*  Count up or counter down.                       */
  79 +#define TIMER_FLAG_UP                   0x0000
  80 +#define TIMER_FLAG_DOWN                 0x0008
  81 +/*  Count on specific level or edge.                */
  82 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
  83 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
  84 +#define TIMER_FLAG_RISE_EDGE            0x0010
  85 +#define TIMER_FLAG_FALL_EDGE            0x0020
  86 +#define TIMER_FLAG_ANY_EDGE             0x0030
  87 +/*  Signal is syncronous to module clock or not.    */
  88 +#define TIMER_FLAG_UNSYNC               0x0000
  89 +#define TIMER_FLAG_SYNC                 0x0080
  90 +/*  Different interrupt handle type.                */
  91 +#define TIMER_FLAG_NO_HANDLE            0x0000
  92 +#if defined(__KERNEL__)
  93 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
  94 +#endif  //  defined(__KERNEL__)
  95 +#define TIMER_FLAG_SIGNAL               0x0300
  96 +/*  Internal clock source or external clock source  */
  97 +#define TIMER_FLAG_INT_SRC              0x0000
  98 +#define TIMER_FLAG_EXT_SRC              0x1000
  99 +
 100 +
 101 +/*
 102 + *  ioctl Command
 103 + */
 104 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 105 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 106 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 107 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 108 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 109 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 110 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 111 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 112 +
 113 +/*
 114 + *  Data Type Used to Call ioctl
 115 + */
 116 +struct gptu_ioctl_param {
 117 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 118 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 119 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 120 +                                                 *  be dynamically allocated and ID would be stored in  *
 121 +                                                 *  this field.                                         *
 122 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 123 +                                                 *  ignored.                                            *
 124 +                                                 *  In other command, this field is ID of timer/counter *
 125 +                                                 *  allocated.                                          */
 126 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 127 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 128 +                                                 *  specify how to configure timer/counter.             *
 129 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 130 +                                                 *  and non-zero indicate resume timer/counter.         *
 131 +                                                 *  In other command, this field is ignored.            */
 132 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 133 +                                                 *  init/reload value.                                  *
 134 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 135 +                                                 *  frequency (0.001Hz) of timer.                       *
 136 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 137 +                                                 *  value would be stored in this field.                *
 138 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 139 +                                                 *  contains frequency wanted, and after calculation,   *
 140 +                                                 *  divider would be stored in this field to overwrite  *
 141 +                                                 *  the frequency.                                      *
 142 +                                                 *  In other command, this field is ignored.            */
 143 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 144 +                                                 *  if signal is required, this field contains process  *
 145 +                                                 *  ID to which signal would be sent.                   *
 146 +                                                 *  In other command, this field is ignored.            */
 147 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 148 +                                                 *  if signal is required, this field contains signal   *
 149 +                                                 *  number which would be sent.                         *
 150 +                                                 *  In other command, this field is ignored.            */
 151 +};
 152 +
 153 +/*
 154 + * ####################################
 155 + *              Data Type
 156 + * ####################################
 157 + */
 158 +typedef void (*timer_callback)(unsigned long arg);
 159 +
 160 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
 161 +extern int lq_free_timer(unsigned int);
 162 +extern int lq_start_timer(unsigned int, int);
 163 +extern int lq_stop_timer(unsigned int);
 164 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
 165 +extern int lq_get_count_value(unsigned int, unsigned long *);
 166 +extern u32 lq_cal_divider(unsigned long);
 167 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
 168 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
 169 +       u32 reload, unsigned long arg1, unsigned long arg2);
 170 +
 171 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
 172 --- a/arch/mips/lantiq/xway/Makefile
 173 +++ b/arch/mips/lantiq/xway/Makefile
 174 @@ -1,4 +1,4 @@
 175 -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
 176 +obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o
 177
 178  obj-y += eth_mac.o vmmc.o
 179  obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o
 180 --- /dev/null
 181 +++ b/arch/mips/lantiq/xway/timer.c
 182 @@ -0,0 +1,845 @@
 183 +#ifndef CONFIG_SOC_AMAZON_SE
 184 +
 185 +#include <linux/kernel.h>
 186 +#include <linux/module.h>
 187 +#include <linux/version.h>
 188 +#include <linux/types.h>
 189 +#include <linux/fs.h>
 190 +#include <linux/miscdevice.h>
 191 +#include <linux/init.h>
 192 +#include <linux/uaccess.h>
 193 +#include <linux/unistd.h>
 194 +#include <linux/errno.h>
 195 +#include <linux/interrupt.h>
 196 +#include <linux/sched.h>
 197 +
 198 +#include <asm/irq.h>
 199 +#include <asm/div64.h>
 200 +#include "../clk.h"
 201 +
 202 +#include <lantiq_soc.h>
 203 +#include <lantiq_irq.h>
 204 +#include <lantiq_timer.h>
 205 +
 206 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
 207 +
 208 +#ifdef TIMER1A
 209 +#define FIRST_TIMER                    TIMER1A
 210 +#else
 211 +#define FIRST_TIMER                    2
 212 +#endif
 213 +
 214 +/*
 215 + *  GPTC divider is set or not.
 216 + */
 217 +#define GPTU_CLC_RMC_IS_SET            0
 218 +
 219 +/*
 220 + *  Timer Interrupt (IRQ)
 221 + */
 222 +/*  Must be adjusted when ICU driver is available */
 223 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
 224 +
 225 +/*
 226 + *  Bits Operation
 227 + */
 228 +#define GET_BITS(x, msb, lsb)          \
 229 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
 230 +#define SET_BITS(x, msb, lsb, value)   \
 231 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
 232 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
 233 +
 234 +/*
 235 + *  GPTU Register Mapping
 236 + */
 237 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
 238 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
 239 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
 240 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 241 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 242 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 243 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 244 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
 245 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
 246 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
 247 +
 248 +/*
 249 + *  Clock Control Register
 250 + */
 251 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
 252 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
 253 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
 254 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
 255 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
 256 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
 257 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
 258 +
 259 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
 260 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
 261 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
 262 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
 263 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
 264 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
 265 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
 266 +
 267 +/*
 268 + *  ID Register
 269 + */
 270 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
 271 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
 272 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
 273 +
 274 +/*
 275 + *  Control Register of Timer/Counter nX
 276 + *    n is the index of block (1 based index)
 277 + *    X is either A or B
 278 + */
 279 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 280 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 281 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 282 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 283 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 284 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 285 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 286 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 287 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 288 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 289 +
 290 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 291 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 292 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 293 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 294 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 295 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 296 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 297 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 298 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 299 +
 300 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 301 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 302 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 303 +
 304 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 305 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 306 +
 307 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 308 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 309 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 310 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 311 +#define TIMER_FLAG_NONE_EDGE           0x0000
 312 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 313 +#define TIMER_FLAG_REAL                        0x0000
 314 +#define TIMER_FLAG_INVERT              0x0040
 315 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 316 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 317 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 318 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 319 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 320 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 321 +
 322 +struct timer_dev_timer {
 323 +       unsigned int f_irq_on;
 324 +       unsigned int irq;
 325 +       unsigned int flag;
 326 +       unsigned long arg1;
 327 +       unsigned long arg2;
 328 +};
 329 +
 330 +struct timer_dev {
 331 +       struct mutex gptu_mutex;
 332 +       unsigned int number_of_timers;
 333 +       unsigned int occupation;
 334 +       unsigned int f_gptu_on;
 335 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 336 +};
 337 +
 338 +
 339 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 340 +       struct clk *clk = clk_get_fpi();
 341 +       return clk_get_rate(clk);
 342 +}
 343 +
 344 +
 345 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 346 +static int gptu_open(struct inode *, struct file *);
 347 +static int gptu_release(struct inode *, struct file *);
 348 +
 349 +static struct file_operations gptu_fops = {
 350 +       .owner = THIS_MODULE,
 351 +       .unlocked_ioctl = gptu_ioctl,
 352 +       .open = gptu_open,
 353 +       .release = gptu_release
 354 +};
 355 +
 356 +static struct miscdevice gptu_miscdev = {
 357 +       .minor = MISC_DYNAMIC_MINOR,
 358 +       .name = "gptu",
 359 +       .fops = &gptu_fops,
 360 +};
 361 +
 362 +static struct timer_dev timer_dev;
 363 +
 364 +static irqreturn_t timer_irq_handler(int irq, void *p)
 365 +{
 366 +       unsigned int timer;
 367 +       unsigned int flag;
 368 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 369 +
 370 +       timer = irq - TIMER_INTERRUPT;
 371 +       if (timer < timer_dev.number_of_timers
 372 +               && dev_timer == &timer_dev.timer[timer]) {
 373 +               /*  Clear interrupt.    */
 374 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 375 +
 376 +               /*  Call user hanler or signal. */
 377 +               flag = dev_timer->flag;
 378 +               if (!(timer & 0x01)
 379 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 380 +                       /* 16-bit timer or timer A of 32-bit timer  */
 381 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 382 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 383 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 384 +                               if (dev_timer->arg1)
 385 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 386 +                               break;
 387 +                       case TIMER_FLAG_SIGNAL:
 388 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 389 +                               break;
 390 +                       }
 391 +               }
 392 +       }
 393 +       return IRQ_HANDLED;
 394 +}
 395 +
 396 +static inline void lq_enable_gptu(void)
 397 +{
 398 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 399 +       clk_enable(clk);
 400 +
 401 +       //ltq_pmu_enable(PMU_GPT);
 402 +
 403 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 404 +       *LQ_GPTU_CLC =
 405 +               GPTU_CLC_SMC_SET(0x00) |
 406 +               GPTU_CLC_RMC_SET(0x01) |
 407 +               GPTU_CLC_FSOE_SET(0) |
 408 +               GPTU_CLC_SBWE_SET(1) |
 409 +               GPTU_CLC_EDIS_SET(0) |
 410 +               GPTU_CLC_SPEN_SET(0) |
 411 +               GPTU_CLC_DISR_SET(0);
 412 +}
 413 +
 414 +static inline void lq_disable_gptu(void)
 415 +{
 416 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 417 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 418 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 419 +
 420 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 421 +       *LQ_GPTU_CLC =
 422 +               GPTU_CLC_SMC_SET(0x00) |
 423 +               GPTU_CLC_RMC_SET(0x00) |
 424 +               GPTU_CLC_FSOE_SET(0) |
 425 +               GPTU_CLC_SBWE_SET(0) |
 426 +               GPTU_CLC_EDIS_SET(0) |
 427 +               GPTU_CLC_SPEN_SET(0) |
 428 +               GPTU_CLC_DISR_SET(1);
 429 +
 430 +       clk_enable(clk);
 431 +}
 432 +
 433 +int lq_request_timer(unsigned int timer, unsigned int flag,
 434 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 435 +{
 436 +       int ret = 0;
 437 +       unsigned int con_reg, irnen_reg;
 438 +       int n, X;
 439 +
 440 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 441 +               return -EINVAL;
 442 +
 443 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 444 +               timer, flag, value);
 445 +
 446 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 447 +               value &= 0xFFFF;
 448 +       else
 449 +               timer &= ~0x01;
 450 +
 451 +       mutex_lock(&timer_dev.gptu_mutex);
 452 +
 453 +       /*
 454 +        *  Allocate timer.
 455 +        */
 456 +       if (timer < FIRST_TIMER) {
 457 +               unsigned int mask;
 458 +               unsigned int shift;
 459 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 460 +               unsigned int offset = TIMER2A;
 461 +
 462 +               /*
 463 +                *  Pick up a free timer.
 464 +                */
 465 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 466 +                       mask = 1 << offset;
 467 +                       shift = 1;
 468 +               } else {
 469 +                       mask = 3 << offset;
 470 +                       shift = 2;
 471 +               }
 472 +               for (timer = offset;
 473 +                    timer < offset + timer_dev.number_of_timers;
 474 +                    timer += shift, mask <<= shift)
 475 +                       if (!(timer_dev.occupation & mask)) {
 476 +                               timer_dev.occupation |= mask;
 477 +                               break;
 478 +                       }
 479 +               if (timer >= offset + timer_dev.number_of_timers) {
 480 +                       printk("failed![%d]\n", __LINE__);
 481 +                       mutex_unlock(&timer_dev.gptu_mutex);
 482 +                       return -EINVAL;
 483 +               } else
 484 +                       ret = timer;
 485 +       } else {
 486 +               register unsigned int mask;
 487 +
 488 +               /*
 489 +                *  Check if the requested timer is free.
 490 +                */
 491 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 492 +               if ((timer_dev.occupation & mask)) {
 493 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 494 +                               __LINE__, mask, timer_dev.occupation);
 495 +                       mutex_unlock(&timer_dev.gptu_mutex);
 496 +                       return -EBUSY;
 497 +               } else {
 498 +                       timer_dev.occupation |= mask;
 499 +                       ret = 0;
 500 +               }
 501 +       }
 502 +
 503 +       /*
 504 +        *  Prepare control register value.
 505 +        */
 506 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 507 +       default:
 508 +       case TIMER_FLAG_NONE_EDGE:
 509 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 510 +               break;
 511 +       case TIMER_FLAG_RISE_EDGE:
 512 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 513 +               break;
 514 +       case TIMER_FLAG_FALL_EDGE:
 515 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 516 +               break;
 517 +       case TIMER_FLAG_ANY_EDGE:
 518 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 519 +               break;
 520 +       }
 521 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 522 +               con_reg |=
 523 +                       TIMER_FLAG_MASK_SRC(flag) ==
 524 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 525 +                       GPTU_CON_SRC_EXT_SET(0);
 526 +       else
 527 +               con_reg |=
 528 +                       TIMER_FLAG_MASK_SRC(flag) ==
 529 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 530 +                       GPTU_CON_SRC_EG_SET(0);
 531 +       con_reg |=
 532 +               TIMER_FLAG_MASK_SYNC(flag) ==
 533 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 534 +               GPTU_CON_SYNC_SET(1);
 535 +       con_reg |=
 536 +               TIMER_FLAG_MASK_INVERT(flag) ==
 537 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 538 +       con_reg |=
 539 +               TIMER_FLAG_MASK_SIZE(flag) ==
 540 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 541 +               GPTU_CON_EXT_SET(1);
 542 +       con_reg |=
 543 +               TIMER_FLAG_MASK_STOP(flag) ==
 544 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 545 +       con_reg |=
 546 +               TIMER_FLAG_MASK_TYPE(flag) ==
 547 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 548 +               GPTU_CON_CNT_SET(1);
 549 +       con_reg |=
 550 +               TIMER_FLAG_MASK_DIR(flag) ==
 551 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 552 +
 553 +       /*
 554 +        *  Fill up running data.
 555 +        */
 556 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 557 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 558 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 559 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 560 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 561 +
 562 +       /*
 563 +        *  Enable GPTU module.
 564 +        */
 565 +       if (!timer_dev.f_gptu_on) {
 566 +               lq_enable_gptu();
 567 +               timer_dev.f_gptu_on = 1;
 568 +       }
 569 +
 570 +       /*
 571 +        *  Enable IRQ.
 572 +        */
 573 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 574 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 575 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 576 +                               (unsigned long) find_task_by_vpid((int) arg1);
 577 +
 578 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 579 +
 580 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 581 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 582 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 583 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 584 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 585 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 586 +               }
 587 +       } else
 588 +               irnen_reg = 0;
 589 +
 590 +       /*
 591 +        *  Write config register, reload value and enable interrupt.
 592 +        */
 593 +       n = timer >> 1;
 594 +       X = timer & 0x01;
 595 +       *LQ_GPTU_CON(n, X) = con_reg;
 596 +       *LQ_GPTU_RELOAD(n, X) = value;
 597 +       /* printk("reload value = %d\n", (u32)value); */
 598 +       *LQ_GPTU_IRNEN |= irnen_reg;
 599 +
 600 +       mutex_unlock(&timer_dev.gptu_mutex);
 601 +       printk("successful!\n");
 602 +       return ret;
 603 +}
 604 +EXPORT_SYMBOL(lq_request_timer);
 605 +
 606 +int lq_free_timer(unsigned int timer)
 607 +{
 608 +       unsigned int flag;
 609 +       unsigned int mask;
 610 +       int n, X;
 611 +
 612 +       if (!timer_dev.f_gptu_on)
 613 +               return -EINVAL;
 614 +
 615 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 616 +               return -EINVAL;
 617 +
 618 +       mutex_lock(&timer_dev.gptu_mutex);
 619 +
 620 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 621 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 622 +               timer &= ~0x01;
 623 +
 624 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 625 +       if (((timer_dev.occupation & mask) ^ mask)) {
 626 +               mutex_unlock(&timer_dev.gptu_mutex);
 627 +               return -EINVAL;
 628 +       }
 629 +
 630 +       n = timer >> 1;
 631 +       X = timer & 0x01;
 632 +
 633 +       if (GPTU_CON_EN(n, X))
 634 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 635 +
 636 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 637 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 638 +
 639 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 640 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 641 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 642 +       }
 643 +
 644 +       timer_dev.occupation &= ~mask;
 645 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 646 +               lq_disable_gptu();
 647 +               timer_dev.f_gptu_on = 0;
 648 +       }
 649 +
 650 +       mutex_unlock(&timer_dev.gptu_mutex);
 651 +
 652 +       return 0;
 653 +}
 654 +EXPORT_SYMBOL(lq_free_timer);
 655 +
 656 +int lq_start_timer(unsigned int timer, int is_resume)
 657 +{
 658 +       unsigned int flag;
 659 +       unsigned int mask;
 660 +       int n, X;
 661 +
 662 +       if (!timer_dev.f_gptu_on)
 663 +               return -EINVAL;
 664 +
 665 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 666 +               return -EINVAL;
 667 +
 668 +       mutex_lock(&timer_dev.gptu_mutex);
 669 +
 670 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 671 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 672 +               timer &= ~0x01;
 673 +
 674 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 675 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 676 +       if (((timer_dev.occupation & mask) ^ mask)) {
 677 +               mutex_unlock(&timer_dev.gptu_mutex);
 678 +               return -EINVAL;
 679 +       }
 680 +
 681 +       n = timer >> 1;
 682 +       X = timer & 0x01;
 683 +
 684 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 685 +
 686 +
 687 +       mutex_unlock(&timer_dev.gptu_mutex);
 688 +
 689 +       return 0;
 690 +}
 691 +EXPORT_SYMBOL(lq_start_timer);
 692 +
 693 +int lq_stop_timer(unsigned int timer)
 694 +{
 695 +       unsigned int flag;
 696 +       unsigned int mask;
 697 +       int n, X;
 698 +
 699 +       if (!timer_dev.f_gptu_on)
 700 +               return -EINVAL;
 701 +
 702 +       if (timer < FIRST_TIMER
 703 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 704 +               return -EINVAL;
 705 +
 706 +       mutex_lock(&timer_dev.gptu_mutex);
 707 +
 708 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 709 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 710 +               timer &= ~0x01;
 711 +
 712 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 713 +       if (((timer_dev.occupation & mask) ^ mask)) {
 714 +               mutex_unlock(&timer_dev.gptu_mutex);
 715 +               return -EINVAL;
 716 +       }
 717 +
 718 +       n = timer >> 1;
 719 +       X = timer & 0x01;
 720 +
 721 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 722 +
 723 +       mutex_unlock(&timer_dev.gptu_mutex);
 724 +
 725 +       return 0;
 726 +}
 727 +EXPORT_SYMBOL(lq_stop_timer);
 728 +
 729 +int lq_reset_counter_flags(u32 timer, u32 flags)
 730 +{
 731 +       unsigned int oflag;
 732 +       unsigned int mask, con_reg;
 733 +       int n, X;
 734 +
 735 +       if (!timer_dev.f_gptu_on)
 736 +               return -EINVAL;
 737 +
 738 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 739 +               return -EINVAL;
 740 +
 741 +       mutex_lock(&timer_dev.gptu_mutex);
 742 +
 743 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 744 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 745 +               timer &= ~0x01;
 746 +
 747 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 748 +       if (((timer_dev.occupation & mask) ^ mask)) {
 749 +               mutex_unlock(&timer_dev.gptu_mutex);
 750 +               return -EINVAL;
 751 +       }
 752 +
 753 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 754 +       default:
 755 +       case TIMER_FLAG_NONE_EDGE:
 756 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 757 +               break;
 758 +       case TIMER_FLAG_RISE_EDGE:
 759 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 760 +               break;
 761 +       case TIMER_FLAG_FALL_EDGE:
 762 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 763 +               break;
 764 +       case TIMER_FLAG_ANY_EDGE:
 765 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 766 +               break;
 767 +       }
 768 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 769 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 770 +       else
 771 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 772 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 773 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 774 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 775 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 776 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 777 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 778 +
 779 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 780 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 781 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 782 +
 783 +       n = timer >> 1;
 784 +       X = timer & 0x01;
 785 +
 786 +       *LQ_GPTU_CON(n, X) = con_reg;
 787 +       smp_wmb();
 788 +       mutex_unlock(&timer_dev.gptu_mutex);
 789 +       return 0;
 790 +}
 791 +EXPORT_SYMBOL(lq_reset_counter_flags);
 792 +
 793 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 794 +{
 795 +       unsigned int flag;
 796 +       unsigned int mask;
 797 +       int n, X;
 798 +
 799 +       if (!timer_dev.f_gptu_on)
 800 +               return -EINVAL;
 801 +
 802 +       if (timer < FIRST_TIMER
 803 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 804 +               return -EINVAL;
 805 +
 806 +       mutex_lock(&timer_dev.gptu_mutex);
 807 +
 808 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 809 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 810 +               timer &= ~0x01;
 811 +
 812 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 813 +       if (((timer_dev.occupation & mask) ^ mask)) {
 814 +               mutex_unlock(&timer_dev.gptu_mutex);
 815 +               return -EINVAL;
 816 +       }
 817 +
 818 +       n = timer >> 1;
 819 +       X = timer & 0x01;
 820 +
 821 +       *value = *LQ_GPTU_COUNT(n, X);
 822 +
 823 +
 824 +       mutex_unlock(&timer_dev.gptu_mutex);
 825 +
 826 +       return 0;
 827 +}
 828 +EXPORT_SYMBOL(lq_get_count_value);
 829 +
 830 +u32 lq_cal_divider(unsigned long freq)
 831 +{
 832 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 833 +       u32 clock_divider = 1;
 834 +       module_freq = fpi * 1000;
 835 +       do_div(module_freq, clock_divider * freq);
 836 +       return module_freq;
 837 +}
 838 +EXPORT_SYMBOL(lq_cal_divider);
 839 +
 840 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 841 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 842 +       unsigned long arg2)
 843 +{
 844 +       unsigned long divider;
 845 +       unsigned int flag;
 846 +
 847 +       divider = lq_cal_divider(freq);
 848 +       if (divider == 0)
 849 +               return -EINVAL;
 850 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 851 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 852 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 853 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 854 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 855 +
 856 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 857 +               timer, freq, divider);
 858 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 859 +}
 860 +EXPORT_SYMBOL(lq_set_timer);
 861 +
 862 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 863 +       unsigned long arg1, unsigned long arg2)
 864 +{
 865 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 866 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 867 +}
 868 +EXPORT_SYMBOL(lq_set_counter);
 869 +
 870 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 871 +       unsigned long arg)
 872 +{
 873 +       int ret;
 874 +       struct gptu_ioctl_param param;
 875 +
 876 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 877 +               return -EFAULT;
 878 +       copy_from_user(&param, (void *) arg, sizeof(param));
 879 +
 880 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 881 +              || GPTU_SET_COUNTER) && param.timer < 2)
 882 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 883 +           && !access_ok(VERIFY_WRITE, arg,
 884 +                          sizeof(struct gptu_ioctl_param)))
 885 +               return -EFAULT;
 886 +
 887 +       switch (cmd) {
 888 +       case GPTU_REQUEST_TIMER:
 889 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 890 +                                    (unsigned long) param.pid,
 891 +                                    (unsigned long) param.sig);
 892 +               if (ret > 0) {
 893 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 894 +                                     timer, &ret, sizeof(&ret));
 895 +                       ret = 0;
 896 +               }
 897 +               break;
 898 +       case GPTU_FREE_TIMER:
 899 +               ret = lq_free_timer(param.timer);
 900 +               break;
 901 +       case GPTU_START_TIMER:
 902 +               ret = lq_start_timer(param.timer, param.flag);
 903 +               break;
 904 +       case GPTU_STOP_TIMER:
 905 +               ret = lq_stop_timer(param.timer);
 906 +               break;
 907 +       case GPTU_GET_COUNT_VALUE:
 908 +               ret = lq_get_count_value(param.timer, &param.value);
 909 +               if (!ret)
 910 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 911 +                                     value, &param.value,
 912 +                                     sizeof(param.value));
 913 +               break;
 914 +       case GPTU_CALCULATE_DIVIDER:
 915 +               param.value = lq_cal_divider(param.value);
 916 +               if (param.value == 0)
 917 +                       ret = -EINVAL;
 918 +               else {
 919 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 920 +                                     value, &param.value,
 921 +                                     sizeof(param.value));
 922 +                       ret = 0;
 923 +               }
 924 +               break;
 925 +       case GPTU_SET_TIMER:
 926 +               ret = lq_set_timer(param.timer, param.value,
 927 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 928 +                                TIMER_FLAG_ONCE ? 1 : 0,
 929 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 930 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 931 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 932 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 933 +                                TIMER_FLAG_NO_HANDLE,
 934 +                                (unsigned long) param.pid,
 935 +                                (unsigned long) param.sig);
 936 +               if (ret > 0) {
 937 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 938 +                                     timer, &ret, sizeof(&ret));
 939 +                       ret = 0;
 940 +               }
 941 +               break;
 942 +       case GPTU_SET_COUNTER:
 943 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 944 +               if (ret > 0) {
 945 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 946 +                                     timer, &ret, sizeof(&ret));
 947 +                       ret = 0;
 948 +               }
 949 +               break;
 950 +       default:
 951 +               ret = -ENOTTY;
 952 +       }
 953 +
 954 +       return ret;
 955 +}
 956 +
 957 +static int gptu_open(struct inode *inode, struct file *file)
 958 +{
 959 +       return 0;
 960 +}
 961 +
 962 +static int gptu_release(struct inode *inode, struct file *file)
 963 +{
 964 +       return 0;
 965 +}
 966 +
 967 +int __init lq_gptu_init(void)
 968 +{
 969 +       int ret;
 970 +       unsigned int i;
 971 +
 972 +       ltq_w32(0, LQ_GPTU_IRNEN);
 973 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 974 +
 975 +       memset(&timer_dev, 0, sizeof(timer_dev));
 976 +       mutex_init(&timer_dev.gptu_mutex);
 977 +
 978 +       lq_enable_gptu();
 979 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 980 +       lq_disable_gptu();
 981 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 982 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 983 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 984 +
 985 +       ret = misc_register(&gptu_miscdev);
 986 +       if (ret) {
 987 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
 988 +               return ret;
 989 +       } else {
 990 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
 991 +       }
 992 +
 993 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 994 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
 995 +               if (ret) {
 996 +                       for (; i >= 0; i--)
 997 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
 998 +                       misc_deregister(&gptu_miscdev);
 999 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
1000 +                       return ret;
1001 +               } else {
1002 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
1003 +                       disable_irq(timer_dev.timer[i].irq);
1004 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
1005 +               }
1006 +       }
1007 +
1008 +       return 0;
1009 +}
1010 +
1011 +void __exit lq_gptu_exit(void)
1012 +{
1013 +       unsigned int i;
1014 +
1015 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1016 +               if (timer_dev.timer[i].f_irq_on)
1017 +                       disable_irq(timer_dev.timer[i].irq);
1018 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1019 +       }
1020 +       lq_disable_gptu();
1021 +       misc_deregister(&gptu_miscdev);
1022 +}
1023 +
1024 +module_init(lq_gptu_init);
1025 +module_exit(lq_gptu_exit);
1026 +
1027 +#endif