target/linux/lantiq/patches-3.8/0027-NET-PHY-adds-driver-for-lantiq-PHY11G.patch

   1 From 0721e9f0502e633390044e651970692213283686 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 13 Mar 2013 09:30:22 +0100
   4 Subject: [PATCH 27/40] NET: PHY: adds driver for lantiq PHY11G
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/phy/Kconfig  |    5 ++
   9  drivers/net/phy/Makefile |    1 +
  10  drivers/net/phy/lantiq.c |  220 ++++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 226 insertions(+)
  12  create mode 100644 drivers/net/phy/lantiq.c
  13
  14 Index: linux-3.8.13/drivers/net/phy/Kconfig
  15 ===================================================================
  16 --- linux-3.8.13.orig/drivers/net/phy/Kconfig   2013-07-29 14:53:02.281688583 +0200
  17 +++ linux-3.8.13/drivers/net/phy/Kconfig        2013-07-29 14:53:04.033688626 +0200
  18 @@ -150,6 +150,11 @@
  19         ---help---
  20           Currently has a driver for the KSZ8041
  21
  22 +config LANTIQ_PHY
  23 +       tristate "Driver for Lantiq PHYs"
  24 +       ---help---
  25 +         Supports the 11G and 22E PHYs.
  26 +
  27  config FIXED_PHY
  28         bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
  29         depends on PHYLIB=y
  30 Index: linux-3.8.13/drivers/net/phy/Makefile
  31 ===================================================================
  32 --- linux-3.8.13.orig/drivers/net/phy/Makefile  2013-07-29 14:53:02.281688583 +0200
  33 +++ linux-3.8.13/drivers/net/phy/Makefile       2013-07-29 14:53:04.033688626 +0200
  34 @@ -39,6 +39,7 @@
  35  obj-$(CONFIG_DP83640_PHY)      += dp83640.o
  36  obj-$(CONFIG_STE10XP)          += ste10Xp.o
  37  obj-$(CONFIG_MICREL_PHY)       += micrel.o
  38 +obj-$(CONFIG_LANTIQ_PHY)        += lantiq.o
  39  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  40  obj-$(CONFIG_MICREL_KS8995MA)  += spi_ks8995.o
  41  obj-$(CONFIG_AT803X_PHY)       += at803x.o
  42 Index: linux-3.8.13/drivers/net/phy/lantiq.c
  43 ===================================================================
  44 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  45 +++ linux-3.8.13/drivers/net/phy/lantiq.c       2013-07-29 14:53:30.029689243 +0200
  46 @@ -0,0 +1,231 @@
  47 +/*
  48 + *   This program is free software; you can redistribute it and/or modify
  49 + *   it under the terms of the GNU General Public License as published by
  50 + *   the Free Software Foundation; either version 2 of the License, or
  51 + *   (at your option) any later version.
  52 + *
  53 + *   This program is distributed in the hope that it will be useful,
  54 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  55 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  56 + *   GNU General Public License for more details.
  57 + *
  58 + *   You should have received a copy of the GNU General Public License
  59 + *   along with this program; if not, write to the Free Software
  60 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  61 + *
  62 + *   Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  63 + */
  64 +
  65 +#include <linux/module.h>
  66 +#include <linux/phy.h>
  67 +
  68 +#define MII_MMDCTRL            0x0d
  69 +#define MII_MMDDATA            0x0e
  70 +
  71 +#define MII_VR9_11G_IMASK      0x19    /* interrupt mask */
  72 +#define MII_VR9_11G_ISTAT      0x1a    /* interrupt status */
  73 +
  74 +#define INT_VR9_11G_WOL                BIT(15) /* Wake-On-LAN */
  75 +#define INT_VR9_11G_ANE                BIT(11) /* Auto-Neg error */
  76 +#define INT_VR9_11G_ANC                BIT(10) /* Auto-Neg complete */
  77 +#define INT_VR9_11G_ADSC       BIT(5)  /* Link auto-downspeed detect */
  78 +#define INT_VR9_11G_DXMC       BIT(2)  /* Duplex mode change */
  79 +#define INT_VR9_11G_LSPC       BIT(1)  /* Link speed change */
  80 +#define INT_VR9_11G_LSTC       BIT(0)  /* Link state change */
  81 +#define INT_VR9_11G_MASK       (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
  82 +
  83 +#define ADVERTISED_MPD         BIT(10) /* Multi-port device */
  84 +
  85 +#define MMD_DEVAD              0x1f
  86 +#define MMD_ACTYPE_SHIFT       14
  87 +#define MMD_ACTYPE_ADDRESS     (0 << MMD_ACTYPE_SHIFT)
  88 +#define MMD_ACTYPE_DATA                (1 << MMD_ACTYPE_SHIFT)
  89 +#define MMD_ACTYPE_DATA_PI     (2 << MMD_ACTYPE_SHIFT)
  90 +#define MMD_ACTYPE_DATA_PIWR   (3 << MMD_ACTYPE_SHIFT)
  91 +
  92 +static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
  93 +                                               u16 regnum)
  94 +{
  95 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
  96 +       phy_write(phydev, MII_MMDDATA, regnum);
  97 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
  98 +
  99 +       return phy_read(phydev, MII_MMDDATA);
 100 +}
 101 +
 102 +static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
 103 +                                               u16 regnum, u16 val)
 104 +{
 105 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
 106 +       phy_write(phydev, MII_MMDDATA, regnum);
 107 +       phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
 108 +       phy_write(phydev, MII_MMDDATA, val);
 109 +
 110 +       return 0;
 111 +}
 112 +
 113 +static int vr9_gphy_config_init(struct phy_device *phydev)
 114 +{
 115 +       int err;
 116 +
 117 +       dev_dbg(&phydev->dev, "%s\n", __func__);
 118 +
 119 +       /* Mask all interrupts */
 120 +       err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 121 +       if (err)
 122 +               return err;
 123 +
 124 +       /* Clear all pending interrupts */
 125 +       phy_read(phydev, MII_VR9_11G_ISTAT);
 126 +
 127 +       vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5);
 128 +       vr9_gphy_mmd_write(phydev, 0x1e1, 0x67);
 129 +       vr9_gphy_mmd_write(phydev, 0x1e2, 0x42);
 130 +       vr9_gphy_mmd_write(phydev, 0x1e3, 0x10);
 131 +       vr9_gphy_mmd_write(phydev, 0x1e4, 0x70);
 132 +       vr9_gphy_mmd_write(phydev, 0x1e5, 0x03);
 133 +       vr9_gphy_mmd_write(phydev, 0x1e6, 0x20);
 134 +       vr9_gphy_mmd_write(phydev, 0x1e7, 0x00);
 135 +       vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);
 136 +       vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);
 137 +
 138 +       return 0;
 139 +}
 140 +
 141 +static int vr9_gphy_config_aneg(struct phy_device *phydev)
 142 +{
 143 +       int reg, err;
 144 +
 145 +       /* Advertise as multi-port device */
 146 +       reg = phy_read(phydev, MII_CTRL1000);
 147 +       reg |= ADVERTISED_MPD;
 148 +       err = phy_write(phydev, MII_CTRL1000, reg);
 149 +       if (err)
 150 +               return err;
 151 +
 152 +       return genphy_config_aneg(phydev);
 153 +}
 154 +
 155 +static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
 156 +{
 157 +       int reg;
 158 +
 159 +       /*
 160 +        * Possible IRQ numbers:
 161 +        * - IM3_IRL18 for GPHY0
 162 +        * - IM3_IRL17 for GPHY1
 163 +        *
 164 +        * Due to a silicon bug IRQ lines are not really independent from
 165 +        * each other. Sometimes the two lines are driven at the same time
 166 +        * if only one GPHY core raises the interrupt.
 167 +        */
 168 +
 169 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 170 +
 171 +       return (reg < 0) ? reg : 0;
 172 +}
 173 +
 174 +static int vr9_gphy_did_interrupt(struct phy_device *phydev)
 175 +{
 176 +       int reg;
 177 +
 178 +       reg = phy_read(phydev, MII_VR9_11G_ISTAT);
 179 +
 180 +       return reg > 0;
 181 +}
 182 +
 183 +static int vr9_gphy_config_intr(struct phy_device *phydev)
 184 +{
 185 +       int err;
 186 +
 187 +       if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 188 +               err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
 189 +       else
 190 +               err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
 191 +
 192 +       return err;
 193 +}
 194 +
 195 +static struct phy_driver lantiq_phy[] = {
 196 +       {
 197 +               .phy_id         = 0xd565a400,
 198 +               .phy_id_mask    = 0xffffffff,
 199 +               .name           = "Lantiq XWAY PEF7071",
 200 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 201 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 202 +               .config_init    = vr9_gphy_config_init,
 203 +               .config_aneg    = vr9_gphy_config_aneg,
 204 +               .read_status    = genphy_read_status,
 205 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 206 +               .did_interrupt  = vr9_gphy_did_interrupt,
 207 +               .config_intr    = vr9_gphy_config_intr,
 208 +               .driver         = { .owner = THIS_MODULE },
 209 +       }, {
 210 +               .phy_id         = 0x030260D0,
 211 +               .phy_id_mask    = 0xfffffff0,
 212 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.3",
 213 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 214 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 215 +               .config_init    = vr9_gphy_config_init,
 216 +               .config_aneg    = vr9_gphy_config_aneg,
 217 +               .read_status    = genphy_read_status,
 218 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 219 +               .did_interrupt  = vr9_gphy_did_interrupt,
 220 +               .config_intr    = vr9_gphy_config_intr,
 221 +               .driver         = { .owner = THIS_MODULE },
 222 +       }, {
 223 +               .phy_id         = 0xd565a408,
 224 +               .phy_id_mask    = 0xfffffff8,
 225 +               .name           = "Lantiq XWAY VR9 GPHY 11G v1.4",
 226 +               .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 227 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 228 +               .config_init    = vr9_gphy_config_init,
 229 +               .config_aneg    = vr9_gphy_config_aneg,
 230 +               .read_status    = genphy_read_status,
 231 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 232 +               .did_interrupt  = vr9_gphy_did_interrupt,
 233 +               .config_intr    = vr9_gphy_config_intr,
 234 +               .driver         = { .owner = THIS_MODULE },
 235 +       }, {
 236 +               .phy_id         = 0xd565a418,
 237 +               .phy_id_mask    = 0xfffffff8,
 238 +               .name           = "Lantiq XWAY XRX PHY22F v1.4",
 239 +               .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 240 +               .flags          = 0, /*PHY_HAS_INTERRUPT,*/
 241 +               .config_init    = vr9_gphy_config_init,
 242 +               .config_aneg    = vr9_gphy_config_aneg,
 243 +               .read_status    = genphy_read_status,
 244 +               .ack_interrupt  = vr9_gphy_ack_interrupt,
 245 +               .did_interrupt  = vr9_gphy_did_interrupt,
 246 +               .config_intr    = vr9_gphy_config_intr,
 247 +               .driver         = { .owner = THIS_MODULE },
 248 +       },
 249 +};
 250 +
 251 +static int __init ltq_phy_init(void)
 252 +{
 253 +       int i;
 254 +
 255 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) {
 256 +               int err = phy_driver_register(&lantiq_phy[i]);
 257 +               if (err)
 258 +                       pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name);
 259 +       }
 260 +
 261 +       return 0;
 262 +}
 263 +
 264 +static void __exit ltq_phy_exit(void)
 265 +{
 266 +       int i;
 267 +
 268 +       for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++)
 269 +               phy_driver_unregister(&lantiq_phy[i]);
 270 +}
 271 +
 272 +module_init(ltq_phy_init);
 273 +module_exit(ltq_phy_exit);
 274 +
 275 +MODULE_DESCRIPTION("Lantiq PHY drivers");
 276 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
 277 +MODULE_LICENSE("GPL");