target/linux/lantiq/patches-3.7/0103-MIPS-lantiq-adds-static-clock-for-PP32.patch

   1 From 8cbac4b30bed1552503b95bc0ac6276e3cdda9d8 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 30 Nov 2012 21:08:49 +0100
   4 Subject: [PATCH 103/123] MIPS: lantiq: adds static clock for PP32
   5
   6 The Lantiq DSL SoCs have an internal networking processor. Add code to read
   7 the static clock rate.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  arch/mips/include/asm/mach-lantiq/lantiq.h |    1 +
  12  arch/mips/lantiq/clk.c                     |   12 ++++++--
  13  arch/mips/lantiq/clk.h                     |    7 ++++-
  14  arch/mips/lantiq/falcon/sysctrl.c          |    4 +--
  15  arch/mips/lantiq/xway/clk.c                |   43 ++++++++++++++++++++++++++++
  16  arch/mips/lantiq/xway/sysctrl.c            |   12 ++++----
  17  6 files changed, 69 insertions(+), 10 deletions(-)
  18
  19 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
  20 index 5e8a6e9..76be7a0 100644
  21 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
  22 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
  23 @@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *clk);
  24  extern struct clk *clk_get_cpu(void);
  25  extern struct clk *clk_get_fpi(void);
  26  extern struct clk *clk_get_io(void);
  27 +extern struct clk *clk_get_ppe(void);
  28
  29  /* find out what bootsource we have */
  30  extern unsigned char ltq_boot_select(void);
  31 diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
  32 index 9128ff8..292ef1a 100644
  33 --- a/arch/mips/lantiq/clk.c
  34 +++ b/arch/mips/lantiq/clk.c
  35 @@ -26,13 +26,15 @@
  36  #include "prom.h"
  37
  38  /* lantiq socs have 3 static clocks */
  39 -static struct clk cpu_clk_generic[3];
  40 +static struct clk cpu_clk_generic[4];
  41
  42 -void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
  43 +void clkdev_add_static(unsigned long cpu, unsigned long fpi,
  44 +                       unsigned long io, unsigned long ppe)
  45  {
  46         cpu_clk_generic[0].rate = cpu;
  47         cpu_clk_generic[1].rate = fpi;
  48         cpu_clk_generic[2].rate = io;
  49 +       cpu_clk_generic[3].rate = ppe;
  50  }
  51
  52  struct clk *clk_get_cpu(void)
  53 @@ -51,6 +53,12 @@ struct clk *clk_get_io(void)
  54         return &cpu_clk_generic[2];
  55  }
  56
  57 +struct clk *clk_get_ppe(void)
  58 +{
  59 +       return &cpu_clk_generic[3];
  60 +}
  61 +EXPORT_SYMBOL_GPL(clk_get_ppe);
  62 +
  63  static inline int clk_good(struct clk *clk)
  64  {
  65         return clk && !IS_ERR(clk);
  66 diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
  67 index c169e2b..4739366 100644
  68 --- a/arch/mips/lantiq/clk.h
  69 +++ b/arch/mips/lantiq/clk.h
  70 @@ -27,12 +27,15 @@
  71  #define CLOCK_167M     166666667
  72  #define CLOCK_196_608M 196608000
  73  #define CLOCK_200M     200000000
  74 +#define CLOCK_222M     222000000
  75 +#define CLOCK_240M     240000000
  76  #define CLOCK_250M     250000000
  77  #define CLOCK_266M     266666666
  78  #define CLOCK_300M     300000000
  79  #define CLOCK_333M     333333333
  80  #define CLOCK_393M     393215332
  81  #define CLOCK_400M     400000000
  82 +#define CLOCK_450M     450000000
  83  #define CLOCK_500M     500000000
  84  #define CLOCK_600M     600000000
  85
  86 @@ -64,16 +67,18 @@ struct clk {
  87  };
  88
  89  extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
  90 -                               unsigned long io);
  91 +                               unsigned long io, unsigned long ppe);
  92
  93  extern unsigned long ltq_danube_cpu_hz(void);
  94  extern unsigned long ltq_danube_fpi_hz(void);
  95 +extern unsigned long ltq_danube_pp32_hz(void);
  96
  97  extern unsigned long ltq_ar9_cpu_hz(void);
  98  extern unsigned long ltq_ar9_fpi_hz(void);
  99
 100  extern unsigned long ltq_vr9_cpu_hz(void);
 101  extern unsigned long ltq_vr9_fpi_hz(void);
 102 +extern unsigned long ltq_vr9_pp32_hz(void);
 103
 104  extern unsigned long ltq_svip_cpu_hz(void);
 105  extern unsigned long ltq_svip_fpi_hz(void);
 106 diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
 107 index 2d4ced3..ff4894a 100644
 108 --- a/arch/mips/lantiq/falcon/sysctrl.c
 109 +++ b/arch/mips/lantiq/falcon/sysctrl.c
 110 @@ -241,9 +241,9 @@ void __init ltq_soc_init(void)
 111
 112         /* get our 3 static rates for cpu, fpi and io clocks */
 113         if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
 114 -               clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
 115 +               clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
 116         else
 117 -               clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
 118 +               clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
 119
 120         /* add our clock domains */
 121         clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
 122 diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
 123 index 9aa17f7..1ab576d 100644
 124 --- a/arch/mips/lantiq/xway/clk.c
 125 +++ b/arch/mips/lantiq/xway/clk.c
 126 @@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void)
 127         }
 128  }
 129
 130 +unsigned long ltq_danube_pp32_hz(void)
 131 +{
 132 +       unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
 133 +       unsigned long clk;
 134 +
 135 +       switch (clksys) {
 136 +       case 1:
 137 +               clk = CLOCK_240M;
 138 +               break;
 139 +       case 2:
 140 +               clk = CLOCK_222M;
 141 +               break;
 142 +       case 3:
 143 +               clk = CLOCK_133M;
 144 +               break;
 145 +       default:
 146 +               clk = CLOCK_266M;
 147 +               break;
 148 +       }
 149 +
 150 +       return clk;
 151 +}
 152 +
 153  unsigned long ltq_ar9_sys_hz(void)
 154  {
 155         if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
 156 @@ -149,3 +172,23 @@ unsigned long ltq_vr9_fpi_hz(void)
 157
 158         return clk;
 159  }
 160 +
 161 +unsigned long ltq_vr9_pp32_hz(void)
 162 +{
 163 +       unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;
 164 +       unsigned long clk;
 165 +
 166 +       switch (clksys) {
 167 +       case 1:
 168 +               clk = CLOCK_450M;
 169 +               break;
 170 +       case 2:
 171 +               clk = CLOCK_300M;
 172 +               break;
 173 +       default:
 174 +               clk = CLOCK_500M;
 175 +               break;
 176 +       }
 177 +
 178 +       return clk;
 179 +}
 180 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
 181 index 6e0e135..75e1b7d 100644
 182 --- a/arch/mips/lantiq/xway/sysctrl.c
 183 +++ b/arch/mips/lantiq/xway/sysctrl.c
 184 @@ -356,14 +356,16 @@ void __init ltq_soc_init(void)
 185
 186         if (of_machine_is_compatible("lantiq,ase")) {
 187                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 188 -                       clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
 189 +                       clkdev_add_static(CLOCK_266M, CLOCK_133M,
 190 +                                               CLOCK_133M, CLOCK_266M);
 191                 else
 192 -                       clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 193 +                       clkdev_add_static(CLOCK_133M, CLOCK_133M,
 194 +                                               CLOCK_133M, CLOCK_133M);
 195                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
 196                 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
 197         } else if (of_machine_is_compatible("lantiq,vr9")) {
 198                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 199 -                               ltq_vr9_fpi_hz());
 200 +                               ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
 201                 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
 202                 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
 203                 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
 204 @@ -377,10 +379,10 @@ void __init ltq_soc_init(void)
 205                 clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
 206         } else if (of_machine_is_compatible("lantiq,ar9")) {
 207                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 208 -                               ltq_ar9_fpi_hz());
 209 +                               ltq_ar9_fpi_hz(), CLOCK_250M);
 210                 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
 211         } else {
 212                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 213 -                               ltq_danube_fpi_hz());
 214 +                               ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
 215         }
 216  }
 217 --
 218 1.7.10.4
 219