target/linux/lantiq/patches-3.2/0046-MIPS-lantiq-adds-GPTU-driver.patch

   1 From 688c075ddc08723848df01fc0426d69d0b3a464b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 29 Sep 2011 17:16:38 +0200
   4 Subject: [PATCH 46/73] MIPS: lantiq: adds GPTU driver
   5
   6 ---
   7  arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
   8  arch/mips/lantiq/xway/Makefile                   |    2 +-
   9  arch/mips/lantiq/xway/sysctrl.c                  |    1 +
  10  arch/mips/lantiq/xway/timer.c                    |  846 ++++++++++++++++++++++
  11  4 files changed, 1003 insertions(+), 1 deletions(-)
  12  create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  13  create mode 100644 arch/mips/lantiq/xway/timer.c
  14
  15 --- /dev/null
  16 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  17 @@ -0,0 +1,155 @@
  18 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  19 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  20 +
  21 +
  22 +/******************************************************************************
  23 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
  24 +
  25 +                               No Warranty
  26 +   Because the program is licensed free of charge, there is no warranty for
  27 +   the program, to the extent permitted by applicable law.  Except when
  28 +   otherwise stated in writing the copyright holders and/or other parties
  29 +   provide the program "as is" without warranty of any kind, either
  30 +   expressed or implied, including, but not limited to, the implied
  31 +   warranties of merchantability and fitness for a particular purpose. The
  32 +   entire risk as to the quality and performance of the program is with
  33 +   you.  should the program prove defective, you assume the cost of all
  34 +   necessary servicing, repair or correction.
  35 +
  36 +   In no event unless required by applicable law or agreed to in writing
  37 +   will any copyright holder, or any other party who may modify and/or
  38 +   redistribute the program as permitted above, be liable to you for
  39 +   damages, including any general, special, incidental or consequential
  40 +   damages arising out of the use or inability to use the program
  41 +   (including but not limited to loss of data or data being rendered
  42 +   inaccurate or losses sustained by you or third parties or a failure of
  43 +   the program to operate with any other programs), even if such holder or
  44 +   other party has been advised of the possibility of such damages.
  45 +******************************************************************************/
  46 +
  47 +
  48 +/*
  49 + * ####################################
  50 + *              Definition
  51 + * ####################################
  52 + */
  53 +
  54 +/*
  55 + *  Available Timer/Counter Index
  56 + */
  57 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
  58 +#define TIMER_ANY                       0x00
  59 +#define TIMER1A                         TIMER(1, 0)
  60 +#define TIMER1B                         TIMER(1, 1)
  61 +#define TIMER2A                         TIMER(2, 0)
  62 +#define TIMER2B                         TIMER(2, 1)
  63 +#define TIMER3A                         TIMER(3, 0)
  64 +#define TIMER3B                         TIMER(3, 1)
  65 +
  66 +/*
  67 + *  Flag of Timer/Counter
  68 + *  These flags specify the way in which timer is configured.
  69 + */
  70 +/*  Bit size of timer/counter.                      */
  71 +#define TIMER_FLAG_16BIT                0x0000
  72 +#define TIMER_FLAG_32BIT                0x0001
  73 +/*  Switch between timer and counter.               */
  74 +#define TIMER_FLAG_TIMER                0x0000
  75 +#define TIMER_FLAG_COUNTER              0x0002
  76 +/*  Stop or continue when overflowing/underflowing. */
  77 +#define TIMER_FLAG_ONCE                 0x0000
  78 +#define TIMER_FLAG_CYCLIC               0x0004
  79 +/*  Count up or counter down.                       */
  80 +#define TIMER_FLAG_UP                   0x0000
  81 +#define TIMER_FLAG_DOWN                 0x0008
  82 +/*  Count on specific level or edge.                */
  83 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
  84 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
  85 +#define TIMER_FLAG_RISE_EDGE            0x0010
  86 +#define TIMER_FLAG_FALL_EDGE            0x0020
  87 +#define TIMER_FLAG_ANY_EDGE             0x0030
  88 +/*  Signal is syncronous to module clock or not.    */
  89 +#define TIMER_FLAG_UNSYNC               0x0000
  90 +#define TIMER_FLAG_SYNC                 0x0080
  91 +/*  Different interrupt handle type.                */
  92 +#define TIMER_FLAG_NO_HANDLE            0x0000
  93 +#if defined(__KERNEL__)
  94 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
  95 +#endif  //  defined(__KERNEL__)
  96 +#define TIMER_FLAG_SIGNAL               0x0300
  97 +/*  Internal clock source or external clock source  */
  98 +#define TIMER_FLAG_INT_SRC              0x0000
  99 +#define TIMER_FLAG_EXT_SRC              0x1000
 100 +
 101 +
 102 +/*
 103 + *  ioctl Command
 104 + */
 105 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 106 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 107 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 108 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 109 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 110 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 111 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 112 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 113 +
 114 +/*
 115 + *  Data Type Used to Call ioctl
 116 + */
 117 +struct gptu_ioctl_param {
 118 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 119 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 120 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 121 +                                                 *  be dynamically allocated and ID would be stored in  *
 122 +                                                 *  this field.                                         *
 123 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 124 +                                                 *  ignored.                                            *
 125 +                                                 *  In other command, this field is ID of timer/counter *
 126 +                                                 *  allocated.                                          */
 127 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 128 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 129 +                                                 *  specify how to configure timer/counter.             *
 130 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 131 +                                                 *  and non-zero indicate resume timer/counter.         *
 132 +                                                 *  In other command, this field is ignored.            */
 133 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 134 +                                                 *  init/reload value.                                  *
 135 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 136 +                                                 *  frequency (0.001Hz) of timer.                       *
 137 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 138 +                                                 *  value would be stored in this field.                *
 139 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 140 +                                                 *  contains frequency wanted, and after calculation,   *
 141 +                                                 *  divider would be stored in this field to overwrite  *
 142 +                                                 *  the frequency.                                      *
 143 +                                                 *  In other command, this field is ignored.            */
 144 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 145 +                                                 *  if signal is required, this field contains process  *
 146 +                                                 *  ID to which signal would be sent.                   *
 147 +                                                 *  In other command, this field is ignored.            */
 148 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 149 +                                                 *  if signal is required, this field contains signal   *
 150 +                                                 *  number which would be sent.                         *
 151 +                                                 *  In other command, this field is ignored.            */
 152 +};
 153 +
 154 +/*
 155 + * ####################################
 156 + *              Data Type
 157 + * ####################################
 158 + */
 159 +typedef void (*timer_callback)(unsigned long arg);
 160 +
 161 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
 162 +extern int lq_free_timer(unsigned int);
 163 +extern int lq_start_timer(unsigned int, int);
 164 +extern int lq_stop_timer(unsigned int);
 165 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
 166 +extern int lq_get_count_value(unsigned int, unsigned long *);
 167 +extern u32 lq_cal_divider(unsigned long);
 168 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
 169 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
 170 +       u32 reload, unsigned long arg1, unsigned long arg2);
 171 +
 172 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
 173 --- a/arch/mips/lantiq/xway/Makefile
 174 +++ b/arch/mips/lantiq/xway/Makefile
 175 @@ -1,4 +1,4 @@
 176 -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o
 177 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o
 178
 179  obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
 180  obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
 181 --- a/arch/mips/lantiq/xway/sysctrl.c
 182 +++ b/arch/mips/lantiq/xway/sysctrl.c
 183 @@ -147,6 +147,7 @@ void __init ltq_soc_init(void)
 184         clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
 185         clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
 186         clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
 187 +        clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT);
 188         if (!ltq_is_vr9())
 189                 clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 190         if (ltq_is_ase()) {
 191 --- /dev/null
 192 +++ b/arch/mips/lantiq/xway/timer.c
 193 @@ -0,0 +1,846 @@
 194 +#include <linux/kernel.h>
 195 +#include <linux/module.h>
 196 +#include <linux/version.h>
 197 +#include <linux/types.h>
 198 +#include <linux/fs.h>
 199 +#include <linux/miscdevice.h>
 200 +#include <linux/init.h>
 201 +#include <linux/uaccess.h>
 202 +#include <linux/unistd.h>
 203 +#include <linux/errno.h>
 204 +#include <linux/interrupt.h>
 205 +#include <linux/sched.h>
 206 +
 207 +#include <asm/irq.h>
 208 +#include <asm/div64.h>
 209 +#include "../clk.h"
 210 +
 211 +#include <lantiq_soc.h>
 212 +#include <lantiq_irq.h>
 213 +#include <lantiq_timer.h>
 214 +
 215 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
 216 +
 217 +#ifdef TIMER1A
 218 +#define FIRST_TIMER                    TIMER1A
 219 +#else
 220 +#define FIRST_TIMER                    2
 221 +#endif
 222 +
 223 +/*
 224 + *  GPTC divider is set or not.
 225 + */
 226 +#define GPTU_CLC_RMC_IS_SET            0
 227 +
 228 +/*
 229 + *  Timer Interrupt (IRQ)
 230 + */
 231 +/*  Must be adjusted when ICU driver is available */
 232 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
 233 +
 234 +/*
 235 + *  Bits Operation
 236 + */
 237 +#define GET_BITS(x, msb, lsb)          \
 238 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
 239 +#define SET_BITS(x, msb, lsb, value)   \
 240 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
 241 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
 242 +
 243 +/*
 244 + *  GPTU Register Mapping
 245 + */
 246 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
 247 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
 248 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
 249 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 250 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 251 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 252 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 253 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
 254 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
 255 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
 256 +
 257 +/*
 258 + *  Clock Control Register
 259 + */
 260 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
 261 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
 262 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
 263 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
 264 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
 265 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
 266 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
 267 +
 268 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
 269 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
 270 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
 271 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
 272 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
 273 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
 274 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
 275 +
 276 +/*
 277 + *  ID Register
 278 + */
 279 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
 280 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
 281 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
 282 +
 283 +/*
 284 + *  Control Register of Timer/Counter nX
 285 + *    n is the index of block (1 based index)
 286 + *    X is either A or B
 287 + */
 288 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 289 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 290 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 291 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 292 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 293 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 294 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 295 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 296 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 297 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 298 +
 299 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 300 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 301 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 302 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 303 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 304 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 305 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 306 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 307 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 308 +
 309 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 310 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 311 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 312 +
 313 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 314 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 315 +
 316 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 317 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 318 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 319 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 320 +#define TIMER_FLAG_NONE_EDGE           0x0000
 321 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 322 +#define TIMER_FLAG_REAL                        0x0000
 323 +#define TIMER_FLAG_INVERT              0x0040
 324 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 325 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 326 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 327 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 328 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 329 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 330 +
 331 +struct timer_dev_timer {
 332 +       unsigned int f_irq_on;
 333 +       unsigned int irq;
 334 +       unsigned int flag;
 335 +       unsigned long arg1;
 336 +       unsigned long arg2;
 337 +};
 338 +
 339 +struct timer_dev {
 340 +       struct mutex gptu_mutex;
 341 +       unsigned int number_of_timers;
 342 +       unsigned int occupation;
 343 +       unsigned int f_gptu_on;
 344 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 345 +};
 346 +
 347 +unsigned long ltq_danube_fpi_bus_clock(int fpi);
 348 +unsigned long ltq_vr9_fpi_bus_clock(int fpi);
 349 +
 350 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 351 +       if (ltq_is_ase())
 352 +               return CLOCK_133M;
 353 +       else if (ltq_is_vr9())
 354 +               return ltq_vr9_fpi_bus_clock(fpi);
 355 +
 356 +       return ltq_danube_fpi_bus_clock(fpi);
 357 +}
 358 +
 359 +
 360 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 361 +static int gptu_open(struct inode *, struct file *);
 362 +static int gptu_release(struct inode *, struct file *);
 363 +
 364 +static struct file_operations gptu_fops = {
 365 +       .owner = THIS_MODULE,
 366 +       .unlocked_ioctl = gptu_ioctl,
 367 +       .open = gptu_open,
 368 +       .release = gptu_release
 369 +};
 370 +
 371 +static struct miscdevice gptu_miscdev = {
 372 +       .minor = MISC_DYNAMIC_MINOR,
 373 +       .name = "gptu",
 374 +       .fops = &gptu_fops,
 375 +};
 376 +
 377 +static struct timer_dev timer_dev;
 378 +
 379 +static irqreturn_t timer_irq_handler(int irq, void *p)
 380 +{
 381 +       unsigned int timer;
 382 +       unsigned int flag;
 383 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 384 +
 385 +       timer = irq - TIMER_INTERRUPT;
 386 +       if (timer < timer_dev.number_of_timers
 387 +               && dev_timer == &timer_dev.timer[timer]) {
 388 +               /*  Clear interrupt.    */
 389 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 390 +
 391 +               /*  Call user hanler or signal. */
 392 +               flag = dev_timer->flag;
 393 +               if (!(timer & 0x01)
 394 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 395 +                       /* 16-bit timer or timer A of 32-bit timer  */
 396 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 397 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 398 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 399 +                               if (dev_timer->arg1)
 400 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 401 +                               break;
 402 +                       case TIMER_FLAG_SIGNAL:
 403 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 404 +                               break;
 405 +                       }
 406 +               }
 407 +       }
 408 +       return IRQ_HANDLED;
 409 +}
 410 +
 411 +static inline void lq_enable_gptu(void)
 412 +{
 413 +       struct clk *clk = clk_get_sys("ltq_gptu", NULL);
 414 +       clk_enable(clk);
 415 +
 416 +       //ltq_pmu_enable(PMU_GPT);
 417 +
 418 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 419 +       *LQ_GPTU_CLC =
 420 +               GPTU_CLC_SMC_SET(0x00) |
 421 +               GPTU_CLC_RMC_SET(0x01) |
 422 +               GPTU_CLC_FSOE_SET(0) |
 423 +               GPTU_CLC_SBWE_SET(1) |
 424 +               GPTU_CLC_EDIS_SET(0) |
 425 +               GPTU_CLC_SPEN_SET(0) |
 426 +               GPTU_CLC_DISR_SET(0);
 427 +}
 428 +
 429 +static inline void lq_disable_gptu(void)
 430 +{
 431 +       struct clk *clk = clk_get_sys("ltq_gptu", NULL);
 432 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 433 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 434 +
 435 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 436 +       *LQ_GPTU_CLC =
 437 +               GPTU_CLC_SMC_SET(0x00) |
 438 +               GPTU_CLC_RMC_SET(0x00) |
 439 +               GPTU_CLC_FSOE_SET(0) |
 440 +               GPTU_CLC_SBWE_SET(0) |
 441 +               GPTU_CLC_EDIS_SET(0) |
 442 +               GPTU_CLC_SPEN_SET(0) |
 443 +               GPTU_CLC_DISR_SET(1);
 444 +
 445 +       clk_enable(clk);
 446 +}
 447 +
 448 +int lq_request_timer(unsigned int timer, unsigned int flag,
 449 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 450 +{
 451 +       int ret = 0;
 452 +       unsigned int con_reg, irnen_reg;
 453 +       int n, X;
 454 +
 455 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 456 +               return -EINVAL;
 457 +
 458 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 459 +               timer, flag, value);
 460 +
 461 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 462 +               value &= 0xFFFF;
 463 +       else
 464 +               timer &= ~0x01;
 465 +
 466 +       mutex_lock(&timer_dev.gptu_mutex);
 467 +
 468 +       /*
 469 +        *  Allocate timer.
 470 +        */
 471 +       if (timer < FIRST_TIMER) {
 472 +               unsigned int mask;
 473 +               unsigned int shift;
 474 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 475 +               unsigned int offset = TIMER2A;
 476 +
 477 +               /*
 478 +                *  Pick up a free timer.
 479 +                */
 480 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 481 +                       mask = 1 << offset;
 482 +                       shift = 1;
 483 +               } else {
 484 +                       mask = 3 << offset;
 485 +                       shift = 2;
 486 +               }
 487 +               for (timer = offset;
 488 +                    timer < offset + timer_dev.number_of_timers;
 489 +                    timer += shift, mask <<= shift)
 490 +                       if (!(timer_dev.occupation & mask)) {
 491 +                               timer_dev.occupation |= mask;
 492 +                               break;
 493 +                       }
 494 +               if (timer >= offset + timer_dev.number_of_timers) {
 495 +                       printk("failed![%d]\n", __LINE__);
 496 +                       mutex_unlock(&timer_dev.gptu_mutex);
 497 +                       return -EINVAL;
 498 +               } else
 499 +                       ret = timer;
 500 +       } else {
 501 +               register unsigned int mask;
 502 +
 503 +               /*
 504 +                *  Check if the requested timer is free.
 505 +                */
 506 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 507 +               if ((timer_dev.occupation & mask)) {
 508 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 509 +                               __LINE__, mask, timer_dev.occupation);
 510 +                       mutex_unlock(&timer_dev.gptu_mutex);
 511 +                       return -EBUSY;
 512 +               } else {
 513 +                       timer_dev.occupation |= mask;
 514 +                       ret = 0;
 515 +               }
 516 +       }
 517 +
 518 +       /*
 519 +        *  Prepare control register value.
 520 +        */
 521 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 522 +       default:
 523 +       case TIMER_FLAG_NONE_EDGE:
 524 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 525 +               break;
 526 +       case TIMER_FLAG_RISE_EDGE:
 527 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 528 +               break;
 529 +       case TIMER_FLAG_FALL_EDGE:
 530 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 531 +               break;
 532 +       case TIMER_FLAG_ANY_EDGE:
 533 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 534 +               break;
 535 +       }
 536 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 537 +               con_reg |=
 538 +                       TIMER_FLAG_MASK_SRC(flag) ==
 539 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 540 +                       GPTU_CON_SRC_EXT_SET(0);
 541 +       else
 542 +               con_reg |=
 543 +                       TIMER_FLAG_MASK_SRC(flag) ==
 544 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 545 +                       GPTU_CON_SRC_EG_SET(0);
 546 +       con_reg |=
 547 +               TIMER_FLAG_MASK_SYNC(flag) ==
 548 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 549 +               GPTU_CON_SYNC_SET(1);
 550 +       con_reg |=
 551 +               TIMER_FLAG_MASK_INVERT(flag) ==
 552 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 553 +       con_reg |=
 554 +               TIMER_FLAG_MASK_SIZE(flag) ==
 555 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 556 +               GPTU_CON_EXT_SET(1);
 557 +       con_reg |=
 558 +               TIMER_FLAG_MASK_STOP(flag) ==
 559 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 560 +       con_reg |=
 561 +               TIMER_FLAG_MASK_TYPE(flag) ==
 562 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 563 +               GPTU_CON_CNT_SET(1);
 564 +       con_reg |=
 565 +               TIMER_FLAG_MASK_DIR(flag) ==
 566 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 567 +
 568 +       /*
 569 +        *  Fill up running data.
 570 +        */
 571 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 572 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 573 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 574 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 575 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 576 +
 577 +       /*
 578 +        *  Enable GPTU module.
 579 +        */
 580 +       if (!timer_dev.f_gptu_on) {
 581 +               lq_enable_gptu();
 582 +               timer_dev.f_gptu_on = 1;
 583 +       }
 584 +
 585 +       /*
 586 +        *  Enable IRQ.
 587 +        */
 588 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 589 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 590 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 591 +                               (unsigned long) find_task_by_vpid((int) arg1);
 592 +
 593 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 594 +
 595 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 596 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 597 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 598 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 599 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 600 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 601 +               }
 602 +       } else
 603 +               irnen_reg = 0;
 604 +
 605 +       /*
 606 +        *  Write config register, reload value and enable interrupt.
 607 +        */
 608 +       n = timer >> 1;
 609 +       X = timer & 0x01;
 610 +       *LQ_GPTU_CON(n, X) = con_reg;
 611 +       *LQ_GPTU_RELOAD(n, X) = value;
 612 +       /* printk("reload value = %d\n", (u32)value); */
 613 +       *LQ_GPTU_IRNEN |= irnen_reg;
 614 +
 615 +       mutex_unlock(&timer_dev.gptu_mutex);
 616 +       printk("successful!\n");
 617 +       return ret;
 618 +}
 619 +EXPORT_SYMBOL(lq_request_timer);
 620 +
 621 +int lq_free_timer(unsigned int timer)
 622 +{
 623 +       unsigned int flag;
 624 +       unsigned int mask;
 625 +       int n, X;
 626 +
 627 +       if (!timer_dev.f_gptu_on)
 628 +               return -EINVAL;
 629 +
 630 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 631 +               return -EINVAL;
 632 +
 633 +       mutex_lock(&timer_dev.gptu_mutex);
 634 +
 635 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 636 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 637 +               timer &= ~0x01;
 638 +
 639 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 640 +       if (((timer_dev.occupation & mask) ^ mask)) {
 641 +               mutex_unlock(&timer_dev.gptu_mutex);
 642 +               return -EINVAL;
 643 +       }
 644 +
 645 +       n = timer >> 1;
 646 +       X = timer & 0x01;
 647 +
 648 +       if (GPTU_CON_EN(n, X))
 649 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 650 +
 651 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 652 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 653 +
 654 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 655 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 656 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 657 +       }
 658 +
 659 +       timer_dev.occupation &= ~mask;
 660 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 661 +               lq_disable_gptu();
 662 +               timer_dev.f_gptu_on = 0;
 663 +       }
 664 +
 665 +       mutex_unlock(&timer_dev.gptu_mutex);
 666 +
 667 +       return 0;
 668 +}
 669 +EXPORT_SYMBOL(lq_free_timer);
 670 +
 671 +int lq_start_timer(unsigned int timer, int is_resume)
 672 +{
 673 +       unsigned int flag;
 674 +       unsigned int mask;
 675 +       int n, X;
 676 +
 677 +       if (!timer_dev.f_gptu_on)
 678 +               return -EINVAL;
 679 +
 680 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 681 +               return -EINVAL;
 682 +
 683 +       mutex_lock(&timer_dev.gptu_mutex);
 684 +
 685 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 686 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 687 +               timer &= ~0x01;
 688 +
 689 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 690 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 691 +       if (((timer_dev.occupation & mask) ^ mask)) {
 692 +               mutex_unlock(&timer_dev.gptu_mutex);
 693 +               return -EINVAL;
 694 +       }
 695 +
 696 +       n = timer >> 1;
 697 +       X = timer & 0x01;
 698 +
 699 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 700 +
 701 +       mutex_unlock(&timer_dev.gptu_mutex);
 702 +
 703 +       return 0;
 704 +}
 705 +EXPORT_SYMBOL(lq_start_timer);
 706 +
 707 +int lq_stop_timer(unsigned int timer)
 708 +{
 709 +       unsigned int flag;
 710 +       unsigned int mask;
 711 +       int n, X;
 712 +
 713 +       if (!timer_dev.f_gptu_on)
 714 +               return -EINVAL;
 715 +
 716 +       if (timer < FIRST_TIMER
 717 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 718 +               return -EINVAL;
 719 +
 720 +       mutex_lock(&timer_dev.gptu_mutex);
 721 +
 722 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 723 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 724 +               timer &= ~0x01;
 725 +
 726 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 727 +       if (((timer_dev.occupation & mask) ^ mask)) {
 728 +               mutex_unlock(&timer_dev.gptu_mutex);
 729 +               return -EINVAL;
 730 +       }
 731 +
 732 +       n = timer >> 1;
 733 +       X = timer & 0x01;
 734 +
 735 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 736 +
 737 +       mutex_unlock(&timer_dev.gptu_mutex);
 738 +
 739 +       return 0;
 740 +}
 741 +EXPORT_SYMBOL(lq_stop_timer);
 742 +
 743 +int lq_reset_counter_flags(u32 timer, u32 flags)
 744 +{
 745 +       unsigned int oflag;
 746 +       unsigned int mask, con_reg;
 747 +       int n, X;
 748 +
 749 +       if (!timer_dev.f_gptu_on)
 750 +               return -EINVAL;
 751 +
 752 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 753 +               return -EINVAL;
 754 +
 755 +       mutex_lock(&timer_dev.gptu_mutex);
 756 +
 757 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 758 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 759 +               timer &= ~0x01;
 760 +
 761 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 762 +       if (((timer_dev.occupation & mask) ^ mask)) {
 763 +               mutex_unlock(&timer_dev.gptu_mutex);
 764 +               return -EINVAL;
 765 +       }
 766 +
 767 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 768 +       default:
 769 +       case TIMER_FLAG_NONE_EDGE:
 770 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 771 +               break;
 772 +       case TIMER_FLAG_RISE_EDGE:
 773 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 774 +               break;
 775 +       case TIMER_FLAG_FALL_EDGE:
 776 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 777 +               break;
 778 +       case TIMER_FLAG_ANY_EDGE:
 779 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 780 +               break;
 781 +       }
 782 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 783 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 784 +       else
 785 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 786 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 787 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 788 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 789 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 790 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 791 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 792 +
 793 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 794 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 795 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 796 +
 797 +       n = timer >> 1;
 798 +       X = timer & 0x01;
 799 +
 800 +       *LQ_GPTU_CON(n, X) = con_reg;
 801 +       smp_wmb();
 802 +       printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
 803 +       mutex_unlock(&timer_dev.gptu_mutex);
 804 +       return 0;
 805 +}
 806 +EXPORT_SYMBOL(lq_reset_counter_flags);
 807 +
 808 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 809 +{
 810 +       unsigned int flag;
 811 +       unsigned int mask;
 812 +       int n, X;
 813 +
 814 +       if (!timer_dev.f_gptu_on)
 815 +               return -EINVAL;
 816 +
 817 +       if (timer < FIRST_TIMER
 818 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 819 +               return -EINVAL;
 820 +
 821 +       mutex_lock(&timer_dev.gptu_mutex);
 822 +
 823 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 824 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 825 +               timer &= ~0x01;
 826 +
 827 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 828 +       if (((timer_dev.occupation & mask) ^ mask)) {
 829 +               mutex_unlock(&timer_dev.gptu_mutex);
 830 +               return -EINVAL;
 831 +       }
 832 +
 833 +       n = timer >> 1;
 834 +       X = timer & 0x01;
 835 +
 836 +       *value = *LQ_GPTU_COUNT(n, X);
 837 +
 838 +       mutex_unlock(&timer_dev.gptu_mutex);
 839 +
 840 +       return 0;
 841 +}
 842 +EXPORT_SYMBOL(lq_get_count_value);
 843 +
 844 +u32 lq_cal_divider(unsigned long freq)
 845 +{
 846 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 847 +       u32 clock_divider = 1;
 848 +       module_freq = fpi * 1000;
 849 +       do_div(module_freq, clock_divider * freq);
 850 +       return module_freq;
 851 +}
 852 +EXPORT_SYMBOL(lq_cal_divider);
 853 +
 854 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 855 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 856 +       unsigned long arg2)
 857 +{
 858 +       unsigned long divider;
 859 +       unsigned int flag;
 860 +
 861 +       divider = lq_cal_divider(freq);
 862 +       if (divider == 0)
 863 +               return -EINVAL;
 864 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 865 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 866 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 867 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 868 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 869 +
 870 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 871 +               timer, freq, divider);
 872 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 873 +}
 874 +EXPORT_SYMBOL(lq_set_timer);
 875 +
 876 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 877 +       unsigned long arg1, unsigned long arg2)
 878 +{
 879 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 880 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 881 +}
 882 +EXPORT_SYMBOL(lq_set_counter);
 883 +
 884 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 885 +       unsigned long arg)
 886 +{
 887 +       int ret;
 888 +       struct gptu_ioctl_param param;
 889 +
 890 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 891 +               return -EFAULT;
 892 +       copy_from_user(&param, (void *) arg, sizeof(param));
 893 +
 894 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 895 +              || GPTU_SET_COUNTER) && param.timer < 2)
 896 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 897 +           && !access_ok(VERIFY_WRITE, arg,
 898 +                          sizeof(struct gptu_ioctl_param)))
 899 +               return -EFAULT;
 900 +
 901 +       switch (cmd) {
 902 +       case GPTU_REQUEST_TIMER:
 903 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 904 +                                    (unsigned long) param.pid,
 905 +                                    (unsigned long) param.sig);
 906 +               if (ret > 0) {
 907 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 908 +                                     timer, &ret, sizeof(&ret));
 909 +                       ret = 0;
 910 +               }
 911 +               break;
 912 +       case GPTU_FREE_TIMER:
 913 +               ret = lq_free_timer(param.timer);
 914 +               break;
 915 +       case GPTU_START_TIMER:
 916 +               ret = lq_start_timer(param.timer, param.flag);
 917 +               break;
 918 +       case GPTU_STOP_TIMER:
 919 +               ret = lq_stop_timer(param.timer);
 920 +               break;
 921 +       case GPTU_GET_COUNT_VALUE:
 922 +               ret = lq_get_count_value(param.timer, &param.value);
 923 +               if (!ret)
 924 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 925 +                                     value, &param.value,
 926 +                                     sizeof(param.value));
 927 +               break;
 928 +       case GPTU_CALCULATE_DIVIDER:
 929 +               param.value = lq_cal_divider(param.value);
 930 +               if (param.value == 0)
 931 +                       ret = -EINVAL;
 932 +               else {
 933 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 934 +                                     value, &param.value,
 935 +                                     sizeof(param.value));
 936 +                       ret = 0;
 937 +               }
 938 +               break;
 939 +       case GPTU_SET_TIMER:
 940 +               ret = lq_set_timer(param.timer, param.value,
 941 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 942 +                                TIMER_FLAG_ONCE ? 1 : 0,
 943 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 944 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 945 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 946 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 947 +                                TIMER_FLAG_NO_HANDLE,
 948 +                                (unsigned long) param.pid,
 949 +                                (unsigned long) param.sig);
 950 +               if (ret > 0) {
 951 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 952 +                                     timer, &ret, sizeof(&ret));
 953 +                       ret = 0;
 954 +               }
 955 +               break;
 956 +       case GPTU_SET_COUNTER:
 957 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 958 +               if (ret > 0) {
 959 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 960 +                                     timer, &ret, sizeof(&ret));
 961 +                       ret = 0;
 962 +               }
 963 +               break;
 964 +       default:
 965 +               ret = -ENOTTY;
 966 +       }
 967 +
 968 +       return ret;
 969 +}
 970 +
 971 +static int gptu_open(struct inode *inode, struct file *file)
 972 +{
 973 +       return 0;
 974 +}
 975 +
 976 +static int gptu_release(struct inode *inode, struct file *file)
 977 +{
 978 +       return 0;
 979 +}
 980 +
 981 +int __init lq_gptu_init(void)
 982 +{
 983 +       int ret;
 984 +       unsigned int i;
 985 +
 986 +       ltq_w32(0, LQ_GPTU_IRNEN);
 987 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 988 +
 989 +       memset(&timer_dev, 0, sizeof(timer_dev));
 990 +       mutex_init(&timer_dev.gptu_mutex);
 991 +
 992 +       lq_enable_gptu();
 993 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 994 +       lq_disable_gptu();
 995 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 996 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 997 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 998 +
 999 +       ret = misc_register(&gptu_miscdev);
1000 +       if (ret) {
1001 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
1002 +               return ret;
1003 +       } else {
1004 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
1005 +       }
1006 +
1007 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1008 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
1009 +               if (ret) {
1010 +                       for (; i >= 0; i--)
1011 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
1012 +                       misc_deregister(&gptu_miscdev);
1013 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
1014 +                       return ret;
1015 +               } else {
1016 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
1017 +                       disable_irq(timer_dev.timer[i].irq);
1018 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
1019 +               }
1020 +       }
1021 +
1022 +       return 0;
1023 +}
1024 +
1025 +void __exit lq_gptu_exit(void)
1026 +{
1027 +       unsigned int i;
1028 +
1029 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1030 +               if (timer_dev.timer[i].f_irq_on)
1031 +                       disable_irq(timer_dev.timer[i].irq);
1032 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1033 +       }
1034 +       lq_disable_gptu();
1035 +       misc_deregister(&gptu_miscdev);
1036 +}
1037 +
1038 +module_init(lq_gptu_init);
1039 +module_exit(lq_gptu_exit);