target/linux/lantiq/patches-3.2/0039-SPI-MIPS-lantiq-add-FALC-ON-spi-driver.patch

   1 From 0ebdb2202a06d096114aa7676f02d5f426a20366 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 27 Aug 2011 18:12:26 +0200
   4 Subject: [PATCH 39/70] SPI: MIPS: lantiq: add FALC-ON spi driver
   5
   6 The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is
   7 designed for serial flash access. This driver has only been tested with m25p80
   8 type chips. The hardware has no support for other types of spi peripherals.
   9
  10 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 Cc: spi-devel-general@lists.sourceforge.net
  13 ---
  14  arch/mips/lantiq/falcon/devices.c        |   13 +
  15  arch/mips/lantiq/falcon/devices.h        |    4 +
  16  arch/mips/lantiq/falcon/mach-easy98000.c |   27 ++
  17  drivers/spi/Kconfig                      |    4 +
  18  drivers/spi/Makefile                     |    1 +
  19  drivers/spi/spi-falcon.c                 |  483 ++++++++++++++++++++++++++++++
  20  6 files changed, 532 insertions(+), 0 deletions(-)
  21  create mode 100644 drivers/spi/spi-falcon.c
  22
  23 --- a/arch/mips/lantiq/falcon/devices.c
  24 +++ b/arch/mips/lantiq/falcon/devices.c
  25 @@ -121,3 +121,16 @@ falcon_register_gpio_extra(void)
  26         platform_device_register_simple("falcon_gpio", 4,
  27                 falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
  28  }
  29 +
  30 +/* spi flash */
  31 +static struct platform_device ltq_spi = {
  32 +       .name                   = "falcon_spi",
  33 +       .num_resources          = 0,
  34 +};
  35 +
  36 +void __init
  37 +falcon_register_spi_flash(struct spi_board_info *data)
  38 +{
  39 +       spi_register_board_info(data, 1);
  40 +       platform_device_register(&ltq_spi);
  41 +}
  42 --- a/arch/mips/lantiq/falcon/devices.h
  43 +++ b/arch/mips/lantiq/falcon/devices.h
  44 @@ -11,10 +11,14 @@
  45  #ifndef _FALCON_DEVICES_H__
  46  #define _FALCON_DEVICES_H__
  47
  48 +#include <linux/spi/spi.h>
  49 +#include <linux/spi/flash.h>
  50 +
  51  #include "../devices.h"
  52
  53  extern void falcon_register_nand(void);
  54  extern void falcon_register_gpio(void);
  55  extern void falcon_register_gpio_extra(void);
  56 +extern void falcon_register_spi_flash(struct spi_board_info *data);
  57
  58  #endif
  59 --- a/arch/mips/lantiq/falcon/mach-easy98000.c
  60 +++ b/arch/mips/lantiq/falcon/mach-easy98000.c
  61 @@ -40,6 +40,21 @@ struct physmap_flash_data easy98000_nor_
  62         .parts          = easy98000_nor_partitions,
  63  };
  64
  65 +static struct flash_platform_data easy98000_spi_flash_platform_data = {
  66 +       .name = "sflash",
  67 +       .parts = easy98000_nor_partitions,
  68 +       .nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
  69 +};
  70 +
  71 +static struct spi_board_info easy98000_spi_flash_data __initdata = {
  72 +       .modalias               = "m25p80",
  73 +       .bus_num                = 0,
  74 +       .chip_select            = 0,
  75 +       .max_speed_hz           = 10 * 1000 * 1000,
  76 +       .mode                   = SPI_MODE_3,
  77 +       .platform_data          = &easy98000_spi_flash_platform_data
  78 +};
  79 +
  80  /* setup gpio based spi bus/device for access to the eeprom on the board */
  81  #define SPI_GPIO_MRST          102
  82  #define SPI_GPIO_MTSR          103
  83 @@ -93,6 +108,13 @@ easy98000_init(void)
  84  }
  85
  86  static void __init
  87 +easy98000sf_init(void)
  88 +{
  89 +       easy98000_init_common();
  90 +       falcon_register_spi_flash(&easy98000_spi_flash_data);
  91 +}
  92 +
  93 +static void __init
  94  easy98000nand_init(void)
  95  {
  96         easy98000_init_common();
  97 @@ -104,6 +126,11 @@ MIPS_MACHINE(LANTIQ_MACH_EASY98000,
  98                         "EASY98000 Eval Board",
  99                         easy98000_init);
 100
 101 +MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
 102 +                       "EASY98000SF",
 103 +                       "EASY98000 Eval Board (Serial Flash)",
 104 +                       easy98000sf_init);
 105 +
 106  MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
 107                         "EASY98000NAND",
 108                         "EASY98000 Eval Board (NAND Flash)",
 109 --- a/drivers/spi/Kconfig
 110 +++ b/drivers/spi/Kconfig
 111 @@ -189,6 +189,10 @@ config SPI_MPC52xx
 112           This drivers supports the MPC52xx SPI controller in master SPI
 113           mode.
 114
 115 +config SPI_FALCON
 116 +       tristate "Falcon SPI controller support"
 117 +       depends on SOC_FALCON
 118 +
 119  config SPI_MPC52xx_PSC
 120         tristate "Freescale MPC52xx PSC SPI controller"
 121         depends on PPC_MPC52xx && EXPERIMENTAL
 122 --- a/drivers/spi/Makefile
 123 +++ b/drivers/spi/Makefile
 124 @@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO)             += spi-dw-mmi
 125  obj-$(CONFIG_SPI_DW_PCI)               += spi-dw-midpci.o
 126  spi-dw-midpci-objs                     := spi-dw-pci.o spi-dw-mid.o
 127  obj-$(CONFIG_SPI_EP93XX)               += spi-ep93xx.o
 128 +obj-$(CONFIG_SPI_FALCON)               += spi-falcon.o
 129  obj-$(CONFIG_SPI_FSL_LIB)              += spi-fsl-lib.o
 130  obj-$(CONFIG_SPI_FSL_ESPI)             += spi-fsl-espi.o
 131  obj-$(CONFIG_SPI_FSL_SPI)              += spi-fsl-spi.o
 132 --- /dev/null
 133 +++ b/drivers/spi/spi-falcon.c
 134 @@ -0,0 +1,483 @@
 135 +/*
 136 + *  This program is free software; you can redistribute it and/or modify it
 137 + *  under the terms of the GNU General Public License version 2 as published
 138 + *  by the Free Software Foundation.
 139 + *
 140 + *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 141 + */
 142 +
 143 +#include <linux/module.h>
 144 +#include <linux/device.h>
 145 +#include <linux/platform_device.h>
 146 +#include <linux/spi/spi.h>
 147 +#include <linux/delay.h>
 148 +#include <linux/workqueue.h>
 149 +
 150 +#include <lantiq_soc.h>
 151 +
 152 +#define DRV_NAME                       "falcon_spi"
 153 +
 154 +#define FALCON_SPI_XFER_BEGIN          (1 << 0)
 155 +#define FALCON_SPI_XFER_END            (1 << 1)
 156 +
 157 +/* Bus Read Configuration Register0 */
 158 +#define LTQ_BUSRCON0   0x00000010
 159 +/* Bus Write Configuration Register0 */
 160 +#define LTQ_BUSWCON0   0x00000018
 161 +/* Serial Flash Configuration Register */
 162 +#define LTQ_SFCON      0x00000080
 163 +/* Serial Flash Time Register */
 164 +#define LTQ_SFTIME     0x00000084
 165 +/* Serial Flash Status Register */
 166 +#define LTQ_SFSTAT     0x00000088
 167 +/* Serial Flash Command Register */
 168 +#define LTQ_SFCMD      0x0000008C
 169 +/* Serial Flash Address Register */
 170 +#define LTQ_SFADDR     0x00000090
 171 +/* Serial Flash Data Register */
 172 +#define LTQ_SFDATA     0x00000094
 173 +/* Serial Flash I/O Control Register */
 174 +#define LTQ_SFIO       0x00000098
 175 +/* EBU Clock Control Register */
 176 +#define LTQ_EBUCC      0x000000C4
 177 +
 178 +/* Dummy Phase Length */
 179 +#define SFCMD_DUMLEN_OFFSET    16
 180 +#define SFCMD_DUMLEN_MASK      0x000F0000
 181 +/* Chip Select */
 182 +#define SFCMD_CS_OFFSET                24
 183 +#define SFCMD_CS_MASK          0x07000000
 184 +/* field offset */
 185 +#define SFCMD_ALEN_OFFSET      20
 186 +#define SFCMD_ALEN_MASK                0x00700000
 187 +/* SCK Rise-edge Position */
 188 +#define SFTIME_SCKR_POS_OFFSET 8
 189 +#define SFTIME_SCKR_POS_MASK   0x00000F00
 190 +/* SCK Period */
 191 +#define SFTIME_SCK_PER_OFFSET  0
 192 +#define SFTIME_SCK_PER_MASK    0x0000000F
 193 +/* SCK Fall-edge Position */
 194 +#define SFTIME_SCKF_POS_OFFSET 12
 195 +#define SFTIME_SCKF_POS_MASK   0x0000F000
 196 +/* Device Size */
 197 +#define SFCON_DEV_SIZE_A23_0   0x03000000
 198 +#define SFCON_DEV_SIZE_MASK    0x0F000000
 199 +/* Read Data Position */
 200 +#define SFTIME_RD_POS_MASK     0x000F0000
 201 +/* Data Output */
 202 +#define SFIO_UNUSED_WD_MASK    0x0000000F
 203 +/* Command Opcode mask */
 204 +#define SFCMD_OPC_MASK         0x000000FF
 205 +/* dlen bytes of data to write */
 206 +#define SFCMD_DIR_WRITE                0x00000100
 207 +/* Data Length offset */
 208 +#define SFCMD_DLEN_OFFSET      9
 209 +/* Command Error */
 210 +#define SFSTAT_CMD_ERR         0x20000000
 211 +/* Access Command Pending */
 212 +#define SFSTAT_CMD_PEND                0x00400000
 213 +/* Frequency set to 100MHz. */
 214 +#define EBUCC_EBUDIV_SELF100   0x00000001
 215 +/* Serial Flash */
 216 +#define BUSRCON0_AGEN_SERIAL_FLASH     0xF0000000
 217 +/* 8-bit multiplexed */
 218 +#define BUSRCON0_PORTW_8_BIT_MUX       0x00000000
 219 +/* Serial Flash */
 220 +#define BUSWCON0_AGEN_SERIAL_FLASH     0xF0000000
 221 +/* Chip Select after opcode */
 222 +#define SFCMD_KEEP_CS_KEEP_SELECTED    0x00008000
 223 +
 224 +struct falcon_spi {
 225 +       u32 sfcmd; /* for caching of opcode, direction, ... */
 226 +       struct spi_master *master;
 227 +};
 228 +
 229 +int
 230 +falcon_spi_xfer(struct spi_device *spi,
 231 +                   struct spi_transfer *t,
 232 +                   unsigned long flags)
 233 +{
 234 +       struct device *dev = &spi->dev;
 235 +       struct falcon_spi *priv = spi_master_get_devdata(spi->master);
 236 +       const u8 *txp = t->tx_buf;
 237 +       u8 *rxp = t->rx_buf;
 238 +       unsigned int bytelen = ((8 * t->len + 7) / 8);
 239 +       unsigned int len, alen, dumlen;
 240 +       u32 val;
 241 +       enum {
 242 +               state_init,
 243 +               state_command_prepare,
 244 +               state_write,
 245 +               state_read,
 246 +               state_disable_cs,
 247 +               state_end
 248 +       } state = state_init;
 249 +
 250 +       do {
 251 +               switch (state) {
 252 +               case state_init: /* detect phase of upper layer sequence */
 253 +               {
 254 +                       /* initial write ? */
 255 +                       if (flags & FALCON_SPI_XFER_BEGIN) {
 256 +                               if (!txp) {
 257 +                                       dev_err(dev,
 258 +                                               "BEGIN without tx data!\n");
 259 +                                       return -1;
 260 +                               }
 261 +                               /*
 262 +                                * Prepare the parts of the sfcmd register,
 263 +                                * which should not
 264 +                                * change during a sequence!
 265 +                                * Only exception are the length fields,
 266 +                                * especially alen and dumlen.
 267 +                                */
 268 +
 269 +                               priv->sfcmd = ((spi->chip_select
 270 +                                               << SFCMD_CS_OFFSET)
 271 +                                              & SFCMD_CS_MASK);
 272 +                               priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
 273 +                               priv->sfcmd |= *txp;
 274 +                               txp++;
 275 +                               bytelen--;
 276 +                               if (bytelen) {
 277 +                                       /*
 278 +                                        * more data:
 279 +                                        * maybe address and/or dummy
 280 +                                        */
 281 +                                       state = state_command_prepare;
 282 +                                       break;
 283 +                               } else {
 284 +                                       dev_dbg(dev, "write cmd %02X\n",
 285 +                                               priv->sfcmd & SFCMD_OPC_MASK);
 286 +                               }
 287 +                       }
 288 +                       /* continued write ? */
 289 +                       if (txp && bytelen) {
 290 +                               state = state_write;
 291 +                               break;
 292 +                       }
 293 +                       /* read data? */
 294 +                       if (rxp && bytelen) {
 295 +                               state = state_read;
 296 +                               break;
 297 +                       }
 298 +                       /* end of sequence? */
 299 +                       if (flags & FALCON_SPI_XFER_END)
 300 +                               state = state_disable_cs;
 301 +                       else
 302 +                               state = state_end;
 303 +                       break;
 304 +               }
 305 +               /* collect tx data for address and dummy phase */
 306 +               case state_command_prepare:
 307 +               {
 308 +                       /* txp is valid, already checked */
 309 +                       val = 0;
 310 +                       alen = 0;
 311 +                       dumlen = 0;
 312 +                       while (bytelen > 0) {
 313 +                               if (alen < 3) {
 314 +                                       val = (val<<8)|(*txp++);
 315 +                                       alen++;
 316 +                               } else if ((dumlen < 15) && (*txp == 0)) {
 317 +                                       /*
 318 +                                        * assume dummy bytes are set to 0
 319 +                                        * from upper layer
 320 +                                        */
 321 +                                       dumlen++;
 322 +                                       txp++;
 323 +                               } else
 324 +                                       break;
 325 +                               bytelen--;
 326 +                       }
 327 +                       priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
 328 +                       priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
 329 +                                        (dumlen << SFCMD_DUMLEN_OFFSET);
 330 +                       if (alen > 0)
 331 +                               ltq_ebu_w32(val, LTQ_SFADDR);
 332 +
 333 +                       dev_dbg(dev, "write cmd %02X, alen=%d "
 334 +                               "(addr=%06X) dumlen=%d\n",
 335 +                               priv->sfcmd & SFCMD_OPC_MASK,
 336 +                               alen, val, dumlen);
 337 +
 338 +                       if (bytelen > 0) {
 339 +                               /* continue with write */
 340 +                               state = state_write;
 341 +                       } else if (flags & FALCON_SPI_XFER_END) {
 342 +                               /* end of sequence? */
 343 +                               state = state_disable_cs;
 344 +                       } else {
 345 +                               /*
 346 +                                * go to end and expect another
 347 +                                * call (read or write)
 348 +                                */
 349 +                               state = state_end;
 350 +                       }
 351 +                       break;
 352 +               }
 353 +               case state_write:
 354 +               {
 355 +                       /* txp still valid */
 356 +                       priv->sfcmd |= SFCMD_DIR_WRITE;
 357 +                       len = 0;
 358 +                       val = 0;
 359 +                       do {
 360 +                               if (bytelen--)
 361 +                                       val |= (*txp++) << (8 * len++);
 362 +                               if ((flags & FALCON_SPI_XFER_END)
 363 +                                   && (bytelen == 0)) {
 364 +                                       priv->sfcmd &=
 365 +                                               ~SFCMD_KEEP_CS_KEEP_SELECTED;
 366 +                               }
 367 +                               if ((len == 4) || (bytelen == 0)) {
 368 +                                       ltq_ebu_w32(val, LTQ_SFDATA);
 369 +                                       ltq_ebu_w32(priv->sfcmd
 370 +                                               | (len<<SFCMD_DLEN_OFFSET),
 371 +                                               LTQ_SFCMD);
 372 +                                       len = 0;
 373 +                                       val = 0;
 374 +                                       priv->sfcmd &= ~(SFCMD_ALEN_MASK
 375 +                                                        | SFCMD_DUMLEN_MASK);
 376 +                               }
 377 +                       } while (bytelen);
 378 +                       state = state_end;
 379 +                       break;
 380 +               }
 381 +               case state_read:
 382 +               {
 383 +                       /* read data */
 384 +                       priv->sfcmd &= ~SFCMD_DIR_WRITE;
 385 +                       do {
 386 +                               if ((flags & FALCON_SPI_XFER_END)
 387 +                                   && (bytelen <= 4)) {
 388 +                                       priv->sfcmd &=
 389 +                                               ~SFCMD_KEEP_CS_KEEP_SELECTED;
 390 +                               }
 391 +                               len = (bytelen > 4) ? 4 : bytelen;
 392 +                               bytelen -= len;
 393 +                               ltq_ebu_w32(priv->sfcmd
 394 +                                       |(len<<SFCMD_DLEN_OFFSET), LTQ_SFCMD);
 395 +                               priv->sfcmd &= ~(SFCMD_ALEN_MASK
 396 +                                                | SFCMD_DUMLEN_MASK);
 397 +                               do {
 398 +                                       val = ltq_ebu_r32(LTQ_SFSTAT);
 399 +                                       if (val & SFSTAT_CMD_ERR) {
 400 +                                               /* reset error status */
 401 +                                               dev_err(dev, "SFSTAT: CMD_ERR "
 402 +                                                       "(%x)\n", val);
 403 +                                               ltq_ebu_w32(SFSTAT_CMD_ERR,
 404 +                                                       LTQ_SFSTAT);
 405 +                                               return -1;
 406 +                                       }
 407 +                               } while (val & SFSTAT_CMD_PEND);
 408 +                               val = ltq_ebu_r32(LTQ_SFDATA);
 409 +                               do {
 410 +                                       *rxp = (val & 0xFF);
 411 +                                       rxp++;
 412 +                                       val >>= 8;
 413 +                                       len--;
 414 +                               } while (len);
 415 +                       } while (bytelen);
 416 +                       state = state_end;
 417 +                       break;
 418 +               }
 419 +               case state_disable_cs:
 420 +               {
 421 +                       priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
 422 +                       ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
 423 +                               LTQ_SFCMD);
 424 +                       val = ltq_ebu_r32(LTQ_SFSTAT);
 425 +                       if (val & SFSTAT_CMD_ERR) {
 426 +                               /* reset error status */
 427 +                               dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
 428 +                               ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT);
 429 +                               return -1;
 430 +                       }
 431 +                       state = state_end;
 432 +                       break;
 433 +               }
 434 +               case state_end:
 435 +                       break;
 436 +               }
 437 +       } while (state != state_end);
 438 +
 439 +       return 0;
 440 +}
 441 +
 442 +static int
 443 +falcon_spi_setup(struct spi_device *spi)
 444 +{
 445 +       struct device *dev = &spi->dev;
 446 +       const u32 ebuclk = 100000000;
 447 +       unsigned int i;
 448 +       unsigned long flags;
 449 +
 450 +       dev_dbg(dev, "setup\n");
 451 +
 452 +       if (spi->master->bus_num > 0 || spi->chip_select > 0)
 453 +               return -ENODEV;
 454 +
 455 +       spin_lock_irqsave(&ebu_lock, flags);
 456 +
 457 +       if (ebuclk < spi->max_speed_hz) {
 458 +               /* set EBU clock to 100 MHz */
 459 +               ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC);
 460 +               i = 1; /* divider */
 461 +       } else {
 462 +               /* set EBU clock to 50 MHz */
 463 +               ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC);
 464 +
 465 +               /* search for suitable divider */
 466 +               for (i = 1; i < 7; i++) {
 467 +                       if (ebuclk / i <= spi->max_speed_hz)
 468 +                               break;
 469 +               }
 470 +       }
 471 +
 472 +       /* setup period of serial clock */
 473 +       ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
 474 +                    | SFTIME_SCKR_POS_MASK
 475 +                    | SFTIME_SCK_PER_MASK,
 476 +                    (i << SFTIME_SCKR_POS_OFFSET)
 477 +                    | (i << (SFTIME_SCK_PER_OFFSET + 1)),
 478 +                    LTQ_SFTIME);
 479 +
 480 +       /*
 481 +        * set some bits of unused_wd, to not trigger HOLD/WP
 482 +        * signals on non QUAD flashes
 483 +        */
 484 +       ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO);
 485 +
 486 +       ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
 487 +               LTQ_BUSRCON0);
 488 +       ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0);
 489 +       /* set address wrap around to maximum for 24-bit addresses */
 490 +       ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON);
 491 +
 492 +       spin_unlock_irqrestore(&ebu_lock, flags);
 493 +
 494 +       return 0;
 495 +}
 496 +
 497 +static int
 498 +falcon_spi_transfer(struct spi_device *spi, struct spi_message *m)
 499 +{
 500 +       struct falcon_spi *priv = spi_master_get_devdata(spi->master);
 501 +       struct spi_transfer *t;
 502 +       unsigned long spi_flags;
 503 +       unsigned long flags;
 504 +       int ret = 0;
 505 +
 506 +       priv->sfcmd = 0;
 507 +       m->actual_length = 0;
 508 +
 509 +       spi_flags = FALCON_SPI_XFER_BEGIN;
 510 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 511 +               if (list_is_last(&t->transfer_list, &m->transfers))
 512 +                       spi_flags |= FALCON_SPI_XFER_END;
 513 +
 514 +               spin_lock_irqsave(&ebu_lock, flags);
 515 +               ret = falcon_spi_xfer(spi, t, spi_flags);
 516 +               spin_unlock_irqrestore(&ebu_lock, flags);
 517 +
 518 +               if (ret)
 519 +                       break;
 520 +
 521 +               m->actual_length += t->len;
 522 +
 523 +               if (t->delay_usecs || t->cs_change)
 524 +                       BUG();
 525 +
 526 +               spi_flags = 0;
 527 +       }
 528 +
 529 +       m->status = ret;
 530 +       m->complete(m->context);
 531 +
 532 +       return 0;
 533 +}
 534 +
 535 +static void
 536 +falcon_spi_cleanup(struct spi_device *spi)
 537 +{
 538 +       struct device *dev = &spi->dev;
 539 +
 540 +       dev_dbg(dev, "cleanup\n");
 541 +}
 542 +
 543 +static int __devinit
 544 +falcon_spi_probe(struct platform_device *pdev)
 545 +{
 546 +       struct device *dev = &pdev->dev;
 547 +       struct falcon_spi *priv;
 548 +       struct spi_master *master;
 549 +       int ret;
 550 +
 551 +       dev_dbg(dev, "probing\n");
 552 +
 553 +       master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 554 +       if (!master) {
 555 +               dev_err(dev, "no memory for spi_master\n");
 556 +               return -ENOMEM;
 557 +       }
 558 +
 559 +       priv = spi_master_get_devdata(master);
 560 +       priv->master = master;
 561 +
 562 +       master->mode_bits = SPI_MODE_3;
 563 +       master->num_chipselect = 1;
 564 +       master->bus_num = 0;
 565 +
 566 +       master->setup = falcon_spi_setup;
 567 +       master->transfer = falcon_spi_transfer;
 568 +       master->cleanup = falcon_spi_cleanup;
 569 +
 570 +       platform_set_drvdata(pdev, priv);
 571 +
 572 +       ret = spi_register_master(master);
 573 +       if (ret)
 574 +               spi_master_put(master);
 575 +
 576 +       return ret;
 577 +}
 578 +
 579 +static int __devexit
 580 +falcon_spi_remove(struct platform_device *pdev)
 581 +{
 582 +       struct device *dev = &pdev->dev;
 583 +       struct falcon_spi *priv = platform_get_drvdata(pdev);
 584 +
 585 +       dev_dbg(dev, "removed\n");
 586 +
 587 +       spi_unregister_master(priv->master);
 588 +
 589 +       return 0;
 590 +}
 591 +
 592 +static struct platform_driver falcon_spi_driver = {
 593 +       .probe  = falcon_spi_probe,
 594 +       .remove = __devexit_p(falcon_spi_remove),
 595 +       .driver = {
 596 +               .name   = DRV_NAME,
 597 +               .owner  = THIS_MODULE
 598 +       }
 599 +};
 600 +
 601 +static int __init
 602 +falcon_spi_init(void)
 603 +{
 604 +       return platform_driver_register(&falcon_spi_driver);
 605 +}
 606 +
 607 +static void __exit
 608 +falcon_spi_exit(void)
 609 +{
 610 +       platform_driver_unregister(&falcon_spi_driver);
 611 +}
 612 +
 613 +module_init(falcon_spi_init);
 614 +module_exit(falcon_spi_exit);
 615 +
 616 +MODULE_LICENSE("GPL");
 617 +MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");