target/linux/lantiq/patches-3.2/0037-MIPS-lantiq-add-additional-soc-ids.patch

   1 From 5585147ea9462778decc7146667ac54413acd91f Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 12 Mar 2012 15:23:39 +0100
   4 Subject: [PATCH 37/73] MIPS: lantiq: add additional soc ids
   5
   6 ---
   7  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   38 +++++++++++++++----
   8  arch/mips/lantiq/xway/prom.c                       |   35 ++++++++++++++++--
   9  2 files changed, 61 insertions(+), 12 deletions(-)
  10
  11 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  12 index 5d11eb7..3f22acb 100644
  13 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  14 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  15 @@ -17,20 +17,32 @@
  16  #define SOC_ID_DANUBE1         0x129
  17  #define SOC_ID_DANUBE2         0x12B
  18  #define SOC_ID_TWINPASS                0x12D
  19 -#define SOC_ID_AMAZON_SE       0x152
  20 +#define SOC_ID_AMAZON_SE_1     0x152 /* 50601 */
  21 +#define SOC_ID_AMAZON_SE_2     0x153 /* 50600 */
  22  #define SOC_ID_ARX188          0x16C
  23 -#define SOC_ID_ARX168          0x16D
  24 +#define SOC_ID_ARX168_1                0x16D
  25 +#define SOC_ID_ARX168_2                0x16E
  26  #define SOC_ID_ARX182          0x16F
  27 -#define SOC_ID_VRX288          0x1C0 /* VRX288 v1.1 */
  28 -#define SOC_ID_VRX268          0x1C2 /* VRX268 v1.1 */
  29 -#define SOC_ID_GRX288          0x1C9 /* GRX288 v1.1 */
  30 +#define SOC_ID_GRX188          0x170
  31 +#define SOC_ID_GRX168          0x171
  32 +
  33 +#define SOC_ID_VRX288          0x1C0 /* v1.1 */
  34 +#define SOC_ID_VRX282          0x1C1 /* v1.1 */
  35 +#define SOC_ID_VRX268          0x1C2 /* v1.1 */
  36 +#define SOC_ID_GRX268          0x1C8 /* v1.1 */
  37 +#define SOC_ID_GRX288          0x1C9 /* v1.1 */
  38 +#define SOC_ID_VRX288_2                0x00B /* v1.2 */
  39 +#define SOC_ID_VRX268_2                0x00C /* v1.2 */
  40 +#define SOC_ID_GRX288_2                0x00D /* v1.2 */
  41 +#define SOC_ID_GRX282_2                0x00E /* v1.2 */
  42
  43  /* SoC Types */
  44  #define SOC_TYPE_DANUBE                0x01
  45  #define SOC_TYPE_TWINPASS      0x02
  46  #define SOC_TYPE_AR9           0x03
  47 -#define SOC_TYPE_VR9           0x04
  48 -#define SOC_TYPE_AMAZON_SE     0x05
  49 +#define SOC_TYPE_VR9_1         0x04 /* v1.1 */
  50 +#define SOC_TYPE_VR9_2         0x05 /* v1.2 */
  51 +#define SOC_TYPE_AMAZON_SE     0x06
  52
  53  /* ASC0/1 - serial port */
  54  #define LTQ_ASC0_BASE_ADDR     0x1E100400
  55 @@ -149,9 +161,19 @@ static inline int ltq_is_ar9(void)
  56         return (ltq_get_soc_type() == SOC_TYPE_AR9);
  57  }
  58
  59 +static inline int ltq_is_vr9_1(void)
  60 +{
  61 +       return (ltq_get_soc_type() == SOC_TYPE_VR9_1);
  62 +}
  63 +
  64 +static inline int ltq_is_vr9_2(void)
  65 +{
  66 +       return (ltq_get_soc_type() == SOC_TYPE_VR9_2);
  67 +}
  68 +
  69  static inline int ltq_is_vr9(void)
  70  {
  71 -       return (ltq_get_soc_type() == SOC_TYPE_VR9);
  72 +       return (ltq_is_vr9_1() || ltq_is_vr9_2());
  73  }
  74
  75  static inline int ltq_is_falcon(void)
  76 diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
  77 index b6f56b7..e3dcbbd 100644
  78 --- a/arch/mips/lantiq/xway/prom.c
  79 +++ b/arch/mips/lantiq/xway/prom.c
  80 @@ -18,7 +18,9 @@
  81
  82  #define SOC_DANUBE     "Danube"
  83  #define SOC_TWINPASS   "Twinpass"
  84 +#define SOC_AMAZON_SE  "Amazon_SE"
  85  #define SOC_AR9                "AR9"
  86 +#define SOC_GR9                "GR9"
  87  #define SOC_VR9                "VR9"
  88
  89  #define PART_SHIFT     12
  90 @@ -26,7 +28,6 @@
  91  #define REV_SHIFT      28
  92  #define REV_MASK       0xF0000000
  93
  94 -#define SOC_AMAZON_SE  "Amazon_SE"
  95
  96  void __init ltq_soc_detect(struct ltq_soc_info *i)
  97  {
  98 @@ -46,13 +47,21 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
  99                 break;
 100
 101         case SOC_ID_ARX188:
 102 -       case SOC_ID_ARX168:
 103 +       case SOC_ID_ARX168_1:
 104 +       case SOC_ID_ARX168_2:
 105         case SOC_ID_ARX182:
 106                 i->name = SOC_AR9;
 107                 i->type = SOC_TYPE_AR9;
 108                 break;
 109
 110 -       case SOC_ID_AMAZON_SE:
 111 +       case SOC_ID_GRX188:
 112 +       case SOC_ID_GRX168:
 113 +               i->name = SOC_GR9;
 114 +               i->type = SOC_TYPE_AR9;
 115 +               break;
 116 +
 117 +       case SOC_ID_AMAZON_SE_1:
 118 +       case SOC_ID_AMAZON_SE_2:
 119                 i->name = SOC_AMAZON_SE;
 120                 i->type = SOC_TYPE_AMAZON_SE;
 121  #ifdef CONFIG_PCI
 122 @@ -60,12 +69,30 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
 123  #endif
 124                 break;
 125
 126 +       case SOC_ID_VRX282:
 127         case SOC_ID_VRX268:
 128         case SOC_ID_VRX288:
 129                 i->name = SOC_VR9;
 130 -               i->type = SOC_TYPE_VR9;
 131 +               i->type = SOC_TYPE_VR9_1;
 132                 break;
 133
 134 +       case SOC_ID_GRX268:
 135 +       case SOC_ID_GRX288:
 136 +               i->name = SOC_GR9;
 137 +               i->type = SOC_TYPE_VR9_1;
 138 +               break;
 139 +
 140 +       case SOC_ID_VRX268_2:
 141 +       case SOC_ID_VRX288_2:
 142 +               i->name = SOC_VR9;
 143 +               i->type = SOC_TYPE_VR9_2;
 144 +               break;
 145 +
 146 +       case SOC_ID_GRX282_2:
 147 +       case SOC_ID_GRX288_2:
 148 +               i->name = SOC_GR9;
 149 +               i->type = SOC_TYPE_VR9_2;
 150 +
 151         default:
 152                 unreachable();
 153                 break;
 154 --
 155 1.7.9.1
 156