target/linux/lantiq/patches-3.2/0036-MIPS-lantiq-add-vr9-support.patch

   1 From 27c4128ab1835a2aff1a0ce6413bb21cfa614d93 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 21 Feb 2012 09:48:11 +0100
   4 Subject: [PATCH 36/70] MIPS: lantiq: add vr9 support
   5
   6 VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9.
   7 This patch adds the clkdev init code and SoC detection for the VR9.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  11 ---
  12  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    3 +
  13  arch/mips/lantiq/xway/clk.c                        |   83 ++++++++++++++++++++
  14  arch/mips/lantiq/xway/prom.c                       |    6 ++
  15  arch/mips/lantiq/xway/sysctrl.c                    |   12 +++-
  16  4 files changed, 103 insertions(+), 1 deletions(-)
  17
  18 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  19 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  20 @@ -21,6 +21,9 @@
  21  #define SOC_ID_ARX188          0x16C
  22  #define SOC_ID_ARX168          0x16D
  23  #define SOC_ID_ARX182          0x16F
  24 +#define SOC_ID_VRX288          0x1C0 /* VRX288 v1.1 */
  25 +#define SOC_ID_VRX268          0x1C2 /* VRX268 v1.1 */
  26 +#define SOC_ID_GRX288          0x1C9 /* GRX288 v1.1 */
  27
  28  /* SoC Types */
  29  #define SOC_TYPE_DANUBE                0x01
  30 --- a/arch/mips/lantiq/xway/clk.c
  31 +++ b/arch/mips/lantiq/xway/clk.c
  32 @@ -225,3 +225,86 @@ unsigned long ltq_danube_fpi_hz(void)
  33                 return ddr_clock >> 1;
  34         return ddr_clock;
  35  }
  36 +
  37 +unsigned long ltq_vr9_cpu_hz(void)
  38 +{
  39 +       unsigned int cpu_sel;
  40 +       unsigned long clk;
  41 +
  42 +       cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf;
  43 +
  44 +       switch (cpu_sel) {
  45 +       case 0:
  46 +               clk = CLOCK_600M;
  47 +               break;
  48 +       case 1:
  49 +               clk = CLOCK_500M;
  50 +               break;
  51 +       case 2:
  52 +               clk = CLOCK_393M;
  53 +               break;
  54 +       case 3:
  55 +               clk = CLOCK_333M;
  56 +               break;
  57 +       case 5:
  58 +       case 6:
  59 +               clk = CLOCK_196_608M;
  60 +               break;
  61 +       case 7:
  62 +               clk = CLOCK_167M;
  63 +               break;
  64 +       case 4:
  65 +       case 8:
  66 +       case 9:
  67 +               clk = CLOCK_125M;
  68 +               break;
  69 +       default:
  70 +               clk = 0;
  71 +               break;
  72 +       }
  73 +
  74 +       return clk;
  75 +}
  76 +
  77 +unsigned long ltq_vr9_fpi_hz(void)
  78 +{
  79 +       unsigned int ocp_sel, cpu_clk;
  80 +       unsigned long clk;
  81 +
  82 +       cpu_clk = ltq_vr9_cpu_hz();
  83 +       ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3;
  84 +
  85 +       switch (ocp_sel) {
  86 +       case 0:
  87 +               /* OCP ratio 1 */
  88 +               clk = cpu_clk;
  89 +               break;
  90 +       case 2:
  91 +               /* OCP ratio 2 */
  92 +               clk = cpu_clk / 2;
  93 +               break;
  94 +       case 3:
  95 +               /* OCP ratio 2.5 */
  96 +               clk = (cpu_clk * 2) / 5;
  97 +               break;
  98 +       case 4:
  99 +               /* OCP ratio 3 */
 100 +               clk = cpu_clk / 3;
 101 +               break;
 102 +       default:
 103 +               clk = 0;
 104 +               break;
 105 +       }
 106 +
 107 +       return clk;
 108 +}
 109 +
 110 +unsigned long ltq_vr9_io_region_clock(void)
 111 +{
 112 +       return ltq_vr9_fpi_hz();
 113 +}
 114 +
 115 +unsigned long ltq_vr9_fpi_bus_clock(int fpi)
 116 +{
 117 +       return ltq_vr9_fpi_hz();
 118 +}
 119 --- a/arch/mips/lantiq/xway/prom.c
 120 +++ b/arch/mips/lantiq/xway/prom.c
 121 @@ -60,6 +60,12 @@ void __init ltq_soc_detect(struct ltq_so
 122  #endif
 123                 break;
 124
 125 +       case SOC_ID_VRX268:
 126 +       case SOC_ID_VRX288:
 127 +               i->name = SOC_VR9;
 128 +               i->type = SOC_TYPE_VR9;
 129 +               break;
 130 +
 131         default:
 132                 unreachable();
 133                 break;
 134 --- a/arch/mips/lantiq/xway/sysctrl.c
 135 +++ b/arch/mips/lantiq/xway/sysctrl.c
 136 @@ -147,7 +147,8 @@ void __init ltq_soc_init(void)
 137         clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
 138         clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
 139         clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
 140 -       clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 141 +       if (!ltq_is_vr9())
 142 +               clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 143         if (ltq_is_ase()) {
 144                 if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
 145                         clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
 146 @@ -155,6 +156,15 @@ void __init ltq_soc_init(void)
 147                         clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 148                 clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
 149                 clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
 150 +       } else if (ltq_is_vr9()) {
 151 +               clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 152 +                                       ltq_vr9_io_region_clock());
 153 +               clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
 154 +               clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
 155 +               clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
 156 +               clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
 157 +               clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
 158 +               clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
 159         } else {
 160                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 161                                         ltq_danube_io_region_clock());