target/linux/lantiq/patches-3.10/0101-timer-backport.patch

   1 From 2eb3fca4b1ed36841e281e014cc2e17ec9154533 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 13 Mar 2013 10:01:49 +0100
   4 Subject: [PATCH 08/34] MIPS: lantiq: backport old timer code
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
   9  arch/mips/lantiq/xway/Makefile                   |    2 +-
  10  arch/mips/lantiq/xway/timer.c                    |  845 ++++++++++++++++++++++
  11  3 files changed, 1001 insertions(+), 1 deletion(-)
  12  create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  13  create mode 100644 arch/mips/lantiq/xway/timer.c
  14
  15 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  16 new file mode 100644
  17 index 0000000..ef564ab
  18 --- /dev/null
  19 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  20 @@ -0,0 +1,155 @@
  21 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  22 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  23 +
  24 +
  25 +/******************************************************************************
  26 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
  27 +
  28 +                               No Warranty
  29 +   Because the program is licensed free of charge, there is no warranty for
  30 +   the program, to the extent permitted by applicable law.  Except when
  31 +   otherwise stated in writing the copyright holders and/or other parties
  32 +   provide the program "as is" without warranty of any kind, either
  33 +   expressed or implied, including, but not limited to, the implied
  34 +   warranties of merchantability and fitness for a particular purpose. The
  35 +   entire risk as to the quality and performance of the program is with
  36 +   you.  should the program prove defective, you assume the cost of all
  37 +   necessary servicing, repair or correction.
  38 +
  39 +   In no event unless required by applicable law or agreed to in writing
  40 +   will any copyright holder, or any other party who may modify and/or
  41 +   redistribute the program as permitted above, be liable to you for
  42 +   damages, including any general, special, incidental or consequential
  43 +   damages arising out of the use or inability to use the program
  44 +   (including but not limited to loss of data or data being rendered
  45 +   inaccurate or losses sustained by you or third parties or a failure of
  46 +   the program to operate with any other programs), even if such holder or
  47 +   other party has been advised of the possibility of such damages.
  48 +******************************************************************************/
  49 +
  50 +
  51 +/*
  52 + * ####################################
  53 + *              Definition
  54 + * ####################################
  55 + */
  56 +
  57 +/*
  58 + *  Available Timer/Counter Index
  59 + */
  60 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
  61 +#define TIMER_ANY                       0x00
  62 +#define TIMER1A                         TIMER(1, 0)
  63 +#define TIMER1B                         TIMER(1, 1)
  64 +#define TIMER2A                         TIMER(2, 0)
  65 +#define TIMER2B                         TIMER(2, 1)
  66 +#define TIMER3A                         TIMER(3, 0)
  67 +#define TIMER3B                         TIMER(3, 1)
  68 +
  69 +/*
  70 + *  Flag of Timer/Counter
  71 + *  These flags specify the way in which timer is configured.
  72 + */
  73 +/*  Bit size of timer/counter.                      */
  74 +#define TIMER_FLAG_16BIT                0x0000
  75 +#define TIMER_FLAG_32BIT                0x0001
  76 +/*  Switch between timer and counter.               */
  77 +#define TIMER_FLAG_TIMER                0x0000
  78 +#define TIMER_FLAG_COUNTER              0x0002
  79 +/*  Stop or continue when overflowing/underflowing. */
  80 +#define TIMER_FLAG_ONCE                 0x0000
  81 +#define TIMER_FLAG_CYCLIC               0x0004
  82 +/*  Count up or counter down.                       */
  83 +#define TIMER_FLAG_UP                   0x0000
  84 +#define TIMER_FLAG_DOWN                 0x0008
  85 +/*  Count on specific level or edge.                */
  86 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
  87 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
  88 +#define TIMER_FLAG_RISE_EDGE            0x0010
  89 +#define TIMER_FLAG_FALL_EDGE            0x0020
  90 +#define TIMER_FLAG_ANY_EDGE             0x0030
  91 +/*  Signal is syncronous to module clock or not.    */
  92 +#define TIMER_FLAG_UNSYNC               0x0000
  93 +#define TIMER_FLAG_SYNC                 0x0080
  94 +/*  Different interrupt handle type.                */
  95 +#define TIMER_FLAG_NO_HANDLE            0x0000
  96 +#if defined(__KERNEL__)
  97 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
  98 +#endif  //  defined(__KERNEL__)
  99 +#define TIMER_FLAG_SIGNAL               0x0300
 100 +/*  Internal clock source or external clock source  */
 101 +#define TIMER_FLAG_INT_SRC              0x0000
 102 +#define TIMER_FLAG_EXT_SRC              0x1000
 103 +
 104 +
 105 +/*
 106 + *  ioctl Command
 107 + */
 108 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 109 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 110 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 111 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 112 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 113 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 114 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 115 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 116 +
 117 +/*
 118 + *  Data Type Used to Call ioctl
 119 + */
 120 +struct gptu_ioctl_param {
 121 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 122 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 123 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 124 +                                                 *  be dynamically allocated and ID would be stored in  *
 125 +                                                 *  this field.                                         *
 126 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 127 +                                                 *  ignored.                                            *
 128 +                                                 *  In other command, this field is ID of timer/counter *
 129 +                                                 *  allocated.                                          */
 130 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 131 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 132 +                                                 *  specify how to configure timer/counter.             *
 133 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 134 +                                                 *  and non-zero indicate resume timer/counter.         *
 135 +                                                 *  In other command, this field is ignored.            */
 136 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 137 +                                                 *  init/reload value.                                  *
 138 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 139 +                                                 *  frequency (0.001Hz) of timer.                       *
 140 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 141 +                                                 *  value would be stored in this field.                *
 142 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 143 +                                                 *  contains frequency wanted, and after calculation,   *
 144 +                                                 *  divider would be stored in this field to overwrite  *
 145 +                                                 *  the frequency.                                      *
 146 +                                                 *  In other command, this field is ignored.            */
 147 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 148 +                                                 *  if signal is required, this field contains process  *
 149 +                                                 *  ID to which signal would be sent.                   *
 150 +                                                 *  In other command, this field is ignored.            */
 151 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 152 +                                                 *  if signal is required, this field contains signal   *
 153 +                                                 *  number which would be sent.                         *
 154 +                                                 *  In other command, this field is ignored.            */
 155 +};
 156 +
 157 +/*
 158 + * ####################################
 159 + *              Data Type
 160 + * ####################################
 161 + */
 162 +typedef void (*timer_callback)(unsigned long arg);
 163 +
 164 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
 165 +extern int lq_free_timer(unsigned int);
 166 +extern int lq_start_timer(unsigned int, int);
 167 +extern int lq_stop_timer(unsigned int);
 168 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
 169 +extern int lq_get_count_value(unsigned int, unsigned long *);
 170 +extern u32 lq_cal_divider(unsigned long);
 171 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
 172 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
 173 +       u32 reload, unsigned long arg1, unsigned long arg2);
 174 +
 175 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
 176 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
 177 index a2edc53..da51fe0 100644
 178 --- a/arch/mips/lantiq/xway/Makefile
 179 +++ b/arch/mips/lantiq/xway/Makefile
 180 @@ -1,4 +1,4 @@
 181 -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
 182 +obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o
 183
 184  obj-y += vmmc.o
 185
 186 diff --git a/arch/mips/lantiq/xway/timer.c b/arch/mips/lantiq/xway/timer.c
 187 new file mode 100644
 188 index 0000000..1c0fdb8
 189 --- /dev/null
 190 +++ b/arch/mips/lantiq/xway/timer.c
 191 @@ -0,0 +1,845 @@
 192 +#ifndef CONFIG_SOC_AMAZON_SE
 193 +
 194 +#include <linux/kernel.h>
 195 +#include <linux/module.h>
 196 +#include <linux/version.h>
 197 +#include <linux/types.h>
 198 +#include <linux/fs.h>
 199 +#include <linux/miscdevice.h>
 200 +#include <linux/init.h>
 201 +#include <linux/uaccess.h>
 202 +#include <linux/unistd.h>
 203 +#include <linux/errno.h>
 204 +#include <linux/interrupt.h>
 205 +#include <linux/sched.h>
 206 +
 207 +#include <asm/irq.h>
 208 +#include <asm/div64.h>
 209 +#include "../clk.h"
 210 +
 211 +#include <lantiq_soc.h>
 212 +#include <lantiq_irq.h>
 213 +#include <lantiq_timer.h>
 214 +
 215 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
 216 +
 217 +#ifdef TIMER1A
 218 +#define FIRST_TIMER                    TIMER1A
 219 +#else
 220 +#define FIRST_TIMER                    2
 221 +#endif
 222 +
 223 +/*
 224 + *  GPTC divider is set or not.
 225 + */
 226 +#define GPTU_CLC_RMC_IS_SET            0
 227 +
 228 +/*
 229 + *  Timer Interrupt (IRQ)
 230 + */
 231 +/*  Must be adjusted when ICU driver is available */
 232 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
 233 +
 234 +/*
 235 + *  Bits Operation
 236 + */
 237 +#define GET_BITS(x, msb, lsb)          \
 238 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
 239 +#define SET_BITS(x, msb, lsb, value)   \
 240 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
 241 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
 242 +
 243 +/*
 244 + *  GPTU Register Mapping
 245 + */
 246 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
 247 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
 248 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
 249 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 250 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 251 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 252 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 253 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
 254 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
 255 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
 256 +
 257 +/*
 258 + *  Clock Control Register
 259 + */
 260 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
 261 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
 262 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
 263 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
 264 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
 265 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
 266 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
 267 +
 268 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
 269 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
 270 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
 271 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
 272 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
 273 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
 274 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
 275 +
 276 +/*
 277 + *  ID Register
 278 + */
 279 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
 280 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
 281 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
 282 +
 283 +/*
 284 + *  Control Register of Timer/Counter nX
 285 + *    n is the index of block (1 based index)
 286 + *    X is either A or B
 287 + */
 288 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 289 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 290 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 291 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 292 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 293 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 294 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 295 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 296 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 297 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 298 +
 299 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 300 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 301 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 302 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 303 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 304 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 305 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 306 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 307 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 308 +
 309 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 310 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 311 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 312 +
 313 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 314 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 315 +
 316 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 317 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 318 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 319 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 320 +#define TIMER_FLAG_NONE_EDGE           0x0000
 321 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 322 +#define TIMER_FLAG_REAL                        0x0000
 323 +#define TIMER_FLAG_INVERT              0x0040
 324 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 325 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 326 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 327 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 328 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 329 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 330 +
 331 +struct timer_dev_timer {
 332 +       unsigned int f_irq_on;
 333 +       unsigned int irq;
 334 +       unsigned int flag;
 335 +       unsigned long arg1;
 336 +       unsigned long arg2;
 337 +};
 338 +
 339 +struct timer_dev {
 340 +       struct mutex gptu_mutex;
 341 +       unsigned int number_of_timers;
 342 +       unsigned int occupation;
 343 +       unsigned int f_gptu_on;
 344 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 345 +};
 346 +
 347 +
 348 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 349 +       struct clk *clk = clk_get_fpi();
 350 +       return clk_get_rate(clk);
 351 +}
 352 +
 353 +
 354 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 355 +static int gptu_open(struct inode *, struct file *);
 356 +static int gptu_release(struct inode *, struct file *);
 357 +
 358 +static struct file_operations gptu_fops = {
 359 +       .owner = THIS_MODULE,
 360 +       .unlocked_ioctl = gptu_ioctl,
 361 +       .open = gptu_open,
 362 +       .release = gptu_release
 363 +};
 364 +
 365 +static struct miscdevice gptu_miscdev = {
 366 +       .minor = MISC_DYNAMIC_MINOR,
 367 +       .name = "gptu",
 368 +       .fops = &gptu_fops,
 369 +};
 370 +
 371 +static struct timer_dev timer_dev;
 372 +
 373 +static irqreturn_t timer_irq_handler(int irq, void *p)
 374 +{
 375 +       unsigned int timer;
 376 +       unsigned int flag;
 377 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 378 +
 379 +       timer = irq - TIMER_INTERRUPT;
 380 +       if (timer < timer_dev.number_of_timers
 381 +               && dev_timer == &timer_dev.timer[timer]) {
 382 +               /*  Clear interrupt.    */
 383 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 384 +
 385 +               /*  Call user hanler or signal. */
 386 +               flag = dev_timer->flag;
 387 +               if (!(timer & 0x01)
 388 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 389 +                       /* 16-bit timer or timer A of 32-bit timer  */
 390 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 391 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 392 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 393 +                               if (dev_timer->arg1)
 394 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 395 +                               break;
 396 +                       case TIMER_FLAG_SIGNAL:
 397 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 398 +                               break;
 399 +                       }
 400 +               }
 401 +       }
 402 +       return IRQ_HANDLED;
 403 +}
 404 +
 405 +static inline void lq_enable_gptu(void)
 406 +{
 407 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 408 +       clk_enable(clk);
 409 +
 410 +       //ltq_pmu_enable(PMU_GPT);
 411 +
 412 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 413 +       *LQ_GPTU_CLC =
 414 +               GPTU_CLC_SMC_SET(0x00) |
 415 +               GPTU_CLC_RMC_SET(0x01) |
 416 +               GPTU_CLC_FSOE_SET(0) |
 417 +               GPTU_CLC_SBWE_SET(1) |
 418 +               GPTU_CLC_EDIS_SET(0) |
 419 +               GPTU_CLC_SPEN_SET(0) |
 420 +               GPTU_CLC_DISR_SET(0);
 421 +}
 422 +
 423 +static inline void lq_disable_gptu(void)
 424 +{
 425 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 426 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 427 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 428 +
 429 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 430 +       *LQ_GPTU_CLC =
 431 +               GPTU_CLC_SMC_SET(0x00) |
 432 +               GPTU_CLC_RMC_SET(0x00) |
 433 +               GPTU_CLC_FSOE_SET(0) |
 434 +               GPTU_CLC_SBWE_SET(0) |
 435 +               GPTU_CLC_EDIS_SET(0) |
 436 +               GPTU_CLC_SPEN_SET(0) |
 437 +               GPTU_CLC_DISR_SET(1);
 438 +
 439 +       clk_enable(clk);
 440 +}
 441 +
 442 +int lq_request_timer(unsigned int timer, unsigned int flag,
 443 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 444 +{
 445 +       int ret = 0;
 446 +       unsigned int con_reg, irnen_reg;
 447 +       int n, X;
 448 +
 449 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 450 +               return -EINVAL;
 451 +
 452 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 453 +               timer, flag, value);
 454 +
 455 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 456 +               value &= 0xFFFF;
 457 +       else
 458 +               timer &= ~0x01;
 459 +
 460 +       mutex_lock(&timer_dev.gptu_mutex);
 461 +
 462 +       /*
 463 +        *  Allocate timer.
 464 +        */
 465 +       if (timer < FIRST_TIMER) {
 466 +               unsigned int mask;
 467 +               unsigned int shift;
 468 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 469 +               unsigned int offset = TIMER2A;
 470 +
 471 +               /*
 472 +                *  Pick up a free timer.
 473 +                */
 474 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 475 +                       mask = 1 << offset;
 476 +                       shift = 1;
 477 +               } else {
 478 +                       mask = 3 << offset;
 479 +                       shift = 2;
 480 +               }
 481 +               for (timer = offset;
 482 +                    timer < offset + timer_dev.number_of_timers;
 483 +                    timer += shift, mask <<= shift)
 484 +                       if (!(timer_dev.occupation & mask)) {
 485 +                               timer_dev.occupation |= mask;
 486 +                               break;
 487 +                       }
 488 +               if (timer >= offset + timer_dev.number_of_timers) {
 489 +                       printk("failed![%d]\n", __LINE__);
 490 +                       mutex_unlock(&timer_dev.gptu_mutex);
 491 +                       return -EINVAL;
 492 +               } else
 493 +                       ret = timer;
 494 +       } else {
 495 +               register unsigned int mask;
 496 +
 497 +               /*
 498 +                *  Check if the requested timer is free.
 499 +                */
 500 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 501 +               if ((timer_dev.occupation & mask)) {
 502 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 503 +                               __LINE__, mask, timer_dev.occupation);
 504 +                       mutex_unlock(&timer_dev.gptu_mutex);
 505 +                       return -EBUSY;
 506 +               } else {
 507 +                       timer_dev.occupation |= mask;
 508 +                       ret = 0;
 509 +               }
 510 +       }
 511 +
 512 +       /*
 513 +        *  Prepare control register value.
 514 +        */
 515 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 516 +       default:
 517 +       case TIMER_FLAG_NONE_EDGE:
 518 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 519 +               break;
 520 +       case TIMER_FLAG_RISE_EDGE:
 521 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 522 +               break;
 523 +       case TIMER_FLAG_FALL_EDGE:
 524 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 525 +               break;
 526 +       case TIMER_FLAG_ANY_EDGE:
 527 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 528 +               break;
 529 +       }
 530 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 531 +               con_reg |=
 532 +                       TIMER_FLAG_MASK_SRC(flag) ==
 533 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 534 +                       GPTU_CON_SRC_EXT_SET(0);
 535 +       else
 536 +               con_reg |=
 537 +                       TIMER_FLAG_MASK_SRC(flag) ==
 538 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 539 +                       GPTU_CON_SRC_EG_SET(0);
 540 +       con_reg |=
 541 +               TIMER_FLAG_MASK_SYNC(flag) ==
 542 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 543 +               GPTU_CON_SYNC_SET(1);
 544 +       con_reg |=
 545 +               TIMER_FLAG_MASK_INVERT(flag) ==
 546 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 547 +       con_reg |=
 548 +               TIMER_FLAG_MASK_SIZE(flag) ==
 549 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 550 +               GPTU_CON_EXT_SET(1);
 551 +       con_reg |=
 552 +               TIMER_FLAG_MASK_STOP(flag) ==
 553 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 554 +       con_reg |=
 555 +               TIMER_FLAG_MASK_TYPE(flag) ==
 556 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 557 +               GPTU_CON_CNT_SET(1);
 558 +       con_reg |=
 559 +               TIMER_FLAG_MASK_DIR(flag) ==
 560 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 561 +
 562 +       /*
 563 +        *  Fill up running data.
 564 +        */
 565 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 566 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 567 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 568 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 569 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 570 +
 571 +       /*
 572 +        *  Enable GPTU module.
 573 +        */
 574 +       if (!timer_dev.f_gptu_on) {
 575 +               lq_enable_gptu();
 576 +               timer_dev.f_gptu_on = 1;
 577 +       }
 578 +
 579 +       /*
 580 +        *  Enable IRQ.
 581 +        */
 582 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 583 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 584 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 585 +                               (unsigned long) find_task_by_vpid((int) arg1);
 586 +
 587 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 588 +
 589 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 590 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 591 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 592 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 593 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 594 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 595 +               }
 596 +       } else
 597 +               irnen_reg = 0;
 598 +
 599 +       /*
 600 +        *  Write config register, reload value and enable interrupt.
 601 +        */
 602 +       n = timer >> 1;
 603 +       X = timer & 0x01;
 604 +       *LQ_GPTU_CON(n, X) = con_reg;
 605 +       *LQ_GPTU_RELOAD(n, X) = value;
 606 +       /* printk("reload value = %d\n", (u32)value); */
 607 +       *LQ_GPTU_IRNEN |= irnen_reg;
 608 +
 609 +       mutex_unlock(&timer_dev.gptu_mutex);
 610 +       printk("successful!\n");
 611 +       return ret;
 612 +}
 613 +EXPORT_SYMBOL(lq_request_timer);
 614 +
 615 +int lq_free_timer(unsigned int timer)
 616 +{
 617 +       unsigned int flag;
 618 +       unsigned int mask;
 619 +       int n, X;
 620 +
 621 +       if (!timer_dev.f_gptu_on)
 622 +               return -EINVAL;
 623 +
 624 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 625 +               return -EINVAL;
 626 +
 627 +       mutex_lock(&timer_dev.gptu_mutex);
 628 +
 629 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 630 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 631 +               timer &= ~0x01;
 632 +
 633 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 634 +       if (((timer_dev.occupation & mask) ^ mask)) {
 635 +               mutex_unlock(&timer_dev.gptu_mutex);
 636 +               return -EINVAL;
 637 +       }
 638 +
 639 +       n = timer >> 1;
 640 +       X = timer & 0x01;
 641 +
 642 +       if (GPTU_CON_EN(n, X))
 643 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 644 +
 645 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 646 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 647 +
 648 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 649 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 650 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 651 +       }
 652 +
 653 +       timer_dev.occupation &= ~mask;
 654 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 655 +               lq_disable_gptu();
 656 +               timer_dev.f_gptu_on = 0;
 657 +       }
 658 +
 659 +       mutex_unlock(&timer_dev.gptu_mutex);
 660 +
 661 +       return 0;
 662 +}
 663 +EXPORT_SYMBOL(lq_free_timer);
 664 +
 665 +int lq_start_timer(unsigned int timer, int is_resume)
 666 +{
 667 +       unsigned int flag;
 668 +       unsigned int mask;
 669 +       int n, X;
 670 +
 671 +       if (!timer_dev.f_gptu_on)
 672 +               return -EINVAL;
 673 +
 674 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 675 +               return -EINVAL;
 676 +
 677 +       mutex_lock(&timer_dev.gptu_mutex);
 678 +
 679 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 680 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 681 +               timer &= ~0x01;
 682 +
 683 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 684 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 685 +       if (((timer_dev.occupation & mask) ^ mask)) {
 686 +               mutex_unlock(&timer_dev.gptu_mutex);
 687 +               return -EINVAL;
 688 +       }
 689 +
 690 +       n = timer >> 1;
 691 +       X = timer & 0x01;
 692 +
 693 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 694 +
 695 +
 696 +       mutex_unlock(&timer_dev.gptu_mutex);
 697 +
 698 +       return 0;
 699 +}
 700 +EXPORT_SYMBOL(lq_start_timer);
 701 +
 702 +int lq_stop_timer(unsigned int timer)
 703 +{
 704 +       unsigned int flag;
 705 +       unsigned int mask;
 706 +       int n, X;
 707 +
 708 +       if (!timer_dev.f_gptu_on)
 709 +               return -EINVAL;
 710 +
 711 +       if (timer < FIRST_TIMER
 712 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 713 +               return -EINVAL;
 714 +
 715 +       mutex_lock(&timer_dev.gptu_mutex);
 716 +
 717 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 718 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 719 +               timer &= ~0x01;
 720 +
 721 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 722 +       if (((timer_dev.occupation & mask) ^ mask)) {
 723 +               mutex_unlock(&timer_dev.gptu_mutex);
 724 +               return -EINVAL;
 725 +       }
 726 +
 727 +       n = timer >> 1;
 728 +       X = timer & 0x01;
 729 +
 730 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 731 +
 732 +       mutex_unlock(&timer_dev.gptu_mutex);
 733 +
 734 +       return 0;
 735 +}
 736 +EXPORT_SYMBOL(lq_stop_timer);
 737 +
 738 +int lq_reset_counter_flags(u32 timer, u32 flags)
 739 +{
 740 +       unsigned int oflag;
 741 +       unsigned int mask, con_reg;
 742 +       int n, X;
 743 +
 744 +       if (!timer_dev.f_gptu_on)
 745 +               return -EINVAL;
 746 +
 747 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 748 +               return -EINVAL;
 749 +
 750 +       mutex_lock(&timer_dev.gptu_mutex);
 751 +
 752 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 753 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 754 +               timer &= ~0x01;
 755 +
 756 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 757 +       if (((timer_dev.occupation & mask) ^ mask)) {
 758 +               mutex_unlock(&timer_dev.gptu_mutex);
 759 +               return -EINVAL;
 760 +       }
 761 +
 762 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 763 +       default:
 764 +       case TIMER_FLAG_NONE_EDGE:
 765 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 766 +               break;
 767 +       case TIMER_FLAG_RISE_EDGE:
 768 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 769 +               break;
 770 +       case TIMER_FLAG_FALL_EDGE:
 771 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 772 +               break;
 773 +       case TIMER_FLAG_ANY_EDGE:
 774 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 775 +               break;
 776 +       }
 777 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 778 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 779 +       else
 780 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 781 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 782 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 783 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 784 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 785 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 786 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 787 +
 788 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 789 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 790 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 791 +
 792 +       n = timer >> 1;
 793 +       X = timer & 0x01;
 794 +
 795 +       *LQ_GPTU_CON(n, X) = con_reg;
 796 +       smp_wmb();
 797 +       mutex_unlock(&timer_dev.gptu_mutex);
 798 +       return 0;
 799 +}
 800 +EXPORT_SYMBOL(lq_reset_counter_flags);
 801 +
 802 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 803 +{
 804 +       unsigned int flag;
 805 +       unsigned int mask;
 806 +       int n, X;
 807 +
 808 +       if (!timer_dev.f_gptu_on)
 809 +               return -EINVAL;
 810 +
 811 +       if (timer < FIRST_TIMER
 812 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 813 +               return -EINVAL;
 814 +
 815 +       mutex_lock(&timer_dev.gptu_mutex);
 816 +
 817 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 818 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 819 +               timer &= ~0x01;
 820 +
 821 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 822 +       if (((timer_dev.occupation & mask) ^ mask)) {
 823 +               mutex_unlock(&timer_dev.gptu_mutex);
 824 +               return -EINVAL;
 825 +       }
 826 +
 827 +       n = timer >> 1;
 828 +       X = timer & 0x01;
 829 +
 830 +       *value = *LQ_GPTU_COUNT(n, X);
 831 +
 832 +
 833 +       mutex_unlock(&timer_dev.gptu_mutex);
 834 +
 835 +       return 0;
 836 +}
 837 +EXPORT_SYMBOL(lq_get_count_value);
 838 +
 839 +u32 lq_cal_divider(unsigned long freq)
 840 +{
 841 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 842 +       u32 clock_divider = 1;
 843 +       module_freq = fpi * 1000;
 844 +       do_div(module_freq, clock_divider * freq);
 845 +       return module_freq;
 846 +}
 847 +EXPORT_SYMBOL(lq_cal_divider);
 848 +
 849 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 850 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 851 +       unsigned long arg2)
 852 +{
 853 +       unsigned long divider;
 854 +       unsigned int flag;
 855 +
 856 +       divider = lq_cal_divider(freq);
 857 +       if (divider == 0)
 858 +               return -EINVAL;
 859 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 860 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 861 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 862 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 863 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 864 +
 865 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 866 +               timer, freq, divider);
 867 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 868 +}
 869 +EXPORT_SYMBOL(lq_set_timer);
 870 +
 871 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 872 +       unsigned long arg1, unsigned long arg2)
 873 +{
 874 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 875 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 876 +}
 877 +EXPORT_SYMBOL(lq_set_counter);
 878 +
 879 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 880 +       unsigned long arg)
 881 +{
 882 +       int ret;
 883 +       struct gptu_ioctl_param param;
 884 +
 885 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 886 +               return -EFAULT;
 887 +       copy_from_user(&param, (void *) arg, sizeof(param));
 888 +
 889 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 890 +              || GPTU_SET_COUNTER) && param.timer < 2)
 891 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 892 +           && !access_ok(VERIFY_WRITE, arg,
 893 +                          sizeof(struct gptu_ioctl_param)))
 894 +               return -EFAULT;
 895 +
 896 +       switch (cmd) {
 897 +       case GPTU_REQUEST_TIMER:
 898 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 899 +                                    (unsigned long) param.pid,
 900 +                                    (unsigned long) param.sig);
 901 +               if (ret > 0) {
 902 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 903 +                                     timer, &ret, sizeof(&ret));
 904 +                       ret = 0;
 905 +               }
 906 +               break;
 907 +       case GPTU_FREE_TIMER:
 908 +               ret = lq_free_timer(param.timer);
 909 +               break;
 910 +       case GPTU_START_TIMER:
 911 +               ret = lq_start_timer(param.timer, param.flag);
 912 +               break;
 913 +       case GPTU_STOP_TIMER:
 914 +               ret = lq_stop_timer(param.timer);
 915 +               break;
 916 +       case GPTU_GET_COUNT_VALUE:
 917 +               ret = lq_get_count_value(param.timer, &param.value);
 918 +               if (!ret)
 919 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 920 +                                     value, &param.value,
 921 +                                     sizeof(param.value));
 922 +               break;
 923 +       case GPTU_CALCULATE_DIVIDER:
 924 +               param.value = lq_cal_divider(param.value);
 925 +               if (param.value == 0)
 926 +                       ret = -EINVAL;
 927 +               else {
 928 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 929 +                                     value, &param.value,
 930 +                                     sizeof(param.value));
 931 +                       ret = 0;
 932 +               }
 933 +               break;
 934 +       case GPTU_SET_TIMER:
 935 +               ret = lq_set_timer(param.timer, param.value,
 936 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 937 +                                TIMER_FLAG_ONCE ? 1 : 0,
 938 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 939 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 940 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 941 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 942 +                                TIMER_FLAG_NO_HANDLE,
 943 +                                (unsigned long) param.pid,
 944 +                                (unsigned long) param.sig);
 945 +               if (ret > 0) {
 946 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 947 +                                     timer, &ret, sizeof(&ret));
 948 +                       ret = 0;
 949 +               }
 950 +               break;
 951 +       case GPTU_SET_COUNTER:
 952 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 953 +               if (ret > 0) {
 954 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 955 +                                     timer, &ret, sizeof(&ret));
 956 +                       ret = 0;
 957 +               }
 958 +               break;
 959 +       default:
 960 +               ret = -ENOTTY;
 961 +       }
 962 +
 963 +       return ret;
 964 +}
 965 +
 966 +static int gptu_open(struct inode *inode, struct file *file)
 967 +{
 968 +       return 0;
 969 +}
 970 +
 971 +static int gptu_release(struct inode *inode, struct file *file)
 972 +{
 973 +       return 0;
 974 +}
 975 +
 976 +int __init lq_gptu_init(void)
 977 +{
 978 +       int ret;
 979 +       unsigned int i;
 980 +
 981 +       ltq_w32(0, LQ_GPTU_IRNEN);
 982 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 983 +
 984 +       memset(&timer_dev, 0, sizeof(timer_dev));
 985 +       mutex_init(&timer_dev.gptu_mutex);
 986 +
 987 +       lq_enable_gptu();
 988 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 989 +       lq_disable_gptu();
 990 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 991 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 992 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 993 +
 994 +       ret = misc_register(&gptu_miscdev);
 995 +       if (ret) {
 996 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
 997 +               return ret;
 998 +       } else {
 999 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
1000 +       }
1001 +
1002 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1003 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
1004 +               if (ret) {
1005 +                       for (; i >= 0; i--)
1006 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
1007 +                       misc_deregister(&gptu_miscdev);
1008 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
1009 +                       return ret;
1010 +               } else {
1011 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
1012 +                       disable_irq(timer_dev.timer[i].irq);
1013 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
1014 +               }
1015 +       }
1016 +
1017 +       return 0;
1018 +}
1019 +
1020 +void __exit lq_gptu_exit(void)
1021 +{
1022 +       unsigned int i;
1023 +
1024 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1025 +               if (timer_dev.timer[i].f_irq_on)
1026 +                       disable_irq(timer_dev.timer[i].irq);
1027 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1028 +       }
1029 +       lq_disable_gptu();
1030 +       misc_deregister(&gptu_miscdev);
1031 +}
1032 +
1033 +module_init(lq_gptu_init);
1034 +module_exit(lq_gptu_exit);
1035 +
1036 +#endif
1037 --
1038 1.7.10.4
1039