target/linux/lantiq/patches-3.0/0004-MIPS-lantiq-reorganize-xway-code.patch

   1 From d90739a8962b541969b4c5f7ef1df8fec9c7f153 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 10 Aug 2011 14:57:04 +0200
   4 Subject: [PATCH 04/24] MIPS: lantiq: reorganize xway code
   5
   6 Inside the folder arch/mips/lantiq/xway, there were alot of small files with
   7 lots of duplicated code. This patch adds a wrapper function for inserting and
   8 requesting resources and unifies the small files into one bigger file.
   9
  10 This patch makes the xway code consistent with the falcon support added later
  11 in this series.
  12
  13 Signed-off-by: John Crispin <blogic@openwrt.org>
  14 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  15 Cc: linux-mips@linux-mips.org
  16 ---
  17  arch/mips/include/asm/mach-lantiq/lantiq.h         |   14 +---
  18  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   14 ++++
  19  arch/mips/lantiq/clk.c                             |   25 +------
  20  arch/mips/lantiq/devices.c                         |   30 ++------
  21  arch/mips/lantiq/devices.h                         |    4 +
  22  arch/mips/lantiq/prom.c                            |   50 +++++++++++--
  23  arch/mips/lantiq/prom.h                            |    4 +
  24  arch/mips/lantiq/xway/Makefile                     |    6 +-
  25  arch/mips/lantiq/xway/devices.c                    |   42 ++---------
  26  arch/mips/lantiq/xway/dma.c                        |   21 ++----
  27  arch/mips/lantiq/xway/ebu.c                        |   53 --------------
  28  arch/mips/lantiq/xway/pmu.c                        |   70 ------------------
  29  arch/mips/lantiq/xway/prom-ase.c                   |    9 +++
  30  arch/mips/lantiq/xway/prom-xway.c                  |   10 +++
  31  arch/mips/lantiq/xway/reset.c                      |   21 ++----
  32  arch/mips/lantiq/xway/setup-ase.c                  |   19 -----
  33  arch/mips/lantiq/xway/setup-xway.c                 |   20 -----
  34  arch/mips/lantiq/xway/sysctrl.c                    |   77 ++++++++++++++++++++
  35  drivers/watchdog/lantiq_wdt.c                      |    2 +-
  36  19 files changed, 197 insertions(+), 294 deletions(-)
  37  delete mode 100644 arch/mips/lantiq/xway/ebu.c
  38  delete mode 100644 arch/mips/lantiq/xway/pmu.c
  39  delete mode 100644 arch/mips/lantiq/xway/setup-ase.c
  40  delete mode 100644 arch/mips/lantiq/xway/setup-xway.c
  41  create mode 100644 arch/mips/lantiq/xway/sysctrl.c
  42
  43 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
  44 index ce2f029..66d7300 100644
  45 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
  46 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
  47 @@ -9,6 +9,7 @@
  48  #define _LANTIQ_H__
  49
  50  #include <linux/irq.h>
  51 +#include <linux/ioport.h>
  52
  53  /* generic reg access functions */
  54  #define ltq_r32(reg)           __raw_readl(reg)
  55 @@ -18,15 +19,6 @@
  56  #define ltq_r8(reg)            __raw_readb(reg)
  57  #define ltq_w8(val, reg)       __raw_writeb(val, reg)
  58
  59 -/* register access macros for EBU and CGU */
  60 -#define ltq_ebu_w32(x, y)      ltq_w32((x), ltq_ebu_membase + (y))
  61 -#define ltq_ebu_r32(x)         ltq_r32(ltq_ebu_membase + (x))
  62 -#define ltq_cgu_w32(x, y)      ltq_w32((x), ltq_cgu_membase + (y))
  63 -#define ltq_cgu_r32(x)         ltq_r32(ltq_cgu_membase + (x))
  64 -
  65 -extern __iomem void *ltq_ebu_membase;
  66 -extern __iomem void *ltq_cgu_membase;
  67 -
  68  extern unsigned int ltq_get_cpu_ver(void);
  69  extern unsigned int ltq_get_soc_type(void);
  70
  71 @@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_data *data);
  72
  73  /* find out what caused the last cpu reset */
  74  extern int ltq_reset_cause(void);
  75 -#define LTQ_RST_CAUSE_WDTRST   0x20
  76 +
  77 +/* helper for requesting and remapping resources */
  78 +extern void __iomem *ltq_remap_resource(struct resource *res);
  79
  80  #define IOPORT_RESOURCE_START  0x10000000
  81  #define IOPORT_RESOURCE_END    0xffffffff
  82 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  83 index e6d1ca0..da8ff95 100644
  84 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  85 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  86 @@ -65,6 +65,8 @@
  87  #define LTQ_CGU_BASE_ADDR      0x1F103000
  88  #define LTQ_CGU_SIZE           0x1000
  89
  90 +#define CGU_EPHY               0x10
  91 +
  92  /* ICU - interrupt control unit */
  93  #define LTQ_ICU_BASE_ADDR      0x1F880200
  94  #define LTQ_ICU_SIZE           0x100
  95 @@ -101,6 +103,8 @@
  96  #define LTQ_WDT_BASE_ADDR      0x1F8803F0
  97  #define LTQ_WDT_SIZE           0x10
  98
  99 +#define LTQ_RST_CAUSE_WDTRST   0x20
 100 +
 101  /* STP - serial to parallel conversion unit */
 102  #define LTQ_STP_BASE_ADDR      0x1E100BB0
 103  #define LTQ_STP_SIZE           0x40
 104 @@ -125,11 +129,21 @@
 105  #define LTQ_MPS_BASE_ADDR      (KSEG1 + 0x1F107000)
 106  #define LTQ_MPS_CHIPID         ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
 107
 108 +/* register access macros for EBU and CGU */
 109 +#define ltq_ebu_w32(x, y)      ltq_w32((x), ltq_ebu_membase + (y))
 110 +#define ltq_ebu_r32(x)         ltq_r32(ltq_ebu_membase + (x))
 111 +#define ltq_cgu_w32(x, y)      ltq_w32((x), ltq_cgu_membase + (y))
 112 +#define ltq_cgu_r32(x)         ltq_r32(ltq_cgu_membase + (x))
 113 +
 114 +extern __iomem void *ltq_ebu_membase;
 115 +extern __iomem void *ltq_cgu_membase;
 116 +
 117  /* request a non-gpio and set the PIO config */
 118  extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
 119         unsigned int alt1, unsigned int dir, const char *name);
 120  extern void ltq_pmu_enable(unsigned int module);
 121  extern void ltq_pmu_disable(unsigned int module);
 122 +extern void ltq_cgu_enable(unsigned int clk);
 123
 124  static inline int ltq_is_ar9(void)
 125  {
 126 diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
 127 index 7e9c0ff..4254f08 100644
 128 --- a/arch/mips/lantiq/clk.c
 129 +++ b/arch/mips/lantiq/clk.c
 130 @@ -22,6 +22,7 @@
 131  #include <lantiq_soc.h>
 132
 133  #include "clk.h"
 134 +#include "prom.h"
 135
 136  struct clk {
 137         const char *name;
 138 @@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = {
 139         },
 140  };
 141
 142 -static struct resource ltq_cgu_resource = {
 143 -       .name   = "cgu",
 144 -       .start  = LTQ_CGU_BASE_ADDR,
 145 -       .end    = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1,
 146 -       .flags  = IORESOURCE_MEM,
 147 -};
 148 -
 149 -/* remapped clock register range */
 150 -void __iomem *ltq_cgu_membase;
 151 -
 152  void clk_init(void)
 153  {
 154         cpu_clk = cpu_clk_generic;
 155 @@ -133,21 +124,11 @@ void __init plat_time_init(void)
 156  {
 157         struct clk *clk;
 158
 159 -       if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
 160 -               panic("Failed to insert cgu memory\n");
 161 -
 162 -       if (request_mem_region(ltq_cgu_resource.start,
 163 -                       resource_size(&ltq_cgu_resource), "cgu") < 0)
 164 -               panic("Failed to request cgu memory\n");
 165 +       ltq_soc_init();
 166
 167 -       ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
 168 -                               resource_size(&ltq_cgu_resource));
 169 -       if (!ltq_cgu_membase) {
 170 -               pr_err("Failed to remap cgu memory\n");
 171 -               unreachable();
 172 -       }
 173         clk = clk_get(0, "cpu");
 174         mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
 175         write_c0_compare(read_c0_count());
 176 +       pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
 177         clk_put(clk);
 178  }
 179 diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c
 180 index 44a3677..81c7aab 100644
 181 --- a/arch/mips/lantiq/devices.c
 182 +++ b/arch/mips/lantiq/devices.c
 183 @@ -27,12 +27,8 @@
 184  #include "devices.h"
 185
 186  /* nor flash */
 187 -static struct resource ltq_nor_resource = {
 188 -       .name   = "nor",
 189 -       .start  = LTQ_FLASH_START,
 190 -       .end    = LTQ_FLASH_START + LTQ_FLASH_MAX - 1,
 191 -       .flags  = IORESOURCE_MEM,
 192 -};
 193 +static struct resource ltq_nor_resource =
 194 +       MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX);
 195
 196  static struct platform_device ltq_nor = {
 197         .name           = "ltq_nor",
 198 @@ -47,12 +43,8 @@ void __init ltq_register_nor(struct physmap_flash_data *data)
 199  }
 200
 201  /* watchdog */
 202 -static struct resource ltq_wdt_resource = {
 203 -       .name   = "watchdog",
 204 -       .start  = LTQ_WDT_BASE_ADDR,
 205 -       .end    = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1,
 206 -       .flags  = IORESOURCE_MEM,
 207 -};
 208 +static struct resource ltq_wdt_resource =
 209 +       MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE);
 210
 211  void __init ltq_register_wdt(void)
 212  {
 213 @@ -61,24 +53,14 @@ void __init ltq_register_wdt(void)
 214
 215  /* asc ports */
 216  static struct resource ltq_asc0_resources[] = {
 217 -       {
 218 -               .name   = "asc0",
 219 -               .start  = LTQ_ASC0_BASE_ADDR,
 220 -               .end    = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1,
 221 -               .flags  = IORESOURCE_MEM,
 222 -       },
 223 +       MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE),
 224         IRQ_RES(tx, LTQ_ASC_TIR(0)),
 225         IRQ_RES(rx, LTQ_ASC_RIR(0)),
 226         IRQ_RES(err, LTQ_ASC_EIR(0)),
 227  };
 228
 229  static struct resource ltq_asc1_resources[] = {
 230 -       {
 231 -               .name   = "asc1",
 232 -               .start  = LTQ_ASC1_BASE_ADDR,
 233 -               .end    = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
 234 -               .flags  = IORESOURCE_MEM,
 235 -       },
 236 +       MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
 237         IRQ_RES(tx, LTQ_ASC_TIR(1)),
 238         IRQ_RES(rx, LTQ_ASC_RIR(1)),
 239         IRQ_RES(err, LTQ_ASC_EIR(1)),
 240 diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h
 241 index 2947bb1..a03c23f 100644
 242 --- a/arch/mips/lantiq/devices.h
 243 +++ b/arch/mips/lantiq/devices.h
 244 @@ -14,6 +14,10 @@
 245
 246  #define IRQ_RES(resname, irq) \
 247         {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ}
 248 +#define MEM_RES(resname, adr_start, adr_size) \
 249 +       { .name = resname, .flags = IORESOURCE_MEM, \
 250 +         .start = ((adr_start) & ~KSEG1), \
 251 +         .end = ((adr_start + adr_size - 1) & ~KSEG1) }
 252
 253  extern void ltq_register_nor(struct physmap_flash_data *data);
 254  extern void ltq_register_wdt(void);
 255 diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
 256 index 5035c10..fead2cc 100644
 257 --- a/arch/mips/lantiq/prom.c
 258 +++ b/arch/mips/lantiq/prom.c
 259 @@ -16,6 +16,10 @@
 260  #include "prom.h"
 261  #include "clk.h"
 262
 263 +/* access to the ebu needs to be locked between different drivers */
 264 +DEFINE_SPINLOCK(ebu_lock);
 265 +EXPORT_SYMBOL_GPL(ebu_lock);
 266 +
 267  static struct ltq_soc_info soc_info;
 268
 269  unsigned int ltq_get_cpu_ver(void)
 270 @@ -57,16 +61,50 @@ static void __init prom_init_cmdline(void)
 271         }
 272  }
 273
 274 -void __init prom_init(void)
 275 +void __iomem *ltq_remap_resource(struct resource *res)
 276  {
 277 -       struct clk *clk;
 278 +       __iomem void *ret = NULL;
 279 +       struct resource *lookup = lookup_resource(&iomem_resource, res->start);
 280 +
 281 +       if (lookup && strcmp(lookup->name, res->name)) {
 282 +               panic("conflicting memory range %s\n", res->name);
 283 +               return NULL;
 284 +       }
 285 +       if (!lookup) {
 286 +               if (insert_resource(&iomem_resource, res) < 0) {
 287 +                       panic("Failed to insert %s memory\n", res->name);
 288 +                       return NULL;
 289 +               }
 290 +       }
 291 +       if (request_mem_region(res->start,
 292 +                       resource_size(res), res->name) < 0) {
 293 +               panic("Failed to request %s memory\n", res->name);
 294 +               goto err_res;
 295 +       }
 296
 297 +       ret = ioremap_nocache(res->start, resource_size(res));
 298 +       if (!ret)
 299 +               goto err_mem;
 300 +
 301 +       pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n",
 302 +               res->start, res->end, res->name);
 303 +       return ret;
 304 +
 305 +err_mem:
 306 +       panic("Failed to remap %s memory\n", res->name);
 307 +       release_mem_region(res->start, resource_size(res));
 308 +
 309 +err_res:
 310 +       release_resource(res);
 311 +       return NULL;
 312 +}
 313 +
 314 +void __init prom_init(void)
 315 +{
 316         ltq_soc_detect(&soc_info);
 317         clk_init();
 318 -       clk = clk_get(0, "cpu");
 319 -       snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
 320 -               soc_info.name, soc_info.rev);
 321 -       clk_put(clk);
 322 +       snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
 323 +               soc_info.name, soc_info.rev_type);
 324         soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
 325         pr_info("SoC: %s\n", soc_info.sys_type);
 326         prom_init_cmdline();
 327 diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
 328 index b4229d9..51dba1b 100644
 329 --- a/arch/mips/lantiq/prom.h
 330 +++ b/arch/mips/lantiq/prom.h
 331 @@ -9,17 +9,21 @@
 332  #ifndef _LTQ_PROM_H__
 333  #define _LTQ_PROM_H__
 334
 335 +#define LTQ_SYS_REV_LEN                0x10
 336  #define LTQ_SYS_TYPE_LEN       0x100
 337
 338  struct ltq_soc_info {
 339         unsigned char *name;
 340         unsigned int rev;
 341 +       unsigned char rev_type[LTQ_SYS_REV_LEN];
 342 +       unsigned int srev;
 343         unsigned int partnum;
 344         unsigned int type;
 345         unsigned char sys_type[LTQ_SYS_TYPE_LEN];
 346  };
 347
 348  extern void ltq_soc_detect(struct ltq_soc_info *i);
 349 +extern void ltq_soc_init(void);
 350  extern void ltq_soc_setup(void);
 351
 352  #endif
 353 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
 354 index c517f2e..6678402 100644
 355 --- a/arch/mips/lantiq/xway/Makefile
 356 +++ b/arch/mips/lantiq/xway/Makefile
 357 @@ -1,7 +1,7 @@
 358 -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
 359 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
 360
 361 -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
 362 -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
 363 +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
 364 +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
 365
 366  obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
 367  obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
 368 diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
 369 index d0e32ab..9bacaa8 100644
 370 --- a/arch/mips/lantiq/xway/devices.c
 371 +++ b/arch/mips/lantiq/xway/devices.c
 372 @@ -31,22 +31,9 @@
 373
 374  /* gpio */
 375  static struct resource ltq_gpio_resource[] = {
 376 -       {
 377 -               .name   = "gpio0",
 378 -               .start  = LTQ_GPIO0_BASE_ADDR,
 379 -               .end    = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
 380 -               .flags  = IORESOURCE_MEM,
 381 -       }, {
 382 -               .name   = "gpio1",
 383 -               .start  = LTQ_GPIO1_BASE_ADDR,
 384 -               .end    = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
 385 -               .flags  = IORESOURCE_MEM,
 386 -       }, {
 387 -               .name   = "gpio2",
 388 -               .start  = LTQ_GPIO2_BASE_ADDR,
 389 -               .end    = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
 390 -               .flags  = IORESOURCE_MEM,
 391 -       }
 392 +       MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
 393 +       MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
 394 +       MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
 395  };
 396
 397  void __init ltq_register_gpio(void)
 398 @@ -64,12 +51,8 @@ void __init ltq_register_gpio(void)
 399  }
 400
 401  /* serial to parallel conversion */
 402 -static struct resource ltq_stp_resource = {
 403 -       .name   = "stp",
 404 -       .start  = LTQ_STP_BASE_ADDR,
 405 -       .end    = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
 406 -       .flags  = IORESOURCE_MEM,
 407 -};
 408 +static struct resource ltq_stp_resource =
 409 +       MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE);
 410
 411  void __init ltq_register_gpio_stp(void)
 412  {
 413 @@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void)
 414
 415  /* asc ports - amazon se has its own serial mapping */
 416  static struct resource ltq_ase_asc_resources[] = {
 417 -       {
 418 -               .name   = "asc0",
 419 -               .start  = LTQ_ASC1_BASE_ADDR,
 420 -               .end    = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
 421 -               .flags  = IORESOURCE_MEM,
 422 -       },
 423 +       MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
 424         IRQ_RES(tx, LTQ_ASC_ASE_TIR),
 425         IRQ_RES(rx, LTQ_ASC_ASE_RIR),
 426         IRQ_RES(err, LTQ_ASC_ASE_EIR),
 427 @@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void)
 428  }
 429
 430  /* ethernet */
 431 -static struct resource ltq_etop_resources = {
 432 -       .name   = "etop",
 433 -       .start  = LTQ_ETOP_BASE_ADDR,
 434 -       .end    = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
 435 -       .flags  = IORESOURCE_MEM,
 436 -};
 437 +static struct resource ltq_etop_resources =
 438 +       MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE);
 439
 440  static struct platform_device ltq_etop = {
 441         .name           = "ltq_etop",
 442 diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
 443 index 4278a45..af35e62 100644
 444 --- a/arch/mips/lantiq/xway/dma.c
 445 +++ b/arch/mips/lantiq/xway/dma.c
 446 @@ -23,6 +23,8 @@
 447  #include <lantiq_soc.h>
 448  #include <xway_dma.h>
 449
 450 +#include "../devices.h"
 451 +
 452  #define LTQ_DMA_CTRL           0x10
 453  #define LTQ_DMA_CPOLL          0x14
 454  #define LTQ_DMA_CS             0x18
 455 @@ -54,12 +56,8 @@
 456  #define ltq_dma_w32_mask(x, y, z)      ltq_w32_mask(x, y, \
 457                                                 ltq_dma_membase + (z))
 458
 459 -static struct resource ltq_dma_resource = {
 460 -       .name   = "dma",
 461 -       .start  = LTQ_DMA_BASE_ADDR,
 462 -       .end    = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
 463 -       .flags  = IORESOURCE_MEM,
 464 -};
 465 +static struct resource ltq_dma_resource =
 466 +       MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE);
 467
 468  static void __iomem *ltq_dma_membase;
 469
 470 @@ -219,17 +217,8 @@ ltq_dma_init(void)
 471  {
 472         int i;
 473
 474 -       /* insert and request the memory region */
 475 -       if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
 476 -               panic("Failed to insert dma memory\n");
 477 -
 478 -       if (request_mem_region(ltq_dma_resource.start,
 479 -                       resource_size(&ltq_dma_resource), "dma") < 0)
 480 -               panic("Failed to request dma memory\n");
 481 -
 482         /* remap dma register range */
 483 -       ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
 484 -                               resource_size(&ltq_dma_resource));
 485 +       ltq_dma_membase = ltq_remap_resource(&ltq_dma_resource);
 486         if (!ltq_dma_membase)
 487                 panic("Failed to remap dma memory\n");
 488
 489 diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
 490 deleted file mode 100644
 491 index 66eb52f..0000000
 492 --- a/arch/mips/lantiq/xway/ebu.c
 493 +++ /dev/null
 494 @@ -1,53 +0,0 @@
 495 -/*
 496 - *  This program is free software; you can redistribute it and/or modify it
 497 - *  under the terms of the GNU General Public License version 2 as published
 498 - *  by the Free Software Foundation.
 499 - *
 500 - *  EBU - the external bus unit attaches PCI, NOR and NAND
 501 - *
 502 - *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 503 - */
 504 -
 505 -#include <linux/kernel.h>
 506 -#include <linux/module.h>
 507 -#include <linux/version.h>
 508 -#include <linux/ioport.h>
 509 -
 510 -#include <lantiq_soc.h>
 511 -
 512 -/* all access to the ebu must be locked */
 513 -DEFINE_SPINLOCK(ebu_lock);
 514 -EXPORT_SYMBOL_GPL(ebu_lock);
 515 -
 516 -static struct resource ltq_ebu_resource = {
 517 -       .name   = "ebu",
 518 -       .start  = LTQ_EBU_BASE_ADDR,
 519 -       .end    = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
 520 -       .flags  = IORESOURCE_MEM,
 521 -};
 522 -
 523 -/* remapped base addr of the clock unit and external bus unit */
 524 -void __iomem *ltq_ebu_membase;
 525 -
 526 -static int __init lantiq_ebu_init(void)
 527 -{
 528 -       /* insert and request the memory region */
 529 -       if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
 530 -               panic("Failed to insert ebu memory\n");
 531 -
 532 -       if (request_mem_region(ltq_ebu_resource.start,
 533 -                       resource_size(&ltq_ebu_resource), "ebu") < 0)
 534 -               panic("Failed to request ebu memory\n");
 535 -
 536 -       /* remap ebu register range */
 537 -       ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
 538 -                               resource_size(&ltq_ebu_resource));
 539 -       if (!ltq_ebu_membase)
 540 -               panic("Failed to remap ebu memory\n");
 541 -
 542 -       /* make sure to unprotect the memory region where flash is located */
 543 -       ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 544 -       return 0;
 545 -}
 546 -
 547 -postcore_initcall(lantiq_ebu_init);
 548 diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
 549 deleted file mode 100644
 550 index 9d69f01e..0000000
 551 --- a/arch/mips/lantiq/xway/pmu.c
 552 +++ /dev/null
 553 @@ -1,70 +0,0 @@
 554 -/*
 555 - *  This program is free software; you can redistribute it and/or modify it
 556 - *  under the terms of the GNU General Public License version 2 as published
 557 - *  by the Free Software Foundation.
 558 - *
 559 - *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 560 - */
 561 -
 562 -#include <linux/kernel.h>
 563 -#include <linux/module.h>
 564 -#include <linux/version.h>
 565 -#include <linux/ioport.h>
 566 -
 567 -#include <lantiq_soc.h>
 568 -
 569 -/* PMU - the power management unit allows us to turn part of the core
 570 - * on and off
 571 - */
 572 -
 573 -/* the enable / disable registers */
 574 -#define LTQ_PMU_PWDCR  0x1C
 575 -#define LTQ_PMU_PWDSR  0x20
 576 -
 577 -#define ltq_pmu_w32(x, y)      ltq_w32((x), ltq_pmu_membase + (y))
 578 -#define ltq_pmu_r32(x)         ltq_r32(ltq_pmu_membase + (x))
 579 -
 580 -static struct resource ltq_pmu_resource = {
 581 -       .name   = "pmu",
 582 -       .start  = LTQ_PMU_BASE_ADDR,
 583 -       .end    = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
 584 -       .flags  = IORESOURCE_MEM,
 585 -};
 586 -
 587 -static void __iomem *ltq_pmu_membase;
 588 -
 589 -void ltq_pmu_enable(unsigned int module)
 590 -{
 591 -       int err = 1000000;
 592 -
 593 -       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
 594 -       do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
 595 -
 596 -       if (!err)
 597 -               panic("activating PMU module failed!\n");
 598 -}
 599 -EXPORT_SYMBOL(ltq_pmu_enable);
 600 -
 601 -void ltq_pmu_disable(unsigned int module)
 602 -{
 603 -       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
 604 -}
 605 -EXPORT_SYMBOL(ltq_pmu_disable);
 606 -
 607 -int __init ltq_pmu_init(void)
 608 -{
 609 -       if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
 610 -               panic("Failed to insert pmu memory\n");
 611 -
 612 -       if (request_mem_region(ltq_pmu_resource.start,
 613 -                       resource_size(&ltq_pmu_resource), "pmu") < 0)
 614 -               panic("Failed to request pmu memory\n");
 615 -
 616 -       ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
 617 -                               resource_size(&ltq_pmu_resource));
 618 -       if (!ltq_pmu_membase)
 619 -               panic("Failed to remap pmu memory\n");
 620 -       return 0;
 621 -}
 622 -
 623 -core_initcall(ltq_pmu_init);
 624 diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
 625 index abe49f4..aaccdcb 100644
 626 --- a/arch/mips/lantiq/xway/prom-ase.c
 627 +++ b/arch/mips/lantiq/xway/prom-ase.c
 628 @@ -13,6 +13,7 @@
 629
 630  #include <lantiq_soc.h>
 631
 632 +#include "devices.h"
 633  #include "../prom.h"
 634
 635  #define SOC_AMAZON_SE  "Amazon_SE"
 636 @@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
 637  {
 638         i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
 639         i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
 640 +       sprintf(i->rev_type, "1.%d", i->rev);
 641         switch (i->partnum) {
 642         case SOC_ID_AMAZON_SE:
 643                 i->name = SOC_AMAZON_SE;
 644 @@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
 645                 break;
 646         }
 647  }
 648 +
 649 +void __init ltq_soc_setup(void)
 650 +{
 651 +       ltq_register_ase_asc();
 652 +       ltq_register_gpio();
 653 +       ltq_register_wdt();
 654 +}
 655 diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
 656 index 1686692a..f3d1228 100644
 657 --- a/arch/mips/lantiq/xway/prom-xway.c
 658 +++ b/arch/mips/lantiq/xway/prom-xway.c
 659 @@ -13,6 +13,7 @@
 660
 661  #include <lantiq_soc.h>
 662
 663 +#include "devices.h"
 664  #include "../prom.h"
 665
 666  #define SOC_DANUBE     "Danube"
 667 @@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
 668  {
 669         i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
 670         i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
 671 +       sprintf(i->rev_type, "1.%d", i->rev);
 672         switch (i->partnum) {
 673         case SOC_ID_DANUBE1:
 674         case SOC_ID_DANUBE2:
 675 @@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
 676                 break;
 677         }
 678  }
 679 +
 680 +void __init ltq_soc_setup(void)
 681 +{
 682 +       ltq_register_asc(0);
 683 +       ltq_register_asc(1);
 684 +       ltq_register_gpio();
 685 +       ltq_register_wdt();
 686 +}
 687 diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
 688 index a1be36d..e701a48 100644
 689 --- a/arch/mips/lantiq/xway/reset.c
 690 +++ b/arch/mips/lantiq/xway/reset.c
 691 @@ -15,6 +15,8 @@
 692
 693  #include <lantiq_soc.h>
 694
 695 +#include "../devices.h"
 696 +
 697  #define ltq_rcu_w32(x, y)      ltq_w32((x), ltq_rcu_membase + (y))
 698  #define ltq_rcu_r32(x)         ltq_r32(ltq_rcu_membase + (x))
 699
 700 @@ -25,12 +27,8 @@
 701  #define LTQ_RCU_RST_STAT       0x0014
 702  #define LTQ_RCU_STAT_SHIFT     26
 703
 704 -static struct resource ltq_rcu_resource = {
 705 -       .name   = "rcu",
 706 -       .start  = LTQ_RCU_BASE_ADDR,
 707 -       .end    = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1,
 708 -       .flags  = IORESOURCE_MEM,
 709 -};
 710 +static struct resource ltq_rcu_resource =
 711 +       MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
 712
 713  /* remapped base addr of the reset control unit */
 714  static void __iomem *ltq_rcu_membase;
 715 @@ -67,17 +65,8 @@ static void ltq_machine_power_off(void)
 716
 717  static int __init mips_reboot_setup(void)
 718  {
 719 -       /* insert and request the memory region */
 720 -       if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0)
 721 -               panic("Failed to insert rcu memory\n");
 722 -
 723 -       if (request_mem_region(ltq_rcu_resource.start,
 724 -                       resource_size(&ltq_rcu_resource), "rcu") < 0)
 725 -               panic("Failed to request rcu memory\n");
 726 -
 727         /* remap rcu register range */
 728 -       ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
 729 -                               resource_size(&ltq_rcu_resource));
 730 +       ltq_rcu_membase = ltq_remap_resource(&ltq_rcu_resource);
 731         if (!ltq_rcu_membase)
 732                 panic("Failed to remap rcu memory\n");
 733
 734 diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c
 735 deleted file mode 100644
 736 index f6f3267..0000000
 737 --- a/arch/mips/lantiq/xway/setup-ase.c
 738 +++ /dev/null
 739 @@ -1,19 +0,0 @@
 740 -/*
 741 - *  This program is free software; you can redistribute it and/or modify it
 742 - *  under the terms of the GNU General Public License version 2 as published
 743 - *  by the Free Software Foundation.
 744 - *
 745 - *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 746 - */
 747 -
 748 -#include <lantiq_soc.h>
 749 -
 750 -#include "../prom.h"
 751 -#include "devices.h"
 752 -
 753 -void __init ltq_soc_setup(void)
 754 -{
 755 -       ltq_register_ase_asc();
 756 -       ltq_register_gpio();
 757 -       ltq_register_wdt();
 758 -}
 759 diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c
 760 deleted file mode 100644
 761 index c292f64..0000000
 762 --- a/arch/mips/lantiq/xway/setup-xway.c
 763 +++ /dev/null
 764 @@ -1,20 +0,0 @@
 765 -/*
 766 - *  This program is free software; you can redistribute it and/or modify it
 767 - *  under the terms of the GNU General Public License version 2 as published
 768 - *  by the Free Software Foundation.
 769 - *
 770 - *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 771 - */
 772 -
 773 -#include <lantiq_soc.h>
 774 -
 775 -#include "../prom.h"
 776 -#include "devices.h"
 777 -
 778 -void __init ltq_soc_setup(void)
 779 -{
 780 -       ltq_register_asc(0);
 781 -       ltq_register_asc(1);
 782 -       ltq_register_gpio();
 783 -       ltq_register_wdt();
 784 -}
 785 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
 786 new file mode 100644
 787 index 0000000..a29944f
 788 --- /dev/null
 789 +++ b/arch/mips/lantiq/xway/sysctrl.c
 790 @@ -0,0 +1,77 @@
 791 +/*
 792 + *  This program is free software; you can redistribute it and/or modify it
 793 + *  under the terms of the GNU General Public License version 2 as published
 794 + *  by the Free Software Foundation.
 795 + *
 796 + *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 797 + */
 798 +
 799 +#include <linux/ioport.h>
 800 +
 801 +#include <lantiq_soc.h>
 802 +
 803 +#include "../devices.h"
 804 +
 805 +/* clock control register */
 806 +#define LTQ_CGU_IFCCR  0x0018
 807 +
 808 +/* the enable / disable registers */
 809 +#define LTQ_PMU_PWDCR  0x1C
 810 +#define LTQ_PMU_PWDSR  0x20
 811 +
 812 +#define ltq_pmu_w32(x, y)      ltq_w32((x), ltq_pmu_membase + (y))
 813 +#define ltq_pmu_r32(x)         ltq_r32(ltq_pmu_membase + (x))
 814 +
 815 +static struct resource ltq_cgu_resource =
 816 +       MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE);
 817 +
 818 +static struct resource ltq_pmu_resource =
 819 +       MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE);
 820 +
 821 +static struct resource ltq_ebu_resource =
 822 +       MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
 823 +
 824 +void __iomem *ltq_cgu_membase;
 825 +void __iomem *ltq_ebu_membase;
 826 +static void __iomem *ltq_pmu_membase;
 827 +
 828 +void ltq_cgu_enable(unsigned int clk)
 829 +{
 830 +       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
 831 +}
 832 +
 833 +void ltq_pmu_enable(unsigned int module)
 834 +{
 835 +       int err = 1000000;
 836 +
 837 +       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
 838 +       do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
 839 +
 840 +       if (!err)
 841 +               panic("activating PMU module failed!\n");
 842 +}
 843 +EXPORT_SYMBOL(ltq_pmu_enable);
 844 +
 845 +void ltq_pmu_disable(unsigned int module)
 846 +{
 847 +       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
 848 +}
 849 +EXPORT_SYMBOL(ltq_pmu_disable);
 850 +
 851 +void __init ltq_soc_init(void)
 852 +{
 853 +       ltq_pmu_membase = ltq_remap_resource(&ltq_pmu_resource);
 854 +       if (!ltq_pmu_membase)
 855 +               panic("Failed to remap pmu memory\n");
 856 +
 857 +       ltq_cgu_membase = ltq_remap_resource(&ltq_cgu_resource);
 858 +       if (!ltq_cgu_membase)
 859 +               panic("Failed to remap cgu memory\n");
 860 +
 861 +       ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_resource);
 862 +       if (!ltq_ebu_membase)
 863 +               panic("Failed to remap ebu memory\n");
 864 +
 865 +       /* make sure to unprotect the memory region where flash is located */
 866 +       ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 867 +}
 868 diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
 869 index 102aed0..179bf98 100644
 870 --- a/drivers/watchdog/lantiq_wdt.c
 871 +++ b/drivers/watchdog/lantiq_wdt.c
 872 @@ -16,7 +16,7 @@
 873  #include <linux/clk.h>
 874  #include <linux/io.h>
 875
 876 -#include <lantiq.h>
 877 +#include <lantiq_soc.h>
 878
 879  /* Section 3.4 of the datasheet
 880   * The password sequence protects the WDT control register from unintended
 881 --
 882 1.7.5.4
 883