target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.c $
   3  * $Revision: 1.1.1.1 $
   4  * $Date: 2009-04-17 06:15:34 $
   5  * $Change: 631780 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  *
  36  * The Core Interface Layer provides basic services for accessing and
  37  * managing the DWC_otg hardware. These services are used by both the
  38  * Host Controller Driver and the Peripheral Controller Driver.
  39  *
  40  * The CIL manages the memory map for the core so that the HCD and PCD
  41  * don't have to do this separately. It also handles basic tasks like
  42  * reading/writing the registers and data FIFOs in the controller.
  43  * Some of the data access functions provide encapsulation of several
  44  * operations required to perform a task, such as writing multiple
  45  * registers to start a transfer. Finally, the CIL performs basic
  46  * services that are not specific to either the host or device modes
  47  * of operation. These services include management of the OTG Host
  48  * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
  49  * Diagnostic API is also provided to allow testing of the controller
  50  * hardware.
  51  *
  52  * The Core Interface Layer has the following requirements:
  53  * - Provides basic controller operations.
  54  * - Minimal use of OS services.
  55  * - The OS services used will be abstracted by using inline functions
  56  *   or macros.
  57  *
  58  */
  59 #include <asm/unaligned.h>
  60
  61 #ifdef DEBUG
  62 #include <linux/jiffies.h>
  63 #endif
  64
  65 #include "dwc_otg_plat.h"
  66
  67 #include "dwc_otg_regs.h"
  68 #include "dwc_otg_cil.h"
  69
  70 /**
  71  * This function is called to initialize the DWC_otg CSR data
  72  * structures.  The register addresses in the device and host
  73  * structures are initialized from the base address supplied by the
  74  * caller.  The calling function must make the OS calls to get the
  75  * base address of the DWC_otg controller registers.  The core_params
  76  * argument holds the parameters that specify how the core should be
  77  * configured.
  78  *
  79  * @param[in] _reg_base_addr Base address of DWC_otg core registers
  80  * @param[in] _core_params Pointer to the core configuration parameters
  81  *
  82  */
  83 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
  84                                     dwc_otg_core_params_t *_core_params)
  85 {
  86     dwc_otg_core_if_t *core_if = 0;
  87     dwc_otg_dev_if_t *dev_if = 0;
  88     dwc_otg_host_if_t *host_if = 0;
  89     uint8_t *reg_base = (uint8_t *)_reg_base_addr;
  90     int i = 0;
  91
  92     DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, _reg_base_addr, _core_params);
  93
  94     core_if = kmalloc( sizeof(dwc_otg_core_if_t), GFP_KERNEL);
  95     if (core_if == 0) {
  96         DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n");
  97         return 0;
  98     }
  99     memset(core_if, 0, sizeof(dwc_otg_core_if_t));
 100
 101     core_if->core_params = _core_params;
 102     core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
 103     /*
 104      * Allocate the Device Mode structures.
 105      */
 106     dev_if = kmalloc( sizeof(dwc_otg_dev_if_t), GFP_KERNEL);
 107     if (dev_if == 0) {
 108         DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
 109         kfree( core_if );
 110         return 0;
 111     }
 112
 113     dev_if->dev_global_regs =
 114         (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET);
 115
 116     for (i=0; i<MAX_EPS_CHANNELS; i++) {
 117         dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
 118             (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
 119             (i * DWC_EP_REG_OFFSET));
 120
 121         dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
 122             (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
 123             (i * DWC_EP_REG_OFFSET));
 124         DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
 125                             i, &dev_if->in_ep_regs[i]->diepctl);
 126         DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
 127                             i, &dev_if->out_ep_regs[i]->doepctl);
 128     }
 129     dev_if->speed = 0; // unknown
 130     //dev_if->num_eps = MAX_EPS_CHANNELS;
 131     //dev_if->num_perio_eps = 0;
 132
 133     core_if->dev_if = dev_if;
 134     /*
 135     * Allocate the Host Mode structures.
 136     */
 137     host_if = kmalloc( sizeof(dwc_otg_host_if_t), GFP_KERNEL);
 138     if (host_if == 0) {
 139         DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
 140         kfree( dev_if );
 141         kfree( core_if );
 142         return 0;
 143     }
 144
 145     host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
 146         (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
 147     host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
 148     for (i=0; i<MAX_EPS_CHANNELS; i++) {
 149         host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
 150             (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
 151             (i * DWC_OTG_CHAN_REGS_OFFSET));
 152         DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
 153                             i, &host_if->hc_regs[i]->hcchar);
 154     }
 155     host_if->num_host_channels = MAX_EPS_CHANNELS;
 156     core_if->host_if = host_if;
 157
 158     for (i=0; i<MAX_EPS_CHANNELS; i++) {
 159         core_if->data_fifo[i] =
 160             (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET +
 161             (i * DWC_OTG_DATA_FIFO_SIZE));
 162         DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
 163             i, (unsigned)core_if->data_fifo[i]);
 164     } // for loop.
 165
 166     core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET);
 167
 168     /*
 169      * Store the contents of the hardware configuration registers here for
 170      * easy access later.
 171      */
 172     core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
 173     core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
 174     core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
 175     core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
 176
 177     DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32);
 178     DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32);
 179     DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32);
 180     DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
 181
 182
 183     DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
 184     DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
 185     DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep);
 186     DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan);
 187     DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth);
 188     DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth);
 189     DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth);
 190
 191     DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth);
 192     DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width);
 193
 194     /*
 195      * Set the SRP sucess bit for FS-I2c
 196      */
 197     core_if->srp_success = 0;
 198     core_if->srp_timer_started = 0;
 199
 200     return core_if;
 201 }
 202 /**
 203  * This function frees the structures allocated by dwc_otg_cil_init().
 204  *
 205  * @param[in] _core_if The core interface pointer returned from
 206  * dwc_otg_cil_init().
 207  *
 208  */
 209 void dwc_otg_cil_remove( dwc_otg_core_if_t *_core_if )
 210 {
 211         /* Disable all interrupts */
 212         dwc_modify_reg32( &_core_if->core_global_regs->gahbcfg, 1, 0);
 213         dwc_write_reg32( &_core_if->core_global_regs->gintmsk, 0);
 214
 215         if ( _core_if->dev_if ) {
 216                 kfree( _core_if->dev_if );
 217         }
 218         if ( _core_if->host_if ) {
 219                 kfree( _core_if->host_if );
 220         }
 221         kfree( _core_if );
 222 }
 223
 224 /**
 225  * This function enables the controller's Global Interrupt in the AHB Config
 226  * register.
 227  *
 228  * @param[in] _core_if Programming view of DWC_otg controller.
 229  */
 230 extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if )
 231 {
 232         gahbcfg_data_t ahbcfg = { .d32 = 0};
 233         ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
 234         dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
 235 }
 236 /**
 237  * This function disables the controller's Global Interrupt in the AHB Config
 238  * register.
 239  *
 240  * @param[in] _core_if Programming view of DWC_otg controller.
 241  */
 242 extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if )
 243 {
 244         gahbcfg_data_t ahbcfg = { .d32 = 0};
 245         ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
 246         dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
 247 }
 248
 249 /**
 250  * This function initializes the commmon interrupts, used in both
 251  * device and host modes.
 252  *
 253  * @param[in] _core_if Programming view of the DWC_otg controller
 254  *
 255  */
 256 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *_core_if)
 257 {
 258         dwc_otg_core_global_regs_t *global_regs =
 259                 _core_if->core_global_regs;
 260         gintmsk_data_t intr_mask = { .d32 = 0};
 261         /* Clear any pending OTG Interrupts */
 262         dwc_write_reg32( &global_regs->gotgint, 0xFFFFFFFF);
 263         /* Clear any pending interrupts */
 264         dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF);
 265         /*
 266          * Enable the interrupts in the GINTMSK.
 267          */
 268         intr_mask.b.modemismatch = 1;
 269         intr_mask.b.otgintr = 1;
 270         if (!_core_if->dma_enable) {
 271                 intr_mask.b.rxstsqlvl = 1;
 272         }
 273         intr_mask.b.conidstschng = 1;
 274         intr_mask.b.wkupintr = 1;
 275         intr_mask.b.disconnect = 1;
 276         intr_mask.b.usbsuspend = 1;
 277         intr_mask.b.sessreqintr = 1;
 278         dwc_write_reg32( &global_regs->gintmsk, intr_mask.d32);
 279 }
 280
 281 /**
 282  * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
 283  * type.
 284  */
 285 static void init_fslspclksel(dwc_otg_core_if_t *_core_if)
 286 {
 287         uint32_t        val;
 288         hcfg_data_t     hcfg;
 289
 290         if (((_core_if->hwcfg2.b.hs_phy_type == 2) &&
 291              (_core_if->hwcfg2.b.fs_phy_type == 1) &&
 292              (_core_if->core_params->ulpi_fs_ls)) ||
 293             (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS))
 294         {
 295                 /* Full speed PHY */
 296                 val = DWC_HCFG_48_MHZ;
 297         } else {
 298                 /* High speed PHY running at full speed or high speed */
 299                 val = DWC_HCFG_30_60_MHZ;
 300         }
 301
 302         DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
 303         hcfg.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hcfg);
 304         hcfg.b.fslspclksel = val;
 305         dwc_write_reg32(&_core_if->host_if->host_global_regs->hcfg, hcfg.d32);
 306 }
 307
 308 /**
 309  * Initializes the DevSpd field of the DCFG register depending on the PHY type
 310  * and the enumeration speed of the device.
 311  */
 312 static void init_devspd(dwc_otg_core_if_t *_core_if)
 313 {
 314         uint32_t        val;
 315         dcfg_data_t     dcfg;
 316
 317         if (((_core_if->hwcfg2.b.hs_phy_type == 2) &&
 318              (_core_if->hwcfg2.b.fs_phy_type == 1) &&
 319              (_core_if->core_params->ulpi_fs_ls)) ||
 320              (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS))
 321         {
 322                 /* Full speed PHY */
 323                 val = 0x3;
 324         } else if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
 325                 /* High speed PHY running at full speed */
 326                 val = 0x1;
 327         } else {
 328                 /* High speed PHY running at high speed */
 329                 val = 0x0;
 330         }
 331
 332         DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
 333         dcfg.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dcfg);
 334         dcfg.b.devspd = val;
 335         dwc_write_reg32(&_core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
 336 }
 337
 338 /**
 339  * This function calculates the number of IN EPS
 340  * using GHWCFG1 and GHWCFG2 registers values
 341  *
 342  * @param _pcd the pcd structure.
 343  */
 344 static uint32_t calc_num_in_eps(dwc_otg_core_if_t * _core_if)
 345 {
 346         uint32_t num_in_eps = 0;
 347         uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep;
 348         uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2;
 349         uint32_t num_tx_fifos = _core_if->hwcfg4.b.num_in_eps;
 350         int i;
 351         for (i = 0; i < num_eps; ++i) {
 352                 if (!(hwcfg1 & 0x1))
 353                         num_in_eps++;
 354                 hwcfg1 >>= 2;
 355         }
 356         if (_core_if->hwcfg4.b.ded_fifo_en) {
 357                 num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
 358         }
 359         return num_in_eps;
 360 }
 361
 362
 363 /**
 364  * This function calculates the number of OUT EPS
 365  * using GHWCFG1 and GHWCFG2 registers values
 366  *
 367  * @param _pcd the pcd structure.
 368  */
 369 static uint32_t calc_num_out_eps(dwc_otg_core_if_t * _core_if)
 370 {
 371         uint32_t num_out_eps = 0;
 372         uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep;
 373         uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2;
 374         int i;
 375         for (i = 0; i < num_eps; ++i) {
 376                 if (!(hwcfg1 & 0x2))
 377                         num_out_eps++;
 378                 hwcfg1 >>= 2;
 379         }
 380         return num_out_eps;
 381 }
 382 /**
 383  * This function initializes the DWC_otg controller registers and
 384  * prepares the core for device mode or host mode operation.
 385  *
 386  * @param _core_if Programming view of the DWC_otg controller
 387  *
 388  */
 389 void dwc_otg_core_init(dwc_otg_core_if_t *_core_if)
 390 {
 391         dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs;
 392     dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
 393     int i = 0;
 394     gahbcfg_data_t ahbcfg = { .d32 = 0};
 395     gusbcfg_data_t usbcfg = { .d32 = 0 };
 396     gi2cctl_data_t i2cctl = {.d32 = 0};
 397
 398     DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n",_core_if);
 399
 400     /* Common Initialization */
 401
 402     usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
 403         DWC_DEBUGPL(DBG_CIL, "USB config register: 0x%08x\n", usbcfg.d32);
 404
 405     /* Program the ULPI External VBUS bit if needed */
 406     //usbcfg.b.ulpi_ext_vbus_drv = 1;
 407     //usbcfg.b.ulpi_ext_vbus_drv = 0;
 408     usbcfg.b.ulpi_ext_vbus_drv =
 409         (_core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
 410
 411     /* Set external TS Dline pulsing */
 412     usbcfg.b.term_sel_dl_pulse = (_core_if->core_params->ts_dline == 1) ? 1 : 0;
 413     dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
 414
 415     /* Reset the Controller */
 416     dwc_otg_core_reset( _core_if );
 417
 418     /* Initialize parameters from Hardware configuration registers. */
 419 #if 0
 420     dev_if->num_eps = _core_if->hwcfg2.b.num_dev_ep;
 421     dev_if->num_perio_eps = _core_if->hwcfg4.b.num_dev_perio_in_ep;
 422 #else
 423         dev_if->num_in_eps = calc_num_in_eps(_core_if);
 424         dev_if->num_out_eps = calc_num_out_eps(_core_if);
 425 #endif
 426         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
 427                        _core_if->hwcfg4.b.num_dev_perio_in_ep);
 428         DWC_DEBUGPL(DBG_CIL, "Is power optimization enabled?  %s\n",
 429                      _core_if->hwcfg4.b.power_optimiz ? "Yes" : "No");
 430         DWC_DEBUGPL(DBG_CIL, "vbus_valid filter enabled?  %s\n",
 431                      _core_if->hwcfg4.b.vbus_valid_filt_en ? "Yes" : "No");
 432         DWC_DEBUGPL(DBG_CIL, "iddig filter enabled?  %s\n",
 433                      _core_if->hwcfg4.b.iddig_filt_en ? "Yes" : "No");
 434
 435     DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",_core_if->hwcfg4.b.num_dev_perio_in_ep);
 436     for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
 437         dev_if->perio_tx_fifo_size[i] =
 438                     dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
 439                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", i,
 440                              dev_if->perio_tx_fifo_size[i]);
 441         }
 442         for (i = 0; i < _core_if->hwcfg4.b.num_in_eps; i++) {
 443                 dev_if->tx_fifo_size[i] =
 444                     dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
 445                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", i,
 446                              dev_if->perio_tx_fifo_size[i]);
 447         }
 448
 449     _core_if->total_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
 450         _core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz);
 451         _core_if->nperio_tx_fifo_size = dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
 452
 453     DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", _core_if->total_fifo_size);
 454     DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", _core_if->rx_fifo_size);
 455     DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", _core_if->nperio_tx_fifo_size);
 456
 457     /* This programming sequence needs to happen in FS mode before any other
 458     * programming occurs */
 459     if ((_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
 460         (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
 461         /* If FS mode with FS PHY */
 462
 463         /* core_init() is now called on every switch so only call the
 464          * following for the first time through. */
 465         if (!_core_if->phy_init_done) {
 466             _core_if->phy_init_done = 1;
 467             DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
 468             usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
 469             usbcfg.b.physel = 1;
 470             dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
 471
 472             /* Reset after a PHY select */
 473             dwc_otg_core_reset( _core_if );
 474         }
 475
 476         /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.  Also
 477          * do this on HNP Dev/Host mode switches (done in dev_init and
 478          * host_init). */
 479         if (dwc_otg_is_host_mode(_core_if)) {
 480                         DWC_DEBUGPL(DBG_CIL, "host mode\n");
 481             init_fslspclksel(_core_if);
 482                 } else {
 483                         DWC_DEBUGPL(DBG_CIL, "device mode\n");
 484             init_devspd(_core_if);
 485         }
 486
 487         if (_core_if->core_params->i2c_enable) {
 488             DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
 489             /* Program GUSBCFG.OtgUtmifsSel to I2C */
 490             usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
 491             usbcfg.b.otgutmifssel = 1;
 492             dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
 493
 494             /* Program GI2CCTL.I2CEn */
 495             i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
 496             i2cctl.b.i2cdevaddr = 1;
 497             i2cctl.b.i2cen = 0;
 498             dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
 499             i2cctl.b.i2cen = 1;
 500             dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
 501         }
 502
 503     } /* endif speed == DWC_SPEED_PARAM_FULL */
 504         else {
 505         /* High speed PHY. */
 506         if (!_core_if->phy_init_done) {
 507             _core_if->phy_init_done = 1;
 508                         DWC_DEBUGPL(DBG_CIL, "High spped PHY\n");
 509             /* HS PHY parameters.  These parameters are preserved
 510              * during soft reset so only program the first time.  Do
 511              * a soft reset immediately after setting phyif.  */
 512             usbcfg.b.ulpi_utmi_sel = _core_if->core_params->phy_type;
 513             if (usbcfg.b.ulpi_utmi_sel == 2) { // winder
 514                                 DWC_DEBUGPL(DBG_CIL, "ULPI\n");
 515                 /* ULPI interface */
 516                 usbcfg.b.phyif = 0;
 517                 usbcfg.b.ddrsel = _core_if->core_params->phy_ulpi_ddr;
 518             } else {
 519                 /* UTMI+ interface */
 520                 if (_core_if->core_params->phy_utmi_width == 16) {
 521                     usbcfg.b.phyif = 1;
 522                                         DWC_DEBUGPL(DBG_CIL, "UTMI+ 16\n");
 523                                 } else {
 524                                         DWC_DEBUGPL(DBG_CIL, "UTMI+ 8\n");
 525                     usbcfg.b.phyif = 0;
 526                 }
 527             }
 528             dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32);
 529
 530             /* Reset after setting the PHY parameters */
 531             dwc_otg_core_reset( _core_if );
 532         }
 533     }
 534
 535     if ((_core_if->hwcfg2.b.hs_phy_type == 2) &&
 536         (_core_if->hwcfg2.b.fs_phy_type == 1) &&
 537         (_core_if->core_params->ulpi_fs_ls))
 538     {
 539         DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
 540         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
 541         usbcfg.b.ulpi_fsls = 1;
 542         usbcfg.b.ulpi_clk_sus_m = 1;
 543         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
 544         } else {
 545                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS=0\n");
 546         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
 547         usbcfg.b.ulpi_fsls = 0;
 548         usbcfg.b.ulpi_clk_sus_m = 0;
 549         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
 550     }
 551
 552     /* Program the GAHBCFG Register.*/
 553     switch (_core_if->hwcfg2.b.architecture){
 554
 555         case DWC_SLAVE_ONLY_ARCH:
 556             DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
 557             ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
 558             ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
 559             _core_if->dma_enable = 0;
 560             break;
 561
 562         case DWC_EXT_DMA_ARCH:
 563             DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
 564             ahbcfg.b.hburstlen = _core_if->core_params->dma_burst_size;
 565             _core_if->dma_enable = (_core_if->core_params->dma_enable != 0);
 566             break;
 567
 568         case DWC_INT_DMA_ARCH:
 569             DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
 570             //ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
 571             ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR4;
 572             _core_if->dma_enable = (_core_if->core_params->dma_enable != 0);
 573             break;
 574     }
 575     ahbcfg.b.dmaenable = _core_if->dma_enable;
 576     dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
 577         _core_if->en_multiple_tx_fifo = _core_if->hwcfg4.b.ded_fifo_en;
 578
 579     /*
 580      * Program the GUSBCFG register.
 581      */
 582     usbcfg.d32 = dwc_read_reg32( &global_regs->gusbcfg );
 583
 584     switch (_core_if->hwcfg2.b.op_mode) {
 585         case DWC_MODE_HNP_SRP_CAPABLE:
 586             usbcfg.b.hnpcap = (_core_if->core_params->otg_cap ==
 587             DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
 588             usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
 589             DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
 590             break;
 591
 592         case DWC_MODE_SRP_ONLY_CAPABLE:
 593             usbcfg.b.hnpcap = 0;
 594             usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
 595             DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
 596             break;
 597
 598         case DWC_MODE_NO_HNP_SRP_CAPABLE:
 599             usbcfg.b.hnpcap = 0;
 600             usbcfg.b.srpcap = 0;
 601             break;
 602
 603         case DWC_MODE_SRP_CAPABLE_DEVICE:
 604             usbcfg.b.hnpcap = 0;
 605             usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
 606             DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
 607             break;
 608
 609         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
 610             usbcfg.b.hnpcap = 0;
 611             usbcfg.b.srpcap = 0;
 612             break;
 613
 614         case DWC_MODE_SRP_CAPABLE_HOST:
 615             usbcfg.b.hnpcap = 0;
 616             usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
 617             DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
 618             break;
 619
 620         case DWC_MODE_NO_SRP_CAPABLE_HOST:
 621             usbcfg.b.hnpcap = 0;
 622             usbcfg.b.srpcap = 0;
 623             break;
 624     }
 625
 626     dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32);
 627
 628     /* Enable common interrupts */
 629     dwc_otg_enable_common_interrupts( _core_if );
 630
 631     /* Do device or host intialization based on mode during PCD
 632      * and HCD initialization  */
 633     if (dwc_otg_is_host_mode( _core_if )) {
 634         DWC_DEBUGPL(DBG_ANY, "Host Mode\n" );
 635         _core_if->op_state = A_HOST;
 636     } else {
 637         DWC_DEBUGPL(DBG_ANY, "Device Mode\n" );
 638         _core_if->op_state = B_PERIPHERAL;
 639 #ifdef DWC_DEVICE_ONLY
 640         dwc_otg_core_dev_init( _core_if );
 641 #endif
 642     }
 643 }
 644
 645
 646 /**
 647  * This function enables the Device mode interrupts.
 648  *
 649  * @param _core_if Programming view of DWC_otg controller
 650  */
 651 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if)
 652 {
 653         gintmsk_data_t intr_mask = { .d32 = 0};
 654         dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs;
 655
 656         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
 657
 658         /* Disable all interrupts. */
 659         dwc_write_reg32( &global_regs->gintmsk, 0);
 660
 661         /* Clear any pending interrupts */
 662         dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF);
 663
 664         /* Enable the common interrupts */
 665         dwc_otg_enable_common_interrupts( _core_if );
 666
 667         /* Enable interrupts */
 668         intr_mask.b.usbreset = 1;
 669         intr_mask.b.enumdone = 1;
 670         //intr_mask.b.epmismatch = 1;
 671         intr_mask.b.inepintr = 1;
 672         intr_mask.b.outepintr = 1;
 673         intr_mask.b.erlysuspend = 1;
 674         if (_core_if->en_multiple_tx_fifo == 0) {
 675                 intr_mask.b.epmismatch = 1;
 676         }
 677
 678         /** @todo NGS: Should this be a module parameter? */
 679         intr_mask.b.isooutdrop = 1;
 680         intr_mask.b.eopframe = 1;
 681         intr_mask.b.incomplisoin = 1;
 682         intr_mask.b.incomplisoout = 1;
 683
 684         dwc_modify_reg32( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
 685
 686         DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
 687                     dwc_read_reg32( &global_regs->gintmsk));
 688 }
 689
 690 /**
 691  * This function initializes the DWC_otg controller registers for
 692  * device mode.
 693  *
 694  * @param _core_if Programming view of DWC_otg controller
 695  *
 696  */
 697 void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if)
 698 {
 699         dwc_otg_core_global_regs_t *global_regs =
 700                 _core_if->core_global_regs;
 701         dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
 702         dwc_otg_core_params_t *params = _core_if->core_params;
 703         dcfg_data_t dcfg = {.d32 = 0};
 704         grstctl_t resetctl = { .d32=0 };
 705         int i;
 706         uint32_t rx_fifo_size;
 707         fifosize_data_t nptxfifosize;
 708         fifosize_data_t txfifosize;
 709         dthrctl_data_t dthrctl;
 710
 711         fifosize_data_t ptxfifosize;
 712
 713         /* Restart the Phy Clock */
 714         dwc_write_reg32(_core_if->pcgcctl, 0);
 715
 716         /* Device configuration register */
 717         init_devspd(_core_if);
 718         dcfg.d32 = dwc_read_reg32( &dev_if->dev_global_regs->dcfg);
 719         dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
 720         dwc_write_reg32( &dev_if->dev_global_regs->dcfg, dcfg.d32 );
 721
 722         /* Configure data FIFO sizes */
 723         if ( _core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo ) {
 724
 725                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", _core_if->total_fifo_size);
 726                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
 727                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
 728
 729                 /* Rx FIFO */
 730                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
 731                             dwc_read_reg32(&global_regs->grxfsiz));
 732                 rx_fifo_size = params->dev_rx_fifo_size;
 733                 dwc_write_reg32( &global_regs->grxfsiz, rx_fifo_size );
 734                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
 735                             dwc_read_reg32(&global_regs->grxfsiz));
 736
 737                 /** Set Periodic Tx FIFO Mask all bits 0 */
 738             _core_if->p_tx_msk = 0;
 739
 740                 /** Set Tx FIFO Mask all bits 0 */
 741             _core_if->tx_msk = 0;
 742                 if (_core_if->en_multiple_tx_fifo == 0) {
 743                 /* Non-periodic Tx FIFO */
 744                 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
 745                             dwc_read_reg32(&global_regs->gnptxfsiz));
 746                 nptxfifosize.b.depth  = params->dev_nperio_tx_fifo_size;
 747                 nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
 748                 dwc_write_reg32( &global_regs->gnptxfsiz, nptxfifosize.d32 );
 749                 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
 750                             dwc_read_reg32(&global_regs->gnptxfsiz));
 751
 752
 753                 /**@todo NGS: Fix Periodic FIFO Sizing! */
 754                 /*
 755                  * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
 756                  * Indexes of the FIFO size module parameters in the
 757                  * dev_perio_tx_fifo_size array and the FIFO size registers in
 758                  * the dptxfsiz array run from 0 to 14.
 759                  */
 760                 /** @todo Finish debug of this */
 761                     ptxfifosize.b.startaddr =
 762                     nptxfifosize.b.startaddr + nptxfifosize.b.depth;
 763                         for (i = 0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) {
 764                         ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i];
 765                                 DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n",
 766                                      i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
 767                                 dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],ptxfifosize.d32);
 768                                 DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n",
 769                                      i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
 770                         ptxfifosize.b.startaddr += ptxfifosize.b.depth;
 771                 }
 772                 } else {
 773
 774                     /*
 775                      * Tx FIFOs These FIFOs are numbered from 1 to 15.
 776                      * Indexes of the FIFO size module parameters in the
 777                      * dev_tx_fifo_size array and the FIFO size registers in
 778                      * the dptxfsiz_dieptxf array run from 0 to 14.
 779                      */
 780
 781                     /* Non-periodic Tx FIFO */
 782                     DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
 783                                 dwc_read_reg32(&global_regs->gnptxfsiz));
 784                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
 785                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
 786                         dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
 787                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
 788                                       dwc_read_reg32(&global_regs->gnptxfsiz));
 789                         txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
 790                         for (i = 1;i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) {
 791                                 txfifosize.b.depth = params->dev_tx_fifo_size[i];
 792                                 DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n",
 793                                       i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
 794                                 dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i - 1],txfifosize.d32);
 795                                 DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n",
 796                                       i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1]));
 797                                 txfifosize.b.startaddr += txfifosize.b.depth;
 798         }
 799                 }
 800         }
 801         /* Flush the FIFOs */
 802         dwc_otg_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */
 803         dwc_otg_flush_rx_fifo(_core_if);
 804
 805         /* Flush the Learning Queue. */
 806         resetctl.b.intknqflsh = 1;
 807         dwc_write_reg32( &_core_if->core_global_regs->grstctl, resetctl.d32);
 808
 809         /* Clear all pending Device Interrupts */
 810         dwc_write_reg32( &dev_if->dev_global_regs->diepmsk, 0 );
 811         dwc_write_reg32( &dev_if->dev_global_regs->doepmsk, 0 );
 812         dwc_write_reg32( &dev_if->dev_global_regs->daint, 0xFFFFFFFF );
 813         dwc_write_reg32( &dev_if->dev_global_regs->daintmsk, 0 );
 814
 815         for (i = 0; i <= dev_if->num_in_eps; i++) {
 816                 depctl_data_t depctl;
 817                 depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
 818                 if (depctl.b.epena) {
 819                         depctl.d32 = 0;
 820                         depctl.b.epdis = 1;
 821                         depctl.b.snak = 1;
 822                 } else {
 823                         depctl.d32 = 0;
 824                 }
 825                 dwc_write_reg32( &dev_if->in_ep_regs[i]->diepctl, depctl.d32);
 826
 827                 dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
 828                 dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
 829                 dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
 830         }
 831         for (i = 0; i <= dev_if->num_out_eps; i++) {
 832                 depctl_data_t depctl;
 833                 depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
 834                 if (depctl.b.epena) {
 835                         depctl.d32 = 0;
 836                         depctl.b.epdis = 1;
 837                         depctl.b.snak = 1;
 838                 } else {
 839                         depctl.d32 = 0;
 840                 }
 841                 dwc_write_reg32( &dev_if->out_ep_regs[i]->doepctl, depctl.d32);
 842
 843                 //dwc_write_reg32( &dev_if->in_ep_regs[i]->dieptsiz, 0);
 844                 dwc_write_reg32( &dev_if->out_ep_regs[i]->doeptsiz, 0);
 845                 //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepdma, 0);
 846                 dwc_write_reg32( &dev_if->out_ep_regs[i]->doepdma, 0);
 847                 //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepint, 0xFF);
 848                 dwc_write_reg32( &dev_if->out_ep_regs[i]->doepint, 0xFF);
 849         }
 850
 851         if (_core_if->en_multiple_tx_fifo && _core_if->dma_enable) {
 852                 dev_if->non_iso_tx_thr_en = _core_if->core_params->thr_ctl & 0x1;
 853                 dev_if->iso_tx_thr_en = (_core_if->core_params->thr_ctl >> 1) & 0x1;
 854                 dev_if->rx_thr_en = (_core_if->core_params->thr_ctl >> 2) & 0x1;
 855                 dev_if->rx_thr_length = _core_if->core_params->rx_thr_length;
 856                 dev_if->tx_thr_length = _core_if->core_params->tx_thr_length;
 857                 dthrctl.d32 = 0;
 858                 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
 859                 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
 860                 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
 861                 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
 862                 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
 863                 dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,dthrctl.d32);
 864                 DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\n"
 865                                         "Rx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
 866                                         dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
 867                                         dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
 868                                         dthrctl.b.rx_thr_len);
 869         }
 870         dwc_otg_enable_device_interrupts( _core_if );
 871         {
 872                 diepmsk_data_t msk = {.d32 = 0};
 873                 msk.b.txfifoundrn = 1;
 874                 dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32,msk.d32);
 875 }
 876 }
 877
 878 /**
 879  * This function enables the Host mode interrupts.
 880  *
 881  * @param _core_if Programming view of DWC_otg controller
 882  */
 883 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if)
 884 {
 885         dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
 886         gintmsk_data_t intr_mask = {.d32 = 0};
 887
 888         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
 889
 890         /* Disable all interrupts. */
 891         dwc_write_reg32(&global_regs->gintmsk, 0);
 892
 893         /* Clear any pending interrupts. */
 894         dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
 895
 896         /* Enable the common interrupts */
 897         dwc_otg_enable_common_interrupts(_core_if);
 898
 899         /*
 900          * Enable host mode interrupts without disturbing common
 901          * interrupts.
 902          */
 903         intr_mask.b.sofintr = 1;
 904         intr_mask.b.portintr = 1;
 905         intr_mask.b.hcintr = 1;
 906
 907         //dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
 908         //dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
 909         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
 910 }
 911
 912 /**
 913  * This function disables the Host Mode interrupts.
 914  *
 915  * @param _core_if Programming view of DWC_otg controller
 916  */
 917 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if)
 918 {
 919         dwc_otg_core_global_regs_t *global_regs =
 920                 _core_if->core_global_regs;
 921         gintmsk_data_t intr_mask = {.d32 = 0};
 922
 923         DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
 924
 925         /*
 926          * Disable host mode interrupts without disturbing common
 927          * interrupts.
 928          */
 929         intr_mask.b.sofintr = 1;
 930         intr_mask.b.portintr = 1;
 931         intr_mask.b.hcintr = 1;
 932         intr_mask.b.ptxfempty = 1;
 933         intr_mask.b.nptxfempty = 1;
 934
 935         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
 936 }
 937
 938 #if 0
 939 /* currently not used, keep it here as if needed later */
 940 static int phy_read(dwc_otg_core_if_t * _core_if, int addr)
 941 {
 942         u32 val;
 943         int timeout = 10;
 944
 945         dwc_write_reg32(&_core_if->core_global_regs->gpvndctl,
 946                         0x02000000 | (addr << 16));
 947         val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
 948         while (((val & 0x08000000) == 0) && (timeout--)) {
 949                 udelay(1000);
 950                 val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
 951         }
 952         val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
 953         printk("%s: addr=%02x regval=%02x\n", __func__, addr, val & 0x000000ff);
 954
 955         return 0;
 956 }
 957 #endif
 958
 959 /**
 960  * This function initializes the DWC_otg controller registers for
 961  * host mode.
 962  *
 963  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 964  * request queues. Host channels are reset to ensure that they are ready for
 965  * performing transfers.
 966  *
 967  * @param _core_if Programming view of DWC_otg controller
 968  *
 969  */
 970 void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if)
 971 {
 972         dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
 973         dwc_otg_host_if_t       *host_if = _core_if->host_if;
 974         dwc_otg_core_params_t   *params = _core_if->core_params;
 975         hprt0_data_t            hprt0 = {.d32 = 0};
 976         fifosize_data_t         nptxfifosize;
 977         fifosize_data_t         ptxfifosize;
 978         int                     i;
 979         hcchar_data_t           hcchar;
 980         hcfg_data_t             hcfg;
 981         dwc_otg_hc_regs_t       *hc_regs;
 982         int                     num_channels;
 983         gotgctl_data_t  gotgctl = {.d32 = 0};
 984
 985         DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, _core_if);
 986
 987         /* Restart the Phy Clock */
 988         dwc_write_reg32(_core_if->pcgcctl, 0);
 989
 990         /* Initialize Host Configuration Register */
 991         init_fslspclksel(_core_if);
 992         if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
 993                 hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
 994                 hcfg.b.fslssupp = 1;
 995                 dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
 996         }
 997
 998         /* Configure data FIFO sizes */
 999         if (_core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
1000                 DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", _core_if->total_fifo_size);
1001                 DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
1002                 DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
1003                 DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
1004
1005                 /* Rx FIFO */
1006                 DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
1007                 dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
1008                 DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
1009
1010                 /* Non-periodic Tx FIFO */
1011                 DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
1012                 nptxfifosize.b.depth  = params->host_nperio_tx_fifo_size;
1013                 nptxfifosize.b.startaddr = params->host_rx_fifo_size;
1014                 dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
1015                 DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
1016
1017                 /* Periodic Tx FIFO */
1018                 DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
1019                 ptxfifosize.b.depth  = params->host_perio_tx_fifo_size;
1020                 ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1021                 dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
1022                 DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
1023         }
1024
1025         /* Clear Host Set HNP Enable in the OTG Control Register */
1026         gotgctl.b.hstsethnpen = 1;
1027         dwc_modify_reg32( &global_regs->gotgctl, gotgctl.d32, 0);
1028
1029         /* Make sure the FIFOs are flushed. */
1030         dwc_otg_flush_tx_fifo(_core_if, 0x10 /* all Tx FIFOs */);
1031         dwc_otg_flush_rx_fifo(_core_if);
1032
1033         /* Flush out any leftover queued requests. */
1034         num_channels = _core_if->core_params->host_channels;
1035         for (i = 0; i < num_channels; i++) {
1036                 hc_regs = _core_if->host_if->hc_regs[i];
1037                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1038                 hcchar.b.chen = 0;
1039                 hcchar.b.chdis = 1;
1040                 hcchar.b.epdir = 0;
1041                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1042         }
1043
1044         /* Halt all channels to put them into a known state. */
1045         for (i = 0; i < num_channels; i++) {
1046                 int count = 0;
1047                 hc_regs = _core_if->host_if->hc_regs[i];
1048                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1049                 hcchar.b.chen = 1;
1050                 hcchar.b.chdis = 1;
1051                 hcchar.b.epdir = 0;
1052                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1053                 DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
1054                 do {
1055                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1056                         if (++count > 200) {
1057                                 DWC_ERROR("%s: Unable to clear halt on channel %d\n",
1058                                           __func__, i);
1059                                 break;
1060                         }
1061                         udelay(100);
1062                 } while (hcchar.b.chen);
1063         }
1064
1065         /* Turn on the vbus power. */
1066         DWC_PRINT("Init: Port Power? op_state=%d\n", _core_if->op_state);
1067         if (_core_if->op_state == A_HOST){
1068                 hprt0.d32 = dwc_otg_read_hprt0(_core_if);
1069                 DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
1070                 if (hprt0.b.prtpwr == 0 ) {
1071                         hprt0.b.prtpwr = 1;
1072                         dwc_write_reg32(host_if->hprt0, hprt0.d32);
1073                 }
1074         }
1075
1076         dwc_otg_enable_host_interrupts( _core_if );
1077 }
1078
1079 /**
1080  * Prepares a host channel for transferring packets to/from a specific
1081  * endpoint. The HCCHARn register is set up with the characteristics specified
1082  * in _hc. Host channel interrupts that may need to be serviced while this
1083  * transfer is in progress are enabled.
1084  *
1085  * @param _core_if Programming view of DWC_otg controller
1086  * @param _hc Information needed to initialize the host channel
1087  */
1088 void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
1089 {
1090         uint32_t intr_enable;
1091         hcintmsk_data_t hc_intr_mask;
1092         gintmsk_data_t gintmsk = {.d32 = 0};
1093         hcchar_data_t hcchar;
1094         hcsplt_data_t hcsplt;
1095
1096         uint8_t hc_num = _hc->hc_num;
1097         dwc_otg_host_if_t *host_if = _core_if->host_if;
1098         dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
1099
1100         /* Clear old interrupt conditions for this host channel. */
1101         hc_intr_mask.d32 = 0xFFFFFFFF;
1102         hc_intr_mask.b.reserved = 0;
1103         dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
1104
1105         /* Enable channel interrupts required for this transfer. */
1106         hc_intr_mask.d32 = 0;
1107         hc_intr_mask.b.chhltd = 1;
1108         if (_core_if->dma_enable) {
1109                 hc_intr_mask.b.ahberr = 1;
1110                 if (_hc->error_state && !_hc->do_split &&
1111                     _hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1112                         hc_intr_mask.b.ack = 1;
1113                         if (_hc->ep_is_in) {
1114                                 hc_intr_mask.b.datatglerr = 1;
1115                                 if (_hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
1116                                         hc_intr_mask.b.nak = 1;
1117                                 }
1118                         }
1119                 }
1120         } else {
1121                 switch (_hc->ep_type) {
1122                 case DWC_OTG_EP_TYPE_CONTROL:
1123                 case DWC_OTG_EP_TYPE_BULK:
1124                         hc_intr_mask.b.xfercompl = 1;
1125                         hc_intr_mask.b.stall = 1;
1126                         hc_intr_mask.b.xacterr = 1;
1127                         hc_intr_mask.b.datatglerr = 1;
1128                         if (_hc->ep_is_in) {
1129                                 hc_intr_mask.b.bblerr = 1;
1130                         } else {
1131                                 hc_intr_mask.b.nak = 1;
1132                                 hc_intr_mask.b.nyet = 1;
1133                                 if (_hc->do_ping) {
1134                                         hc_intr_mask.b.ack = 1;
1135                                 }
1136                         }
1137
1138                         if (_hc->do_split) {
1139                                 hc_intr_mask.b.nak = 1;
1140                                 if (_hc->complete_split) {
1141                                         hc_intr_mask.b.nyet = 1;
1142                                 }
1143                                 else {
1144                                         hc_intr_mask.b.ack = 1;
1145                                 }
1146                         }
1147
1148                         if (_hc->error_state) {
1149                                 hc_intr_mask.b.ack = 1;
1150                         }
1151                         break;
1152                 case DWC_OTG_EP_TYPE_INTR:
1153                         hc_intr_mask.b.xfercompl = 1;
1154                         hc_intr_mask.b.nak = 1;
1155                         hc_intr_mask.b.stall = 1;
1156                         hc_intr_mask.b.xacterr = 1;
1157                         hc_intr_mask.b.datatglerr = 1;
1158                         hc_intr_mask.b.frmovrun = 1;
1159
1160                         if (_hc->ep_is_in) {
1161                                 hc_intr_mask.b.bblerr = 1;
1162                         }
1163                         if (_hc->error_state) {
1164                                 hc_intr_mask.b.ack = 1;
1165                         }
1166                         if (_hc->do_split) {
1167                                 if (_hc->complete_split) {
1168                                         hc_intr_mask.b.nyet = 1;
1169                                 }
1170                                 else {
1171                                         hc_intr_mask.b.ack = 1;
1172                                 }
1173                         }
1174                         break;
1175                 case DWC_OTG_EP_TYPE_ISOC:
1176                         hc_intr_mask.b.xfercompl = 1;
1177                         hc_intr_mask.b.frmovrun = 1;
1178                         hc_intr_mask.b.ack = 1;
1179
1180                         if (_hc->ep_is_in) {
1181                                 hc_intr_mask.b.xacterr = 1;
1182                                 hc_intr_mask.b.bblerr = 1;
1183                         }
1184                         break;
1185                 }
1186         }
1187         dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
1188
1189         /* Enable the top level host channel interrupt. */
1190         intr_enable = (1 << hc_num);
1191         dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
1192
1193         /* Make sure host channel interrupts are enabled. */
1194         gintmsk.b.hcintr = 1;
1195         dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
1196
1197         /*
1198          * Program the HCCHARn register with the endpoint characteristics for
1199          * the current transfer.
1200          */
1201         hcchar.d32 = 0;
1202         hcchar.b.devaddr = _hc->dev_addr;
1203         hcchar.b.epnum = _hc->ep_num;
1204         hcchar.b.epdir = _hc->ep_is_in;
1205         hcchar.b.lspddev = (_hc->speed == DWC_OTG_EP_SPEED_LOW);
1206         hcchar.b.eptype = _hc->ep_type;
1207         hcchar.b.mps = _hc->max_packet;
1208
1209         dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
1210
1211         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
1212         DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
1213         DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
1214         DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
1215         DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
1216         DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
1217         DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
1218         DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
1219
1220         /*
1221          * Program the HCSPLIT register for SPLITs
1222          */
1223         hcsplt.d32 = 0;
1224         if (_hc->do_split) {
1225                 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", _hc->hc_num,
1226                            _hc->complete_split ? "CSPLIT" : "SSPLIT");
1227                 hcsplt.b.compsplt = _hc->complete_split;
1228                 hcsplt.b.xactpos = _hc->xact_pos;
1229                 hcsplt.b.hubaddr = _hc->hub_addr;
1230                 hcsplt.b.prtaddr = _hc->port_addr;
1231                 DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", _hc->complete_split);
1232                 DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", _hc->xact_pos);
1233                 DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", _hc->hub_addr);
1234                 DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", _hc->port_addr);
1235                 DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", _hc->ep_is_in);
1236                 DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
1237                 DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", _hc->xfer_len);
1238         }
1239         dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
1240
1241 }
1242
1243 /**
1244  * Attempts to halt a host channel. This function should only be called in
1245  * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
1246  * normal circumstances in DMA mode, the controller halts the channel when the
1247  * transfer is complete or a condition occurs that requires application
1248  * intervention.
1249  *
1250  * In slave mode, checks for a free request queue entry, then sets the Channel
1251  * Enable and Channel Disable bits of the Host Channel Characteristics
1252  * register of the specified channel to intiate the halt. If there is no free
1253  * request queue entry, sets only the Channel Disable bit of the HCCHARn
1254  * register to flush requests for this channel. In the latter case, sets a
1255  * flag to indicate that the host channel needs to be halted when a request
1256  * queue slot is open.
1257  *
1258  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
1259  * HCCHARn register. The controller ensures there is space in the request
1260  * queue before submitting the halt request.
1261  *
1262  * Some time may elapse before the core flushes any posted requests for this
1263  * host channel and halts. The Channel Halted interrupt handler completes the
1264  * deactivation of the host channel.
1265  *
1266  * @param _core_if Controller register interface.
1267  * @param _hc Host channel to halt.
1268  * @param _halt_status Reason for halting the channel.
1269  */
1270 void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
1271                      dwc_hc_t *_hc,
1272                      dwc_otg_halt_status_e _halt_status)
1273 {
1274         gnptxsts_data_t                 nptxsts;
1275         hptxsts_data_t                  hptxsts;
1276         hcchar_data_t                   hcchar;
1277         dwc_otg_hc_regs_t               *hc_regs;
1278         dwc_otg_core_global_regs_t      *global_regs;
1279         dwc_otg_host_global_regs_t      *host_global_regs;
1280
1281         hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
1282         global_regs = _core_if->core_global_regs;
1283         host_global_regs = _core_if->host_if->host_global_regs;
1284
1285         WARN_ON(_halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS);
1286
1287         if (_halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1288             _halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
1289                 /*
1290                  * Disable all channel interrupts except Ch Halted. The QTD
1291                  * and QH state associated with this transfer has been cleared
1292                  * (in the case of URB_DEQUEUE), so the channel needs to be
1293                  * shut down carefully to prevent crashes.
1294                  */
1295                 hcintmsk_data_t hcintmsk;
1296                 hcintmsk.d32 = 0;
1297                 hcintmsk.b.chhltd = 1;
1298                 dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
1299
1300                 /*
1301                  * Make sure no other interrupts besides halt are currently
1302                  * pending. Handling another interrupt could cause a crash due
1303                  * to the QTD and QH state.
1304                  */
1305                 dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
1306
1307                 /*
1308                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1309                  * even if the channel was already halted for some other
1310                  * reason.
1311                  */
1312                 _hc->halt_status = _halt_status;
1313
1314                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1315                 if (hcchar.b.chen == 0) {
1316                         /*
1317                          * The channel is either already halted or it hasn't
1318                          * started yet. In DMA mode, the transfer may halt if
1319                          * it finishes normally or a condition occurs that
1320                          * requires driver intervention. Don't want to halt
1321                          * the channel again. In either Slave or DMA mode,
1322                          * it's possible that the transfer has been assigned
1323                          * to a channel, but not started yet when an URB is
1324                          * dequeued. Don't want to halt a channel that hasn't
1325                          * started yet.
1326                          */
1327                         return;
1328                 }
1329         }
1330
1331         if (_hc->halt_pending) {
1332                 /*
1333                  * A halt has already been issued for this channel. This might
1334                  * happen when a transfer is aborted by a higher level in
1335                  * the stack.
1336                  */
1337 #ifdef DEBUG
1338                 DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
1339                           __func__, _hc->hc_num);
1340
1341 /*              dwc_otg_dump_global_registers(_core_if); */
1342 /*              dwc_otg_dump_host_registers(_core_if); */
1343 #endif
1344                 return;
1345         }
1346
1347         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1348         hcchar.b.chen = 1;
1349         hcchar.b.chdis = 1;
1350
1351         if (!_core_if->dma_enable) {
1352                 /* Check for space in the request queue to issue the halt. */
1353                 if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1354                     _hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
1355                         nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
1356                         if (nptxsts.b.nptxqspcavail == 0) {
1357                                 hcchar.b.chen = 0;
1358                         }
1359                 } else {
1360                         hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
1361                         if ((hptxsts.b.ptxqspcavail == 0) || (_core_if->queuing_high_bandwidth)) {
1362                                 hcchar.b.chen = 0;
1363                         }
1364                 }
1365         }
1366
1367         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1368
1369         _hc->halt_status = _halt_status;
1370
1371         if (hcchar.b.chen) {
1372                 _hc->halt_pending = 1;
1373                 _hc->halt_on_queue = 0;
1374         } else {
1375                 _hc->halt_on_queue = 1;
1376         }
1377
1378         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
1379         DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
1380         DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", _hc->halt_pending);
1381         DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", _hc->halt_on_queue);
1382         DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", _hc->halt_status);
1383
1384         return;
1385 }
1386
1387 /**
1388  * Clears the transfer state for a host channel. This function is normally
1389  * called after a transfer is done and the host channel is being released.
1390  *
1391  * @param _core_if Programming view of DWC_otg controller.
1392  * @param _hc Identifies the host channel to clean up.
1393  */
1394 void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
1395 {
1396         dwc_otg_hc_regs_t *hc_regs;
1397
1398         _hc->xfer_started = 0;
1399
1400         /*
1401          * Clear channel interrupt enables and any unhandled channel interrupt
1402          * conditions.
1403          */
1404         hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
1405         dwc_write_reg32(&hc_regs->hcintmsk, 0);
1406         dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
1407
1408 #ifdef DEBUG
1409         del_timer(&_core_if->hc_xfer_timer[_hc->hc_num]);
1410         {
1411                 hcchar_data_t hcchar;
1412                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1413                 if (hcchar.b.chdis) {
1414                         DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
1415                                  __func__, _hc->hc_num, hcchar.d32);
1416                 }
1417         }
1418 #endif
1419 }
1420
1421 /**
1422  * Sets the channel property that indicates in which frame a periodic transfer
1423  * should occur. This is always set to the _next_ frame. This function has no
1424  * effect on non-periodic transfers.
1425  *
1426  * @param _core_if Programming view of DWC_otg controller.
1427  * @param _hc Identifies the host channel to set up and its properties.
1428  * @param _hcchar Current value of the HCCHAR register for the specified host
1429  * channel.
1430  */
1431 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *_core_if,
1432                                          dwc_hc_t *_hc,
1433                                          hcchar_data_t *_hcchar)
1434 {
1435         if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1436             _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1437                 hfnum_data_t    hfnum;
1438                 hfnum.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hfnum);
1439                 /* 1 if _next_ frame is odd, 0 if it's even */
1440                 _hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
1441 #ifdef DEBUG
1442                 if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR && _hc->do_split && !_hc->complete_split) {
1443                         switch (hfnum.b.frnum & 0x7) {
1444                         case 7:
1445                                 _core_if->hfnum_7_samples++;
1446                                 _core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
1447                                 break;
1448                         case 0:
1449                                 _core_if->hfnum_0_samples++;
1450                                 _core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
1451                                 break;
1452                         default:
1453                                 _core_if->hfnum_other_samples++;
1454                                 _core_if->hfnum_other_frrem_accum += hfnum.b.frrem;
1455                                 break;
1456                         }
1457                 }
1458 #endif
1459         }
1460 }
1461
1462 #ifdef DEBUG
1463 static void hc_xfer_timeout(unsigned long _ptr)
1464 {
1465         hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr;
1466         int hc_num = xfer_info->hc->hc_num;
1467         DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
1468         DWC_WARN("  start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]);
1469 }
1470 #endif
1471
1472 /*
1473  * This function does the setup for a data transfer for a host channel and
1474  * starts the transfer. May be called in either Slave mode or DMA mode. In
1475  * Slave mode, the caller must ensure that there is sufficient space in the
1476  * request queue and Tx Data FIFO.
1477  *
1478  * For an OUT transfer in Slave mode, it loads a data packet into the
1479  * appropriate FIFO. If necessary, additional data packets will be loaded in
1480  * the Host ISR.
1481  *
1482  * For an IN transfer in Slave mode, a data packet is requested. The data
1483  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1484  * additional data packets are requested in the Host ISR.
1485  *
1486  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1487  * register along with a packet count of 1 and the channel is enabled. This
1488  * causes a single PING transaction to occur. Other fields in HCTSIZ are
1489  * simply set to 0 since no data transfer occurs in this case.
1490  *
1491  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1492  * all the information required to perform the subsequent data transfer. In
1493  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1494  * controller performs the entire PING protocol, then starts the data
1495  * transfer.
1496  *
1497  * @param _core_if Programming view of DWC_otg controller.
1498  * @param _hc Information needed to initialize the host channel. The xfer_len
1499  * value may be reduced to accommodate the max widths of the XferSize and
1500  * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
1501  * to reflect the final xfer_len value.
1502  */
1503 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
1504 {
1505         hcchar_data_t hcchar;
1506         hctsiz_data_t hctsiz;
1507         uint16_t num_packets;
1508         uint32_t max_hc_xfer_size = _core_if->core_params->max_transfer_size;
1509         uint16_t max_hc_pkt_count = _core_if->core_params->max_packet_count;
1510         dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
1511
1512         hctsiz.d32 = 0;
1513
1514         if (_hc->do_ping) {
1515                 if (!_core_if->dma_enable) {
1516                         dwc_otg_hc_do_ping(_core_if, _hc);
1517                         _hc->xfer_started = 1;
1518                         return;
1519                 } else {
1520                         hctsiz.b.dopng = 1;
1521                 }
1522         }
1523
1524         if (_hc->do_split) {
1525                 num_packets = 1;
1526
1527                 if (_hc->complete_split && !_hc->ep_is_in) {
1528                         /* For CSPLIT OUT Transfer, set the size to 0 so the
1529                          * core doesn't expect any data written to the FIFO */
1530                         _hc->xfer_len = 0;
1531                 } else if (_hc->ep_is_in || (_hc->xfer_len > _hc->max_packet)) {
1532                         _hc->xfer_len = _hc->max_packet;
1533                 } else if (!_hc->ep_is_in && (_hc->xfer_len > 188)) {
1534                         _hc->xfer_len = 188;
1535                 }
1536
1537                 hctsiz.b.xfersize = _hc->xfer_len;
1538         } else {
1539                 /*
1540                  * Ensure that the transfer length and packet count will fit
1541                  * in the widths allocated for them in the HCTSIZn register.
1542                  */
1543                 if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1544                     _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1545                         /*
1546                          * Make sure the transfer size is no larger than one
1547                          * (micro)frame's worth of data. (A check was done
1548                          * when the periodic transfer was accepted to ensure
1549                          * that a (micro)frame's worth of data can be
1550                          * programmed into a channel.)
1551                          */
1552                         uint32_t max_periodic_len = _hc->multi_count * _hc->max_packet;
1553                         if (_hc->xfer_len > max_periodic_len) {
1554                                 _hc->xfer_len = max_periodic_len;
1555                         } else {
1556                         }
1557                 } else if (_hc->xfer_len > max_hc_xfer_size) {
1558                         /* Make sure that xfer_len is a multiple of max packet size. */
1559                         _hc->xfer_len = max_hc_xfer_size - _hc->max_packet + 1;
1560                 }
1561
1562                 if (_hc->xfer_len > 0) {
1563                         num_packets = (_hc->xfer_len + _hc->max_packet - 1) / _hc->max_packet;
1564                         if (num_packets > max_hc_pkt_count) {
1565                                 num_packets = max_hc_pkt_count;
1566                                 _hc->xfer_len = num_packets * _hc->max_packet;
1567                         }
1568                 } else {
1569                         /* Need 1 packet for transfer length of 0. */
1570                         num_packets = 1;
1571                 }
1572
1573                 if (_hc->ep_is_in) {
1574                         /* Always program an integral # of max packets for IN transfers. */
1575                         _hc->xfer_len = num_packets * _hc->max_packet;
1576                 }
1577
1578                 if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1579                     _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1580                         /*
1581                          * Make sure that the multi_count field matches the
1582                          * actual transfer length.
1583                          */
1584                         _hc->multi_count = num_packets;
1585
1586                 }
1587
1588                 if (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1589                         /* Set up the initial PID for the transfer. */
1590                         if (_hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1591                                 if (_hc->ep_is_in) {
1592                                         if (_hc->multi_count == 1) {
1593                                                 _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
1594                                         } else if (_hc->multi_count == 2) {
1595                                                 _hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1596                                         } else {
1597                                                 _hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
1598                                         }
1599                                 } else {
1600                                         if (_hc->multi_count == 1) {
1601                                                 _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
1602                                         } else {
1603                                                 _hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
1604                                         }
1605                                 }
1606                         } else {
1607                                 _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
1608                         }
1609                 }
1610
1611                 hctsiz.b.xfersize = _hc->xfer_len;
1612         }
1613
1614         _hc->start_pkt_count = num_packets;
1615         hctsiz.b.pktcnt = num_packets;
1616         hctsiz.b.pid = _hc->data_pid_start;
1617         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1618
1619         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
1620         DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
1621         DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
1622         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
1623
1624         if (_core_if->dma_enable) {
1625 #ifdef DEBUG
1626 if(((uint32_t)_hc->xfer_buff)%4)
1627 printk("dwc_otg_hc_start_transfer _hc->xfer_buff not 4 byte alignment\n");
1628 #endif
1629                 dwc_write_reg32(&hc_regs->hcdma, (uint32_t)_hc->xfer_buff);
1630         }
1631
1632         /* Start the split */
1633         if (_hc->do_split) {
1634                 hcsplt_data_t hcsplt;
1635                 hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt);
1636                 hcsplt.b.spltena = 1;
1637                 dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
1638         }
1639
1640         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1641         hcchar.b.multicnt = _hc->multi_count;
1642         hc_set_even_odd_frame(_core_if, _hc, &hcchar);
1643 #ifdef DEBUG
1644         _core_if->start_hcchar_val[_hc->hc_num] = hcchar.d32;
1645         if (hcchar.b.chdis) {
1646                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
1647                          __func__, _hc->hc_num, hcchar.d32);
1648         }
1649 #endif
1650
1651         /* Set host channel enable after all other setup is complete. */
1652         hcchar.b.chen = 1;
1653         hcchar.b.chdis = 0;
1654         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1655
1656         _hc->xfer_started = 1;
1657         _hc->requests++;
1658
1659         if (!_core_if->dma_enable && !_hc->ep_is_in && _hc->xfer_len > 0) {
1660                 /* Load OUT packet into the appropriate Tx FIFO. */
1661                 dwc_otg_hc_write_packet(_core_if, _hc);
1662         }
1663
1664 #ifdef DEBUG
1665         /* Start a timer for this transfer. */
1666         _core_if->hc_xfer_timer[_hc->hc_num].function = hc_xfer_timeout;
1667         _core_if->hc_xfer_info[_hc->hc_num].core_if = _core_if;
1668         _core_if->hc_xfer_info[_hc->hc_num].hc = _hc;
1669         _core_if->hc_xfer_timer[_hc->hc_num].data = (unsigned long)(&_core_if->hc_xfer_info[_hc->hc_num]);
1670         _core_if->hc_xfer_timer[_hc->hc_num].expires = jiffies + (HZ*10);
1671         add_timer(&_core_if->hc_xfer_timer[_hc->hc_num]);
1672 #endif
1673 }
1674
1675 /**
1676  * This function continues a data transfer that was started by previous call
1677  * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
1678  * sufficient space in the request queue and Tx Data FIFO. This function
1679  * should only be called in Slave mode. In DMA mode, the controller acts
1680  * autonomously to complete transfers programmed to a host channel.
1681  *
1682  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1683  * if there is any data remaining to be queued. For an IN transfer, another
1684  * data packet is always requested. For the SETUP phase of a control transfer,
1685  * this function does nothing.
1686  *
1687  * @return 1 if a new request is queued, 0 if no more requests are required
1688  * for this transfer.
1689  */
1690 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
1691 {
1692         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
1693
1694         if (_hc->do_split) {
1695                 /* SPLITs always queue just once per channel */
1696                 return 0;
1697         } else if (_hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1698                 /* SETUPs are queued only once since they can't be NAKed. */
1699                 return 0;
1700         } else if (_hc->ep_is_in) {
1701                 /*
1702                  * Always queue another request for other IN transfers. If
1703                  * back-to-back INs are issued and NAKs are received for both,
1704                  * the driver may still be processing the first NAK when the
1705                  * second NAK is received. When the interrupt handler clears
1706                  * the NAK interrupt for the first NAK, the second NAK will
1707                  * not be seen. So we can't depend on the NAK interrupt
1708                  * handler to requeue a NAKed request. Instead, IN requests
1709                  * are issued each time this function is called. When the
1710                  * transfer completes, the extra requests for the channel will
1711                  * be flushed.
1712                  */
1713                 hcchar_data_t hcchar;
1714                 dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
1715
1716                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1717                 hc_set_even_odd_frame(_core_if, _hc, &hcchar);
1718                 hcchar.b.chen = 1;
1719                 hcchar.b.chdis = 0;
1720                 DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n", hcchar.d32);
1721                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1722                 _hc->requests++;
1723                 return 1;
1724         } else {
1725                 /* OUT transfers. */
1726                 if (_hc->xfer_count < _hc->xfer_len) {
1727                         if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1728                             _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1729                                 hcchar_data_t hcchar;
1730                                 dwc_otg_hc_regs_t *hc_regs;
1731                                 hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
1732                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1733                                 hc_set_even_odd_frame(_core_if, _hc, &hcchar);
1734                         }
1735
1736                         /* Load OUT packet into the appropriate Tx FIFO. */
1737                         dwc_otg_hc_write_packet(_core_if, _hc);
1738                         _hc->requests++;
1739                         return 1;
1740                 } else {
1741                         return 0;
1742                 }
1743         }
1744 }
1745
1746 /**
1747  * Starts a PING transfer. This function should only be called in Slave mode.
1748  * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
1749  */
1750 void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
1751 {
1752         hcchar_data_t hcchar;
1753         hctsiz_data_t hctsiz;
1754         dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
1755
1756         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
1757
1758         hctsiz.d32 = 0;
1759         hctsiz.b.dopng = 1;
1760         hctsiz.b.pktcnt = 1;
1761         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1762
1763         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1764         hcchar.b.chen = 1;
1765         hcchar.b.chdis = 0;
1766         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1767 }
1768
1769 /*
1770  * This function writes a packet into the Tx FIFO associated with the Host
1771  * Channel. For a channel associated with a non-periodic EP, the non-periodic
1772  * Tx FIFO is written. For a channel associated with a periodic EP, the
1773  * periodic Tx FIFO is written. This function should only be called in Slave
1774  * mode.
1775  *
1776  * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
1777  * then number of bytes written to the Tx FIFO.
1778  */
1779 void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
1780 {
1781         uint32_t i;
1782         uint32_t remaining_count;
1783         uint32_t byte_count;
1784         uint32_t dword_count;
1785
1786         uint32_t *data_buff = (uint32_t *)(_hc->xfer_buff);
1787         uint32_t *data_fifo = _core_if->data_fifo[_hc->hc_num];
1788
1789         remaining_count = _hc->xfer_len - _hc->xfer_count;
1790         if (remaining_count > _hc->max_packet) {
1791                 byte_count = _hc->max_packet;
1792         } else {
1793                 byte_count = remaining_count;
1794         }
1795
1796         dword_count = (byte_count + 3) / 4;
1797
1798         if ((((unsigned long)data_buff) & 0x3) == 0) {
1799                 /* xfer_buff is DWORD aligned. */
1800                 for (i = 0; i < dword_count; i++, data_buff++) {
1801                         dwc_write_reg32(data_fifo, *data_buff);
1802                 }
1803         } else {
1804                 /* xfer_buff is not DWORD aligned. */
1805                 for (i = 0; i < dword_count; i++, data_buff++) {
1806                         dwc_write_reg32(data_fifo, get_unaligned(data_buff));
1807                 }
1808         }
1809
1810         _hc->xfer_count += byte_count;
1811         _hc->xfer_buff += byte_count;
1812 }
1813
1814 /**
1815  * Gets the current USB frame number. This is the frame number from the last
1816  * SOF packet.
1817  */
1818 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if)
1819 {
1820         dsts_data_t dsts;
1821         dsts.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts);
1822
1823         /* read current frame/microfreme number from DSTS register */
1824         return dsts.b.soffn;
1825 }
1826
1827 /**
1828  * This function reads a setup packet from the Rx FIFO into the destination
1829  * buffer.  This function is called from the Rx Status Queue Level (RxStsQLvl)
1830  * Interrupt routine when a SETUP packet has been received in Slave mode.
1831  *
1832  * @param _core_if Programming view of DWC_otg controller.
1833  * @param _dest Destination buffer for packet data.
1834  */
1835 void dwc_otg_read_setup_packet(dwc_otg_core_if_t *_core_if, uint32_t *_dest)
1836 {
1837         /* Get the 8 bytes of a setup transaction data */
1838
1839         /* Pop 2 DWORDS off the receive data FIFO into memory */
1840         _dest[0] = dwc_read_reg32(_core_if->data_fifo[0]);
1841         _dest[1] = dwc_read_reg32(_core_if->data_fifo[0]);
1842     //_dest[0] = dwc_read_datafifo32(_core_if->data_fifo[0]);
1843         //_dest[1] = dwc_read_datafifo32(_core_if->data_fifo[0]);
1844 }
1845
1846
1847 /**
1848  * This function enables EP0 OUT to receive SETUP packets and configures EP0
1849  * IN for transmitting packets.  It is normally called when the
1850  * "Enumeration Done" interrupt occurs.
1851  *
1852  * @param _core_if Programming view of DWC_otg controller.
1853  * @param _ep The EP0 data.
1854  */
1855 void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
1856 {
1857         dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1858         dsts_data_t dsts;
1859         depctl_data_t diepctl;
1860         depctl_data_t doepctl;
1861         dctl_data_t dctl ={.d32=0};
1862
1863         /* Read the Device Status and Endpoint 0 Control registers */
1864         dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
1865         diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
1866         doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
1867
1868         /* Set the MPS of the IN EP based on the enumeration speed */
1869         switch (dsts.b.enumspd) {
1870         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
1871         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
1872         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
1873                 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
1874                 break;
1875         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
1876                 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
1877                 break;
1878         }
1879
1880         dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
1881
1882         /* Enable OUT EP for receive */
1883         doepctl.b.epena = 1;
1884         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
1885
1886 #ifdef VERBOSE
1887         DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
1888                     dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
1889         DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
1890                     dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
1891 #endif
1892         dctl.b.cgnpinnak = 1;
1893         dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
1894         DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n",
1895                     dwc_read_reg32(&dev_if->dev_global_regs->dctl));
1896 }
1897
1898 /**
1899  * This function activates an EP.  The Device EP control register for
1900  * the EP is configured as defined in the ep structure.  Note: This
1901  * function is not used for EP0.
1902  *
1903  * @param _core_if Programming view of DWC_otg controller.
1904  * @param _ep The EP to activate.
1905  */
1906 void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
1907 {
1908         dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1909         depctl_data_t depctl;
1910         volatile uint32_t *addr;
1911         daint_data_t daintmsk = {.d32=0};
1912
1913         DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, _ep->num,
1914                     (_ep->is_in?"IN":"OUT"));
1915
1916         /* Read DEPCTLn register */
1917         if (_ep->is_in == 1) {
1918                 addr = &dev_if->in_ep_regs[_ep->num]->diepctl;
1919                 daintmsk.ep.in = 1<<_ep->num;
1920         } else {
1921                 addr = &dev_if->out_ep_regs[_ep->num]->doepctl;
1922                 daintmsk.ep.out = 1<<_ep->num;
1923         }
1924
1925         /* If the EP is already active don't change the EP Control
1926          * register. */
1927         depctl.d32 = dwc_read_reg32(addr);
1928         if (!depctl.b.usbactep) {
1929                 depctl.b.mps = _ep->maxpacket;
1930                 depctl.b.eptype = _ep->type;
1931                 depctl.b.txfnum = _ep->tx_fifo_num;
1932
1933                 if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
1934                         depctl.b.setd0pid = 1;  // ???
1935                 } else {
1936                         depctl.b.setd0pid = 1;
1937                 }
1938                 depctl.b.usbactep = 1;
1939
1940                 dwc_write_reg32(addr, depctl.d32);
1941                 DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr));
1942         }
1943
1944
1945         /* Enable the Interrupt for this EP */
1946         dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
1947                          0, daintmsk.d32);
1948         DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n",
1949                     dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
1950         _ep->stall_clear_flag = 0;
1951         return;
1952 }
1953
1954 /**
1955  * This function deactivates an EP.  This is done by clearing the USB Active
1956  * EP bit in the Device EP control register.  Note: This function is not used
1957  * for EP0. EP0 cannot be deactivated.
1958  *
1959  * @param _core_if Programming view of DWC_otg controller.
1960  * @param _ep The EP to deactivate.
1961  */
1962 void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
1963 {
1964         depctl_data_t depctl ={.d32 = 0};
1965         volatile uint32_t *addr;
1966         daint_data_t daintmsk = {.d32=0};
1967
1968         /* Read DEPCTLn register */
1969         if (_ep->is_in == 1) {
1970                 addr = &_core_if->dev_if->in_ep_regs[_ep->num]->diepctl;
1971                 daintmsk.ep.in = 1<<_ep->num;
1972         } else {
1973                 addr = &_core_if->dev_if->out_ep_regs[_ep->num]->doepctl;
1974                 daintmsk.ep.out = 1<<_ep->num;
1975         }
1976
1977         depctl.b.usbactep = 0;
1978         dwc_write_reg32(addr, depctl.d32);
1979
1980         /* Disable the Interrupt for this EP */
1981         dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->daintmsk,
1982                          daintmsk.d32, 0);
1983
1984         return;
1985 }
1986
1987 /**
1988  * This function does the setup for a data transfer for an EP and
1989  * starts the transfer.  For an IN transfer, the packets will be
1990  * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
1991  * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
1992  *
1993  * @param _core_if Programming view of DWC_otg controller.
1994  * @param _ep The EP to start the transfer on.
1995  */
1996 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
1997 {
1998         /** @todo Refactor this funciton to check the transfer size
1999          * count value does not execed the number bits in the Transfer
2000          * count register. */
2001         depctl_data_t depctl;
2002         deptsiz_data_t deptsiz;
2003         gintmsk_data_t intr_mask = { .d32 = 0};
2004
2005 #ifdef CHECK_PACKET_COUNTER_WIDTH
2006         const uint32_t MAX_XFER_SIZE =
2007                 _core_if->core_params->max_transfer_size;
2008         const uint32_t MAX_PKT_COUNT =
2009                 _core_if->core_params->max_packet_count;
2010         uint32_t num_packets;
2011         uint32_t transfer_len;
2012         dwc_otg_dev_out_ep_regs_t *out_regs =
2013                 _core_if->dev_if->out_ep_regs[_ep->num];
2014         dwc_otg_dev_in_ep_regs_t *in_regs =
2015                 _core_if->dev_if->in_ep_regs[_ep->num];
2016         gnptxsts_data_t txstatus;
2017
2018         int lvl = SET_DEBUG_LEVEL(DBG_PCD);
2019
2020
2021         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
2022                     "xfer_buff=%p start_xfer_buff=%p\n",
2023                     _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
2024                     _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff);
2025
2026         transfer_len = _ep->xfer_len - _ep->xfer_count;
2027         if (transfer_len > MAX_XFER_SIZE) {
2028                 transfer_len = MAX_XFER_SIZE;
2029         }
2030         if (transfer_len == 0) {
2031                 num_packets = 1;
2032                 /* OUT EP to recieve Zero-length packet set transfer
2033                  * size to maxpacket size. */
2034                 if (!_ep->is_in) {
2035                         transfer_len = _ep->maxpacket;
2036                 }
2037         } else {
2038                 num_packets =
2039                         (transfer_len + _ep->maxpacket - 1) / _ep->maxpacket;
2040                 if (num_packets > MAX_PKT_COUNT) {
2041                         num_packets = MAX_PKT_COUNT;
2042                 }
2043         }
2044         DWC_DEBUGPL(DBG_PCD, "transfer_len=%d #pckt=%d\n", transfer_len,
2045                     num_packets);
2046
2047         deptsiz.b.xfersize = transfer_len;
2048         deptsiz.b.pktcnt = num_packets;
2049
2050         /* IN endpoint */
2051         if (_ep->is_in == 1) {
2052                 depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
2053         } else {/* OUT endpoint */
2054                 depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
2055         }
2056
2057         /* EP enable, IN data in FIFO */
2058         depctl.b.cnak = 1;
2059         depctl.b.epena = 1;
2060         /* IN endpoint */
2061         if (_ep->is_in == 1) {
2062                 txstatus.d32 =
2063                         dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
2064                 if (txstatus.b.nptxqspcavail == 0) {
2065                         DWC_DEBUGPL(DBG_ANY, "TX Queue Full (0x%0x)\n",
2066                                     txstatus.d32);
2067                         return;
2068                 }
2069                 dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
2070                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
2071                 /**
2072                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
2073                  * data will be written into the fifo by the ISR.
2074                  */
2075                 if (_core_if->dma_enable) {
2076                         dwc_write_reg32(&in_regs->diepdma, (uint32_t) _ep->xfer_buff);
2077                 } else {
2078                         if (_core_if->en_multiple_tx_fifo == 0) {
2079                         intr_mask.b.nptxfempty = 1;
2080                         dwc_modify_reg32( &_core_if->core_global_regs->gintsts,
2081                                           intr_mask.d32, 0);
2082                         dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
2083                                           intr_mask.d32, intr_mask.d32);
2084                         } else {
2085                             /* Enable the Tx FIFO Empty Interrupt for this EP */
2086                             if (_ep->xfer_len > 0 &&
2087                                          _ep->type != DWC_OTG_EP_TYPE_ISOC) {
2088                                         uint32_t fifoemptymsk = 0;
2089                                         fifoemptymsk = (0x1 << _ep->num);
2090                                         dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->
2091                                                         dtknqr4_fifoemptymsk,0, fifoemptymsk);
2092                 }
2093                         }
2094                 }
2095         } else {            /* OUT endpoint */
2096                 dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
2097                 dwc_write_reg32(&out_regs->doepctl, depctl.d32);
2098                 if (_core_if->dma_enable) {
2099                         dwc_write_reg32(&out_regs->doepdma,(uint32_t) _ep->xfer_buff);
2100                 }
2101         }
2102         DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
2103                     dwc_read_reg32(&out_regs->doepctl),
2104                     dwc_read_reg32(&out_regs->doeptsiz));
2105         DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
2106                     dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk),
2107                     dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
2108
2109         SET_DEBUG_LEVEL(lvl);
2110 #endif
2111         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
2112
2113         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
2114                     "xfer_buff=%p start_xfer_buff=%p\n",
2115                     _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
2116                     _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff);
2117
2118         /* IN endpoint */
2119         if (_ep->is_in == 1) {
2120                 dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[_ep->num];
2121                 gnptxsts_data_t gtxstatus;
2122                 gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
2123                 if (_core_if->en_multiple_tx_fifo == 0 &&
2124                         gtxstatus.b.nptxqspcavail == 0) {
2125 #ifdef DEBUG
2126                         DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32);
2127 #endif
2128                         //return;
2129                         MDELAY(100); //james
2130                 }
2131
2132                 depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
2133                 deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
2134
2135                 /* Zero Length Packet? */
2136                 if (_ep->xfer_len == 0) {
2137                         deptsiz.b.xfersize = 0;
2138                         deptsiz.b.pktcnt = 1;
2139                 } else {
2140
2141                         /* Program the transfer size and packet count
2142                          *  as follows: xfersize = N * maxpacket +
2143                          *  short_packet pktcnt = N + (short_packet
2144                          *  exist ? 1 : 0)
2145                          */
2146                         deptsiz.b.xfersize = _ep->xfer_len;
2147                         deptsiz.b.pktcnt = (_ep->xfer_len - 1 + _ep->maxpacket) / _ep->maxpacket;
2148                 }
2149
2150                 dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
2151
2152                 /* Write the DMA register */
2153                 if (_core_if->dma_enable) {
2154 #if 1 // winder
2155                         dma_cache_wback_inv((unsigned long) _ep->xfer_buff, _ep->xfer_len); // winder
2156                         dwc_write_reg32 (&(in_regs->diepdma),
2157                                          CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder
2158 #else
2159                         dwc_write_reg32 (&(in_regs->diepdma),
2160                                          (uint32_t)_ep->dma_addr);
2161 #endif
2162                 } else {
2163                         if (_ep->type != DWC_OTG_EP_TYPE_ISOC) {
2164                         /**
2165                          * Enable the Non-Periodic Tx FIFO empty interrupt,
2166                                  * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
2167                          * the data will be written into the fifo by the ISR.
2168                          */
2169                             if (_core_if->en_multiple_tx_fifo == 0) {
2170                         intr_mask.b.nptxfempty = 1;
2171                         dwc_modify_reg32( &_core_if->core_global_regs->gintsts,
2172                                           intr_mask.d32, 0);
2173                         dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
2174                                           intr_mask.d32, intr_mask.d32);
2175                                 } else {
2176                                     /* Enable the Tx FIFO Empty Interrupt for this EP */
2177                                     if (_ep->xfer_len > 0) {
2178                                                 uint32_t fifoemptymsk = 0;
2179                                                 fifoemptymsk = 1 << _ep->num;
2180                                                 dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->
2181                                                                   dtknqr4_fifoemptymsk,0,fifoemptymsk);
2182                                         }
2183                                 }
2184                         }
2185                 }
2186
2187                 /* EP enable, IN data in FIFO */
2188                 depctl.b.cnak = 1;
2189                 depctl.b.epena = 1;
2190                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
2191
2192                 if (_core_if->dma_enable) {
2193                 depctl.d32 = dwc_read_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl);
2194                 depctl.b.nextep = _ep->num;
2195                 dwc_write_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
2196
2197                 }
2198         } else {
2199                 /* OUT endpoint */
2200             dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num];
2201
2202                 depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
2203                 deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
2204
2205                 /* Program the transfer size and packet count as follows:
2206                  *
2207                  *  pktcnt = N
2208                  *  xfersize = N * maxpacket
2209                  */
2210                 if (_ep->xfer_len == 0) {
2211                         /* Zero Length Packet */
2212                         deptsiz.b.xfersize = _ep->maxpacket;
2213                         deptsiz.b.pktcnt = 1;
2214                 } else {
2215                         deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket;
2216                         deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket;
2217                 }
2218                 dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
2219
2220                 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
2221                               _ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
2222
2223                 if (_core_if->dma_enable) {
2224 #if 1 // winder
2225                         dwc_write_reg32 (&(out_regs->doepdma),
2226                                          CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder
2227 #else
2228                         dwc_write_reg32 (&(out_regs->doepdma),
2229                                          (uint32_t)_ep->dma_addr);
2230 #endif
2231                 }
2232
2233                 if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
2234                         /** @todo NGS: dpid is read-only. Use setd0pid
2235                          * or setd1pid. */
2236                         if (_ep->even_odd_frame) {
2237                                 depctl.b.setd1pid = 1;
2238                         } else {
2239                                 depctl.b.setd0pid = 1;
2240                         }
2241                 }
2242
2243                 /* EP enable */
2244                 depctl.b.cnak = 1;
2245                 depctl.b.epena = 1;
2246
2247                 dwc_write_reg32(&out_regs->doepctl, depctl.d32);
2248
2249                 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
2250                             dwc_read_reg32(&out_regs->doepctl),
2251                             dwc_read_reg32(&out_regs->doeptsiz));
2252                 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
2253                             dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk),
2254                             dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
2255         }
2256 }
2257
2258
2259 /**
2260  * This function does the setup for a data transfer for EP0 and starts
2261  * the transfer.  For an IN transfer, the packets will be loaded into
2262  * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
2263  * unloaded from the Rx FIFO in the ISR.
2264  *
2265  * @param _core_if Programming view of DWC_otg controller.
2266  * @param _ep The EP0 data.
2267  */
2268 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2269 {
2270         volatile depctl_data_t depctl;
2271         volatile deptsiz0_data_t deptsiz;
2272         gintmsk_data_t intr_mask = { .d32 = 0};
2273
2274         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
2275                     "xfer_buff=%p start_xfer_buff=%p total_len=%d\n",
2276                     _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
2277                     _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff,
2278                     _ep->total_len);
2279         _ep->total_len = _ep->xfer_len;
2280
2281         /* IN endpoint */
2282         if (_ep->is_in == 1) {
2283                 dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[0];
2284                 gnptxsts_data_t gtxstatus;
2285                 gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
2286                 if (_core_if->en_multiple_tx_fifo == 0 &&
2287                         gtxstatus.b.nptxqspcavail == 0) {
2288 #ifdef DEBUG
2289                         deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
2290                         DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n",
2291                                     dwc_read_reg32(&in_regs->diepctl));
2292                         DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
2293                                      deptsiz.d32, deptsiz.b.xfersize,deptsiz.b.pktcnt);
2294                         DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n", gtxstatus.d32);
2295 #endif  /*  */
2296                                                 printk("TX Queue or FIFO Full!!!!\n"); // test-only
2297                         //return;
2298                         MDELAY(100); //james
2299                 }
2300
2301                 depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
2302                 deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
2303
2304                 /* Zero Length Packet? */
2305                 if (_ep->xfer_len == 0) {
2306                         deptsiz.b.xfersize = 0;
2307                         deptsiz.b.pktcnt = 1;
2308                 } else {
2309                         /* Program the transfer size and packet count
2310                          *  as follows: xfersize = N * maxpacket +
2311                          *  short_packet pktcnt = N + (short_packet
2312                          *  exist ? 1 : 0)
2313                          */
2314                         if (_ep->xfer_len > _ep->maxpacket) {
2315                                 _ep->xfer_len = _ep->maxpacket;
2316                                 deptsiz.b.xfersize = _ep->maxpacket;
2317                         }
2318                         else {
2319                                 deptsiz.b.xfersize = _ep->xfer_len;
2320                         }
2321                         deptsiz.b.pktcnt = 1;
2322
2323                 }
2324                 dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
2325                 DWC_DEBUGPL(DBG_PCDV, "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
2326                              _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt, deptsiz.d32);
2327
2328                 /* Write the DMA register */
2329                 if (_core_if->dma_enable) {
2330                         dwc_write_reg32(&(in_regs->diepdma), (uint32_t) _ep->dma_addr);
2331                 }
2332
2333                 /* EP enable, IN data in FIFO */
2334                 depctl.b.cnak = 1;
2335                 depctl.b.epena = 1;
2336                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
2337
2338                 /**
2339                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
2340                  * data will be written into the fifo by the ISR.
2341                  */
2342                 if (!_core_if->dma_enable) {
2343                         if (_core_if->en_multiple_tx_fifo == 0) {
2344                         intr_mask.b.nptxfempty = 1;
2345                                 dwc_modify_reg32(&_core_if->core_global_regs->gintsts, intr_mask.d32, 0);
2346                                 dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, intr_mask.d32,
2347                                                   intr_mask.d32);
2348                         } else {
2349                             /* Enable the Tx FIFO Empty Interrupt for this EP */
2350                             if (_ep->xfer_len > 0) {
2351                                         uint32_t fifoemptymsk = 0;
2352                                         fifoemptymsk |= 1 << _ep->num;
2353                                         dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
2354                                                  0, fifoemptymsk);
2355                 }
2356
2357                         }
2358                 }
2359         } else {
2360             /* OUT endpoint */
2361             dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num];
2362
2363                 depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
2364                 deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
2365
2366                 /* Program the transfer size and packet count as follows:
2367                  *  xfersize = N * (maxpacket + 4 - (maxpacket % 4))
2368                  *  pktcnt = N                                          */
2369                 if (_ep->xfer_len == 0) {
2370                         /* Zero Length Packet */
2371                         deptsiz.b.xfersize = _ep->maxpacket;
2372                         deptsiz.b.pktcnt = 1;
2373                 } else {
2374                         deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket;
2375                         deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket;
2376                 }
2377
2378                 dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
2379                 DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
2380                              _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt);
2381
2382                 if (_core_if->dma_enable) {
2383                         dwc_write_reg32(&(out_regs->doepdma), (uint32_t) _ep->dma_addr);
2384                 }
2385
2386                 /* EP enable */
2387                 depctl.b.cnak = 1;
2388                 depctl.b.epena = 1;
2389                 dwc_write_reg32 (&(out_regs->doepctl), depctl.d32);
2390         }
2391 }
2392
2393 /**
2394  * This function continues control IN transfers started by
2395  * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
2396  * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
2397  * bit for the packet count.
2398  *
2399  * @param _core_if Programming view of DWC_otg controller.
2400  * @param _ep The EP0 data.
2401  */
2402 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2403 {
2404         depctl_data_t depctl;
2405         deptsiz0_data_t deptsiz;
2406         gintmsk_data_t intr_mask = { .d32 = 0};
2407
2408         if (_ep->is_in == 1) {
2409                 dwc_otg_dev_in_ep_regs_t *in_regs =
2410                         _core_if->dev_if->in_ep_regs[0];
2411                 gnptxsts_data_t tx_status = {.d32 = 0};
2412
2413                 tx_status.d32 = dwc_read_reg32( &_core_if->core_global_regs->gnptxsts );
2414                 /** @todo Should there be check for room in the Tx
2415                  * Status Queue.  If not remove the code above this comment. */
2416
2417                 depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
2418                 deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
2419
2420                 /* Program the transfer size and packet count
2421                  *  as follows: xfersize = N * maxpacket +
2422                  *  short_packet pktcnt = N + (short_packet
2423                  *  exist ? 1 : 0)
2424                  */
2425                 deptsiz.b.xfersize = (_ep->total_len - _ep->xfer_count) > _ep->maxpacket ? _ep->maxpacket :
2426                         (_ep->total_len - _ep->xfer_count);
2427                 deptsiz.b.pktcnt = 1;
2428                 _ep->xfer_len += deptsiz.b.xfersize;
2429
2430                 dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
2431                 DWC_DEBUGPL(DBG_PCDV, "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
2432                             _ep->xfer_len,
2433                             deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
2434
2435                 /* Write the DMA register */
2436                 if (_core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
2437                         dwc_write_reg32 (&(in_regs->diepdma),
2438                                          CPHYSADDR((uint32_t)_ep->dma_addr)); // winder
2439                 }
2440
2441                 /* EP enable, IN data in FIFO */
2442                 depctl.b.cnak = 1;
2443                 depctl.b.epena = 1;
2444                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
2445
2446                 /**
2447                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
2448                  * data will be written into the fifo by the ISR.
2449                  */
2450                 if (!_core_if->dma_enable) {
2451                         /* First clear it from GINTSTS */
2452                         intr_mask.b.nptxfempty = 1;
2453                         dwc_write_reg32( &_core_if->core_global_regs->gintsts,
2454                                          intr_mask.d32 );
2455
2456                         dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
2457                                           intr_mask.d32, intr_mask.d32);
2458                 }
2459
2460         }
2461
2462 }
2463
2464 #ifdef DEBUG
2465 void dump_msg(const u8 *buf, unsigned int length)
2466 {
2467         unsigned int    start, num, i;
2468         char            line[52], *p;
2469
2470         if (length >= 512)
2471                 return;
2472         start = 0;
2473         while (length > 0) {
2474                 num = min(length, 16u);
2475                 p = line;
2476                 for (i = 0; i < num; ++i) {
2477                         if (i == 8)
2478                                 *p++ = ' ';
2479                         sprintf(p, " %02x", buf[i]);
2480                         p += 3;
2481                 }
2482                 *p = 0;
2483                 DWC_PRINT( "%6x: %s\n", start, line);
2484                 buf += num;
2485                 start += num;
2486                 length -= num;
2487         }
2488 }
2489 #else
2490 static inline void dump_msg(const u8 *buf, unsigned int length)
2491 {
2492 }
2493 #endif
2494
2495 /**
2496  * This function writes a packet into the Tx FIFO associated with the
2497  * EP.  For non-periodic EPs the non-periodic Tx FIFO is written.  For
2498  * periodic EPs the periodic Tx FIFO associated with the EP is written
2499  * with all packets for the next micro-frame.
2500  *
2501  * @param _core_if Programming view of DWC_otg controller.
2502  * @param _ep The EP to write packet for.
2503  * @param _dma Indicates if DMA is being used.
2504  */
2505 void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)
2506 {
2507         /**
2508          * The buffer is padded to DWORD on a per packet basis in
2509          * slave/dma mode if the MPS is not DWORD aligned.  The last
2510          * packet, if short, is also padded to a multiple of DWORD.
2511          *
2512          * ep->xfer_buff always starts DWORD aligned in memory and is a
2513          * multiple of DWORD in length
2514          *
2515          * ep->xfer_len can be any number of bytes
2516          *
2517          * ep->xfer_count is a multiple of ep->maxpacket until the last
2518          *  packet
2519          *
2520          * FIFO access is DWORD */
2521
2522         uint32_t i;
2523         uint32_t byte_count;
2524         uint32_t dword_count;
2525         uint32_t *fifo;
2526         uint32_t *data_buff = (uint32_t *)_ep->xfer_buff;
2527
2528         //DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, _core_if, _ep);
2529         if (_ep->xfer_count >= _ep->xfer_len) {
2530                 DWC_WARN("%s() No data for EP%d!!!\n", __func__, _ep->num);
2531                 return;
2532         }
2533
2534         /* Find the byte length of the packet either short packet or MPS */
2535         if ((_ep->xfer_len - _ep->xfer_count) < _ep->maxpacket) {
2536                 byte_count = _ep->xfer_len - _ep->xfer_count;
2537         }
2538         else {
2539                 byte_count = _ep->maxpacket;
2540         }
2541
2542         /* Find the DWORD length, padded by extra bytes as neccessary if MPS
2543          * is not a multiple of DWORD */
2544         dword_count =  (byte_count + 3) / 4;
2545
2546 #ifdef VERBOSE
2547         dump_msg(_ep->xfer_buff, byte_count);
2548 #endif
2549         if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
2550                 /**@todo NGS Where are the Periodic Tx FIFO addresses
2551                  * intialized?  What should this be? */
2552                 fifo = _core_if->data_fifo[_ep->tx_fifo_num];
2553         } else {
2554                 fifo = _core_if->data_fifo[_ep->num];
2555         }
2556
2557         DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
2558                     fifo, data_buff, *data_buff, byte_count);
2559
2560
2561         if (!_dma) {
2562                 for (i=0; i<dword_count; i++, data_buff++) {
2563                         dwc_write_reg32( fifo, *data_buff );
2564                 }
2565         }
2566
2567         _ep->xfer_count += byte_count;
2568         _ep->xfer_buff += byte_count;
2569 #if 1 // winder, why do we need this??
2570         _ep->dma_addr += byte_count;
2571 #endif
2572 }
2573
2574 /**
2575  * Set the EP STALL.
2576  *
2577  * @param _core_if Programming view of DWC_otg controller.
2578  * @param _ep The EP to set the stall on.
2579  */
2580 void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2581 {
2582         depctl_data_t depctl;
2583         volatile uint32_t *depctl_addr;
2584
2585         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num,
2586                   (_ep->is_in?"IN":"OUT"));
2587
2588         if (_ep->is_in == 1) {
2589                 depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl);
2590                 depctl.d32 = dwc_read_reg32(depctl_addr);
2591
2592                 /* set the disable and stall bits */
2593                 if (depctl.b.epena) {
2594                         depctl.b.epdis = 1;
2595                 }
2596                 depctl.b.stall = 1;
2597                 dwc_write_reg32(depctl_addr, depctl.d32);
2598
2599         } else {
2600                 depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl);
2601                 depctl.d32 = dwc_read_reg32(depctl_addr);
2602
2603                 /* set the stall bit */
2604                 depctl.b.stall = 1;
2605                 dwc_write_reg32(depctl_addr, depctl.d32);
2606         }
2607         DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
2608         return;
2609 }
2610
2611 /**
2612  * Clear the EP STALL.
2613  *
2614  * @param _core_if Programming view of DWC_otg controller.
2615  * @param _ep The EP to clear stall from.
2616  */
2617 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2618 {
2619         depctl_data_t depctl;
2620         volatile uint32_t *depctl_addr;
2621
2622         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num,
2623                     (_ep->is_in?"IN":"OUT"));
2624
2625         if (_ep->is_in == 1) {
2626                 depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl);
2627         } else {
2628                 depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl);
2629         }
2630
2631         depctl.d32 = dwc_read_reg32(depctl_addr);
2632
2633         /* clear the stall bits */
2634         depctl.b.stall = 0;
2635
2636         /*
2637          * USB Spec 9.4.5: For endpoints using data toggle, regardless
2638          * of whether an endpoint has the Halt feature set, a
2639          * ClearFeature(ENDPOINT_HALT) request always results in the
2640          * data toggle being reinitialized to DATA0.
2641          */
2642         if (_ep->type == DWC_OTG_EP_TYPE_INTR ||
2643             _ep->type == DWC_OTG_EP_TYPE_BULK) {
2644                 depctl.b.setd0pid = 1; /* DATA0 */
2645         }
2646
2647         dwc_write_reg32(depctl_addr, depctl.d32);
2648         DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
2649         return;
2650 }
2651
2652 /**
2653  * This function reads a packet from the Rx FIFO into the destination
2654  * buffer.  To read SETUP data use dwc_otg_read_setup_packet.
2655  *
2656  * @param _core_if Programming view of DWC_otg controller.
2657  * @param _dest   Destination buffer for the packet.
2658  * @param _bytes  Number of bytes to copy to the destination.
2659  */
2660 void dwc_otg_read_packet(dwc_otg_core_if_t *_core_if,
2661                          uint8_t *_dest,
2662                          uint16_t _bytes)
2663 {
2664         int i;
2665         int word_count = (_bytes + 3) / 4;
2666
2667         volatile uint32_t *fifo = _core_if->data_fifo[0];
2668         uint32_t *data_buff = (uint32_t *)_dest;
2669
2670         /**
2671          * @todo Account for the case where _dest is not dword aligned. This
2672          * requires reading data from the FIFO into a uint32_t temp buffer,
2673          * then moving it into the data buffer.
2674          */
2675
2676         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
2677                     _core_if, _dest, _bytes);
2678
2679         for (i=0; i<word_count; i++, data_buff++) {
2680                 *data_buff = dwc_read_reg32(fifo);
2681         }
2682
2683         return;
2684 }
2685
2686
2687 #ifdef DEBUG
2688 /**
2689  * This functions reads the device registers and prints them
2690  *
2691  * @param _core_if Programming view of DWC_otg controller.
2692  */
2693 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if)
2694 {
2695         int i;
2696         volatile uint32_t *addr;
2697
2698         DWC_PRINT("Device Global Registers\n");
2699         addr=&_core_if->dev_if->dev_global_regs->dcfg;
2700         DWC_PRINT("DCFG      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2701         addr=&_core_if->dev_if->dev_global_regs->dctl;
2702         DWC_PRINT("DCTL      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2703         addr=&_core_if->dev_if->dev_global_regs->dsts;
2704         DWC_PRINT("DSTS      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2705         addr=&_core_if->dev_if->dev_global_regs->diepmsk;
2706         DWC_PRINT("DIEPMSK   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2707         addr=&_core_if->dev_if->dev_global_regs->doepmsk;
2708         DWC_PRINT("DOEPMSK   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2709         addr=&_core_if->dev_if->dev_global_regs->daint;
2710         DWC_PRINT("DAINT     @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2711         addr=&_core_if->dev_if->dev_global_regs->dtknqr1;
2712         DWC_PRINT("DTKNQR1   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2713         if (_core_if->hwcfg2.b.dev_token_q_depth > 6) {
2714                 addr=&_core_if->dev_if->dev_global_regs->dtknqr2;
2715                 DWC_PRINT("DTKNQR2   @0x%08X : 0x%08X\n",
2716                           (uint32_t)addr,dwc_read_reg32(addr));
2717         }
2718
2719         addr=&_core_if->dev_if->dev_global_regs->dvbusdis;
2720         DWC_PRINT("DVBUSID   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2721
2722         addr=&_core_if->dev_if->dev_global_regs->dvbuspulse;
2723         DWC_PRINT("DVBUSPULSE   @0x%08X : 0x%08X\n",
2724                   (uint32_t)addr,dwc_read_reg32(addr));
2725
2726         if (_core_if->hwcfg2.b.dev_token_q_depth > 14) {
2727                 addr = &_core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
2728                 DWC_PRINT("DTKNQR3   @0x%08X : 0x%08X\n",
2729                           (uint32_t)addr, dwc_read_reg32(addr));
2730         }
2731
2732         if (_core_if->hwcfg2.b.dev_token_q_depth > 22) {
2733                 addr = &_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
2734                 DWC_PRINT("DTKNQR4       @0x%08X : 0x%08X\n", (uint32_t) addr,
2735                            dwc_read_reg32(addr));
2736         }
2737         for (i = 0; i <= _core_if->dev_if->num_in_eps; i++) {
2738                 DWC_PRINT("Device IN EP %d Registers\n", i);
2739                 addr=&_core_if->dev_if->in_ep_regs[i]->diepctl;
2740                 DWC_PRINT("DIEPCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2741                 addr=&_core_if->dev_if->in_ep_regs[i]->diepint;
2742                 DWC_PRINT("DIEPINT   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2743                 addr=&_core_if->dev_if->in_ep_regs[i]->dieptsiz;
2744                 DWC_PRINT("DIETSIZ   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2745                 addr=&_core_if->dev_if->in_ep_regs[i]->diepdma;
2746                 DWC_PRINT("DIEPDMA   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2747
2748 addr = &_core_if->dev_if->in_ep_regs[i]->dtxfsts;
2749                 DWC_PRINT("DTXFSTS       @0x%08X : 0x%08X\n", (uint32_t) addr,
2750                            dwc_read_reg32(addr));
2751         }
2752         for (i = 0; i <= _core_if->dev_if->num_out_eps; i++) {
2753                 DWC_PRINT("Device OUT EP %d Registers\n", i);
2754                 addr=&_core_if->dev_if->out_ep_regs[i]->doepctl;
2755                 DWC_PRINT("DOEPCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2756                 addr=&_core_if->dev_if->out_ep_regs[i]->doepfn;
2757                 DWC_PRINT("DOEPFN    @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2758                 addr=&_core_if->dev_if->out_ep_regs[i]->doepint;
2759                 DWC_PRINT("DOEPINT   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2760                 addr=&_core_if->dev_if->out_ep_regs[i]->doeptsiz;
2761                 DWC_PRINT("DOETSIZ   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2762                 addr=&_core_if->dev_if->out_ep_regs[i]->doepdma;
2763                 DWC_PRINT("DOEPDMA   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2764         }
2765         return;
2766 }
2767
2768 /**
2769  * This function reads the host registers and prints them
2770  *
2771  * @param _core_if Programming view of DWC_otg controller.
2772  */
2773 void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if)
2774 {
2775         int i;
2776         volatile uint32_t *addr;
2777
2778         DWC_PRINT("Host Global Registers\n");
2779         addr=&_core_if->host_if->host_global_regs->hcfg;
2780         DWC_PRINT("HCFG      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2781         addr=&_core_if->host_if->host_global_regs->hfir;
2782         DWC_PRINT("HFIR      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2783         addr=&_core_if->host_if->host_global_regs->hfnum;
2784         DWC_PRINT("HFNUM     @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2785         addr=&_core_if->host_if->host_global_regs->hptxsts;
2786         DWC_PRINT("HPTXSTS   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2787         addr=&_core_if->host_if->host_global_regs->haint;
2788         DWC_PRINT("HAINT     @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2789         addr=&_core_if->host_if->host_global_regs->haintmsk;
2790         DWC_PRINT("HAINTMSK  @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2791         addr=_core_if->host_if->hprt0;
2792         DWC_PRINT("HPRT0     @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2793
2794         for (i=0; i<_core_if->core_params->host_channels; i++) {
2795                 DWC_PRINT("Host Channel %d Specific Registers\n", i);
2796                 addr=&_core_if->host_if->hc_regs[i]->hcchar;
2797                 DWC_PRINT("HCCHAR    @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2798                 addr=&_core_if->host_if->hc_regs[i]->hcsplt;
2799                 DWC_PRINT("HCSPLT    @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2800                 addr=&_core_if->host_if->hc_regs[i]->hcint;
2801                 DWC_PRINT("HCINT     @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2802                 addr=&_core_if->host_if->hc_regs[i]->hcintmsk;
2803                 DWC_PRINT("HCINTMSK  @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2804                 addr=&_core_if->host_if->hc_regs[i]->hctsiz;
2805                 DWC_PRINT("HCTSIZ    @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2806                 addr=&_core_if->host_if->hc_regs[i]->hcdma;
2807                 DWC_PRINT("HCDMA     @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2808
2809         }
2810         return;
2811 }
2812
2813 /**
2814  * This function reads the core global registers and prints them
2815  *
2816  * @param _core_if Programming view of DWC_otg controller.
2817  */
2818 void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if)
2819 {
2820         int i;
2821         volatile uint32_t *addr;
2822
2823         DWC_PRINT("Core Global Registers\n");
2824         addr=&_core_if->core_global_regs->gotgctl;
2825         DWC_PRINT("GOTGCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2826         addr=&_core_if->core_global_regs->gotgint;
2827         DWC_PRINT("GOTGINT   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2828         addr=&_core_if->core_global_regs->gahbcfg;
2829         DWC_PRINT("GAHBCFG   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2830         addr=&_core_if->core_global_regs->gusbcfg;
2831         DWC_PRINT("GUSBCFG   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2832         addr=&_core_if->core_global_regs->grstctl;
2833         DWC_PRINT("GRSTCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2834         addr=&_core_if->core_global_regs->gintsts;
2835         DWC_PRINT("GINTSTS   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2836         addr=&_core_if->core_global_regs->gintmsk;
2837         DWC_PRINT("GINTMSK   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2838         addr=&_core_if->core_global_regs->grxstsr;
2839         DWC_PRINT("GRXSTSR   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2840         //addr=&_core_if->core_global_regs->grxstsp;
2841         //DWC_PRINT("GRXSTSP   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2842         addr=&_core_if->core_global_regs->grxfsiz;
2843         DWC_PRINT("GRXFSIZ   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2844         addr=&_core_if->core_global_regs->gnptxfsiz;
2845         DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2846         addr=&_core_if->core_global_regs->gnptxsts;
2847         DWC_PRINT("GNPTXSTS  @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2848         addr=&_core_if->core_global_regs->gi2cctl;
2849         DWC_PRINT("GI2CCTL   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2850         addr=&_core_if->core_global_regs->gpvndctl;
2851         DWC_PRINT("GPVNDCTL  @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2852         addr=&_core_if->core_global_regs->ggpio;
2853         DWC_PRINT("GGPIO     @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2854         addr=&_core_if->core_global_regs->guid;
2855         DWC_PRINT("GUID      @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2856         addr=&_core_if->core_global_regs->gsnpsid;
2857         DWC_PRINT("GSNPSID   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2858         addr=&_core_if->core_global_regs->ghwcfg1;
2859         DWC_PRINT("GHWCFG1   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2860         addr=&_core_if->core_global_regs->ghwcfg2;
2861         DWC_PRINT("GHWCFG2   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2862         addr=&_core_if->core_global_regs->ghwcfg3;
2863         DWC_PRINT("GHWCFG3   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2864         addr=&_core_if->core_global_regs->ghwcfg4;
2865         DWC_PRINT("GHWCFG4   @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2866         addr=&_core_if->core_global_regs->hptxfsiz;
2867         DWC_PRINT("HPTXFSIZ  @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
2868
2869         for (i=0; i<_core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
2870                 addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
2871                 DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr));
2872         }
2873
2874 }
2875 #endif
2876
2877 /**
2878  * Flush a Tx FIFO.
2879  *
2880  * @param _core_if Programming view of DWC_otg controller.
2881  * @param _num Tx FIFO to flush.
2882  */
2883 extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
2884                                    const int _num )
2885 {
2886         dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
2887         volatile grstctl_t greset = { .d32 = 0};
2888         int count = 0;
2889
2890         DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num);
2891
2892         greset.b.txfflsh = 1;
2893         greset.b.txfnum = _num;
2894         dwc_write_reg32( &global_regs->grstctl, greset.d32 );
2895
2896         do {
2897                 greset.d32 = dwc_read_reg32( &global_regs->grstctl);
2898                 if (++count > 10000){
2899                         DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
2900                                   __func__, greset.d32,
2901                                   dwc_read_reg32( &global_regs->gnptxsts));
2902                         break;
2903                 }
2904
2905                 udelay(1);
2906         } while (greset.b.txfflsh == 1);
2907         /* Wait for 3 PHY Clocks*/
2908         UDELAY(1);
2909 }
2910
2911 /**
2912  * Flush Rx FIFO.
2913  *
2914  * @param _core_if Programming view of DWC_otg controller.
2915  */
2916 extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if )
2917 {
2918         dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
2919         volatile grstctl_t greset = { .d32 = 0};
2920         int count = 0;
2921
2922         DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
2923         /*
2924          *
2925          */
2926         greset.b.rxfflsh = 1;
2927         dwc_write_reg32( &global_regs->grstctl, greset.d32 );
2928
2929         do {
2930                 greset.d32 = dwc_read_reg32( &global_regs->grstctl);
2931                 if (++count > 10000){
2932                         DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
2933                                  greset.d32);
2934                         break;
2935                 }
2936         } while (greset.b.rxfflsh == 1);
2937         /* Wait for 3 PHY Clocks*/
2938         UDELAY(1);
2939 }
2940
2941 /**
2942  * Do core a soft reset of the core.  Be careful with this because it
2943  * resets all the internal state machines of the core.
2944  */
2945
2946 void dwc_otg_core_reset(dwc_otg_core_if_t *_core_if)
2947 {
2948         dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
2949         volatile grstctl_t greset = { .d32 = 0};
2950         int count = 0;
2951
2952         DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
2953         /* Wait for AHB master IDLE state. */
2954         do {
2955                 UDELAY(10);
2956                 greset.d32 = dwc_read_reg32( &global_regs->grstctl);
2957                 if (++count > 100000){
2958                         DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__,
2959                         greset.d32, greset.b.ahbidle);
2960                         return;
2961                 }
2962         } while (greset.b.ahbidle == 0);
2963
2964 // winder add.
2965 #if 1
2966         /* Note: Actually, I don't exactly why we need to put delay here. */
2967         MDELAY(100);
2968 #endif
2969         /* Core Soft Reset */
2970         count = 0;
2971         greset.b.csftrst = 1;
2972         dwc_write_reg32( &global_regs->grstctl, greset.d32 );
2973 // winder add.
2974 #if 1
2975         /* Note: Actually, I don't exactly why we need to put delay here. */
2976         MDELAY(100);
2977 #endif
2978         do {
2979                 greset.d32 = dwc_read_reg32( &global_regs->grstctl);
2980                 if (++count > 10000){
2981                         DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__,
2982                                 greset.d32);
2983                         break;
2984                 }
2985                 udelay(1);
2986         } while (greset.b.csftrst == 1);
2987         /* Wait for 3 PHY Clocks*/
2988         //DWC_PRINT("100ms\n");
2989         MDELAY(100);
2990 }
2991
2992
2993
2994 /**
2995  * Register HCD callbacks.  The callbacks are used to start and stop
2996  * the HCD for interrupt processing.
2997  *
2998  * @param _core_if Programming view of DWC_otg controller.
2999  * @param _cb the HCD callback structure.
3000  * @param _p pointer to be passed to callback function (usb_hcd*).
3001  */
3002 extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
3003                                                 dwc_otg_cil_callbacks_t *_cb,
3004                                                 void *_p)
3005 {
3006         _core_if->hcd_cb = _cb;
3007         _cb->p = _p;
3008 }
3009
3010 /**
3011  * Register PCD callbacks.  The callbacks are used to start and stop
3012  * the PCD for interrupt processing.
3013  *
3014  * @param _core_if Programming view of DWC_otg controller.
3015  * @param _cb the PCD callback structure.
3016  * @param _p pointer to be passed to callback function (pcd*).
3017  */
3018 extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
3019                                                 dwc_otg_cil_callbacks_t *_cb,
3020                                                 void *_p)
3021 {
3022         _core_if->pcd_cb = _cb;
3023         _cb->p = _p;
3024 }
3025