1 #include <linux/init.h>
2 #include <linux/module.h>
3 #include <linux/types.h>
4 #include <linux/string.h>
5 #include <linux/mtd/physmap.h>
6 #include <linux/kernel.h>
7 #include <linux/reboot.h>
8 #include <linux/platform_device.h>
9 #include <linux/leds.h>
10 #include <linux/etherdevice.h>
11 #include <linux/reboot.h>
12 #include <linux/time.h>
14 #include <linux/gpio.h>
15 #include <linux/leds.h>
16 #include <linux/spi/spi.h>
17 #include <linux/mtd/nand.h>
19 #include <asm/bootinfo.h>
31 #include <lantiq_soc.h>
36 void __init svip_register_asc(int port)
41 svip_sys1_clk_enable(SYS1_CLKENR_ASC0);
45 svip_sys1_clk_enable(SYS1_CLKENR_ASC1);
53 static unsigned char svip_ethaddr[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
55 static struct platform_device ltq_mii = {
56 .name = "ifxmips_mii0",
58 .platform_data = svip_ethaddr,
62 static int __init svip_set_ethaddr(char *str)
64 sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
65 &svip_ethaddr[0], &svip_ethaddr[1], &svip_ethaddr[2],
66 &svip_ethaddr[3], &svip_ethaddr[4], &svip_ethaddr[5]);
69 __setup("ethaddr=", svip_set_ethaddr);
71 void __init svip_register_eth(void)
73 if (!is_valid_ether_addr(svip_ethaddr))
74 random_ether_addr(svip_ethaddr);
76 platform_device_register(<q_mii);
77 svip_sys1_clk_enable(SYS1_CLKENR_ETHSW);
80 /* Virtual Ethernet */
81 static struct platform_device ltq_ve = {
82 .name = "ifxmips_svip_ve",
85 void __init svip_register_virtual_eth(void)
87 platform_device_register(<q_ve);
91 static void __init ltq_register_ssc(int bus_num, unsigned long base, int irq_rx,
92 int irq_tx, int irq_err, int irq_frm)
94 struct resource res[] = {
98 .end = base + 0x20 - 1,
99 .flags = IORESOURCE_MEM,
103 .flags = IORESOURCE_IRQ,
107 .flags = IORESOURCE_IRQ,
111 .flags = IORESOURCE_IRQ,
115 .flags = IORESOURCE_IRQ,
119 platform_device_register_simple("ifx_ssc", bus_num, res,
123 static struct spi_board_info bdinfo[] __initdata = {
127 .irq = INT_NUM_IM5_IRL0 + 28,
128 .max_speed_hz = 1000000,
135 .irq = INT_NUM_IM5_IRL0 + 19,
136 .max_speed_hz = 1000000,
142 .mode = SPI_MODE_0 | SPI_LOOP,
144 .max_speed_hz = 10000000,
150 void __init svip_register_spi(void)
153 ltq_register_ssc(0, LTQ_SSC0_BASE, INT_NUM_IM1_IRL0 + 6,
154 INT_NUM_IM1_IRL0 + 7, INT_NUM_IM1_IRL0 + 8,
155 INT_NUM_IM1_IRL0 + 9);
157 ltq_register_ssc(1, LTQ_SSC1_BASE, INT_NUM_IM1_IRL0 + 10,
158 INT_NUM_IM1_IRL0 + 11, INT_NUM_IM1_IRL0 + 12,
159 INT_NUM_IM1_IRL0 + 13);
161 spi_register_board_info(bdinfo, ARRAY_SIZE(bdinfo));
163 svip_sys1_clk_enable(SYS1_CLKENR_SSC0 | SYS1_CLKENR_SSC1);
166 void __init svip_register_spi_flash(struct spi_board_info *bdinfo)
168 spi_register_board_info(bdinfo, 1);
172 static struct platform_device ltq_gpio = {
173 .name = "ifxmips_gpio",
176 static struct platform_device ltq_gpiodev = {
180 void __init svip_register_gpio(void)
182 platform_device_register(<q_gpio);
183 platform_device_register(<q_gpiodev);
187 static struct ltq_mux_settings ltq_mux_settings;
189 static struct platform_device ltq_mux = {
192 .platform_data = <q_mux_settings,
196 void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS],
197 const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS],
198 const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS],
199 const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS],
200 const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS])
202 ltq_mux_settings.mux_p0 = mux_p0;
203 ltq_mux_settings.mux_p1 = mux_p1;
204 ltq_mux_settings.mux_p2 = mux_p2;
205 ltq_mux_settings.mux_p3 = mux_p3;
206 ltq_mux_settings.mux_p4 = mux_p4;
209 svip_sys1_clk_enable(SYS1_CLKENR_PORT0);
212 svip_sys1_clk_enable(SYS1_CLKENR_PORT1);
215 svip_sys1_clk_enable(SYS1_CLKENR_PORT2);
218 svip_sys1_clk_enable(SYS1_CLKENR_PORT3);
221 svip_sys2_clk_enable(SYS2_CLKENR_PORT4);
223 platform_device_register(<q_mux);
227 #define NAND_ADDR_REGION_BASE (LTQ_EBU_SEG1_BASE)
228 #define NAND_CLE_BIT (1 << 3)
229 #define NAND_ALE_BIT (1 << 2)
231 static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE;
233 static int svip_nand_probe(struct platform_device *pdev)
235 ebu_w32(LTQ_EBU_ADDR_SEL_0_BASE_VAL(CPHYSADDR(NAND_ADDR_REGION_BASE)
237 | LTQ_EBU_ADDR_SEL_0_MASK_VAL(15)
238 | LTQ_EBU_ADDR_SEL_0_MRME_VAL(0)
239 | LTQ_EBU_ADDR_SEL_0_REGEN_VAL(1),
242 ebu_w32(LTQ_EBU_CON_0_WRDIS_VAL(0)
243 | LTQ_EBU_CON_0_ADSWP_VAL(1)
244 | LTQ_EBU_CON_0_AGEN_VAL(0x00)
245 | LTQ_EBU_CON_0_SETUP_VAL(1)
246 | LTQ_EBU_CON_0_WAIT_VAL(0x00)
247 | LTQ_EBU_CON_0_WINV_VAL(0)
248 | LTQ_EBU_CON_0_PW_VAL(0x00)
249 | LTQ_EBU_CON_0_ALEC_VAL(0)
250 | LTQ_EBU_CON_0_BCGEN_VAL(0x01)
251 | LTQ_EBU_CON_0_WAITWRC_VAL(1)
252 | LTQ_EBU_CON_0_WAITRDC_VAL(1)
253 | LTQ_EBU_CON_0_HOLDC_VAL(1)
254 | LTQ_EBU_CON_0_RECOVC_VAL(0)
255 | LTQ_EBU_CON_0_CMULT_VAL(0x01),
260 * CLE, ALE and CS are pulse, all other signal are latches based
261 * CLE and ALE are active high, PRE, WP, SE and CS/CE are active low
262 * OUT_CS_S is disabled
263 * NAND mode is disabled
265 ebu_w32(LTQ_EBU_NAND_CON_ECC_ON_VAL(0)
266 | LTQ_EBU_NAND_CON_LAT_EN_VAL(0x38)
267 | LTQ_EBU_NAND_CON_OUT_CS_S_VAL(0)
268 | LTQ_EBU_NAND_CON_IN_CS_S_VAL(0)
269 | LTQ_EBU_NAND_CON_PRE_P_VAL(1)
270 | LTQ_EBU_NAND_CON_WP_P_VAL(1)
271 | LTQ_EBU_NAND_CON_SE_P_VAL(1)
272 | LTQ_EBU_NAND_CON_CS_P_VAL(1)
273 | LTQ_EBU_NAND_CON_CLE_P_VAL(0)
274 | LTQ_EBU_NAND_CON_ALE_P_VAL(0)
275 | LTQ_EBU_NAND_CON_CSMUX_E_VAL(0)
276 | LTQ_EBU_NAND_CON_NANDMODE_VAL(0),
282 static void svip_nand_hwcontrol(struct mtd_info *mtd, int cmd,
285 struct nand_chip *this = mtd->priv;
287 if (ctrl & NAND_CTRL_CHANGE) {
289 /* Coming here means to change either the enable state or
290 * the address for controlling ALE or CLE */
292 /* NAND_NCE: Select the chip by setting nCE to low.
293 * This is done in CON register */
295 ebu_w32_mask(0, LTQ_EBU_NAND_CON_NANDMODE_VAL(1),
298 ebu_w32_mask(LTQ_EBU_NAND_CON_NANDMODE_VAL(1),
301 /* The addressing of CLE or ALE is done via different addresses.
302 We are now changing the address depending on the given action
303 SVIPs NAND_CLE_BIT = (1 << 3), NAND_CLE = 0x02
304 NAND_ALE_BIT = (1 << 2) = NAND_ALE (0x04) */
305 adr = (unsigned long)this->IO_ADDR_W;
306 adr &= ~(NAND_CLE_BIT | NAND_ALE_BIT);
307 adr |= (ctrl & NAND_CLE) << 2 | (ctrl & NAND_ALE);
308 this->IO_ADDR_W = (void __iomem *)adr;
311 if (cmd != NAND_CMD_NONE)
312 writeb(cmd, this->IO_ADDR_W);
315 static int svip_nand_ready(struct mtd_info *mtd)
317 return (ebu_r32(nand_wait) & 0x01) == 0x01;
320 static inline void svip_nand_wait(void)
322 static const int nops = 150;
325 for (i = 0; i < nops; i++)
329 static void svip_nand_write_buf(struct mtd_info *mtd,
330 const u_char *buf, int len)
333 struct nand_chip *this = mtd->priv;
335 for (i = 0; i < len; i++) {
336 writeb(buf[i], this->IO_ADDR_W);
341 static void svip_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
344 struct nand_chip *this = mtd->priv;
346 for (i = 0; i < len; i++) {
347 buf[i] = readb(this->IO_ADDR_R);
352 static const char *part_probes[] = { "cmdlinepart", NULL };
354 static struct platform_nand_data svip_flash_nand_data = {
357 .part_probe_types = part_probes,
360 .probe = svip_nand_probe,
361 .cmd_ctrl = svip_nand_hwcontrol,
362 .dev_ready = svip_nand_ready,
363 .write_buf = svip_nand_write_buf,
364 .read_buf = svip_nand_read_buf,
368 static struct resource svip_nand_resources[] = {
369 MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX),
372 static struct platform_device svip_flash_nand = {
375 .num_resources = ARRAY_SIZE(svip_nand_resources),
376 .resource = svip_nand_resources,
378 .platform_data = &svip_flash_nand_data,
382 void __init svip_register_nand(void)
384 platform_device_register(&svip_flash_nand);