target/linux/kirkwood/patches-3.10/0011-arm-kirkwood-add-SoC-level-Device-Tree-data-for-PCIe.patch

   1 From b2198f4cd8cffdfd5030a176a9ee4d4367526cac Mon Sep 17 00:00:00 2001
   2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   3 Date: Wed, 15 May 2013 15:36:56 +0200
   4 Subject: [PATCH 11/29] arm: kirkwood: add SoC-level Device Tree data for PCIe
   5  interfaces
   6
   7 This commit adds Device Tree details to enable the PCIe interfaces on
   8 Kirkwood. The 6281 has one PCIe interface, the 6282 has two PCIe
   9 interfaces.
  10
  11 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  12 Tested-by: Andrew Lunn <andrew@lunn.ch>
  13 Signed-off-by: Jason Cooper <jason@lakedaemon.net>
  14 ---
  15  arch/arm/boot/dts/kirkwood-6281.dtsi | 31 +++++++++++++++++++++++
  16  arch/arm/boot/dts/kirkwood-6282.dtsi | 48 ++++++++++++++++++++++++++++++++++++
  17  arch/arm/boot/dts/kirkwood.dtsi      |  1 +
  18  3 files changed, 80 insertions(+)
  19
  20 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi
  21 +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
  22 @@ -40,5 +40,36 @@
  23                                 marvell,function = "sdio";
  24                         };
  25                 };
  26 +
  27 +               pcie-controller {
  28 +                       compatible = "marvell,kirkwood-pcie";
  29 +                       status = "disabled";
  30 +                       device_type = "pci";
  31 +
  32 +                       #address-cells = <3>;
  33 +                       #size-cells = <2>;
  34 +
  35 +                       bus-range = <0x00 0xff>;
  36 +
  37 +                       ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
  38 +                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
  39 +                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
  40 +
  41 +                       pcie@1,0 {
  42 +                               device_type = "pci";
  43 +                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
  44 +                               reg = <0x0800 0 0 0 0>;
  45 +                               #address-cells = <3>;
  46 +                               #size-cells = <2>;
  47 +                               #interrupt-cells = <1>;
  48 +                               ranges;
  49 +                               interrupt-map-mask = <0 0 0 0>;
  50 +                               interrupt-map = <0 0 0 0 &intc 9>;
  51 +                               marvell,pcie-port = <0>;
  52 +                               marvell,pcie-lane = <0>;
  53 +                               clocks = <&gate_clk 2>;
  54 +                               status = "disabled";
  55 +                       };
  56 +               };
  57         };
  58  };
  59 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi
  60 +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
  61 @@ -65,5 +65,53 @@
  62                         clocks = <&gate_clk 7>;
  63                         status = "disabled";
  64                 };
  65 +
  66 +               pcie-controller {
  67 +                       compatible = "marvell,kirkwood-pcie";
  68 +                       status = "disabled";
  69 +                       device_type = "pci";
  70 +
  71 +                       #address-cells = <3>;
  72 +                       #size-cells = <2>;
  73 +
  74 +                       bus-range = <0x00 0xff>;
  75 +
  76 +                       ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
  77 +                                 0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
  78 +                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
  79 +                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
  80 +
  81 +                       pcie@1,0 {
  82 +                               device_type = "pci";
  83 +                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
  84 +                               reg = <0x0800 0 0 0 0>;
  85 +                               #address-cells = <3>;
  86 +                               #size-cells = <2>;
  87 +                               #interrupt-cells = <1>;
  88 +                               ranges;
  89 +                               interrupt-map-mask = <0 0 0 0>;
  90 +                               interrupt-map = <0 0 0 0 &intc 9>;
  91 +                               marvell,pcie-port = <0>;
  92 +                               marvell,pcie-lane = <0>;
  93 +                               clocks = <&gate_clk 2>;
  94 +                               status = "disabled";
  95 +                       };
  96 +
  97 +                       pcie@2,0 {
  98 +                               device_type = "pci";
  99 +                               assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
 100 +                               reg = <0x1000 0 0 0 0>;
 101 +                               #address-cells = <3>;
 102 +                               #size-cells = <2>;
 103 +                               #interrupt-cells = <1>;
 104 +                               ranges;
 105 +                               interrupt-map-mask = <0 0 0 0>;
 106 +                               interrupt-map = <0 0 0 0 &intc 10>;
 107 +                               marvell,pcie-port = <1>;
 108 +                               marvell,pcie-lane = <0>;
 109 +                               clocks = <&gate_clk 18>;
 110 +                               status = "disabled";
 111 +                       };
 112 +               };
 113         };
 114  };
 115 --- a/arch/arm/boot/dts/kirkwood.dtsi
 116 +++ b/arch/arm/boot/dts/kirkwood.dtsi
 117 @@ -19,6 +19,7 @@
 118         ocp@f1000000 {
 119                 compatible = "simple-bus";
 120                 ranges = <0x00000000 0xf1000000 0x4000000
 121 +                         0xe0000000 0xe0000000 0x8100000 /* PCIE */
 122                           0xf5000000 0xf5000000 0x0000400>;
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;