target/linux/ixp4xx/patches-3.10/190-cambria_support.patch

   1 --- a/arch/arm/mach-ixp4xx/Kconfig
   2 +++ b/arch/arm/mach-ixp4xx/Kconfig
   3 @@ -25,6 +25,14 @@ config MACH_AVILA
   4           Avila Network Platform. For more information on this platform,
   5           see <file:Documentation/arm/IXP4xx>.
   6
   7 +config MACH_CAMBRIA
   8 +       bool "Cambria"
   9 +       select PCI
  10 +       help
  11 +         Say 'Y' here if you want your kernel to support the Gateworks
  12 +         Cambria series. For more information on this platform,
  13 +         see <file:Documentation/arm/IXP4xx>.
  14 +
  15  config MACH_LOFT
  16      bool "Loft"
  17      depends on MACH_AVILA
  18 @@ -222,7 +230,7 @@ config CPU_IXP46X
  19
  20  config CPU_IXP43X
  21         bool
  22 -       depends on MACH_KIXRP435
  23 +       depends on MACH_KIXRP435 || MACH_CAMBRIA
  24         default y
  25
  26  config MACH_GTWX5715
  27 --- a/arch/arm/mach-ixp4xx/Makefile
  28 +++ b/arch/arm/mach-ixp4xx/Makefile
  29 @@ -7,6 +7,7 @@ obj-pci-n       :=
  30
  31  obj-pci-$(CONFIG_ARCH_IXDP4XX)         += ixdp425-pci.o
  32  obj-pci-$(CONFIG_MACH_AVILA)           += avila-pci.o
  33 +obj-pci-$(CONFIG_MACH_CAMBRIA)         += cambria-pci.o
  34  obj-pci-$(CONFIG_MACH_IXDPG425)                += ixdpg425-pci.o
  35  obj-pci-$(CONFIG_ARCH_ADI_COYOTE)      += coyote-pci.o
  36  obj-pci-$(CONFIG_MACH_GTWX5715)                += gtwx5715-pci.o
  37 @@ -31,6 +32,7 @@ obj-y += common.o
  38
  39  obj-$(CONFIG_ARCH_IXDP4XX)     += ixdp425-setup.o
  40  obj-$(CONFIG_MACH_AVILA)       += avila-setup.o
  41 +obj-$(CONFIG_MACH_CAMBRIA)     += cambria-setup.o
  42  obj-$(CONFIG_MACH_IXDPG425)    += coyote-setup.o
  43  obj-$(CONFIG_ARCH_ADI_COYOTE)  += coyote-setup.o
  44  obj-$(CONFIG_MACH_GTWX5715)    += gtwx5715-setup.o
  45 --- /dev/null
  46 +++ b/arch/arm/mach-ixp4xx/cambria-pci.c
  47 @@ -0,0 +1,78 @@
  48 +/*
  49 + * arch/arch/mach-ixp4xx/cambria-pci.c
  50 + *
  51 + * PCI setup routines for Gateworks Cambria series
  52 + *
  53 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  54 + *
  55 + * based on coyote-pci.c:
  56 + *     Copyright (C) 2002 Jungo Software Technologies.
  57 + *     Copyright (C) 2003 MontaVista Softwrae, Inc.
  58 + *
  59 + * Maintainer: Imre Kaloz <kaloz@openwrt.org>
  60 + *
  61 + * This program is free software; you can redistribute it and/or modify
  62 + * it under the terms of the GNU General Public License version 2 as
  63 + * published by the Free Software Foundation.
  64 + *
  65 + */
  66 +
  67 +#include <linux/kernel.h>
  68 +#include <linux/pci.h>
  69 +#include <linux/init.h>
  70 +#include <linux/irq.h>
  71 +
  72 +#include <asm/mach-types.h>
  73 +#include <mach/hardware.h>
  74 +#include <asm/irq.h>
  75 +
  76 +#include <asm/mach/pci.h>
  77 +
  78 +extern void ixp4xx_pci_preinit(void);
  79 +extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
  80 +extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
  81 +
  82 +void __init cambria_pci_preinit(void)
  83 +{
  84 +       irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
  85 +       irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
  86 +       irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
  87 +       irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
  88 +
  89 +       ixp4xx_pci_preinit();
  90 +}
  91 +
  92 +static int __init cambria_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  93 +{
  94 +       if (slot == 1)
  95 +               return IRQ_IXP4XX_GPIO11;
  96 +       else if (slot == 2)
  97 +               return IRQ_IXP4XX_GPIO10;
  98 +       else if (slot == 3)
  99 +               return IRQ_IXP4XX_GPIO9;
 100 +       else if (slot == 4)
 101 +               return IRQ_IXP4XX_GPIO8;
 102 +       else if (slot == 6)
 103 +               return IRQ_IXP4XX_GPIO10;
 104 +       else if (slot == 15)
 105 +               return IRQ_IXP4XX_GPIO8;
 106 +
 107 +       else return -1;
 108 +}
 109 +
 110 +struct hw_pci cambria_pci __initdata = {
 111 +       .nr_controllers = 1,
 112 +       .preinit =        cambria_pci_preinit,
 113 +       .ops =            &ixp4xx_ops,
 114 +       .setup =          ixp4xx_setup,
 115 +       .map_irq =        cambria_map_irq,
 116 +};
 117 +
 118 +int __init cambria_pci_init(void)
 119 +{
 120 +       if (machine_is_cambria())
 121 +               pci_common_init(&cambria_pci);
 122 +       return 0;
 123 +}
 124 +
 125 +subsys_initcall(cambria_pci_init);
 126 --- /dev/null
 127 +++ b/arch/arm/mach-ixp4xx/cambria-setup.c
 128 @@ -0,0 +1,993 @@
 129 +/*
 130 + * arch/arm/mach-ixp4xx/cambria-setup.c
 131 + *
 132 + * Board setup for the Gateworks Cambria series
 133 + *
 134 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 135 + * Copyright (C) 2012 Gateworks Corporation <support@gateworks.com>
 136 + *
 137 + * based on coyote-setup.c:
 138 + *      Copyright (C) 2003-2005 MontaVista Software, Inc.
 139 + *
 140 + * Author: Imre Kaloz <kaloz@openwrt.org>
 141 + *         Tim Harvey <tharvey@gateworks.com>
 142 + */
 143 +
 144 +#include <linux/device.h>
 145 +#include <linux/gpio_keys.h>
 146 +#include <linux/gpio.h>
 147 +#include <linux/i2c.h>
 148 +#include <linux/i2c-gpio.h>
 149 +#include <linux/i2c/at24.h>
 150 +#include <linux/i2c/gw_i2c_pld.h>
 151 +#include <linux/i2c/pca953x.h>
 152 +#include <linux/if_ether.h>
 153 +#include <linux/init.h>
 154 +#include <linux/input.h>
 155 +#include <linux/kernel.h>
 156 +#include <linux/leds.h>
 157 +#include <linux/memory.h>
 158 +#include <linux/netdevice.h>
 159 +#include <linux/serial.h>
 160 +#include <linux/serial_8250.h>
 161 +#include <linux/slab.h>
 162 +#include <linux/socket.h>
 163 +#include <linux/types.h>
 164 +#include <linux/tty.h>
 165 +#include <linux/irq.h>
 166 +
 167 +#include <mach/hardware.h>
 168 +#include <asm/irq.h>
 169 +#include <asm/mach-types.h>
 170 +#include <asm/mach/arch.h>
 171 +#include <asm/mach/flash.h>
 172 +#include <asm/setup.h>
 173 +
 174 +#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 175 +
 176 +struct cambria_board_info {
 177 +       unsigned char   *model;
 178 +       void            (*setup)(void);
 179 +};
 180 +
 181 +static struct cambria_board_info *cambria_info __initdata;
 182 +
 183 +static struct flash_platform_data cambria_flash_data = {
 184 +       .map_name       = "cfi_probe",
 185 +       .width          = 2,
 186 +};
 187 +
 188 +static struct resource cambria_flash_resource = {
 189 +       .flags          = IORESOURCE_MEM,
 190 +};
 191 +
 192 +static struct platform_device cambria_flash = {
 193 +       .name           = "IXP4XX-Flash",
 194 +       .id             = 0,
 195 +       .dev            = {
 196 +               .platform_data = &cambria_flash_data,
 197 +       },
 198 +       .num_resources  = 1,
 199 +       .resource       = &cambria_flash_resource,
 200 +};
 201 +
 202 +static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
 203 +       .sda_pin        = 7,
 204 +       .scl_pin        = 6,
 205 +};
 206 +
 207 +static struct platform_device cambria_i2c_gpio = {
 208 +       .name           = "i2c-gpio",
 209 +       .id             = 0,
 210 +       .dev = {
 211 +               .platform_data  = &cambria_i2c_gpio_data,
 212 +       },
 213 +};
 214 +
 215 +#ifdef SFP_SERIALID
 216 +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpa_data = {
 217 +       .sda_pin        = 113,
 218 +       .scl_pin        = 112,
 219 +       .sda_is_open_drain = 0,
 220 +       .scl_is_open_drain = 0,
 221 +};
 222 +
 223 +static struct platform_device cambria_i2c_gpio_sfpa = {
 224 +       .name           = "i2c-gpio",
 225 +       .id             = 1,
 226 +       .dev = {
 227 +               .platform_data  = &cambria_i2c_gpio_sfpa_data,
 228 +       },
 229 +};
 230 +
 231 +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpb_data = {
 232 +       .sda_pin        = 115,
 233 +       .scl_pin        = 114,
 234 +       .sda_is_open_drain = 0,
 235 +       .scl_is_open_drain = 0,
 236 +};
 237 +
 238 +static struct platform_device cambria_i2c_gpio_sfpb = {
 239 +       .name           = "i2c-gpio",
 240 +       .id             = 2,
 241 +       .dev = {
 242 +               .platform_data  = &cambria_i2c_gpio_sfpb_data,
 243 +       },
 244 +};
 245 +#endif // #ifdef SFP_SERIALID
 246 +
 247 +static struct eth_plat_info cambria_npec_data = {
 248 +       .phy            = 1,
 249 +       .rxq            = 4,
 250 +       .txreadyq       = 21,
 251 +};
 252 +
 253 +static struct eth_plat_info cambria_npea_data = {
 254 +       .phy            = 2,
 255 +       .rxq            = 2,
 256 +       .txreadyq       = 19,
 257 +};
 258 +
 259 +static struct platform_device cambria_npec_device = {
 260 +       .name                   = "ixp4xx_eth",
 261 +       .id                     = IXP4XX_ETH_NPEC,
 262 +       .dev.platform_data      = &cambria_npec_data,
 263 +       .dev.coherent_dma_mask  = DMA_BIT_MASK(32),
 264 +};
 265 +
 266 +static struct platform_device cambria_npea_device = {
 267 +       .name                   = "ixp4xx_eth",
 268 +       .id                     = IXP4XX_ETH_NPEA,
 269 +       .dev.platform_data      = &cambria_npea_data,
 270 +       .dev.coherent_dma_mask  = DMA_BIT_MASK(32),
 271 +};
 272 +
 273 +static struct resource cambria_uart_resource = {
 274 +       .start  = IXP4XX_UART1_BASE_PHYS,
 275 +       .end    = IXP4XX_UART1_BASE_PHYS + 0x0fff,
 276 +       .flags  = IORESOURCE_MEM,
 277 +};
 278 +
 279 +static struct plat_serial8250_port cambria_uart_data[] = {
 280 +       {
 281 +               .mapbase        = IXP4XX_UART1_BASE_PHYS,
 282 +               .membase        = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
 283 +               .irq            = IRQ_IXP4XX_UART1,
 284 +               .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 285 +               .iotype         = UPIO_MEM,
 286 +               .regshift       = 2,
 287 +               .uartclk        = IXP4XX_UART_XTAL,
 288 +       },
 289 +       { },
 290 +};
 291 +
 292 +static struct platform_device cambria_uart = {
 293 +       .name           = "serial8250",
 294 +       .id             = PLAT8250_DEV_PLATFORM,
 295 +       .dev = {
 296 +               .platform_data  = cambria_uart_data,
 297 +       },
 298 +       .num_resources  = 1,
 299 +       .resource       = &cambria_uart_resource,
 300 +};
 301 +
 302 +static struct resource cambria_optional_uart_resources[] = {
 303 +       {
 304 +               .start  = 0x52000000,
 305 +               .end    = 0x52000fff,
 306 +               .flags  = IORESOURCE_MEM
 307 +       },
 308 +       {
 309 +               .start  = 0x53000000,
 310 +               .end    = 0x53000fff,
 311 +               .flags  = IORESOURCE_MEM
 312 +       },
 313 +       {
 314 +               .start  = 0x52000000,
 315 +               .end    = 0x52000fff,
 316 +               .flags  = IORESOURCE_MEM
 317 +       },
 318 +       {
 319 +               .start  = 0x52000000,
 320 +               .end    = 0x52000fff,
 321 +               .flags  = IORESOURCE_MEM
 322 +       },
 323 +       {
 324 +               .start  = 0x52000000,
 325 +               .end    = 0x52000fff,
 326 +               .flags  = IORESOURCE_MEM
 327 +       },
 328 +       {
 329 +               .start  = 0x52000000,
 330 +               .end    = 0x52000fff,
 331 +               .flags  = IORESOURCE_MEM
 332 +       },
 333 +       {
 334 +               .start  = 0x52000000,
 335 +               .end    = 0x52000fff,
 336 +               .flags  = IORESOURCE_MEM
 337 +       },
 338 +       {
 339 +               .start  = 0x53000000,
 340 +               .end    = 0x53000fff,
 341 +               .flags  = IORESOURCE_MEM
 342 +       }
 343 +};
 344 +
 345 +static struct plat_serial8250_port cambria_optional_uart_data[] = {
 346 +       {
 347 +               .flags          = UPF_BOOT_AUTOCONF,
 348 +               .iotype         = UPIO_MEM_DELAY,
 349 +               .regshift       = 0,
 350 +               .uartclk        = 1843200,
 351 +               .rw_delay       = 10,
 352 +       },
 353 +       {
 354 +               .flags          = UPF_BOOT_AUTOCONF,
 355 +               .iotype         = UPIO_MEM_DELAY,
 356 +               .regshift       = 0,
 357 +               .uartclk        = 1843200,
 358 +               .rw_delay       = 10,
 359 +       },
 360 +       {
 361 +               .flags          = UPF_BOOT_AUTOCONF,
 362 +               .iotype         = UPIO_MEM,
 363 +               .regshift       = 0,
 364 +               .uartclk        = 18432000,
 365 +       },
 366 +       {
 367 +               .flags          = UPF_BOOT_AUTOCONF,
 368 +               .iotype         = UPIO_MEM,
 369 +               .regshift       = 0,
 370 +               .uartclk        = 18432000,
 371 +       },
 372 +       {
 373 +               .flags          = UPF_BOOT_AUTOCONF,
 374 +               .iotype         = UPIO_MEM,
 375 +               .regshift       = 0,
 376 +               .uartclk        = 18432000,
 377 +       },
 378 +       {
 379 +               .flags          = UPF_BOOT_AUTOCONF,
 380 +               .iotype         = UPIO_MEM,
 381 +               .regshift       = 0,
 382 +               .uartclk        = 18432000,
 383 +       },
 384 +       {
 385 +               .flags          = UPF_BOOT_AUTOCONF,
 386 +               .iotype         = UPIO_MEM,
 387 +               .regshift       = 0,
 388 +               .uartclk        = 18432000,
 389 +       },
 390 +  { },
 391 +};
 392 +
 393 +static struct platform_device cambria_optional_uart = {
 394 +       .name           = "serial8250",
 395 +       .id             = PLAT8250_DEV_PLATFORM1,
 396 +       .dev.platform_data      = cambria_optional_uart_data,
 397 +       .num_resources  = 2,
 398 +       .resource       = cambria_optional_uart_resources,
 399 +};
 400 +
 401 +static struct resource cambria_pata_resources[] = {
 402 +       {
 403 +               .flags  = IORESOURCE_MEM
 404 +       },
 405 +       {
 406 +               .flags  = IORESOURCE_MEM,
 407 +       },
 408 +       {
 409 +               .name   = "intrq",
 410 +               .start  = IRQ_IXP4XX_GPIO12,
 411 +               .end    = IRQ_IXP4XX_GPIO12,
 412 +               .flags  = IORESOURCE_IRQ,
 413 +       },
 414 +};
 415 +
 416 +static struct ixp4xx_pata_data cambria_pata_data = {
 417 +       .cs0_bits       = 0xbfff3c03,
 418 +       .cs1_bits       = 0xbfff3c03,
 419 +};
 420 +
 421 +static struct platform_device cambria_pata = {
 422 +       .name                   = "pata_ixp4xx_cf",
 423 +       .id                     = 0,
 424 +       .dev.platform_data      = &cambria_pata_data,
 425 +       .num_resources          = ARRAY_SIZE(cambria_pata_resources),
 426 +       .resource               = cambria_pata_resources,
 427 +};
 428 +
 429 +static struct gpio_led cambria_gpio_leds[] = {
 430 +       {
 431 +               .name           = "user",
 432 +               .gpio           = 5,
 433 +               .active_low     = 1,
 434 +       },
 435 +       {
 436 +               .name           = "user2",
 437 +               .gpio           = 0,
 438 +               .active_low     = 1,
 439 +       },
 440 +       {
 441 +               .name           = "user3",
 442 +               .gpio           = 0,
 443 +               .active_low     = 1,
 444 +       },
 445 +       {
 446 +               .name           = "user4",
 447 +               .gpio           = 0,
 448 +               .active_low     = 1,
 449 +       }
 450 +};
 451 +
 452 +static struct gpio_led_platform_data cambria_gpio_leds_data = {
 453 +       .num_leds       = 1,
 454 +       .leds           = cambria_gpio_leds,
 455 +};
 456 +
 457 +static struct platform_device cambria_gpio_leds_device = {
 458 +       .name           = "leds-gpio",
 459 +       .id             = -1,
 460 +       .dev.platform_data = &cambria_gpio_leds_data,
 461 +};
 462 +
 463 +static struct resource cambria_gpio_resources[] = {
 464 +       {
 465 +               .name = "gpio",
 466 +               .flags  = 0,
 467 +       },
 468 +};
 469 +
 470 +static struct gpio cambria_gpios_gw2350[] = {
 471 +       // ARM GPIO
 472 +#if 0 // configured from bootloader
 473 +       {  0, GPIOF_IN,            "ARM_DIO0" },
 474 +       {  1, GPIOF_IN,            "ARM_DIO1" },
 475 +       {  2, GPIOF_IN,            "ARM_DIO2" },
 476 +       {  3, GPIOF_IN,            "ARM_DIO3" },
 477 +       {  4, GPIOF_IN,            "ARM_DIO4" },
 478 +       {  5, GPIOF_IN,            "ARM_DIO5" },
 479 +       { 12, GPIOF_OUT_INIT_HIGH, "WDOGEN#" },
 480 +#endif
 481 +       {  8, GPIOF_IN,            "ARM_DIO8" },
 482 +       {  9, GPIOF_IN,            "ARM_DIO9" },
 483 +};
 484 +
 485 +static struct gpio cambria_gpios_gw2358[] = {
 486 +       // ARM GPIO
 487 +#if 0 // configured from bootloader
 488 +       {  0, GPIOF_IN,            "*VINLOW#" },
 489 +       {  2, GPIOF_IN,            "*GPS_PPS" },
 490 +       {  3, GPIOF_IN,            "*GPS_IRQ#" },
 491 +       {  4, GPIOF_IN,            "*RS485_IRQ#" },
 492 +       {  5, GPIOF_IN,            "*SER_EN#" },
 493 +       { 14, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" },
 494 +#endif
 495 +};
 496 +
 497 +static struct gpio cambria_gpios_gw2359[] = {
 498 +       // ARM GPIO
 499 +#if 0 // configured from bootloader
 500 +       {  0, GPIOF_IN,            "*PCA_IRQ#" },
 501 +       {  1, GPIOF_IN,            "ARM_DIO1" },
 502 +       {  2, GPIOF_IN,            "ARM_DIO2" },
 503 +       {  3, GPIOF_IN,            "ARM_DIO3" },
 504 +       {  4, GPIOF_IN,            "ARM_DIO4" },
 505 +       {  5, GPIOF_IN,            "ARM_DIO5" },
 506 +       {  8, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" },
 507 +#endif
 508 +       { 11, GPIOF_OUT_INIT_HIGH, "*SER_EN"   },       // console serial enable
 509 +       { 12, GPIOF_IN,            "*GSC_IRQ#" },
 510 +       { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"},
 511 +       // GSC GPIO
 512 +#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
 513 +       {100, GPIOF_IN,            "*USER_PB#" },
 514 +#endif
 515 +       {103, GPIOF_OUT_INIT_HIGH, "*5V_EN" },         // 5V aux supply enable
 516 +       {108, GPIOF_IN,            "*SMUXDA0" },
 517 +       {109, GPIOF_IN,            "*SMUXDA1" },
 518 +       {110, GPIOF_IN,            "*SMUXDA2" },
 519 +       {111, GPIOF_IN,            "*SMUXDB0" },
 520 +       {112, GPIOF_IN,            "*SMUXDB1" },
 521 +       {113, GPIOF_IN,            "*SMUXDB2" },
 522 +       // PCA GPIO
 523 +       {118, GPIOF_IN,            "*USIM2_DET#"},     // USIM2 Detect
 524 +       {120, GPIOF_OUT_INIT_LOW,  "*USB1_PCI_SEL"},   // USB1  Select (1=PCI, 0=FP)
 525 +       {121, GPIOF_OUT_INIT_LOW,  "*USB2_PCI_SEL"},   // USB2  Select (1=PCI, 0=FP)
 526 +       {122, GPIOF_IN,            "*USIM1_DET#"},     // USIM1 Detect
 527 +       {123, GPIOF_OUT_INIT_HIGH, "*COM1_DTR#" },     // J21/J10
 528 +       {124, GPIOF_IN,            "*COM1_DSR#" },     // J21/J10
 529 +       {127, GPIOF_IN,            "PCA_DIO0" },
 530 +       {128, GPIOF_IN,            "PCA_DIO1" },
 531 +       {129, GPIOF_IN,            "PCA_DIO2" },
 532 +       {130, GPIOF_IN,            "PCA_DIO3" },
 533 +       {131, GPIOF_IN,            "PCA_DIO4" },
 534 +};
 535 +
 536 +static struct gpio cambria_gpios_gw2360[] = {
 537 +       // ARM GPIO
 538 +       {  0, GPIOF_IN,            "*PCA_IRQ#" },
 539 +       { 11, GPIOF_OUT_INIT_LOW, "*SER0_EN#" },
 540 +       { 12, GPIOF_IN,            "*GSC_IRQ#" },
 541 +       { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"},
 542 +       // GSC GPIO
 543 +#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
 544 +       {100, GPIOF_IN,            "*USER_PB#" },
 545 +#endif
 546 +       {108, GPIOF_OUT_INIT_LOW,  "*ENET1_EN#" },     // ENET1 TX Enable
 547 +       {109, GPIOF_IN,            "*ENET1_PRES#" },   // ENET1 Detect (0=SFP present)
 548 +       {110, GPIOF_OUT_INIT_LOW,  "*ENET2_EN#" },     // ENET2 TX Enable
 549 +       {111, GPIOF_IN,            "*ENET2_PRES#"},    // ENET2 Detect (0=SFP present)
 550 +       // PCA GPIO
 551 +       {116, GPIOF_OUT_INIT_HIGH, "*USIM2_LOC"},      // USIM2 Select (1=Loc, 0=Rem)
 552 +       {117, GPIOF_IN,            "*USIM2_DET_LOC#" },// USIM2 Detect (Local Slot)
 553 +       {118, GPIOF_IN,            "*USIM2_DET_REM#" },// USIM2 Detect (Remote Slot)
 554 +       {120, GPIOF_OUT_INIT_LOW,  "*USB1_PCI_SEL"},   // USB1  Select (1=PCIe1, 0=J1)
 555 +       {121, GPIOF_OUT_INIT_LOW,  "*USB2_PCI_SEL"},   // USB2  Select (1=PCIe2, 0=J1)
 556 +       {122, GPIOF_IN,            "*USIM1_DET#"},     // USIM1 Detect
 557 +       {127, GPIOF_IN,            "DIO0" },
 558 +       {128, GPIOF_IN,            "DIO1" },
 559 +       {129, GPIOF_IN,            "DIO2" },
 560 +       {130, GPIOF_IN,            "DIO3" },
 561 +       {131, GPIOF_IN,            "DIO4" },
 562 +};
 563 +
 564 +static struct latch_led cambria_latch_leds[] = {
 565 +       {
 566 +               .name   = "ledA",  /* green led */
 567 +               .bit    = 0,
 568 +       },
 569 +       {
 570 +               .name   = "ledB",  /* green led */
 571 +               .bit    = 1,
 572 +       },
 573 +       {
 574 +               .name   = "ledC",  /* green led */
 575 +               .bit    = 2,
 576 +       },
 577 +       {
 578 +               .name   = "ledD",  /* green led */
 579 +               .bit    = 3,
 580 +       },
 581 +       {
 582 +               .name   = "ledE",  /* green led */
 583 +               .bit    = 4,
 584 +       },
 585 +       {
 586 +               .name   = "ledF",  /* green led */
 587 +               .bit    = 5,
 588 +       },
 589 +       {
 590 +               .name   = "ledG",  /* green led */
 591 +               .bit    = 6,
 592 +       },
 593 +       {
 594 +               .name   = "ledH",  /* green led */
 595 +               .bit    = 7,
 596 +       }
 597 +};
 598 +
 599 +static struct latch_led_platform_data cambria_latch_leds_data = {
 600 +       .num_leds       = 8,
 601 +       .leds           = cambria_latch_leds,
 602 +       .mem            = 0x53F40000,
 603 +};
 604 +
 605 +static struct platform_device cambria_latch_leds_device = {
 606 +       .name           = "leds-latch",
 607 +       .id             = -1,
 608 +       .dev.platform_data = &cambria_latch_leds_data,
 609 +};
 610 +
 611 +static struct resource cambria_usb0_resources[] = {
 612 +       {
 613 +               .start  = 0xCD000000,
 614 +               .end    = 0xCD000300,
 615 +               .flags  = IORESOURCE_MEM,
 616 +       },
 617 +       {
 618 +               .start  = 32,
 619 +               .flags  = IORESOURCE_IRQ,
 620 +       },
 621 +};
 622 +
 623 +static struct resource cambria_usb1_resources[] = {
 624 +       {
 625 +               .start  = 0xCE000000,
 626 +               .end    = 0xCE000300,
 627 +               .flags  = IORESOURCE_MEM,
 628 +       },
 629 +       {
 630 +               .start  = 33,
 631 +               .flags  = IORESOURCE_IRQ,
 632 +       },
 633 +};
 634 +
 635 +static u64 ehci_dma_mask = ~(u32)0;
 636 +
 637 +static struct platform_device cambria_usb0_device =  {
 638 +       .name           = "ixp4xx-ehci",
 639 +       .id             = 0,
 640 +       .resource       = cambria_usb0_resources,
 641 +       .num_resources  = ARRAY_SIZE(cambria_usb0_resources),
 642 +       .dev = {
 643 +               .dma_mask               = &ehci_dma_mask,
 644 +               .coherent_dma_mask      = 0xffffffff,
 645 +       },
 646 +};
 647 +
 648 +static struct platform_device cambria_usb1_device = {
 649 +       .name           = "ixp4xx-ehci",
 650 +       .id             = 1,
 651 +       .resource       = cambria_usb1_resources,
 652 +       .num_resources  = ARRAY_SIZE(cambria_usb1_resources),
 653 +       .dev = {
 654 +               .dma_mask               = &ehci_dma_mask,
 655 +               .coherent_dma_mask      = 0xffffffff,
 656 +       },
 657 +};
 658 +
 659 +static struct gw_i2c_pld_platform_data gw_i2c_pld_data0 = {
 660 +       .gpio_base      = 16,
 661 +       .nr_gpio        = 8,
 662 +};
 663 +
 664 +static struct gw_i2c_pld_platform_data gw_i2c_pld_data1 = {
 665 +       .gpio_base      = 24,
 666 +       .nr_gpio        = 2,
 667 +};
 668 +
 669 +
 670 +static struct gpio_keys_button cambria_gpio_buttons[] = {
 671 +       {
 672 +               .desc           = "user",
 673 +               .type           = EV_KEY,
 674 +               .code           = BTN_0,
 675 +               .debounce_interval = 6,
 676 +               .gpio           = 25,
 677 +       }
 678 +};
 679 +
 680 +static struct gpio_keys_platform_data cambria_gpio_buttons_data = {
 681 +       .poll_interval  = 500,
 682 +       .nbuttons       = 1,
 683 +       .buttons        = cambria_gpio_buttons,
 684 +};
 685 +
 686 +static struct platform_device cambria_gpio_buttons_device = {
 687 +       .name                   = "gpio-keys-polled",
 688 +       .id                     = -1,
 689 +       .dev.platform_data      = &cambria_gpio_buttons_data,
 690 +};
 691 +
 692 +static struct platform_device *cambria_devices[] __initdata = {
 693 +       &cambria_i2c_gpio,
 694 +       &cambria_flash,
 695 +       &cambria_uart,
 696 +};
 697 +
 698 +static int cambria_register_gpio(struct gpio *array, size_t num)
 699 +{
 700 +       int i, err, ret;
 701 +
 702 +       ret = 0;
 703 +       for (i = 0; i < num; i++, array++) {
 704 +               const char *label = array->label;
 705 +               if (label[0] == '*')
 706 +                       label++;
 707 +               err = gpio_request_one(array->gpio, array->flags, label);
 708 +               if (err)
 709 +                       ret = err;
 710 +               else {
 711 +                       err = gpio_export(array->gpio, array->label[0] != '*');
 712 +               }
 713 +       }
 714 +       return ret;
 715 +}
 716 +
 717 +static void __init cambria_gw23xx_setup(void)
 718 +{
 719 +       cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
 720 +                                                                                                                                               (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
 721 +       cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
 722 +
 723 +       platform_device_register(&cambria_npec_device);
 724 +       platform_device_register(&cambria_npea_device);
 725 +}
 726 +
 727 +static void __init cambria_gw2350_setup(void)
 728 +{
 729 +       *IXP4XX_EXP_CS2 = 0xBFFF3C43;
 730 +       irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
 731 +       cambria_optional_uart_data[0].mapbase   = 0x52FF0000;
 732 +       cambria_optional_uart_data[0].membase   = (void __iomem *)ioremap(0x52FF0000, 0x0fff);
 733 +       cambria_optional_uart_data[0].irq               = IRQ_IXP4XX_GPIO3;
 734 +
 735 +       *IXP4XX_EXP_CS3 = 0xBFFF3C43;
 736 +       irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
 737 +       cambria_optional_uart_data[1].mapbase   = 0x53FF0000;
 738 +       cambria_optional_uart_data[1].membase   = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
 739 +       cambria_optional_uart_data[1].irq               = IRQ_IXP4XX_GPIO4;
 740 +
 741 +       cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
 742 +                                                                                                                                               (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
 743 +       cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
 744 +
 745 +       platform_device_register(&cambria_optional_uart);
 746 +       platform_device_register(&cambria_npec_device);
 747 +       platform_device_register(&cambria_npea_device);
 748 +
 749 +       platform_device_register(&cambria_usb0_device);
 750 +       platform_device_register(&cambria_usb1_device);
 751 +
 752 +       platform_device_register(&cambria_gpio_leds_device);
 753 +
 754 +       /* gpio config (/sys/class/gpio) */
 755 +       cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2350));
 756 +}
 757 +
 758 +static void __init cambria_gw2358_setup(void)
 759 +{
 760 +       *IXP4XX_EXP_CS3 = 0xBFFF3C43; // bit0 = 16bit vs 8bit bus
 761 +       irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
 762 +       cambria_optional_uart_data[0].mapbase   = 0x53FC0000;
 763 +       cambria_optional_uart_data[0].membase   = (void __iomem *)ioremap(0x53FC0000, 0x0fff);
 764 +       cambria_optional_uart_data[0].irq               = IRQ_IXP4XX_GPIO3;
 765 +
 766 +       irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
 767 +       cambria_optional_uart_data[1].mapbase   = 0x53F80000;
 768 +       cambria_optional_uart_data[1].membase   = (void __iomem *)ioremap(0x53F80000, 0x0fff);
 769 +       cambria_optional_uart_data[1].irq               = IRQ_IXP4XX_GPIO4;
 770 +
 771 +       cambria_gpio_resources[0].start = (1 << 14) | (1 << 16) | (1 << 17) | (1 << 18) |\
 772 +                                                                                                                                               (1 << 19) | (1 << 20) | (1 << 24) | (1 << 25);
 773 +       cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
 774 +
 775 +       platform_device_register(&cambria_optional_uart);
 776 +
 777 +       platform_device_register(&cambria_npec_device);
 778 +       platform_device_register(&cambria_npea_device);
 779 +
 780 +       platform_device_register(&cambria_usb0_device);
 781 +       platform_device_register(&cambria_usb1_device);
 782 +
 783 +       platform_device_register(&cambria_pata);
 784 +
 785 +       cambria_gpio_leds[0].gpio = 24;
 786 +       platform_device_register(&cambria_gpio_leds_device);
 787 +
 788 +       platform_device_register(&cambria_latch_leds_device);
 789 +
 790 +       platform_device_register(&cambria_gpio_buttons_device);
 791 +
 792 +       /* gpio config (/sys/class/gpio) */
 793 +       cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2358));
 794 +}
 795 +
 796 +static void __init cambria_gw2359_setup(void)
 797 +{
 798 +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE)
 799 +       /* The mvswitch driver has some hard-coded values which could
 800 +        * easily be turned into a platform resource if needed.  For now they
 801 +        * match our hardware configuration:
 802 +        *  MV_BASE    0x10 - phy base address
 803 +        *  MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module)
 804 +        *  MV_CPUPORT 5 - Port5 is CPU NPEA (eth1)
 805 +        *
 806 +        * The mvswitch driver registers a fixup which forces a driver match
 807 +        * if phy_addr matches MV_BASE
 808 +        *
 809 +        * Two static defautl VLAN's are created: WAN port in 1, and all other ports
 810 +        * in the other.
 811 +        */
 812 +       cambria_npea_data.phy = 0x10; // mvswitch driver catches this
 813 +#else
 814 +       // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the genphy driver
 815 +       cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
 816 +       // CPU NPE-C is in bridge bypass mode to Port4 PHY@0x14
 817 +       cambria_npec_data.phy = 0x14;
 818 +#endif
 819 +       platform_device_register(&cambria_npec_device);
 820 +       platform_device_register(&cambria_npea_device);
 821 +
 822 +       platform_device_register(&cambria_usb0_device);
 823 +       platform_device_register(&cambria_usb1_device);
 824 +
 825 +       cambria_gpio_leds_data.num_leds = 3;
 826 +       cambria_gpio_leds[0].name = "user1";
 827 +       cambria_gpio_leds[0].gpio = 125; // PNLLED1#
 828 +       cambria_gpio_leds[1].gpio = 126; // PNLLED3#
 829 +       cambria_gpio_leds[2].gpio = 119; // PNLLED4#
 830 +       platform_device_register(&cambria_gpio_leds_device);
 831 +
 832 +#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
 833 +       cambria_gpio_buttons[0].gpio = 100;
 834 +       platform_device_register(&cambria_gpio_buttons_device);
 835 +#endif
 836 +
 837 +       /* gpio config (/sys/class/gpio) */
 838 +       cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2359));
 839 +}
 840 +
 841 +static void __init cambria_gw2360_setup(void)
 842 +{
 843 +       /* The GW2360 has 8 UARTs in addition to the 1 IXP4xxx UART.
 844 +        * The chip-selects are expanded via a 3-to-8 decoder and CS2
 845 +        * and they are 8bit devices
 846 +        */
 847 +       *IXP4XX_EXP_CS2 = 0xBFFF3C43;
 848 +       cambria_optional_uart_data[0].mapbase = 0x52000000;
 849 +       cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff);
 850 +       cambria_optional_uart_data[0].uartclk = 18432000;
 851 +       cambria_optional_uart_data[0].iotype  = UPIO_MEM;
 852 +       cambria_optional_uart_data[0].irq     = IRQ_IXP4XX_GPIO2;
 853 +       irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING);
 854 +
 855 +       cambria_optional_uart_data[1].mapbase = 0x52000008;
 856 +       cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x52000008, 0x0fff);
 857 +       cambria_optional_uart_data[1].uartclk = 18432000;
 858 +       cambria_optional_uart_data[1].iotype  = UPIO_MEM;
 859 +       cambria_optional_uart_data[1].irq     = IRQ_IXP4XX_GPIO3;
 860 +       irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
 861 +
 862 +       cambria_optional_uart_data[2].mapbase = 0x52000010;
 863 +       cambria_optional_uart_data[2].membase = (void __iomem *)ioremap(0x52000010, 0x0fff);
 864 +       cambria_optional_uart_data[2].uartclk = 18432000;
 865 +       cambria_optional_uart_data[2].iotype  = UPIO_MEM;
 866 +       cambria_optional_uart_data[2].irq     = IRQ_IXP4XX_GPIO4;
 867 +       irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
 868 +
 869 +       cambria_optional_uart_data[3].mapbase = 0x52000018;
 870 +       cambria_optional_uart_data[3].membase = (void __iomem *)ioremap(0x52000018, 0x0fff);
 871 +       cambria_optional_uart_data[3].uartclk = 18432000;
 872 +       cambria_optional_uart_data[3].iotype  = UPIO_MEM;
 873 +       cambria_optional_uart_data[3].irq     = IRQ_IXP4XX_GPIO5;
 874 +       irq_set_irq_type(IRQ_IXP4XX_GPIO5, IRQ_TYPE_EDGE_RISING);
 875 +
 876 +       cambria_optional_uart_data[4].mapbase = 0x52000020;
 877 +       cambria_optional_uart_data[4].membase = (void __iomem *)ioremap(0x52000020, 0x0fff);
 878 +       cambria_optional_uart_data[4].uartclk = 18432000;
 879 +       cambria_optional_uart_data[4].iotype  = UPIO_MEM;
 880 +       cambria_optional_uart_data[4].irq     = IRQ_IXP4XX_GPIO8;
 881 +       irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_EDGE_RISING);
 882 +
 883 +       cambria_optional_uart_data[5].mapbase = 0x52000028;
 884 +       cambria_optional_uart_data[5].membase = (void __iomem *)ioremap(0x52000028, 0x0fff);
 885 +       cambria_optional_uart_data[5].uartclk = 18432000;
 886 +       cambria_optional_uart_data[5].iotype  = UPIO_MEM;
 887 +       cambria_optional_uart_data[5].irq     = IRQ_IXP4XX_GPIO9;
 888 +       irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_EDGE_RISING);
 889 +
 890 +       cambria_optional_uart_data[6].mapbase = 0x52000030;
 891 +       cambria_optional_uart_data[6].membase = (void __iomem *)ioremap(0x52000030, 0x0fff);
 892 +       cambria_optional_uart_data[6].uartclk = 18432000;
 893 +       cambria_optional_uart_data[6].iotype  = UPIO_MEM;
 894 +       cambria_optional_uart_data[6].irq     = IRQ_IXP4XX_GPIO10;
 895 +       irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING);
 896 +
 897 +       cambria_optional_uart.num_resources   = 7,
 898 +       platform_device_register(&cambria_optional_uart);
 899 +
 900 +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE)
 901 +       /* The mvswitch driver has some hard-coded values which could
 902 +        * easily be turned into a platform resource if needed.  For now they
 903 +        * match our hardware configuration:
 904 +        *  MV_BASE    0x10 - phy base address
 905 +        *  MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module)
 906 +        *  MV_CPUPORT 5 - Port5 is CPU NPEA (eth1)
 907 +        *
 908 +        * The mvswitch driver registers a fixup which forces a driver match
 909 +        * if phy_addr matches MV_BASE
 910 +        *
 911 +        * Two static defautl VLAN's are created: WAN port in 1, and all other ports
 912 +        * in the other.
 913 +        */
 914 +       cambria_npea_data.phy = 0x10; // mvswitch driver catches this
 915 +#else
 916 +       // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the generic PHY driver
 917 +       cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
 918 +#endif
 919 +
 920 +       // disable genphy autonegotiation on NPE-C PHY (eth1) as its 100BaseFX
 921 +       //cambria_npec_data.noautoneg = 1;   // disable autoneg
 922 +       cambria_npec_data.speed_10 = 0;    // 100mbps
 923 +       cambria_npec_data.half_duplex = 0; // full-duplex
 924 +       platform_device_register(&cambria_npec_device);
 925 +       platform_device_register(&cambria_npea_device);
 926 +
 927 +       platform_device_register(&cambria_usb0_device);
 928 +       platform_device_register(&cambria_usb1_device);
 929 +
 930 +       cambria_gpio_leds_data.num_leds = 3;
 931 +       cambria_gpio_leds[0].name = "user1";
 932 +       cambria_gpio_leds[0].gpio = 125;
 933 +       cambria_gpio_leds[1].gpio = 126;
 934 +       cambria_gpio_leds[2].gpio = 119;
 935 +       platform_device_register(&cambria_gpio_leds_device);
 936 +
 937 +#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
 938 +       cambria_gpio_buttons[0].gpio = 100;
 939 +       platform_device_register(&cambria_gpio_buttons_device);
 940 +#endif
 941 +
 942 +#ifdef SFP_SERIALID
 943 +       /* the SFP modules each have an i2c bus for serial ident via GSC GPIO
 944 +        * To use these the i2c-gpio driver must be changed to use the _cansleep
 945 +        * varients of gpio_get_value/gpio_set_value (I don't know why it doesn't
 946 +        * use that anyway as it doesn't operate in an IRQ context).
 947 +        * Additionally the i2c-gpio module must set the gpio to output-high prior
 948 +        * to changing direction to an input to enable internal Pullups
 949 +        */
 950 +       platform_device_register(&cambria_i2c_gpio_sfpa);
 951 +       platform_device_register(&cambria_i2c_gpio_sfpb);
 952 +#endif
 953 +
 954 +       /* gpio config (/sys/class/gpio) */
 955 +       cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2360));
 956 +}
 957 +
 958 +static struct cambria_board_info cambria_boards[] __initdata = {
 959 +       {
 960 +               .model  = "GW2350",
 961 +               .setup  = cambria_gw2350_setup,
 962 +       }, {
 963 +               .model  = "GW2351",
 964 +               .setup  = cambria_gw2350_setup,
 965 +       }, {
 966 +               .model  = "GW2358",
 967 +               .setup  = cambria_gw2358_setup,
 968 +       }, {
 969 +               .model  = "GW2359",
 970 +               .setup  = cambria_gw2359_setup,
 971 +       }, {
 972 +               .model  = "GW2360",
 973 +               .setup  = cambria_gw2360_setup,
 974 +       }, {
 975 +               .model  = "GW2371",
 976 +               .setup  = cambria_gw2358_setup,
 977 +       }
 978 +};
 979 +
 980 +static struct cambria_board_info * __init cambria_find_board_info(char *model)
 981 +{
 982 +       int i;
 983 +       model[6] = '\0';
 984 +
 985 +       for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
 986 +               struct cambria_board_info *info = &cambria_boards[i];
 987 +               if (strcmp(info->model, model) == 0)
 988 +                       return info;
 989 +       }
 990 +
 991 +       return NULL;
 992 +}
 993 +
 994 +static struct memory_accessor *at24_mem_acc;
 995 +
 996 +static void at24_setup(struct memory_accessor *mem_acc, void *context)
 997 +{
 998 +       char mac_addr[ETH_ALEN];
 999 +       char model[7];
1000 +
1001 +       at24_mem_acc = mem_acc;
1002 +
1003 +       /* Read MAC addresses */
1004 +       if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x0, 6) == 6) {
1005 +               memcpy(&cambria_npec_data.hwaddr, mac_addr, ETH_ALEN);
1006 +       }
1007 +       if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x6, 6) == 6) {
1008 +               memcpy(&cambria_npea_data.hwaddr, mac_addr, ETH_ALEN);
1009 +       }
1010 +
1011 +       /* Read the first 6 bytes of the model number */
1012 +       if (at24_mem_acc->read(at24_mem_acc, model, 0x20, 6) == 6) {
1013 +               cambria_info = cambria_find_board_info(model);
1014 +       }
1015 +
1016 +}
1017 +
1018 +static struct at24_platform_data cambria_eeprom_info = {
1019 +       .byte_len       = 1024,
1020 +       .page_size      = 16,
1021 +       .flags          = AT24_FLAG_READONLY,
1022 +       .setup          = at24_setup,
1023 +};
1024 +
1025 +static struct pca953x_platform_data cambria_pca_data = {
1026 +       .gpio_base = 100,
1027 +       .irq_base = -1,
1028 +};
1029 +
1030 +static struct pca953x_platform_data cambria_pca2_data = {
1031 +       .gpio_base = 116,
1032 +       .irq_base = -1,
1033 +};
1034 +
1035 +static struct i2c_board_info __initdata cambria_i2c_board_info[] = {
1036 +       {
1037 +               I2C_BOARD_INFO("pca9555", 0x23),
1038 +               .platform_data = &cambria_pca_data,
1039 +       },
1040 +       {
1041 +               I2C_BOARD_INFO("pca9555", 0x27),
1042 +               .platform_data = &cambria_pca2_data,
1043 +       },
1044 +       {
1045 +               I2C_BOARD_INFO("ds1672", 0x68),
1046 +       },
1047 +       {
1048 +               I2C_BOARD_INFO("gsp", 0x29),
1049 +       },
1050 +       {
1051 +               I2C_BOARD_INFO("ad7418", 0x28),
1052 +       },
1053 +       {
1054 +               I2C_BOARD_INFO("24c08", 0x51),
1055 +               .platform_data  = &cambria_eeprom_info
1056 +       },
1057 +       {
1058 +               I2C_BOARD_INFO("gw_i2c_pld", 0x56),
1059 +               .platform_data  = &gw_i2c_pld_data0,
1060 +       },
1061 +       {
1062 +               I2C_BOARD_INFO("gw_i2c_pld", 0x57),
1063 +               .platform_data  = &gw_i2c_pld_data1,
1064 +       },
1065 +};
1066 +
1067 +static void __init cambria_init(void)
1068 +{
1069 +       ixp4xx_sys_init();
1070 +
1071 +       cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
1072 +       cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
1073 +
1074 +       *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; // make sure window is writable
1075 +       *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
1076 +
1077 +       platform_add_devices(ARRAY_AND_SIZE(cambria_devices));
1078 +
1079 +       cambria_pata_resources[0].start = 0x53e00000;
1080 +       cambria_pata_resources[0].end = 0x53e3ffff;
1081 +
1082 +       cambria_pata_resources[1].start = 0x53e40000;
1083 +       cambria_pata_resources[1].end = 0x53e7ffff;
1084 +
1085 +       cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
1086 +       cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
1087 +
1088 +       i2c_register_board_info(0, ARRAY_AND_SIZE(cambria_i2c_board_info));
1089 +}
1090 +
1091 +static int __init cambria_model_setup(void)
1092 +{
1093 +       if (!machine_is_cambria())
1094 +               return 0;
1095 +
1096 +       if (cambria_info) {
1097 +               printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
1098 +                               cambria_info->model);
1099 +               cambria_info->setup();
1100 +       } else {
1101 +               printk(KERN_INFO "Unknown/missing Cambria model number"
1102 +                               " -- defaults will be used\n");
1103 +               cambria_gw23xx_setup();
1104 +       }
1105 +
1106 +       return 0;
1107 +}
1108 +late_initcall(cambria_model_setup);
1109 +
1110 +MACHINE_START(CAMBRIA, "Gateworks Cambria series")
1111 +       /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
1112 +       .map_io         = ixp4xx_map_io,
1113 +       .init_irq       = ixp4xx_init_irq,
1114 +       .init_time      = ixp4xx_timer_init,
1115 +       .atag_offset    = 0x0100,
1116 +       .init_machine   = cambria_init,
1117 +#if defined(CONFIG_PCI)
1118 +       .dma_zone_size  = SZ_64M,
1119 +#endif
1120 +       .restart        = ixp4xx_restart,
1121 +MACHINE_END