target/linux/ipq806x/patches/0178-dmaengine-qcom_adm-Add-device-tree-binding.patch

   1 From 331294fa5c703536e27b79e9c112d162393f725a Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Thu, 26 Jun 2014 13:55:10 -0500
   4 Subject: [PATCH 178/182] dmaengine: qcom_adm: Add device tree binding
   5
   6 Add device tree binding support for the QCOM ADM DMA driver.
   7
   8 Signed-off-by: Andy Gross <agross@codeaurora.org>
   9 ---
  10  Documentation/devicetree/bindings/dma/qcom_adm.txt |   60 ++++++++++++++++++++
  11  1 file changed, 60 insertions(+)
  12  create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
  13
  14 diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt b/Documentation/devicetree/bindings/dma/qcom_adm.txt
  15 new file mode 100644
  16 index 0000000..7f05cb5
  17 --- /dev/null
  18 +++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
  19 @@ -0,0 +1,60 @@
  20 +QCOM ADM DMA Controller
  21 +
  22 +Required properties:
  23 +- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
  24 +- reg: Address range for DMA registers
  25 +- interrupts: Should contain one interrupt shared by all channels
  26 +- #dma-cells: must be <2>.  First cell denotes the channel number.  Second cell
  27 +  denotes CRCI (client rate control interface) flow control assignment.
  28 +- clocks: Should contain the core clock and interface clock.
  29 +- clock-names: Must contain "core" for the core clock and "iface" for the
  30 +  interface clock.
  31 +- resets: Must contain an entry for each entry in reset names.
  32 +- reset-names: Must include the following entries:
  33 +  - clk
  34 +  - c0
  35 +  - c1
  36 +  - c2
  37 +- qcom,ee: indicates the security domain identifier used in the secure world.
  38 +
  39 +Example:
  40 +               adm_dma: dma@18300000 {
  41 +                       compatible = "qcom,adm";
  42 +                       reg = <0x18300000 0x100000>;
  43 +                       interrupts = <0 170 0>;
  44 +                       #dma-cells = <2>;
  45 +
  46 +                       clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
  47 +                       clock-names = "core", "iface";
  48 +
  49 +                       resets = <&gcc ADM0_RESET>,
  50 +                               <&gcc ADM0_C0_RESET>,
  51 +                               <&gcc ADM0_C1_RESET>,
  52 +                               <&gcc ADM0_C2_RESET>;
  53 +                       reset-names = "clk", "c0", "c1", "c2";
  54 +                       qcom,ee = <0>;
  55 +               };
  56 +
  57 +DMA clients must use the format descripted in the dma.txt file, using a three
  58 +cell specifier for each channel.
  59 +
  60 +Each dmas request consists of 3 cells:
  61 + 1. phandle pointing to the DMA controller
  62 + 2. channel number
  63 + 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 0.
  64 +
  65 +Example:
  66 +
  67 +       spi4: spi@1a280000 {
  68 +               status = "ok";
  69 +               spi-max-frequency = <50000000>;
  70 +
  71 +               pinctrl-0 = <&spi_pins>;
  72 +               pinctrl-names = "default";
  73 +
  74 +               cs-gpios = <&qcom_pinmux 20 0>;
  75 +
  76 +               dmas = <&adm_dma 6 9>,
  77 +                       <&adm_dma 5 10>;
  78 +               dma-names = "rx", "tx";
  79 +       };
  80 --
  81 1.7.10.4
  82