kernel: update 3.14 to 3.14.18
[openwrt.git] / target / linux / ipq806x / patches / 0168-clk-qcom-Add-MSM8960-s-HFPLLs.patch
1 From 0a38d7a21ef0e851d025e4e16f096d5579226299 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Mon, 16 Jun 2014 17:44:08 -0700
4 Subject: [PATCH 168/182] clk: qcom: Add MSM8960's HFPLLs
5
6 Describe the HFPLLs present on MSM8960 devices.
7
8 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
9 ---
10  drivers/clk/qcom/gcc-msm8960.c |   82 ++++++++++++++++++++++++++++++++++++++++
11  1 file changed, 82 insertions(+)
12
13 --- a/drivers/clk/qcom/gcc-msm8960.c
14 +++ b/drivers/clk/qcom/gcc-msm8960.c
15 @@ -30,6 +30,7 @@
16  #include "clk-pll.h"
17  #include "clk-rcg.h"
18  #include "clk-branch.h"
19 +#include "clk-hfpll.h"
20  #include "reset.h"
21  
22  static struct clk_pll pll3 = {
23 @@ -75,6 +76,84 @@ static struct clk_regmap pll8_vote = {
24         },
25  };
26  
27 +static struct hfpll_data hfpll0_data = {
28 +       .mode_reg = 0x3200,
29 +       .l_reg = 0x3208,
30 +       .m_reg = 0x320c,
31 +       .n_reg = 0x3210,
32 +       .config_reg = 0x3204,
33 +       .status_reg = 0x321c,
34 +        .config_val = 0x7845c665,
35 +        .droop_reg = 0x3214,
36 +        .droop_val = 0x0108c000,
37 +       .min_rate = 600000000UL,
38 +       .max_rate = 1800000000UL,
39 +};
40 +
41 +static struct clk_hfpll hfpll0 = {
42 +       .d = &hfpll0_data,
43 +       .clkr.hw.init = &(struct clk_init_data){
44 +               .parent_names = (const char *[]){ "pxo" },
45 +               .num_parents = 1,
46 +               .name = "hfpll0",
47 +               .ops = &clk_ops_hfpll,
48 +               .flags = CLK_IGNORE_UNUSED,
49 +       },
50 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
51 +};
52 +
53 +static struct hfpll_data hfpll1_data = {
54 +       .mode_reg = 0x3300,
55 +       .l_reg = 0x3308,
56 +       .m_reg = 0x330c,
57 +       .n_reg = 0x3310,
58 +       .config_reg = 0x3304,
59 +       .status_reg = 0x331c,
60 +        .config_val = 0x7845c665,
61 +        .droop_reg = 0x3314,
62 +        .droop_val = 0x0108c000,
63 +       .min_rate = 600000000UL,
64 +       .max_rate = 1800000000UL,
65 +};
66 +
67 +static struct clk_hfpll hfpll1 = {
68 +       .d = &hfpll1_data,
69 +       .clkr.hw.init = &(struct clk_init_data){
70 +               .parent_names = (const char *[]){ "pxo" },
71 +               .num_parents = 1,
72 +               .name = "hfpll1",
73 +               .ops = &clk_ops_hfpll,
74 +               .flags = CLK_IGNORE_UNUSED,
75 +       },
76 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
77 +};
78 +
79 +static struct hfpll_data hfpll_l2_data = {
80 +       .mode_reg = 0x3400,
81 +       .l_reg = 0x3408,
82 +       .m_reg = 0x340c,
83 +       .n_reg = 0x3410,
84 +       .config_reg = 0x3404,
85 +       .status_reg = 0x341c,
86 +        .config_val = 0x7845c665,
87 +        .droop_reg = 0x3414,
88 +        .droop_val = 0x0108c000,
89 +       .min_rate = 600000000UL,
90 +       .max_rate = 1800000000UL,
91 +};
92 +
93 +static struct clk_hfpll hfpll_l2 = {
94 +       .d = &hfpll_l2_data,
95 +       .clkr.hw.init = &(struct clk_init_data){
96 +               .parent_names = (const char *[]){ "pxo" },
97 +               .num_parents = 1,
98 +               .name = "hfpll_l2",
99 +               .ops = &clk_ops_hfpll,
100 +               .flags = CLK_IGNORE_UNUSED,
101 +       },
102 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
103 +};
104 +
105  static struct clk_pll pll14 = {
106         .l_reg = 0x31c4,
107         .m_reg = 0x31c8,
108 @@ -2763,6 +2842,9 @@ static struct clk_regmap *gcc_msm8960_cl
109         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
110         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
111         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
112 +       [PLL9] = &hfpll0.clkr,
113 +       [PLL10] = &hfpll1.clkr,
114 +       [PLL12] = &hfpll_l2.clkr,
115  };
116  
117  static const struct qcom_reset_map gcc_msm8960_resets[] = {