target/linux/ipq806x/patches/0139-ARM-dts-msm-Add-PCIe-related-nodes-for-IPQ8064-AP148.patch

   1 From 7c6525a0d5cf88f9244187fbe8ee293fa4ee43c1 Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Mon, 12 May 2014 19:36:23 -0500
   4 Subject: [PATCH 139/182] ARM: dts: msm: Add PCIe related nodes for
   5  IPQ8064/AP148
   6
   7 ---
   8  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   38 ++++++++++++
   9  arch/arm/boot/dts/qcom-ipq8064.dtsi      |   93 ++++++++++++++++++++++++++++++
  10  2 files changed, 131 insertions(+)
  11
  12 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  13 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  14 @@ -21,6 +21,22 @@
  15                                 bias-disable;
  16                         };
  17
  18 +                       pcie1_pins: pcie1_pinmux {
  19 +                               mux {
  20 +                                       pins = "gpio3";
  21 +                                       drive-strength = <2>;
  22 +                                       bias-disable;
  23 +                               };
  24 +                       };
  25 +
  26 +                       pcie2_pins: pcie2_pinmux {
  27 +                               mux {
  28 +                                       pins = "gpio48";
  29 +                                       drive-strength = <2>;
  30 +                                       bias-disable;
  31 +                               };
  32 +                       };
  33 +
  34                         spi_pins: spi_pins {
  35                                 mux {
  36                                         pins = "gpio18", "gpio19", "gpio21";
  37 @@ -80,5 +96,27 @@
  38                                 };
  39                         };
  40                 };
  41 +
  42 +               pci@1b500000 {
  43 +                       status = "ok";
  44 +                       reset-gpio = <&qcom_pinmux 3 0>;
  45 +                       pinctrl-0 = <&pcie1_pins>;
  46 +                       pinctrl-names = "default";
  47 +
  48 +                       ranges = <0x00000000 0 0x00000000 0x0ff00000 0 0x00100000   /* configuration space */
  49 +                                 0x81000000 0 0          0x0fe00000 0 0x00100000   /* downstream I/O */
  50 +                                 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
  51 +               };
  52 +
  53 +               pci@1b700000 {
  54 +                       status = "ok";
  55 +                       reset-gpio = <&qcom_pinmux 48 0>;
  56 +                       pinctrl-0 = <&pcie2_pins>;
  57 +                       pinctrl-names = "default";
  58 +
  59 +                       ranges = <0x00000000 0 0x00000000 0x31f00000 0 0x00100000   /* configuration space */
  60 +                                 0x81000000 0 0          0x31e00000 0 0x00100000   /* downstream I/O */
  61 +                                 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
  62 +               };
  63         };
  64  };
  65 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  66 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  67 @@ -2,6 +2,7 @@
  68
  69  #include "skeleton.dtsi"
  70  #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  71 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  72  #include <dt-bindings/soc/qcom,gsbi.h>
  73
  74  / {
  75 @@ -246,5 +247,97 @@
  76                         #clock-cells = <1>;
  77                         #reset-cells = <1>;
  78                 };
  79 +
  80 +               pci@1b500000 {
  81 +                       compatible = "qcom,pcie-ipq8064";
  82 +                       reg = <0x1b500000 0x1000
  83 +                              0x1b502000 0x80
  84 +                              0x1b600000 0x100
  85 +                               >;
  86 +                       reg-names = "base", "elbi", "parf";
  87 +
  88 +                       #address-cells = <3>;
  89 +                       #size-cells = <2>;
  90 +                       device_type = "pci";
  91 +                       interrupts = <0 35 0x0
  92 +                                     0 36 0x0
  93 +                                     0 37 0x0
  94 +                                     0 38 0x0
  95 +                                     0 39 0x0>;
  96 +                       resets = <&gcc PCIE_ACLK_RESET>,
  97 +                                <&gcc PCIE_HCLK_RESET>,
  98 +                                <&gcc PCIE_POR_RESET>,
  99 +                                <&gcc PCIE_PCI_RESET>,
 100 +                                <&gcc PCIE_PHY_RESET>;
 101 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 102 +
 103 +                       clocks = <&gcc PCIE_A_CLK>,
 104 +                                <&gcc PCIE_H_CLK>,
 105 +                                <&gcc PCIE_PHY_CLK>;
 106 +                       clock-names = "core", "iface", "phy";
 107 +                       status = "disabled";
 108 +               };
 109 +
 110 +               pci@1b700000 {
 111 +                       compatible = "qcom,pcie-ipq8064";
 112 +                       reg = <0x1b700000 0x1000
 113 +                              0x1b702000 0x80
 114 +                              0x1b800000 0x100
 115 +                               >;
 116 +                       reg-names = "base", "elbi", "parf";
 117 +
 118 +                       #address-cells = <3>;
 119 +                       #size-cells = <2>;
 120 +                       device_type = "pci";
 121 +
 122 +                       interrupts = <0 57 0x0
 123 +                                     0 58 0x0
 124 +                                     0 59 0x0
 125 +                                     0 60 0x0
 126 +                                     0 61 0x0>;
 127 +                       resets = <&gcc PCIE_1_ACLK_RESET>,
 128 +                                <&gcc PCIE_1_HCLK_RESET>,
 129 +                                <&gcc PCIE_1_POR_RESET>,
 130 +                                <&gcc PCIE_1_PCI_RESET>,
 131 +                                <&gcc PCIE_1_PHY_RESET>;
 132 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 133 +
 134 +                       clocks = <&gcc PCIE_1_A_CLK>,
 135 +                                <&gcc PCIE_1_H_CLK>,
 136 +                                <&gcc PCIE_1_PHY_CLK>;
 137 +                       clock-names = "core", "iface", "phy";
 138 +                       status = "disabled";
 139 +               };
 140 +
 141 +               pci@1b900000 {
 142 +                       compatible = "qcom,pcie-ipq8064";
 143 +                       reg = <0x1b900000 0x1000
 144 +                              0x1b902000 0x80
 145 +                              0x1ba00000 0x100
 146 +                               >;
 147 +                       reg-names = "base", "elbi", "parf";
 148 +
 149 +                       #address-cells = <3>;
 150 +                       #size-cells = <2>;
 151 +                       device_type = "pci";
 152 +
 153 +                       interrupts = <0 71 0x0
 154 +                                     0 72 0x0
 155 +                                     0 73 0x0
 156 +                                     0 74 0x0
 157 +                                     0 75 0x0>;
 158 +                       resets = <&gcc PCIE_2_ACLK_RESET>,
 159 +                                <&gcc PCIE_2_HCLK_RESET>,
 160 +                                <&gcc PCIE_2_POR_RESET>,
 161 +                                <&gcc PCIE_2_PCI_RESET>,
 162 +                                <&gcc PCIE_2_PHY_RESET>;
 163 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 164 +
 165 +                       clocks = <&gcc PCIE_2_A_CLK>,
 166 +                                <&gcc PCIE_2_H_CLK>,
 167 +                                <&gcc PCIE_2_PHY_CLK>;
 168 +                       clock-names = "core", "iface", "phy";
 169 +                       status = "disabled";
 170 +               };
 171         };
 172  };