target/linux/ipq806x/patches/013-ARM-msm-add-watchdog-entries-to-DT-timer-binding-doc.patch

   1 From e535f01dffb6dd9e09934fa219be52af3437a8f6 Mon Sep 17 00:00:00 2001
   2 From: Mathieu Olivari <mathieu@codeaurora.org>
   3 Date: Thu, 19 Feb 2015 20:36:27 -0800
   4 Subject: [PATCH 3/3] ARM: msm: add watchdog entries to DT timer binding doc
   5
   6 The watchdog has been reworked to use the same DT node as the timer.
   7 This change is updating the device tree doc accordingly.
   8
   9 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  10 ---
  11  Documentation/devicetree/bindings/arm/msm/timer.txt | 16 +++++++++++++---
  12  1 file changed, 13 insertions(+), 3 deletions(-)
  13
  14 --- a/Documentation/devicetree/bindings/arm/msm/timer.txt
  15 +++ b/Documentation/devicetree/bindings/arm/msm/timer.txt
  16 @@ -9,11 +9,17 @@ Properties:
  17                 "qcom,scss-timer" - scorpion subsystem
  18
  19  - interrupts : Interrupts for the the debug timer, the first general purpose
  20 -               timer, and optionally a second general purpose timer in that
  21 -               order.
  22 +               timer, and optionally a second general purpose timer, and
  23 +               optionally as well, 2 watchdog interrupts, in that order.
  24
  25  - reg : Specifies the base address of the timer registers.
  26
  27 +- clocks: Reference to the parent clocks, one per output clock. The parents
  28 +          must appear in the same order as the clock names.
  29 +
  30 +- clock-names: The name of the clocks as free-form strings. They should be in
  31 +               the same order as the clocks.
  32 +
  33  - clock-frequency : The frequency of the debug timer and the general purpose
  34                      timer(s) in Hz in that order.
  35
  36 @@ -29,9 +35,13 @@ Example:
  37                 compatible = "qcom,scss-timer", "qcom,msm-timer";
  38                 interrupts = <1 1 0x301>,
  39                              <1 2 0x301>,
  40 -                            <1 3 0x301>;
  41 +                            <1 3 0x301>,
  42 +                            <1 4 0x301>,
  43 +                            <1 5 0x301>;
  44                 reg = <0x0200a000 0x100>;
  45                 clock-frequency = <19200000>,
  46                                   <32768>;
  47 +               clocks = <&sleep_clk>;
  48 +               clock-names = "sleep";
  49                 cpu-offset = <0x40000>;
  50         };