target/linux/ipq806x/patches/0090-ARM-dts-msm-Add-SDHC-controller-nodes-for-MSM8974-an.patch

   1 From 6632619d49f0f90c4d74caad67749864f154cae4 Mon Sep 17 00:00:00 2001
   2 From: Georgi Djakov <gdjakov@mm-sol.com>
   3 Date: Fri, 31 Jan 2014 16:21:56 +0200
   4 Subject: [PATCH 090/182] ARM: dts: msm: Add SDHC controller nodes for MSM8974
   5  and DB8074 board
   6
   7 Add support for the 2 SDHC controllers on the DB8074 board.  The first
   8 controller (at 0xf9824900) is connected to an on board soldered eMMC.
   9 The second controller (at 0xf98a4900) is connected to a uSD card slot.
  10
  11 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
  12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  13 ---
  14  arch/arm/boot/dts/qcom-apq8074-dragonboard.dts |   13 +++++++++++++
  15  arch/arm/boot/dts/qcom-msm8974.dtsi            |   22 ++++++++++++++++++++++
  16  2 files changed, 35 insertions(+)
  17
  18 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
  19 +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
  20 @@ -3,4 +3,17 @@
  21  / {
  22         model = "Qualcomm APQ8074 Dragonboard";
  23         compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
  24 +
  25 +       soc: soc {
  26 +               sdhci@f9824900 {
  27 +                       bus-width = <8>;
  28 +                       non-removable;
  29 +                       status = "ok";
  30 +               };
  31 +
  32 +               sdhci@f98a4900 {
  33 +                       cd-gpios = <&msmgpio 62 0x1>;
  34 +                       bus-width = <4>;
  35 +               };
  36 +       };
  37  };
  38 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
  39 +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
  40 @@ -192,6 +192,28 @@
  41                         clock-names = "core", "iface";
  42                 };
  43
  44 +               sdhci@f9824900 {
  45 +                       compatible = "qcom,sdhci-msm-v4";
  46 +                       reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
  47 +                       reg-names = "hc_mem", "core_mem";
  48 +                       interrupts = <0 123 0>, <0 138 0>;
  49 +                       interrupt-names = "hc_irq", "pwr_irq";
  50 +                       clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
  51 +                       clock-names = "core", "iface";
  52 +                       status = "disabled";
  53 +               };
  54 +
  55 +               sdhci@f98a4900 {
  56 +                       compatible = "qcom,sdhci-msm-v4";
  57 +                       reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
  58 +                       reg-names = "hc_mem", "core_mem";
  59 +                       interrupts = <0 125 0>, <0 221 0>;
  60 +                       interrupt-names = "hc_irq", "pwr_irq";
  61 +                       clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
  62 +                       clock-names = "core", "iface";
  63 +                       status = "disabled";
  64 +               };
  65 +
  66                 rng@f9bff000 {
  67                         compatible = "qcom,prng";
  68                         reg = <0xf9bff000 0x200>;