target/linux/ipq806x/patches/0013-ARM-qcom-Add-SMP-support-for-KPSSv1.patch

   1 From 8e843640b3c4a43b963332fdc7b233948ad25a5b Mon Sep 17 00:00:00 2001
   2 From: Rohit Vaswani <rvaswani@codeaurora.org>
   3 Date: Tue, 21 May 2013 19:13:50 -0700
   4 Subject: [PATCH 013/182] ARM: qcom: Add SMP support for KPSSv1
   5
   6 Implement support for the Krait CPU release sequence when the
   7 CPUs are part of the first version of the krait processor
   8 subsystem.
   9
  10 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
  11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  13 ---
  14  arch/arm/mach-qcom/platsmp.c  |  106 +++++++++++++++++++++++++++++++++++++++++
  15  arch/arm/mach-qcom/scm-boot.h |    8 ++--
  16  2 files changed, 111 insertions(+), 3 deletions(-)
  17
  18 diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
  19 index ec8604d..cb0783f 100644
  20 --- a/arch/arm/mach-qcom/platsmp.c
  21 +++ b/arch/arm/mach-qcom/platsmp.c
  22 @@ -26,6 +26,16 @@
  23  #define SCSS_CPU1CORE_RESET            0x2d80
  24  #define SCSS_DBG_STATUS_CORE_PWRDUP    0x2e64
  25
  26 +#define APCS_CPU_PWR_CTL       0x04
  27 +#define PLL_CLAMP              BIT(8)
  28 +#define CORE_PWRD_UP           BIT(7)
  29 +#define COREPOR_RST            BIT(5)
  30 +#define CORE_RST               BIT(4)
  31 +#define L2DT_SLP               BIT(3)
  32 +#define CLAMP                  BIT(0)
  33 +
  34 +#define APCS_SAW2_VCTL         0x14
  35 +
  36  extern void secondary_startup(void);
  37
  38  static DEFINE_SPINLOCK(boot_lock);
  39 @@ -71,6 +81,85 @@ static int scss_release_secondary(unsigned int cpu)
  40         return 0;
  41  }
  42
  43 +static int kpssv1_release_secondary(unsigned int cpu)
  44 +{
  45 +       int ret = 0;
  46 +       void __iomem *reg, *saw_reg;
  47 +       struct device_node *cpu_node, *acc_node, *saw_node;
  48 +       u32 val;
  49 +
  50 +       cpu_node = of_get_cpu_node(cpu, NULL);
  51 +       if (!cpu_node)
  52 +               return -ENODEV;
  53 +
  54 +       acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
  55 +       if (!acc_node) {
  56 +               ret = -ENODEV;
  57 +               goto out_acc;
  58 +       }
  59 +
  60 +       saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
  61 +       if (!saw_node) {
  62 +               ret = -ENODEV;
  63 +               goto out_saw;
  64 +       }
  65 +
  66 +       reg = of_iomap(acc_node, 0);
  67 +       if (!reg) {
  68 +               ret = -ENOMEM;
  69 +               goto out_acc_map;
  70 +       }
  71 +
  72 +       saw_reg = of_iomap(saw_node, 0);
  73 +       if (!saw_reg) {
  74 +               ret = -ENOMEM;
  75 +               goto out_saw_map;
  76 +       }
  77 +
  78 +       /* Turn on CPU rail */
  79 +       writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
  80 +       mb();
  81 +       udelay(512);
  82 +
  83 +       /* Krait bring-up sequence */
  84 +       val = PLL_CLAMP | L2DT_SLP | CLAMP;
  85 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
  86 +       val &= ~L2DT_SLP;
  87 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
  88 +       mb();
  89 +       ndelay(300);
  90 +
  91 +       val |= COREPOR_RST;
  92 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
  93 +       mb();
  94 +       udelay(2);
  95 +
  96 +       val &= ~CLAMP;
  97 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
  98 +       mb();
  99 +       udelay(2);
 100 +
 101 +       val &= ~COREPOR_RST;
 102 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
 103 +       mb();
 104 +       udelay(100);
 105 +
 106 +       val |= CORE_PWRD_UP;
 107 +       writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
 108 +       mb();
 109 +
 110 +       iounmap(saw_reg);
 111 +out_saw_map:
 112 +       iounmap(reg);
 113 +out_acc_map:
 114 +       of_node_put(saw_node);
 115 +out_saw:
 116 +       of_node_put(acc_node);
 117 +out_acc:
 118 +       of_node_put(cpu_node);
 119 +       return ret;
 120 +}
 121 +
 122  static DEFINE_PER_CPU(int, cold_boot_done);
 123
 124  static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
 125 @@ -110,6 +199,11 @@ static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
 126         return qcom_boot_secondary(cpu, scss_release_secondary);
 127  }
 128
 129 +static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
 130 +{
 131 +       return qcom_boot_secondary(cpu, kpssv1_release_secondary);
 132 +}
 133 +
 134  static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
 135  {
 136         int cpu, map;
 137 @@ -117,6 +211,8 @@ static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
 138         static const int cold_boot_flags[] = {
 139                 0,
 140                 SCM_FLAG_COLDBOOT_CPU1,
 141 +               SCM_FLAG_COLDBOOT_CPU2,
 142 +               SCM_FLAG_COLDBOOT_CPU3,
 143         };
 144
 145         for_each_present_cpu(cpu) {
 146 @@ -147,3 +243,13 @@ static struct smp_operations smp_msm8660_ops __initdata = {
 147  #endif
 148  };
 149  CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
 150 +
 151 +static struct smp_operations qcom_smp_kpssv1_ops __initdata = {
 152 +       .smp_prepare_cpus       = qcom_smp_prepare_cpus,
 153 +       .smp_secondary_init     = qcom_secondary_init,
 154 +       .smp_boot_secondary     = kpssv1_boot_secondary,
 155 +#ifdef CONFIG_HOTPLUG_CPU
 156 +       .cpu_die                = qcom_cpu_die,
 157 +#endif
 158 +};
 159 +CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
 160 diff --git a/arch/arm/mach-qcom/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h
 161 index 7be32ff..6aabb24 100644
 162 --- a/arch/arm/mach-qcom/scm-boot.h
 163 +++ b/arch/arm/mach-qcom/scm-boot.h
 164 @@ -13,9 +13,11 @@
 165  #define __MACH_SCM_BOOT_H
 166
 167  #define SCM_BOOT_ADDR                  0x1
 168 -#define SCM_FLAG_COLDBOOT_CPU1         0x1
 169 -#define SCM_FLAG_WARMBOOT_CPU1         0x2
 170 -#define SCM_FLAG_WARMBOOT_CPU0         0x4
 171 +#define SCM_FLAG_COLDBOOT_CPU1         0x01
 172 +#define SCM_FLAG_COLDBOOT_CPU2         0x08
 173 +#define SCM_FLAG_COLDBOOT_CPU3         0x20
 174 +#define SCM_FLAG_WARMBOOT_CPU0         0x04
 175 +#define SCM_FLAG_WARMBOOT_CPU1         0x02
 176
 177  int scm_set_boot_addr(phys_addr_t addr, int flags);
 178
 179 --
 180 1.7.10.4
 181