target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch

   1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
   2 From: Mathieu Olivari <mathieu@codeaurora.org>
   3 Date: Tue, 21 Apr 2015 19:01:42 -0700
   4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
   5
   6 qcom-pcie driver now supports version 0 of the controller. This change
   7 adds the corresponding entries to the IPQ806x dtsi file and
   8 corresponding platform (AP148).
   9
  10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
  11 ---
  12  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |  30 ++++++++
  13  arch/arm/boot/dts/qcom-ipq8064.dtsi      | 124 +++++++++++++++++++++++++++++++
  14  2 files changed, 154 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  18 @@ -35,6 +35,24 @@
  19                                 bias-disable;
  20                         };
  21
  22 +                       pcie0_pins: pcie0_pinmux {
  23 +                               mux {
  24 +                                       pins = "gpio3";
  25 +                                       function = "pcie1_rst";
  26 +                                       drive-strength = <12>;
  27 +                                       bias-disable;
  28 +                               };
  29 +                       };
  30 +
  31 +                       pcie1_pins: pcie1_pinmux {
  32 +                               mux {
  33 +                                       pins = "gpio48";
  34 +                                       function = "pcie2_rst";
  35 +                                       drive-strength = <12>;
  36 +                                       bias-disable;
  37 +                               };
  38 +                       };
  39 +
  40                         spi_pins: spi_pins {
  41                                 mux {
  42                                         pins = "gpio18", "gpio19", "gpio21";
  43 @@ -114,5 +132,19 @@
  44                 sata@29000000 {
  45                         status = "ok";
  46                 };
  47 +
  48 +               pcie0: pci@1b500000 {
  49 +                       status = "ok";
  50 +                       reset-gpio = <&qcom_pinmux 3 0>;
  51 +                       pinctrl-0 = <&pcie0_pins>;
  52 +                       pinctrl-names = "default";
  53 +               };
  54 +
  55 +               pcie1: pci@1b700000 {
  56 +                       status = "ok";
  57 +                       reset-gpio = <&qcom_pinmux 48 0>;
  58 +                       pinctrl-0 = <&pcie1_pins>;
  59 +                       pinctrl-names = "default";
  60 +               };
  61         };
  62  };
  63 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
  64 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
  65 @@ -30,6 +30,33 @@
  66                                 bias-disable;
  67                         };
  68
  69 +                       pcie0_pins: pcie0_pinmux {
  70 +                               mux {
  71 +                                       pins = "gpio3";
  72 +                                       function = "pcie1_rst";
  73 +                                       drive-strength = <12>;
  74 +                                       bias-disable;
  75 +                               };
  76 +                       };
  77 +
  78 +                       pcie1_pins: pcie1_pinmux {
  79 +                               mux {
  80 +                                       pins = "gpio48";
  81 +                                       function = "pcie2_rst";
  82 +                                       drive-strength = <12>;
  83 +                                       bias-disable;
  84 +                               };
  85 +                       };
  86 +
  87 +                       pcie2_pins: pcie2_pinmux {
  88 +                               mux {
  89 +                                       pins = "gpio63";
  90 +                                       function = "pcie3_rst";
  91 +                                       drive-strength = <12>;
  92 +                                       bias-disable;
  93 +                               };
  94 +                       };
  95 +
  96                         spi_pins: spi_pins {
  97                                 mux {
  98                                         pins = "gpio18", "gpio19", "gpio21";
  99 @@ -128,5 +155,26 @@
 100                 usb30@1 {
 101                         status = "ok";
 102                 };
 103 +
 104 +               pcie0: pci@1b500000 {
 105 +                       status = "ok";
 106 +                       reset-gpio = <&qcom_pinmux 3 0>;
 107 +                       pinctrl-0 = <&pcie0_pins>;
 108 +                       pinctrl-names = "default";
 109 +               };
 110 +
 111 +               pcie1: pci@1b700000 {
 112 +                       status = "ok";
 113 +                       reset-gpio = <&qcom_pinmux 48 0>;
 114 +                       pinctrl-0 = <&pcie1_pins>;
 115 +                       pinctrl-names = "default";
 116 +               };
 117 +
 118 +               pcie2: pci@1b900000 {
 119 +                       status = "ok";
 120 +                       reset-gpio = <&qcom_pinmux 63 0>;
 121 +                       pinctrl-0 = <&pcie2_pins>;
 122 +                       pinctrl-names = "default";
 123 +               };
 124         };
 125  };
 126 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
 127 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
 128 @@ -4,6 +4,8 @@
 129  #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
 130  #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
 131  #include <dt-bindings/soc/qcom,gsbi.h>
 132 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
 133 +#include <dt-bindings/interrupt-controller/arm-gic.h>
 134
 135  / {
 136         model = "Qualcomm IPQ8064";
 137 @@ -333,6 +335,129 @@
 138                         compatible = "syscon";
 139                         reg = <0x01200600 0x100>;
 140                 };
 141 +
 142 +               pcie0: pci@1b500000 {
 143 +                       compatible = "qcom,pcie-v0";
 144 +                       reg = <0x1b500000 0x1000
 145 +                              0x1b502000 0x80
 146 +                              0x1b600000 0x100
 147 +                              0x0ff00000 0x100000>;
 148 +                       reg-names = "dbi", "elbi", "parf", "config";
 149 +                       device_type = "pci";
 150 +                       linux,pci-domain = <0>;
 151 +                       bus-range = <0x00 0xff>;
 152 +                       num-lanes = <1>;
 153 +                       #address-cells = <3>;
 154 +                       #size-cells = <2>;
 155 +
 156 +                       ranges = <0x81000000 0 0          0x0fe00000 0 0x00100000   /* downstream I/O */
 157 +                                 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 158 +
 159 +                       interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 160 +                       interrupt-names = "msi";
 161 +                       #interrupt-cells = <1>;
 162 +                       interrupt-map-mask = <0 0 0 0x7>;
 163 +                       interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 164 +                                       <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 165 +                                       <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 166 +                                       <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 167 +
 168 +                       clocks = <&gcc PCIE_A_CLK>,
 169 +                                <&gcc PCIE_H_CLK>,
 170 +                                <&gcc PCIE_PHY_CLK>;
 171 +                       clock-names = "core", "iface", "phy";
 172 +
 173 +                       resets = <&gcc PCIE_ACLK_RESET>,
 174 +                                <&gcc PCIE_HCLK_RESET>,
 175 +                                <&gcc PCIE_POR_RESET>,
 176 +                                <&gcc PCIE_PCI_RESET>,
 177 +                                <&gcc PCIE_PHY_RESET>;
 178 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 179 +
 180 +                       status = "disabled";
 181 +               };
 182 +
 183 +               pcie1: pci@1b700000 {
 184 +                       compatible = "qcom,pcie-v0";
 185 +                       reg = <0x1b700000 0x1000
 186 +                              0x1b702000 0x80
 187 +                              0x1b800000 0x100
 188 +                              0x31f00000 0x100000>;
 189 +                       reg-names = "dbi", "elbi", "parf", "config";
 190 +                       device_type = "pci";
 191 +                       linux,pci-domain = <1>;
 192 +                       bus-range = <0x00 0xff>;
 193 +                       num-lanes = <1>;
 194 +                       #address-cells = <3>;
 195 +                       #size-cells = <2>;
 196 +
 197 +                       ranges = <0x81000000 0 0          0x31e00000 0 0x00100000   /* downstream I/O */
 198 +                                 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 199 +
 200 +                       interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 201 +                       interrupt-names = "msi";
 202 +                       #interrupt-cells = <1>;
 203 +                       interrupt-map-mask = <0 0 0 0x7>;
 204 +                       interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 205 +                                       <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 206 +                                       <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 207 +                                       <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 208 +
 209 +                       clocks = <&gcc PCIE_1_A_CLK>,
 210 +                                <&gcc PCIE_1_H_CLK>,
 211 +                                <&gcc PCIE_1_PHY_CLK>;
 212 +                       clock-names = "core", "iface", "phy";
 213 +
 214 +                       resets = <&gcc PCIE_1_ACLK_RESET>,
 215 +                                <&gcc PCIE_1_HCLK_RESET>,
 216 +                                <&gcc PCIE_1_POR_RESET>,
 217 +                                <&gcc PCIE_1_PCI_RESET>,
 218 +                                <&gcc PCIE_1_PHY_RESET>;
 219 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 220 +
 221 +                       status = "disabled";
 222 +               };
 223 +
 224 +               pcie2: pci@1b900000 {
 225 +                       compatible = "qcom,pcie-v0";
 226 +                       reg = <0x1b900000 0x1000
 227 +                              0x1b902000 0x80
 228 +                              0x1ba00000 0x100
 229 +                              0x35f00000 0x100000>;
 230 +                       reg-names = "dbi", "elbi", "parf", "config";
 231 +                       device_type = "pci";
 232 +                       linux,pci-domain = <2>;
 233 +                       bus-range = <0x00 0xff>;
 234 +                       num-lanes = <1>;
 235 +                       #address-cells = <3>;
 236 +                       #size-cells = <2>;
 237 +
 238 +                       ranges = <0x81000000 0 0          0x35e00000 0 0x00100000   /* downstream I/O */
 239 +                                 0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 240 +
 241 +                       interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 242 +                       interrupt-names = "msi";
 243 +                       #interrupt-cells = <1>;
 244 +                       interrupt-map-mask = <0 0 0 0x7>;
 245 +                       interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 246 +                                       <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 247 +                                       <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 248 +                                       <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 249 +
 250 +                       clocks = <&gcc PCIE_2_A_CLK>,
 251 +                                <&gcc PCIE_2_H_CLK>,
 252 +                                <&gcc PCIE_2_PHY_CLK>;
 253 +                       clock-names = "core", "iface", "phy";
 254 +
 255 +                       resets = <&gcc PCIE_2_ACLK_RESET>,
 256 +                                <&gcc PCIE_2_HCLK_RESET>,
 257 +                                <&gcc PCIE_2_POR_RESET>,
 258 +                                <&gcc PCIE_2_PCI_RESET>,
 259 +                                <&gcc PCIE_2_PHY_RESET>;
 260 +                       reset-names = "axi", "ahb", "por", "pci", "phy";
 261 +
 262 +                       status = "disabled";
 263 +               };
 264         };
 265
 266         sfpb_mutex: sfpb-mutex {