1 From 8d6a35fb13406f87d926fffeee0d70360ce3077d Mon Sep 17 00:00:00 2001
2 From: Sean Cross <xobs@kosagi.com>
3 Date: Thu, 26 Sep 2013 11:24:46 +0800
4 Subject: [PATCH] ARM: imx6q: Add PCIe bits to GPR syscon definition
6 PCIe requires additional bits be defined for GPR8 and GPR12.
8 Signed-off-by: Sean Cross <xobs@kosagi.com>
9 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
10 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
12 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
13 1 file changed, 8 insertions(+)
15 diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
16 index b6bdcd6..e00e9f3 100644
17 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
18 +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
21 #define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
23 +#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
24 +#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
25 +#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
26 +#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6)
27 +#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0)
29 #define IMX6Q_GPR9_TZASC2_BYP BIT(1)
30 #define IMX6Q_GPR9_TZASC1_BYP BIT(0)
33 #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
34 #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
35 #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
36 +#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
37 #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
38 +#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
40 #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
41 #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)