target/linux/imx6/patches-3.12/0007-ARM-dts-added-several-new-imx-pinmux-groups.patch

   1 From 3f7fbfad3edc92227b9ae91050837a6d1de374f5 Mon Sep 17 00:00:00 2001
   2 From: Tim Harvey <tharvey@gateworks.com>
   3 Date: Tue, 22 Oct 2013 21:51:25 -0700
   4 Subject: [PATCH] ARM: dts: added several new imx-pinmux groups
   5
   6 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
   7 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
   8 ---
   9  arch/arm/boot/dts/imx6qdl.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
  10  1 file changed, 60 insertions(+)
  11
  12 --- a/arch/arm/boot/dts/imx6qdl.dtsi
  13 +++ b/arch/arm/boot/dts/imx6qdl.dtsi
  14 @@ -639,6 +639,14 @@
  15                                                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
  16                                                 >;
  17                                         };
  18 +
  19 +                                       pinctrl_audmux_4: audmux-4 {
  20 +                                               fsl,pins = <
  21 +                                                       MX6QDL_PAD_EIM_D24__AUD5_RXFS     0x80000000
  22 +                                                       MX6QDL_PAD_EIM_D25__AUD5_RXC      0x80000000
  23 +                                                       MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
  24 +                                               >;
  25 +                                       };
  26                                 };
  27
  28                                 ecspi1 {
  29 @@ -811,6 +819,28 @@
  30                                                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
  31                                                 >;
  32                                         };
  33 +
  34 +                                       /* No Strobe */
  35 +                                       pinctrl_gpmi_nand_2: gpmi-nand-2 {
  36 +                                               fsl,pins = <
  37 +                                                       MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
  38 +                                                       MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
  39 +                                                       MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
  40 +                                                       MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  41 +                                                       MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
  42 +                                                       MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
  43 +                                                       MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
  44 +                                                       MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
  45 +                                                       MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
  46 +                                                       MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
  47 +                                                       MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
  48 +                                                       MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
  49 +                                                       MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
  50 +                                                       MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
  51 +                                                       MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
  52 +                                                       MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
  53 +                                               >;
  54 +                                       };
  55                                 };
  56
  57                                 hdmi_hdcp {
  58 @@ -1058,6 +1088,13 @@
  59                                                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  60                                                 >;
  61                                         };
  62 +
  63 +                                       pinctrl_uart1_2: uart1grp-2 {
  64 +                                               fsl,pins = <
  65 +                                                       MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  66 +                                                       MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  67 +                                               >;
  68 +                                       };
  69                                 };
  70
  71                                 uart2 {
  72 @@ -1076,6 +1113,13 @@
  73                                                         MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
  74                                                 >;
  75                                         };
  76 +
  77 +                                       pinctrl_uart2_3: uart2grp-3 {
  78 +                                               fsl,pins = <
  79 +                                                       MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  80 +                                                       MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  81 +                                               >;
  82 +                                       };
  83                                 };
  84
  85                                 uart3 {
  86 @@ -1096,6 +1140,13 @@
  87                                                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
  88                                                 >;
  89                                         };
  90 +
  91 +                                       pinctrl_uart3_3: uart3grp-3 {
  92 +                                               fsl,pins = <
  93 +                                                       MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  94 +                                                       MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  95 +                                               >;
  96 +                                       };
  97                                 };
  98
  99                                 uart4 {
 100 @@ -1107,6 +1158,15 @@
 101                                         };
 102                                 };
 103
 104 +                               uart5 {
 105 +                                       pinctrl_uart5_1: uart5grp-1 {
 106 +                                               fsl,pins = <
 107 +                                                       MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
 108 +                                                       MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
 109 +                                               >;
 110 +                                       };
 111 +                               };
 112 +
 113                                 usbotg {
 114                                         pinctrl_usbotg_1: usbotggrp-1 {
 115                                                 fsl,pins = <