target/linux/imx6/patches-3.12/0005-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch

   1 From bf22172158cd6dcc5be6dc286ff5c33794dd0ae8 Mon Sep 17 00:00:00 2001
   2 From: Sean Cross <xobs@kosagi.com>
   3 Date: Mon, 16 Sep 2013 08:20:52 +0000
   4 Subject: [PATCH] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
   5
   6 The i.MX6 has two general-purpose LVDS clocks that can be driven
   7 from a variety of sources.  This patch adds a mux and a gate for
   8 both of these clocks.
   9
  10 Signed-off-by: Sean Cross <xobs@kosagi.com>
  11 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
  12 ---
  13  arch/arm/mach-imx/clk-imx6q.c                        | 20 +++++++++++++++++++-
  14  2 files changed, 23 insertions(+), 1 deletion(-)
  15
  16 --- a/arch/arm/mach-imx/clk-imx6q.c
  17 +++ b/arch/arm/mach-imx/clk-imx6q.c
  18 @@ -217,6 +217,11 @@ static const char *cko2_sels[] = {
  19         "uart_serial", "spdif", "asrc", "hsi_tx",
  20  };
  21  static const char *cko_sels[] = { "cko1", "cko2", };
  22 +static const char *lvds_sels[] = {
  23 +       "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
  24 +       "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
  25 +       "pcie_ref", "sata_ref",
  26 +};
  27
  28  enum mx6q_clks {
  29         dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
  30 @@ -251,7 +256,8 @@ enum mx6q_clks {
  31         ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
  32         sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
  33         usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
  34 -       spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max
  35 +       spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
  36 +       lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
  37  };
  38
  39  static struct clk *clk[clk_max];
  40 @@ -342,6 +348,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
  41                         base + 0xe0, 0, 2, 0, clk_enet_ref_table,
  42                         &imx_ccm_lock);
  43
  44 +       clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
  45 +       clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
  46 +
  47 +       /*
  48 +        * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
  49 +        * independently configured as clock inputs or outputs.  We treat
  50 +        * the "output_enable" bit as a gate, even though it's really just
  51 +        * enabling clock output.
  52 +        */
  53 +       clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
  54 +       clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
  55 +
  56         /*                                name              parent_name        reg       idx */
  57         clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
  58         clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);